CS8491 COMPUTER ARCHITECTURE

UNIT - 3
1. Any condition that causes a processor to stall is called as _________
a) Hazard
b) Page fault
c) System error
d) None of the mentioned
Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.
2. The periods of time when the unit is idle is called as ________
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.
3. The contention for the usage of a hardware device is called ______
a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a
deadlock state.
4. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the
destination side.
5. The stalling of the processor due to the unavailability of the instructions is called as
___________
a) Control hazard
b) structural hazard
c) Input hazard
d) None of the mentioned
Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a
cache miss.
6. The time lost due to the branch instruction is often referred to as ____________
a) Latency
b) Delay
c) Branch penalty
d) None of the mentioned
Answer: c
Explanation: This time also retards the performance speed of the processor.
7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
Answer: a
Explanation: The periods of time when the unit is idle is called a Bubble.
8. ____________ method is used in centralized systems to perform out of order execution.
a) Scorecard
b) Score boarding
c) Optimizing
d) Redundancy
Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged.
Instructions are released only when the scoreboard determines that there are no conflicts
with previously issued and incomplete instructions.
9. The algorithm followed in most of the systems to perform out of order execution is
__________
a) Tomasulo algorithm
b) Score carding
c) Reader-writer algorithm
d) None of the mentioned
Answer: a
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert
Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to
certain dependencies to execute non-sequentially (out-of-order execution).
10. The problem where process concurrency becomes an issue is called as ___________
a) Philosophers problem
b) Bakery problem
c) Bankers problem
d) Reader-writer problem
Answer: d
11. Computer has a built-in system clock that emits millions of regularly spaced electric
pulses per _____ called clock cycles.
a) second
b) millisecond
c) microsecond
d) minute
Answer: a
Explanation: The regularly spaced electric pulses per second are referred to as the clock
cycles. All the jobs performed by the processor are on the basis of clock cycles.
12. It takes one clock cycle to perform a basic operation.
a) True
b) False
Answer: a
Explanation: It takes exactly one clock cycle to perform a basic operation, such as moving a
byte of memory from a location to another location in the computer.
13. The operation that does not involves clock cycles is _________
a) Installation of a device
b) Execute
c) Fetch
d) Decode
Answer: a
Explanation: Normally, several clock cycles are required to fetch, execute and decode a
particular program.
Installation of a device is done by the system on its own.
14. The number of clock cycles per second is referred as ________
a) Clock speed
b) Clock frequency
c) Clock rate
d) Clock timing
Answer: a
Explanation: The number of clock cycles per second is the clock speed. It is generally
measured in gigahertz(109 cycles/sec) or megahertz (106 cycles/sec).
15. CISC stands for ____________
a) Complex Information Sensed CPU
b) Complex Instruction Set Computer
c) Complex Intelligence Sensed CPU
d) Complex Instruction Set CPU
Answer: b
Explanation: CISC is a large instruction set computer. It has variable length instructions. It
also has variety of addressing modes.
16. Which of the following processor has a fixed length of instructions?
a) CISC
b) RISC
c) EPIC
d) Multi-core
Answer: b
Explanation: The RISC which stands for Reduced Instruction set computer has a fixed
length of instructions. It has a small instruction set. Also has reduced references to memory
to retrieve operands.
17. Processor which is complex and expensive to produce is ________
a) RISC
b) EPIC
c) CISC
d) Multi-core
Answer: c
Explanation: CISC stands for complex instruction set computer. It is mostly used in personal
computers. It has a large instruction set and a variable length of instructions.
18. The architecture that uses a tighter coupling between the compiler and the processor is
____________
a) EPIC
b) Multi-core
c) RISC
d) CISC
Answer: a
Explanation: EPIC stands for Explicitly parallel instruction computing. It has a tighter
coupling between the compiler and the processor. It enables the compiler to extract
maximum parallelism in the original code.
19. MAR stands for ___________
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register
Answer: a
Explanation: The MAR stands for memory address register. It holds the address of the
active memory location.
20. A circuitry that processes that responds to and processes the basic instructions that are
required to drive a computer system is ________
a) Memory
b) ALU
c) CU
d) Processor
Answer: d
Explanation: The processor is responsible for processing the basic instructions in order to
drive a computer. The primary functions of a processor are fetch, decode and execute.
21. ______ have been developed specifically for pipelined systems.
a) Utility software
b) Speed up utilities
c) Optimizing compilers
d) None of the mentioned
Answer: c
Explanation: The compilers which are designed to remove redundant parts of the code are
called as optimizing compilers.
22. The pipelining process is also called as ______
a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
d) None of the mentioned
Answer: b
Explanation: It is called so because it performs its operation at the assembly level.
23. The fetch and execution cycles are interleaved with the help of ________
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
Answer: b
Explanation: The time cycle of the clock is adjusted to perform the interleaving.
24. Each stage in pipelining should be completed within ___________ cycle.
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: The stages in the pipelining should get completed within one cycle to increase
the speed of performance.
25. In pipelining the task which requires the least time is performed first.
a) True
b) False
Answer: b
Explanation: This is done to avoid starvation of the longer task.
26. If a unit completes its task before the allotted time period, then _______
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to a different task
c) It’ll remain idle for the remaining time
d) None of the mentioned
Answer: c
27. To increase the speed of memory access in pipelining, we make use of _______
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of
28. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
29. The contention for the usage of a hardware device is called ______
a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
Answer: a
30. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the
destination side.
31. ____________ is the raw material used as input and __________ is the processed data
obtained as output of data processing.
a) Data, Instructions
b) Instructions, Program
c) Data, Program
d) Program, Code
Answer: a
Explanation: Data can be assumed as a raw material which, in turns after processing gives
the desired output in the form of instructions. Further, a set of ordered and meaningful
instructions is known as a program.
32. Which of the following is not a characteristic of a computer?
a) Diligence
b) I.Q.
c) Accuracy
d) Versatility
Answer: b
Explanation: The Computer system has no I.Q. of its own. It does only what it is
programmed to do. It cannot take decisions of its own.
A computer is diligent because it can work continuously for hours without getting any errors
or without getting grumbled.
The accuracy of a computer is consistently high and its level of accuracy depends on its
design. A computer can perform any task if, it can be broken down into a series of logical
steps. Therefore, a computer is versatile.
33. Fill in the blank in the diagram.

a) Input Unit
b) Memory Unit
c) Control Unit
d) I/O Unit
Answer: c
Explanation: The control unit manages and coordinates the operations of a computer
system. The ALU is responsible for performing all the arithmetic and bitwise operations .
Therefore, both these units combine to form the brain of the computer ,which is the central
processing unit.
34. The part of a processor which contains hardware necessary to perform all the
operations required by a computer:
a) Data path
b) Controller
c) Registers
d) Cache
Answer: a
Explanation: A processor is a part of the computer which does all the data manipulation and
decision making. A processor comprises of:
A data path which contains the hardware necessary to perform all the operations. A
controller tells the data path what needs to be done.
The registers act as intermediate storage for the data.
35. What does MAR stand for?
a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
d) Memory Address Register
Answer: d
Explanation: MAR is a type of register which is responsible for the fetch operation. MAR is
connected to the address bus and it specifies the address for the read and write operations.
36. If the control signals are generated by combinational logic, then they are generated by a
type of _______________ controlled unit.
a) Micro programmed
b) Software
c) Logic
d) Hardwired
Answer: d
Explanation: The main task of a control unit is to generate control signals. There are two
main types of control units:
A hardwired control unit generates control signals by using combinational logic circuits and
the Micro programmed control unit generates control signals by using some softwares.
37. Which is the simplest method of implementing hardwired control unit?
a) State Table Method
b) Delay Element Method
c) Sequence Counter Method
d) Using Circuits
Answer: a
Explanation: There are 3 ways of implementing hardwired control unit:
A state table is the simplest method in which a number of circuits are designed based on
the cells in the table.
A delay element method consists of a flowchart drawn for the circuit. A D-flip flop is used as
a delay element.
A sequence counter method used k-modulo counter as a replacement for k delay elements.
38. A set of microinstructions for a single machine instruction is called ___________
a) Program
b) Command
c) Micro program
d) Micro command
Answer: c
Explanation: For every micro-operation, a set of microinstructions are written which indicate
the control signals to be activated. A set of microinstructions is a micro program. The
address of the next microinstruction is given by a Micro-program counter.
39. Micro-program consists of a set of microinstructions which are strings of 0s and 1s.
a) True
b) False
Answer: a
Explanation: The computer understands only binary language. So, the micro-program
should have instructions which are in the form of 0s and 1s. Each output line of the micro-
program corresponds to one control signal.
40. A decoder is required in case of a ______________
a) Vertical Microinstruction
b) Horizontal Microinstruction
c) Multilevel Microinstruction
d) All types of microinstructions
Answer: a
Explanation: There are two types of microinstructions: Horizontal and Vertical.
In a horizontal microinstruction, each bit represents a signal to be activated whereas, in
case of vertical microinstruction bits are decoded and, the decoder then produces signals.
41. ________ are the different type/s of generating control signals.
a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired
Answer: d
Explanation: The above is used to generate control signals in different types of system
architectures.
42. The type of control signal is generated based on ________
a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the mentioned
Answer: d
Explanation: Based on the information above the type of control signal is decided.
43. What does the hardwired control generator consist of?
a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned
Answer: d
Explanation: The CU uses the above blocks and IR to produce the necessary signal.
44. What does the end instruction do?
a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
Answer: c
Explanation: It is basically used to start the generation of a new signal.
45. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…
a) True
b) False
Answer: a
Explanation: The signal is generated using the logic of the formula above.
46. What does the RUN signal do?
a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
Answer: d
Explanation: The RUN signal increments the step counter by one for each clock cycle.
47. The name hardwired came because the sequence of operations carried out is
determined by the wiring.
a) True
b) False
Answer: a
Explanation: In other words hardwired is another name for Hardware Control signal
generator.
48. The benefit of using this approach is ________
a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation
49. The disadvantage/s of the hardwired approach is ________
a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions
Answer: d
Explanation: The more complex the instruction set less applicable to a hardwired approach.
50. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
Answer: a