Beckhoff FB1120 0 V10

Hardware Data Sheet
FB1120
Piggyback Controller
Board
Version 1.0
Date: 2008-09-05
CONTENTS
CONTENTS
1 Foreword 6
1.1 Notes on the Documentation 6
1.1.1 Liability Conditions 6
1.2 Safety Instructions 6
1.2.1 Safety Rules 6
1.2.2 State at Delivery 6
1.2.3 Personnel Qualification 6
1.2.4 Description of Safety Symbols 6
1.3 Documentation Issue Status 7
2 Overview 8
2.1 Indicator LEDs 8
2.2 FPGA Type and Speed Grade 9
3 Altera Pinout 10
4 Process Data Interfaces 13
4.1 Pinout 13
4.2 Power Supply 14
5 Electrical Specification 15
5.1 Ratings 15
5.2 EMC – Electro magnetic compatibility 15
6 Mechanical Specification 16
6.1 Board Dimensions 16
6.2 Physical Connector Specification 17
6.3 Recommended Panel Opening 17
6.4 Top/Bottom Side Component Height Definition 18
7 Appendix 20
7.1 Support and Service 20
7.1.1 Beckhoff’s branch offices and representatives 20
7.2 Beckhoff Headquarters 20
II FB1120 Piggyback Controller Board

TABLES
TABLES
Table 1: Indicator LEDs ........................................................................................................................... 8
Table 2: Pinout of the Altera Cyclone III EP1C12F256C8N.................................................................. 10
Table 3: Altera Cyclone I Pinout to FB1120 port mapping .................................................................... 13
Table 4: Typical Ratings ........................................................................................................................ 15
FB1120 Piggyback Controller Board III

FIGURES
FIGURES
Figure 1: Overview of the FB1120........................................................................................................... 8
Figure 2: PDI Connector Power Pin Distribution ................................................................................... 14
Figure 3: Connection to GND-Earth ...................................................................................................... 15
Figure 4: Board dimensions of the FB1120 – Top View........................................................................ 16
Figure 5: Recommended Panel Opening .............................................................................................. 17
Figure 6 Component height zones for the top side of FB1120.............................................................. 18
Figure 7 Component height zones for the bottom side of FB1120........................................................ 19
IV FB1120 Piggyback Controller Board

ABBREVIATIONS
ABBREVIATIONS
DC Direct Current
EEPROM Electrically Erasable Programmable Read Only Memory. Non-volatile memory used
to store ESC configuration and description.
ESC EtherCAT Slave Controller
EtherCAT Real-time Standard for Industrial Ethernet Control Automation Technology
GND-Earth Ground-Earth
LED Light Emitting Diode, used as an indicator
PCB Printed Circuit Board
PDI Process Data interface
SPI Serial Peripheral Interface
RJ45 FCC Registered Jack, standard Ethernet connector (8P8C)
FB1120 Piggyback Controller Board V

Foreword
1 Foreword
1.1 Notes on the Documentation

This description is only intended for the use of trained specialists in control and automation engineer-
ing who are familiar with the applicable national standards. It is essential that the following notes and
explanations are followed when installing and commissioning these components.
1.1.1 Liability Conditions

The responsible staff must ensure that the application or use of the products described satisfy all the
requirements for safety, including all the relevant laws, regulations, guidelines and standards.
The documentation has been prepared with care. The products described are, however, constantly
under development. For that reason the documentation is not in every case checked for consistency
with performance data, standards or other characteristics. None of the statements of this manual
represents a guarantee (Garantie) in the meaning of § 443 BGB of the German Civil Code or a state-
ment about the contractually expected fitness for a particular purpose in the meaning of § 434 par. 1
sentence 1 BGB. In the event that it contains technical or editorial errors, we retain the right to make
alterations at any time and without warning. No claims for the modification of products that have al-
ready been supplied may be made on the basis of the data, diagrams and descriptions in this docu-
mentation.
© This documentation is copyrighted. Any reproduction or third party use of this publication, whether in
whole or in part, without the written permission of Beckhoff Automation GmbH, is forbidden.
1.2 Safety Instructions
1.2.1 Safety Rules

The responsible staff must ensure that the application or use of the products described satisfy all the
requirements for safety, including all the relevant laws, regulations, guidelines and standards.
1.2.2 State at Delivery

All the components are supplied in particular hardware and software configurations appropriate for the
application. Modifications to hardware or software configurations other than those described in the
documentation are not permitted, and nullify the liability of Beckhoff Automation GmbH.
1.2.3 Personnel Qualification

This description is only intended for the use of trained specialists in control and automation engineer-
ing who are familiar with the applicable national standards.
1.2.4 Description of Safety Symbols

The following safety symbols are used in this operating manual. They are intended to alert the reader
to the associated safety instructions.
Danger This symbol is intended to highlight risks for the life or health of personnel.
This symbol is intended to highlight risks for equipment, materials or the envi-
Warning ronment.
Note This symbol indicates information that contributes to better understanding.
6 FB1120 Piggyback Controller Board

Foreword
1.3 Documentation Issue Status
Version Comment
0.1 • Initial Version
1.0 • First Release
•
•
FB1120 Piggyback Controller Board 7

Overview
2 Overview
The EtherCAT Piggyback controller board FB1120 combines Altera Cyclone I FPGA, two E²PROMS,
two EtherCAT ports and a PDI-Connector on a printed circuit board. The first E²PROM configures the
FPGA with the EtherCAT Slave IP Core (FPGA Config. E²P). The second E²PROM configures the IP
Core itself. The Piggyback controller board can as well be used for EtherCAT evaluation purposes as
assembled into customer end products.
Config.
FPGA
Figure 1: Overview of the FB1120
The board is structured in areas for Port 0 and Port 1, the PDI Connector, FPGA Configuration Con-
nector, a PDI Termination Area, EEPROM, LEDs, and the Altera Cyclone I FPGA based EtherCAT
Slave Controller. Each EtherCAT port in Figure 1 combines a PHY, magnetics and an RJ45 connec-
tor.
Purpose of this EtherCAT controller board is either the usage in combination with the EL9800 Evalua-
tion base board or in combination with customer specific hardware.
2.1 EtherCAT Ports 0 an 1

The EtherCAT ports connect the FB1120 Piggyback controller board with the EtherCAT bus system.
For the incoming EtherCAT data stream the port 0 is designated. Accordingly port 1 is assigned for the
outgoing data stream. Standard CAT5-Cable can be used to interface with the Piggyback controller
board. Especially suited EtherCAT cable can be found on the internet representation of the Beckhoff
New Automation Company.
2.2 Indicator LEDs

Table 1 is giving an overview over the indicator LEDs on the FB1120.
Table 1: Indicator LEDs
LED Comment
D300 Link Activity Port 0
D301 Link Activity Port 1
D306 EtherCAT Slave Controller State Indicator LED
D303 User defined
D304 User defined
D307 User defined

Overview
2.3 FPGA Type and Speed Grade

The FB1120 EtherCAT piggyback controller board is equipped with an Altera Cyclone I FPGA with the
parameters following:
Type: EP1C12
Speed: -8
Temperature: Commercial
Footprint: F256
Complete name: EP1C12F256C8N
2.4 FPGA-Configuration EEPROM

For automatic start up of the IP Core the FB1120 Piggyback controller board brings up a FPGA Con-
figuration EEPROM that can be programmed using the programming interface of the EL9800 base
board or equivalent programmers from Altera. The EEPROM type used on the FB1120 Piggyback
controller board is the EPCS1 from Altera.
2.5 EtherCAT SII EEPROM

After the configuration of the FPGA the IP Core loads its configuration parameters out of the EtherCAT
SII EEPROM. Detailed information about the content of the EEPROM can be found in the IP Core
documentation. The EtherCAT SII EEPROM can be programmed over EtherCAT e.g. using TwinCAT.
2.6 JTAG programming interface

The JTAG programming interface supports configuration of the Altera Cyclone I FPGA as well as the
programming of the FPGA-Configuration EEPROM via JTAG-Indirect-Mode. Connector ST201 inter-
faces directly with the EL9800 base board that provides the necessary programming hardware.
When the FB1120 PiggyBack controller board is used in combination with custom hardware, the pro-
gramming of the FPGA Configuration EEPROM can take place using standard programming hardware
from Altera. In Figure 2 the pin configuration of the connector ST2101 is given.
GND 10 9 TDI
8 7
6 5 TMS
+3.3V 4 3 TDO
GND 2 1 TCK
Figure 2: JTAG Interface; Top side view.

Altera Pinout
3 Altera Pinout
In the following the pinout of the Altera Cyclone I EP3C12 is shown. This pinout shows the connection
between the Cyclone II FPGA and the external hardware.
Table 2: Pinout of the Altera Cyclone III EP1C12F256C8N
Pin Pin Name Dir. Description Pin Pin Name Dir. Description
A1 GND Power Supply J1 RX_DV1 I PHY Port0
A2 SPEED1 I PHY Port0 J2 MSEL1 I Configuration signal
A3 VCCIO2 Power Supply J3 MSEL0 I Configuration signal
A4 RX_DATA2[0] I PHY Port1 J4 nCE I Configuration signal
A5 GND Power Supply J5 GNDG_PLL1 Power Supply
A6 TX_ERR2 O PHY Port1 J6 GNDA_PLL1 Power Supply
A7 VCCINT Power Supply J7 GND Power Supply
A8 RES_INPUT I not used J8 VCCINT Power Supply
A9 TX_EN2 O PHY Port1 J9 GND Power Supply
A10 VCCINT Power Supply J10 VCCINT Power Supply
A11 TX_DATA2[3] O PHY Port1 J11 GNDA_PLL2 Power Supply
A12 GND Power Supply J12 GNDG_PLL2 Power Supply
A13 RES_INPUT I not used J13 nSTATUS BD Configuration signal
A14 VCCIO2 Power Supply J14 TCK I JTAG (not used)
A15 RES_INPUT I not used J15 TMS I JTAG (not used)
A16 GND Power Supply J16 PORT_A[0] I/O PDI
B1 CRS1 I PHY Port0 K1 RX_DATA1[1] I PHY Port0
B2 RX_DATA2[3] I PHY Port1 K2 RX_DATA1[0] I PHY Port0
B3 RX_DATA2[2] I PHY Port1 K3 ASDO O Configuration signal
B4 RX_DATA2[1] I PHY Port1 K4 DCLK O Configuration signal
B5 RX_DV2 I PHY Port1 K5 RES_INPUT I not used
B6 RX_ERR2 I PHY Port1 K6 GND Power Supply
B7 TX_CLK2 I PHY Port1 K7 VCCINT Power Supply
B8 RES_INPUT I not used K8 GND Power Supply
B9 TX_DATA2[0] O PHY Port1 K9 VCCINT Power Supply
B10 TX_DATA2[2] O PHY Port1 K10 GND Power Supply
B11 COL2 I PHY Port1 K11 VCCIO3 Power Supply
B12 CRS2 I PHY Port1 K12 RES_INPUT I not used
B13 RES_INPUT I not used K13 CONF_DONE BD Configuration signal
B14 MCLK O PHY Management K14 RES_INPUT I not used
B15 RES_INPUT I not used K15 PORT_A[2] I/O PDI
B16 nRESET I Reset In K16 PORT_A[1] I/O PDI
C1 VCCIO1 Power Supply L1 RX_DATA1[3] I PHY Port0
C2 COL1 I PHY Port0 L2 RX_DATA1[2] I PHY Port0
C3 RES_INPUT I not used L3 RES_INPUT I not used
C6 RES_INPUT I not used L6 GND Power Supply
C7 RES_INPUT I not used L7 VCCIO4 Power Supply
C9 TX_DATA2[1] O PHY Port1 L9 GND Power Supply
C10 RES_INPUT I not used L10 VCCIO4 Power Supply
C13 SPEED2 I PHY Port1 L13 RES_INPUT I not used
C14 MDIO BD PHY Management L14 RES_INPUT I not used
C15 RES_INPUT I not used L15 PORT_A[4] I/O PDI
C16 VCCIO3 Power Supply L16 PORT_A[3] I/O PDI
D1 TX_DATA1[2] O PHY Port0 M1 PORT_E[6] I/O PDI
D2 TX_DATA1[3] O PHY Port0 M2 PORT_E[7] I/O PDI
D3 RES_INPUT I not used M3 RES_INPUT I not used

Altera Pinout
D8 LEDS[0] O Link/Act LED Port0 M8 RES_INPUT I not used
D9 LEDS[1] O Link/Act LED Port1 M9 RES_INPUT I not used
D10 LEDS[2] O reserved M10 RES_INPUT I not used
D14 LEDS[6] O Run LED M14 RES_INPUT I not used
D15 LEDS[7] O reserved M15 PORT_A[6] I/O PDI
D16 PROM_SEL O (not used) M16 PORT_A[5] I/O PDI
E1 TX_DATA1[0] O PHY Port0 N1 PORT_E[4] I/O PDI
E2 TX_DATA1[1] O PHY Port0 N2 PORT_E[5] I/O PDI
E3 RES_INPUT I not used N3 RES_INPUT I not used
E15 PROM_SIZE[0] I EEPROM size[0] N15 PORT_B[0] I/O PDI
E16 PROM_CLK BD EEPROM Clock N16 PORT_A[7] I/O PDI
F1 TX_ERR1 O PHY Port0 P1 VCCIO1 Power Supply
F2 TX_EN1 O PHY Port0 P2 PORT_E[2] I/O PDI
F3 RES_INPUT I not used P3 PORT_E[3] I/O PDI
F4 RES_INPUT I not used P4 RES_INPUT I not used
F6 GND Power Supply P6 RES_INPUT I not used
F7 VCCIO2 Power Supply P7 RES_INPUT I not used
F8 GND Power Supply P8 PORT_C[7] I/O PDI
F9 GND Power Supply P9 PORT_C[4] I/O PDI
F10 VCCIO2 Power Supply P10 RES_INPUT I not used
F11 GND Power Supply P11 RES_INPUT I not used
F15 PROM_SIZE[1] I EEPROM size[1] P15 PORT_B[1] I/O PDI
F16 PROM_DATA BD EEPROM data P16 VCCIO3 Power Supply
G1 TX_CLK1 I PHY Port0 R1 PORT_E[1] I/O PDI
G2 RX_ERR1 I PHY Port0 R2 PORT_D[7] I/O PDI
G3 RES_INPUT I not used R3 PORT_D[6] I/O PDI
G4 nCSO O Configuration signal R4 PORT_D[4] I/O PDI
G5 RES_INPUT I not used R5 PORT_D[3] I/O PDI
G6 VCCIO1 Power Supply R6 PORT_D[1] I/O PDI
G7 GND Power Supply R7 PORT_D[0] I/O PDI
G8 VCCINT Power Supply R8 RES_INPUT I not used
G9 GND Power Supply R9 PORT_C[5] I/O PDI
G10 VCCINT Power Supply R10 PORT_C[3] I/O PDI
G11 GND Power Supply R11 PORT_C[1] I/O PDI
G12 RES_INPUT I not used R12 PORT_C[0] I/O PDI
G13 RES_INPUT I not used R13 PORT_B[6] I/O PDI
G16 RX_CLK2 I PHY Port1 R16 PORT_B[2] I/O PDI

Altera Pinout
H1 RX_CLK1 I PHY Port0 T1 GND Power Supply
H2 DATA0 I Configuration signal T2 PORT_E[0] I/O PDI
H3 nCONFIG I Configuration signal T3 VCCIO4 Power Supply
H4 nCEO O Configuration signal T4 PORT_D[5] I/O PDI
H5 RES_INPUT I not used T5 GND Power Supply
H6 VCCA_PLL1 Power Supply T6 PORT_D[2] I/O PDI
H7 VCCINT Power Supply T7 VCCINT Power Supply
H8 GND Power Supply T8 RES_INPUT I not used
H9 VCCINT Power Supply T9 PORT_C[6] I/O PDI
H10 GND Power Supply T10 VCCINT Power Supply
H11 VCCA_PLL2 Power Supply T11 PORT_C[2] I/O PDI
H12 RES_INPUT I not used T12 GND Power Supply
H13 RES_INPUT I not used T13 PORT_B[7] I/O PDI
H14 TDI I JTAG (not used) T14 VCCIO4 Power Supply
H15 TDO O JTAG (not used) T15 PORT_B[4] I/O PDI
H16 GND+ (CLK3) I Power Supply T16 GND Power Supply

Process Data Interface
4 Process Data Interface

As the FB1120 EtherCAT piggyback controller board is powered by an Altera Cyclone I FPGA, differ-
ent PDI configurations can be achieved by reconfiguring the FPGA with a modified EtherCAT Slave
IP-Core. The mapping between the PDI connector pins and the FPGA pinout is shown in the table in
following section.
4.1 Pinout
Table 3: Altera Cyclone I Pinout to FB1120 port mapping
Pin Number Port IO Port Number Altera Cyclone I Pin Number

1 GND
2 PA0 I/O[0] J16
3 PA1 I/O[1] K16
4 PA2 I/O[2] K15
5 PA3 I/O[3] L1
6 PA4 I/O[4] L15
7 PA5 I/O[5] M16
8 PA6 I/O[6] M15
9 PA7 I/O[7] N16
10 GND
11 PB0 I/O[8] N15
12 PB1 I/O[9] P15
13 PB2 I/O[10] R16
14 PB3 I/O[11] R15
15 PB4 I/O[12] T15
16 PB5 I/O[13] R14
17 PB6 I/O[14] R13
18 PB7 I/O[15] T13
19 GND
20 PC0 I/O[16] R12
21 PC1 I/O[17] R11
22 PC2 I/O[18] T11
23 PC3 I/O[19] R10
24 PC4 I/O[20] P9
25 PC5 I/O[21] R9
26 PC6 I/O[22] T9
27 PC7 I/O[23] P8
28 GND
29 PD0 I/O[24] R7
30 PD1 I/O[25] R6
31 PD2 I/O[26] T6
32 PD3 I/O[27] R5
33 PD4 I/O[28] R4
34 PD5 I/O[29] T4
35 PD6 I/O[30] R3
36 PD7 I/O[31] R2
37 GND
38 PE0 I/O[32] T2
39 PE1 I/O[33] R1

Process Data Interface
Pin Number Port IO Port Number Altera Cyclone I Pin Number

40 PE2 I/O[34] P2
41 PE3 I/O[35] P3
42 PE4 I/O[36] N1
43 PE5 I/O[37] N2
44 PE6 I/O[38] M1
45 PE7 I/O[39] M2
46 GND
47 VCC
48 N.C.
49 VCC (5V Input)
50 3.3V Out
4.2 Power Supply

Figure 3 shows the distribution of the power pins on the PDI Connector from top side view.
Figure 3: PDI Connector Power Pin Distribution
The Pins 47 and 49 have to be supplied with +5V VCC. Pin 50 is a 3.3V Output from one DC-DC con-
verter on the FB1120.The maximum current that can be driven through the 3.3V output (Pin 50) is
limited to 100mA. The GND pins, which are marked blue, have to be connected to a ground plane on
the supplying PCB.

Electrical Specification
5 Electrical Specification
5.1 Ratings
Table 4: Typical Ratings
Symbol Parameter Condition Min Typ Max Units

VCC Board Supply Voltage 4.0 5.0 5.5 V
ICC Board Supply Current 1 Port 135 180 600 mA
2 Ports 225
ϑStorage Storage temperature -65 105 °C
ϑ Ambient Ambient temperature -40 70 °C
5.2 EMC – Electro magnetic compatibility

For proper protection against damage caused by electrostatic discharge, the top left mounting hole of
the EtherCAT piggyback controller board has to be connected to a massive panel or plate that is con-
nected with GND-Earth. The remaining three holes have to be used for mechanical fixation of the pig-
gyback controller board.
Port 1 Port 0
LACT LINK ESC
OUT IN ACT 0 ACT 1 STATE
GND-Earth
Link 1 Link 0
USR0 USR1 USR2
TR 1 TR 0 Config.
FPGA
Altera
PHY PHY Cyclone
1 0 EP1C12F256
FPGA IP Core
CFG E²P E²P
PDI Connector
Figure 4: Connection to GND-Earth
Suitable screw dimensions are: M3x6 DIN-7985.

Mechanical Specification
6 Mechanical Specification
As the EtherCAT piggyback controller board FB1120 can be assembled with customer hardware to
complex end user devices, board dimensions and assembly recommendations have to be taken in
account. In 6.1 the board dimensions including mounting and contact hole positions and diameters
from top view are shown. Panel opening recommendations are shown in section 6.2. All dimensions
are drawn in millimeters.
6.1 Board Dimensions
Pin 1
Pin 50
IN
OUT
Pin 1
Figure 5: Board dimensions of the FB1120 – Top View

6.2 Physical Connector Specification

The Board to Board connector (ST101) can be connected as well from the bottom as from the top side
of the FB1120. The bottom side low profile socket is equivalent to the Samtec (www.samtec.com)
product with the manufacturer number CLH-125-F-D-BE-P-TR. Insertion depth from top side is 4.7
mm, respectively 3.2 mm from bottom side. A suitable pin header for the low profile socket can also
received from Samtec. The TSM series is suitable for the socket. As an example the pin header with
the part number TSM-125-02-L-DV can be used to connect the EtherCAT piggyback controller board
FB1120.
6.3 Recommended Panel Opening
Figure 6: Recommended Panel Opening
In Figure 6 the dimensions of a typical panel opening is illustrated. The two ports and the LED break
throughs have to be labelled as shown in the figure.

6.4 Top/Bottom Side Component Height Definition
13.5 mm
6 mm
3 mm
70
51
16
30
Figure 7 Component height zones for the top side of FB1120

Figure 8 Component height zones for the bottom side of FB1120

Appendix
7 Appendix
7.1 Support and Service

Beckhoff and their partners around the world offer comprehensive support and service, making avail-
able fast and competent assistance with all questions related to Beckhoff products and system solu-
tions.
7.1.1 Beckhoff’s branch offices and representatives

Please contact your Beckhoff branch office or representative for local support and service on Beckhoff
products!
The addresses of Beckhoff's branch offices and representatives round the world can be found on her
internet pages: http://www.beckhoff.com
You will also find further documentation for Beckhoff components there.
7.2 Beckhoff Headquarters

Beckhoff Automation GmbH
Eiserstr. 5
33415 Verl
Germany
phone: + 49 (0) 5246/963-0
fax: + 49 (0) 5246/963-198
e-mail: [email protected]
web: www.beckhoff.com
Beckhoff Support
Support offers you comprehensive technical assistance, helping you no only with the application of
individual Beckhoff products, but also with other, wide-ranging services:
• support
• design, programming and commissioning of complex automation systems
• and extensive training program for Beckhoff system components
hotline: + 49 (0) 5246/963-157
fax: + 49 (0) 5246/963-9157
Beckhoff Service
The Beckhoff Service Center supports you in all matters of after-sales service:
• on-site service
• repair service
• spare parts service
• hotline service
hotline: + 49 (0) 5246/963-460
fax: + 49 (0) 5246/963-479

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Hardware Data Sheet

II FB1120 Piggyback Controller Board

FB1120 Piggyback Controller Board III

IV FB1120 Piggyback Controller Board

EtherCAT Real-time Standard for Industrial Ethernet Control Automation Technology

LED Light Emitting Diode, used as an indicator

PCB Printed Circuit Board

PDI Process Data interface

SPI Serial Peripheral Interface

RJ45 FCC Registered Jack, standard Ethernet connector (8P8C)

FB1120 Piggyback Controller Board V

1.1 Notes on the Documentation

1.1.1 Liability Conditions

1.2 Safety Instructions

1.2.1 Safety Rules

1.2.2 State at Delivery

1.2.3 Personnel Qualification

1.2.4 Description of Safety Symbols

Note This symbol indicates information that contributes to better understanding.

6 FB1120 Piggyback Controller Board

1.3 Documentation Issue Status

FB1120 Piggyback Controller Board 7

2.1 EtherCAT Ports 0 an 1

2.2 Indicator LEDs

Table 1: Indicator LEDs

8 FB1120 Piggyback Controller Board

2.3 FPGA Type and Speed Grade

2.4 FPGA-Configuration EEPROM

2.5 EtherCAT SII EEPROM

2.6 JTAG programming interface

Figure 2: JTAG Interface; Top side view.

FB1120 Piggyback Controller Board 9

Table 2: Pinout of the Altera Cyclone III EP1C12F256C8N

10 FB1120 Piggyback Controller Board

FB1120 Piggyback Controller Board 11

12 FB1120 Piggyback Controller Board

4 Process Data Interface

Table 3: Altera Cyclone I Pinout to FB1120 port mapping

Pin Number Port IO Port Number Altera Cyclone I Pin Number

FB1120 Piggyback Controller Board 13

Pin Number Port IO Port Number Altera Cyclone I Pin Number

4.2 Power Supply

Figure 3: PDI Connector Power Pin Distribution

14 FB1120 Piggyback Controller Board

Table 4: Typical Ratings

Symbol Parameter Condition Min Typ Max Units

ϑ Ambient Ambient temperature -40 70 °C

5.2 EMC – Electro magnetic compatibility

Figure 4: Connection to GND-Earth

Suitable screw dimensions are: M3x6 DIN-7985.

FB1120 Piggyback Controller Board 15

6.1 Board Dimensions

Figure 5: Board dimensions of the FB1120 – Top View

16 FB1120 Piggyback Controller Board

6.2 Physical Connector Specification

6.3 Recommended Panel Opening

Figure 6: Recommended Panel Opening

FB1120 Piggyback Controller Board 17

6.4 Top/Bottom Side Component Height Definition