Dual Power MOSFET Driver Features: File Number Data Sheet April 1999
Dual Power MOSFET Driver Features: File Number Data Sheet April 1999
Dual Power MOSFET Driver Features: File Number Data Sheet April 1999
IN A 2 7 OUT A
IN
V- 3 6 V+
IN B 4 5 OUT B
3-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ICL7667
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
ICL7667C, M ICL7667M
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DC SPECIFICATIONS
Input Current IIL VCC = 15V, VIN = 0V and 15V -0.1 - 0.1 -0.1 - 0.1 µA
Output Voltage High VOH VCC = 4.5V and 15V VCC VCC - VCC VCC - V
-0.05 -0.1
Output Voltage Low VOL VCC = 4.5V and 15V - 0 0.05 - - 0.1 V
Power Supply Current ICC VCC = 15V, VIN = 0V both inputs - 150 400 - - 400 µA
SWITCHING SPECIFICATIONS
Delay Time TD2 Figure 3 - 35 50 - - 60 ns
NOTE: All typical values have been characterized but are not tested.
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ICL7667
Test Circuits
V- = 15V
+5V
90%
INPUT
+
4.7µF 0.1µF
10%
≈0.4V
INPUT OUTPUT TD1 TD2
ICL7667 CL = 1000pF tf tr
15V
INPUT RISE AND 90% 90%
FALL TIMES ≤10ns
OUTPUT
10% 10%
0V
1µs 100
VCC = 15V
90 CL = 1nF
VCC = 15V
80
70
60
tRISE TD2
50
40
10 TD1
30
tFALL 20
10
1 0
10 100 1000 10K 100K
-55 0 25 70 125
CL (pF) TEMPERATURE (oC)
50 30
VCC = 15V
40 200kHz
tr AND tf
tr AND tf , (ns)
10
30
ICC (mA)
CL = 1nF
VCC = 15V 20kHz
20
3.0
10
0
1
-55 0 25 70 125 10 100 1K 10K 100K
TEMPERATURE (oC) CL (pF)
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ICL7667
100 100
VCC = 15V
ICC (mA)
ICC (mA)
10 10 VCC = 15V
VCC = 5V
1
1
VCC = 5V
CL = 1nF
CL = 10pF
100µA 100mA
10K 100K 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
50 50
40 40
tr AND tD2 , (ns)
tD1 AND tf , (ns)
30 30
tr = TD2
tf
20 20
tD1
10
10
CL = 1nF CL = 10pF
0 0
5 10 15 5 10 15
VCC (V) VCC (V)
FIGURE 7. DELAY AND FALL TIMES vs VCC FIGURE 8. RISE TIME vs VCC
3-4
ICL7667
peak current capability of the ICL7667 enables it to drive a 7. Output stage I2R power loss
1000pF load with a rise time of only 40ns. Because the The sum of the above must stay within the specified limits for
output stage impedance is very low, up to 300mA will flow reliable operation.
through the series N-Channel and P-channel output devices
(from VCC to ground) during output transitions. This crossover As noted above, the input inverter current is input voltage
current is responsible for a significant portion of the internal dependent, with an ICC of 0.1mA maximum with a logic 0
power dissipation of the ICL7667 at high frequencies. It can be input and 6mA maximum with a logic 1 input.
minimized by keeping the rise and fall times of the input to the The output stage crowbar current is the current that flows
ICL7667 below 1µs. through the series N-Channel and P-channel devices that
form the output. This current, about 300mA, occurs only
Application Notes during output transitions. Caution: The inputs should never
Although the ICL7667 is simply a dual level-shifting inverter, be allowed to remain between VIL and VIH since this could
there are several areas to which careful attention must be leave the output stage in a high current mode, rapidly
paid. leading to destruction of the device. If only one of the drivers
is being used, be sure to tie the unused input to a ground.
Grounding
NEVER leave an input floating. The average supply current
Since the input and the high current output current paths drawn by the output stage is frequency dependent, as can
both include the ground pin, it is very important to minimize be seen in ICC vs Frequency graph in the Typical
and common impedance in the ground return. Since the Characteristics Graphs.
ICL7667 is an inverter, any common impedance will
generate negative feedback, and will degrade the delay, rise The output stage I2R power dissipation is nothing more than
and fall times. Use a ground plane if possible, or use the product of the output current times the voltage drop
separate ground returns for the input and output circuits. To across the output device. In addition to the current drawn by
minimize any common inductance in the ground return, any resistive load, there will be an output current due to the
separate the input and output circuit ground returns as close charging and discharging of the load capacitance. In most
to the ICL7667 as is possible. high frequency circuits the current used to charge and
discharge capacitance dominates, and the power dissipation
Bypassing is approximately
The rapid charging and discharging of the load capacitance
PAC = CVCC2f
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance where C = Load Capacitance, f = Frequency
over a wide frequency range should be used. A 4.7µF
In cases where the load is a power MOSFET and the gate
tantalum capacitor in parallel with a low inductance 0.1µF
drive requirement are described in terms of gate charge, the
capacitor is usually sufficient bypassing.
ICL7667 power dissipation will be
Output Damping PAC = QGVCCf
Ringing is a common problem in any circuit with very fast where QG = Charge required to switch the gate, in
rise or fall times. Such ringing will be aggravated by long Coulombs, f = Frequency.
inductive lines with capacitive loads. Techniques to reduce
ringing include: Power MOS Driver Circuits
1. Reduce inductance by making printed circuit board traces Power MOS Driver Requirements
as short as possible.
Because it has a very high peak current output, the ICL7667
2. Reduce inductance by using a ground plane or by closely
the at driving the gate of power MOS devices. The high
coupling the output lines to their return paths.
current output is important since it minimizes the time the
3. Use a 10Ω to 30Ω resistor in series with the output of the power MOS device is in the linear region. Figure 9 is a
ICL7667. Although this reduces ringing, it will also slightly
typical curve of charge vs gate voltage for a power MOSFET.
increase the rise and fall times.
The flat region is caused by the Miller capacitance, where
4. Use good bypassing techniques to prevent supply voltage the drain-to-gate capacitance is multiplied by the voltage
ringing.
gain of the FET. This increase in capacitance occurs while
Power Dissipation the power MOSFET is in the linear region and is dissipating
The power dissipation of the ICL7667 has three main significant amounts of power. The very high current output of
components: the ICL7667 is able to rapidly overcome this high
capacitance and quickly turns the MOSFET fully on or off.
5. Input inverter current loss
6. Output stage crossover current loss
3-5
ICL7667
15V
+165VDC
IRF730
+VC +V
SG1527 ICL7667
IRF730
B
GND -V
FIGURE 10A.
15V
+165VDC
IRF730
+VC 1K +V
VOUT
C1
E1
TL494 ICL7667
IRF730
C2
E2
GND 1K -V
+15V
FIGURE 10B.
FIGURE 10. DIRECT DRIVE OF MOSFET GATES
3-6
ICL7667
18V
CA CB VIN +V
1µF +165V
IRF730
EA
470 0V
CA1524 ICL7667
IRF730
1µF
EB
470 -165V
-V VOUT
0.1µF 0.1µF
4.7µF
IN914
+ D1
4.7µF
R1
10k
Q2 1000pF
C1
1/2 2200pF FF10 IRFF120
ICL7667
0V - 5V 5FF10
INPUT
FROM
PWM IC
1/2 ZL
ICL7667
IRFF120
Q1
-4
f = 10kHz
-6
-8
SLOPE = 60Ω
VOUT (V)
-10
+15V
-12
3-7
ICL7667
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