COURSE TITLE : MICROCONTROLLER AND INTERFACING

COURSE CODE :4214

MODULE I INTRODUCTION TO 8051 MICROCONTROLLER

1.1.0 To know the difference between microprocessor and micro controller.

1.1.1 To compare microprocessors and microcontrollers.
1.1.2 To list the various microcontroller manufacturers.
1.2.0 To comprehend the architecture of microprocessor 8085.
1.2.1 To describe the features of 8085.
1.2.2 To explain the internal block diagram of 8085.
1.2.3 To explain registers of 8085.
1.3.0 To comprehend the architecture of microcontroller 8051.
1.3.1 To describe the features of 8051.
1.3.2 To explain the programming model of microcontroller 8051.
1.3.3 To illustrate register structure of 8051.
1.3.4 To explain special function registers of 8051.
1.3.5 To describe internal memory map of 8051
1.3.6 To illustrate the ports of 8051
1.3.7 To explain timer mode of operation
1.3.8 To explain interrupts in 8051

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1.3.9 To describe the stack in 8051
1.3.10 To describe the power saving modes of operation
1.4.0 To understand the pin details of 8051
1.4.1 To list the I/O pins
1.4.2 To explain the dual functions of I/O pins
1.4.3 To describe other various pin details
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8085 MICROPROCESSOR ARCHITECTURE

The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5 V for power. It
can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and address bus width is 16-bit, thus it
can address 2 16 = 64 KB of memory. The internal architecture of 8085 is shown.

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Arithmetic and Logic Unit

The ALU performs the actual numerical and logical operations such as Addition (ADD), Subtraction (SUB),
AND, OR etc. It uses data from memory and from Accumulator to perform operations. The results of the
arithmetic and logical operations are stored in the accumulator.

Registers

The 8085 includes six registers, one accumulator and one flag register, as shown in above figure. In addition,
it has two 16-bit registers: stack pointer and program counter. They are briefly described as follows. The
8085 has six general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H and L. they
can be combined as register pairs - BC, DE and HL to perform some16-bit operations. The programmer can
use these registers to store or copy data into the register by using data copy instructions.
Accumulator

The accumulator is an 8-bit register that is a part of ALU. This register is used to store 8-bit data and to
perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The

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accumulator is also identified as register A.

Flag register

The ALU includes five flip-flops, which are set or reset after an operation according to data condition of the
result in the accumulator and other registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P) and
Auxiliary Carry (AC) flags. Their bit positions in the flag register are shown in Figure below. The
microprocessor uses these flags to test data conditions.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer.
The microprocessor uses this register to sequence the execution of the instructions. The function of the
program counter is to point to the memory address from which the next byte is to be fetched. When a byte is
being fetched, the program counter is automatically incremented by one to point to the next memory
location.
Stack Pointer (SP)

The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory location in R/W
memory, called stack. The beginning of the stack is defined by loading 16- bit address in the stack pointer.

Instruction Register/Decoder

It is an 8-bit register that temporarily stores the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction.
Decoded instruction then passed to next stage.

Control Unit

Generates signals on data bus, address bus and control bus within microprocessor to carry out the instruction,
which has been decoded.

Features of 8085

• 8085 is 8 bit microprocessor

• 16 bit address bus ( Can address up to 64KB)
• 8 bit data bus
• 16 bit stack pointer
• 16 bit program counter
• Six 8-bit general purpose registers.

Various Microcontroller manufacturers : Texas Instruments , Microchip company, Silicon labs, Intel
corporation, Dallas Semiconductor etc.

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 THE 8051 ARCHITECTURE

Programming model of 8051

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8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the program size is more
than 4 K Bytes 8051 will fetch the code automatically from external memory.

Accumulator is an 8 bit register widely used for all arithmetic and logical operations. Accumulator is also
used to transfer data between external memory. B register is used along with Accumulator for multiplication
and division. A and B registers together is also called MATH registers.
Salient features of 8051 microcontroller are given below.

• Eight bit CPU

• On chip clock oscillator
• 16-bit Program Counter
• 8-bit Processor Status Word (PSW)
• 8-bit Stack Pointer

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• Internal RAM of 128bytes
• Special Function Registers (SFRs) of 128 bytes
• 32 I/O pins arranged as four 8-bit ports (P0 - P3)
• Two 16-bit timer/counters : T0 and T1
• Two external and three inter

8051 - PIN DIAGRAM

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STACK

A stack is a last in first out memory. In 8051 internal RAM space can be used as stack. The address
of the stack is contained in a register called stack pointer. Instructions PUSH and POP are used for stack
operations. When a data is to be placed on the stack, the stack pointer increments before storing the data on
the stack so that the stack grows up as data is stored (pre-increment). As the data is retrieved from the stack
the byte is read from the stack, and then SP decrements to point the next available byte of stored data (post
decrement). The stack pointer is set to 07 when the 8051 resets. So that default stack memory starts from
address location 08 onwards (to avoid overwriting the default register bank ie., bank 0).

Internal memory map of 8051

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Register Banks:

00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5, R6,
and R7). There are four such register banks. Selection of register bank can be done through RS1,RS0 bits of
PSW. On reset, the default Register Bank 0 will be selected.

Bit Addressable RAM:

20h to 2Fh . The 8051 supports a special feature which allows access to bit variables. This is where
individual memory bits in Internal RAM can be set or cleared. In all there are 128 bits numbered 00h to 7Fh.
General Purpose RAM:

30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for general-purpose data
storage, user should take care while using the memory location from 00 -2Fh since these locations are also
the default register space, stack space, and bit addressable space.

SFR Map

The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B,
I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control
registers. Some of these registers are bit addressable (they are marked with a * in the diagram below). The
detailed map of various registers is shown in the following figure.

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TIMERS AND COUNTERS

Timers/Counters are used generally for

• Time reference
• Creating delay
• Wave form properties measurement
• Periodic interrupt generation
• Waveform generation
8051 has two timers, Timer 0 and Timer 1.

Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up irrespective of
whether it is used as timer, counter, or baud rate generator: Timer is always incremented by the
microcontroller. The time taken to count one digit up is based on master clock frequency.

If Master CLK=12 MHz,

Timer Clock frequency = Master CLK/12 = 1 MHz
Timer Clock Period = 1micro second
This indicates that one increment in count will take 1 micro second.

The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer
also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

TMOD Register (Timer Mode)

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This register has two identical halves, the upper four bits for timer 1 and the lower four bits for timer 0. The
bits M1 and M0 set the TMOD:

MODE 0 : TH and TL come together to form a 13-bit register where TH has 5 bits. This makes the
microcontroller compatible with an earlier device.

MODE 1 : TH and TL come together to form a 16-bit register.

MODE 2 : TL is the working 8-bit register and TH is the automatic reload register. This mode is used to
define the baud rate of the serial UART interface.

MODE 3 : TH and TL registers of both timers combine to produce three 8-bit timers.
8051 INTERRUPT STRUCTURE:

8051 has five interrupts. They are maskable and vectored interrupts. Out of these five, two are
external interrupt and three are internal interrupts.

Classification of interrupts.

1. External and internal interrupts.

External interrupts are those initiated by peripheral devices through the external pins of the microcontroller.
Internal interrupts are those activated by the internal peripherals of the microcontroller like timers, serial
controller etc.)

2. Maskable and non-maskable interrupts.

The category of interrupts which can be disabled by the processor using program is called maskable
interrupts. Non-maskable interrupts are those category by which the programmer cannot disable it using
program.

3. Vectored and non-vectored interrupt.

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Starting address of the ISR is called interrupt vector. In vectored interrupts the starting address is predefined.
In non-vectored interrupts, the starting address is provided by the peripheral as follows.
• Microcontroller receives an interrupt request from external device.
• Controller sends an acknowledgement (INTA) after completing the execution of current instruction.
• The peripheral device sends the interrupt vector to the microcontroller.

Power saving modes of operation :

8051 has two power saving modes. They are -

1. Idle Mode
2. Power Down mode.

The two power saving modes are entered by setting two bits IDL and PD in the special function register
(PCON) respectively.

Idle mode is entered by setting IDL bit to 1. The clock signal is gated off to CPU, but not to the interrupt,
timer and serial port functions. The CPU status is preserved entirely. SP, PC, PSW, Accumulator and other
registers maintain their data during IDLE mode.

The Power down Mode is entered by setting the PD bit to 1. The internal clock to the entire microcontroller
is stopped (frozen). However, the program is not dead. The Power down Mode is exited (PCON.1 is cleared
to 0) by Hardware Reset only.
MODULE II ASSEMBLY LANGUAGE PROGRAMMING

2.1 .0 To comprehend the instruction set of 8051

2.1.1 To explain the addressing modes
2.1.2 To classify the instructions
2.1.3 To explain the arithmetic ,logic instuctions
2.1.4 To illustrate the Rotate instructions
2.1.5 To describe Jump and call instructions
2.2.0 To understand timing -subroutines
2.2.1 To describe the working of subroutines
2.2.2 To explain the working of timing subroutine
2.2.3 To list the applications of timing subroutine
2.3.0 To comprehend the look-up tables
2.3.1 To explain the applications of look –up tables
2.3.2 To state the need of look –up tables in the program
2.3.3 To illustrate the creation of Look –up table
2.4.0 To understand the serial data communication
2.4.1 To explain the modes of serial data communication
2.4.2 To describe the serial data transmission
2.4.3 To explain the serial data reception
2.5.0 To know the programming of 8051
2.5.1 To familirise the assembly langaguage programming
2.5.2 To explain the programmes like largest in array,sorting,Code etc

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INSTRUCTION SET OF 8051:

The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions

Data transfer instructions :- In this group, the instructions perform data transfer operations

Arithmetic instructions :- The 8051 can perform addition, subtraction. Multiplication and division operations
on 8 bit numbers.

Logical Instructions :- In this group, the instructions perform logical operations like, AND, OR, EXOR,
rotate instructions etc

Branch (JUMP) Instructions :- Jump and Call Program Range

There are 3 types of jump instructions. They are:-
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Subroutine CALL And RETURN Instructions :- Subroutines are handled by CALL and RET instructions
There are two types of CALL instructions. 1. LCALL address(16 bit) 2. ACALL address (11 bit).

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Bit manipulation instructions:- 8051 has 128 bit addressable memory. Bit addressable SFRs and bit
addressable PORT pins. It is possible to perform bit wise operations for these bit addressable locations.

ADDRESSING MODES

Various methods of accessing the data are called addressing modes.

8051 addressing modes are classified as follows.

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.

1. Immediate addressing.

In this addressing mode the data is provided as a part of instruction itself. In other words
data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.

In this addressing mode the register will hold the data. One of the eight general registers (R0 to R7) can be
used and specified as the operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank. The default register bank will be bank 0.

3. Direct addressing

There are two ways to access the internal memory. Using direct address and indirect address. Using direct
addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8 bit
internal data memory address is specified as part of the instruction and hence, it can specify the address only
in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h

4. Indirect addressing

The indirect addressing mode uses a register to hold the actual address that will be used in data movement.
Registers R0 and R1 and DPTR are the only registers that can be used as data pointers. Indirect addressing
cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and DPTR can hold 16 bit
address.
Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR

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5. Indexed addressing.

In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used to hold the base
address, and the A is used to hold the offset address. Adding the value of the base address to the value of the
offset address forms the effective address. Indexed addressing is used with JMP or MOVC instructions. Look
up tables are easily implemented with the help of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing.

Relative addressing is used only with conditional jump instructions. The relative address, (offset), is an 8 bit
signed number, which is automatically added to the PC to make the address of the next instruction. The 8 bit
signed offset value gives an address range of +127 to —128 locations. The jump destination is usually
specified using a label and the assembler calculates the jump offset accordingly. The advantage of relative
addressing is that the program code is easy to relocate and the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute addressing

Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call) instructions.
These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11 bit of the memory
address as part of the instruction. The upper 5 bit of the destination address are the upper 5 bit of the current
program counter. Hence, absolute addressing allows branching only within the current 2 Kbyte page of the
program memory.
Eg. AJMP LOOP1
ACALL LOOP2

8. Long Addressing

The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte instructions.
The address specifies a full 16 bit destination address so that a jump or a call can be made to a location
within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY

9. Bit Inherent Addressing

In this addressing, the address of the flag which contains the operand, is implied in the opcode
of the instruction.
Eg. CLR C ; Clears the carry flag to 0

10. Bit Direct Addressing

In this addressing mode the direct address of the bit is specified in the instruction. The RAM space 20H to
2FH and most of the special function registers are bit addressable. Bit address values are between 00H to
7FH.
Eg. CLR 07h ; Clears the bit 7 of 20h RAM space
SETB 07H ; Sets the bit 7 of 20H RAM space.

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Subroutines
A subroutine is a program that may be used many times in the execution of a larger program.
Subroutines are handled by CALL and RET instructions

There are two types of CALL instructions

1. LCALL address(16 bit)

This is long call instruction which unconditionally calls the subroutine located at the indicated 16 bit
address. This is a 3 byte instruction. The LCALL instruction works as follows.

a. During execution of LCALL, [PC] = [PC]+3; (if address where LCALL resides is say, 0x3254; during
execution of this instruction [PC] = 3254h + 3h = 3257h
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08
c. [[SP]] = [PC 7 - 0 ]; (lower byte of PC content ie., 57 will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC 15 - 8 ]; (higher byte of PC content ie., 32 will be stored in memory location 09. With these
the address (0x3254) which was in PC is stored in stack.
f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No flags are affected.

2. ACALL address(11 bit)

This is absolute call instruction which unconditionally calls the subroutine located at the indicated 11
bit address. This is a 2 byte instruction. The ACALL instruction works as follows.

a. During execution of ACALL, [PC] = [PC]+2; (if address where ACALL resides is say, 0x8549; during
execution of this instruction [PC] = 8549h + 2h = 854Bh
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08

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c. [[SP]] = [PC 7 - 0 ]; (lower byte of PC content ie., 4B will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC 15 - 8 ]; (higher byte of PC content ie., 85 will be stored in memory location 09. With these
the address (0x854B) which was in PC is stored in stack.
f. [PC 10-0 ]= address (11 bit); the new address of subroutine is loaded to PC. No flags are affected.

RET instruction

RET instruction pops top two contents from the stack and load it to PC.

g. [PC 15-8 ] = [[SP]] ;content of current top of the stack will be moved to higher byte of PC.
h. [SP]=[SP]-1; (SP decrements)
i. [PC 7-0 ] = [[SP]] ;content of bottom of the stack will be moved to lower byte of PC.
j. [SP]=[SP]-1; (SP decrements again)

Delay program using 8051 timers

While designing delay programs in 8051, calculating the initial value that has to be loaded inot TH
and TL registers forms a very important thing.

• Assume the processor is clocked by a 12MHz crystal.

• That means, the timer clock input will be 12MHz/12 = 1MHz
• That means, the time taken for the timer to make one increment = 1/1MHz = 1uS
• For a time delay of “X” uS the timer has to make “X” increments.
• 2^16 = 65536 is the maximim number of counts possible for a 16 bit timer.
 • Let TH be the value value that has to be loaded to TH registed and TL be the value that has to be
• loaded to TL register. Then, THTL = Hexadecimal equivalent of (65536-X) where (65536-X) is
considered in decimal.

Example.

Let the required delay be 1000uS (ie; 1mS).

That means X = 100065536 – X = 65536 – 1000 = 64536.
64536 is considered in decimal and converting it t0 hexadecimal gives FC18
That means THTL = FC18
Therefore TH=FC and TL=18

Program for generating 1mS delay using 8051 timer.

The program shown below can be used for generating 1mS delay and it is written as a subroutine so that you
can call it anywhere in the program. Also you can put this in a loop for creating longer time delays (multiples
of 1mS). Here Timer 0 of 8051 is used and it is operating in MODE1 (16 bit timer).

DELAY: MOV TMOD,#00000001B // Sets Timer 0 to MODE1 (16 bit timer). Timer 1 is not used
MOV TH0,#0FCH // Loads TH0 register with FCH
MOV TL0,#018H // Loads TL0 register with 18H
SETB TR0 // Starts the Timer 0
HERE: JNB TF0,HERE // Loops here until TF0 is set (ie;until roll over)
CLR TR0 // Stops Timer 0
CLR TF0 // Clears TF0 flag
RET

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Look-Up Tables

• A look-up table is a table of constants stored in program memory

– Look-up tables can be used to speed up arithmetic operations
– The look-up table may be accessed using the DPTR or PC as a pointer to the start of the
table. The A register is used as an index to the table.
MOVC A, @A+DPTR
MOVC A, @A+PC
– The look-up table is defined using the DB directive
ORG 200H
DB 1,2,4,9
– This code will create a look-up table at address 200H. The value 1 will be stored at
address 200H, 2 at address 201H etc
– Ensure that the look-up table does not overlap with the address space used by code.

Example :

• Write a program to read an 8-bit temperature in Celsius from Port 1 and to output the
Farenheight temperature equivalent onto Port 2

F = ((C * 9)/5) + 32
TABLE EQU 100H
ORG 0
MAIN: MOV DPTR, #TABLE
LOOP: MOV A, P1
MOVC A, @A+DPTR
MOV P2, A
JMP LOOP ;conversion look-up table for 0 to 40 degrees Celsius

ORG TABLE
DB 32,34,36,37,39,41,43,45,46,48,50,52,54,55,57,59,61,63,64,66
DB 70,72,72,75,77,79,81,82,84,86,88,90,91,93,95,97,99,100,102,104
END

SERIAL COMMUNICATION MODES

1. Mode 0

In this mode serial port runs in synchronous mode. The data is transmitted and received through RXD pin
and TXD is used for clock output. In this mode the baud rate is 1/12 of clock frequency.

2. Mode 1

In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8 data bit and 1 stop
bit. The interrupt flag TI/RI will be set once transmission or reception is over. In this mode the baud rate is
variable and is determined by the timer 1 overflow rate.

Baud rate = [2 smod /32] x Timer 1 overflow Rate

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= [2 smod /32] x [Oscillator Clock Frequency] / [12 x [256 – [TH1]]]

3. Mode 2

This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start bit, 8 data bit, a
programmable 9 th data bit, 1 stop bit.

Baud rate = [2 smod /64] x Oscillator Clock Frequency

4. Mode 3

This is similar to mode 2 except baud rate is calculated as in mode 1

Serial Port Control Register (SCON)

Register SCON controls serial data communication. Address: 098H (Bit addressable)
Register PCON controls processor power down, sleep modes and serial data bandrate.
Only one bit of PCON is used with respect to serial communication. The seventh bit (b7)(SMOD) is used to
generate the baud rate of serial communication.

Data Transmission

Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit
TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This
signifies that SBUF is empty so that another byte can be sent.

Data Reception

Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function
bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data
has been received in all modes. The data gets stored in SBUF register from where it can be read.

Serial Data Transmission Modes:

Mode-0: In this mode, the serial port works like a shift register and the data transmission works
synchronously with a clock frequency of f osc /12. Serial data is received and transmitted through RXD.
8 bits are transmitted/ received aty a time. Pin TXD outputs the shift clock pulses of frequency f osc /12,
which is connected to the external circuitry for synchronization. The shift frequency or baud rate is always
1/12 of the oscillator frequency.

Mode-1 (standard UART mode) : In mode-1, the serial port functions as a standard Universal Asynchronous
Receiver Transmitter (UART) mode. 10 bits are transmitted through TXD or received through RXD. The 10
bits consist of one start bit (which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit
(which is usually '1'). Once received, the stop bit goes into RB8 in the special function register SCON. The

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baud rate is variable.

Mode-2 - Multiprocessor Mode : In this mode 11 bits are transmitted through TXD or received through
RXD. The various bits are as follows: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9 th
(TB8 or RB8)bit and a stop bit (usually '1'). While transmitting, the 9 th data bit (TB8 in SCON) can be
assigned the value '0' or '1'. For example, if the information of parity is to be transmitted, the parity bit (P) in
PSW could be moved into TB8. On reception of the data, the 9 th bit goes into RB8 in 'SCON', while the
stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency.

Mode-3 - Multi processor mode with variable baud rate : In this mode 11 bits are transmitted through
TXD or received through RXD. The various bits are: a start bit (usually '0'), 8 data bits (LSB first), a
programmable 9 th bit and a stop bit (usually '1'). Mode-3 is same as mode-2, except the fact that the baud
rate in mode-3 is variable (i.e., just as in mode-1). f baud = (2 SMOD /32) * ( f osc / 12 (256-TH1)) .
This baudrate holds when Timer-1 is programmed in Mode-2.
ASSEMBLY LANGUAGE PROGRAM TO FIND LARGEST NUMBER IN AN ARRAY

1. ALP for finding largest in an array.

2. ALP for arranging numbers in ascending order.

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MODULE III - INTERFACING ICS

3.1.0 To understand architecture of 8255

3.1.1 To describe the architecture of 8255
3.1.2 To list the pins of 8255
3.1.3 To explain the control register of 8255
3.1.4 To explain the modes of 8255
3.1.5 To illustrate the ports of 8255
3.2.0 To comprehend architecture of 8251
3.2.1 To describe the architecture of 8251
3.2.2 To list the pins of 8251
3.2.3 To Explain the control register of 8251
3.3.0 To understand architecture of 8259
3.3.1 To describe the architecture of 8259
3.3.2 To list the pins of 8259
3.3.3 To explain the status register of 8259
3.4.0 To understand architecture of 8279
3.4.1 To describe the architecture of 8279
3.4.2 To list the pins of 8279
3.4.3 To explain the display section of 8279
3.4.4 To illustrate the keyboard section of 8279
3.4.5 To describe the key board debounce and control
3.4.6 To explain the Scan section of 8279

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8255: (Programmable Peripheral Interface)

The 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It
consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be configured to meet different system
I/O needs. The three ports are PORT A, PORT B & PORT C. Port A contains one 8-bit output latch/buffer
and one 8-bit input buffer. Port B is same as PORT A or PORT B. However, PORT C can be split into two
parts PORT C lower (PC 0 -PC 3 ) and PORT C upper (PC 7 -PC 4 ) by the control word. The three ports are
divided in two groups Group A (PORT A and upper PORT C) Group B (PORT B and lower PORT C). The
two groups can be programmed in three different modes. In the first mode (mode 0), each group may be
programmed in either input mode or output mode (PORT A, PORT B, PORT C lower, PORT C upper). In
mode 1 each group may be programmed to have 8-lines of input or output (PORT A or PORT B) of the
remaining 4-lines (PORT C lower or PORT C upper) 3-lines are used for hand shaking and interrupt control
signals. The third mode of operation (mode 2) is a bidirectional bus mode which uses 8-line (PORT A only
for a bidirectional bus and five lines (PORT C upper 4 lines and borrowing one from other group) for
handshaking.

Functional Description:
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This support chip is a general purpose I/O component to interface peripheral equipment to the
microcomputer system bus. It is programmed by the system software so that normally no external logic is
necessary to interface peripheral devices or structures.

Data Bus Buffer:

It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is transmitted or received by
the buffer upon execution of input or output instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
Read/Write and logic control:

The function of this block is to control the internal operation of the device and to control the transfer of data
and control or status words. It accepts inputs from the CPU address and control buses and in turn issues
command to both the control groups.

PORTs A, B and C:
The 8255A contains three 8-bit ports (A, B and C). All can be configured in a variety of functional

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characteristic by the system software.
PORTA: One 8-bit data output latch/buffer and one 8-bit data input latch.
PORT B: One 8-bit data output latch/buffer and one 8-bit data input buffer.
PORT C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can
be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be
used for the control signal outputs and status signals inputs in conjunction with ports A and B.

Group A & Group B control:

The functional configuration of each port is programmed by the system software. The control words
outputted by the CPU configure the associated ports of the each of the two groups. Each control block
accepts command from Read/Write content logic receives control words from the internal data bus and issues
proper commands to its associated ports.

Control Group A – Port A & Port C upper

Control Group B – Port B & Port C lower
The control word register can only be written into No read operation if the control word register is allowed.
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Mode selection:

There are three basic modes of operation that can be selected by the system software.

Mode 0: Basic Input/output

Mode 1: Strobes Input/output
Mode 2: Bi-direction bus.

When the reset input goes HIGH all poets are set to mode’0’ as input which means all 24 lines are
in high impedance state and can be used as normal input. After the reset is removed the 8255A remains in the
input mode with no additional initialization. During the execution of the program any of the other modes
may be selected using a single output instruction.
The modes for PORT A & PORT B can be separately defined, while PORT C is divided into two
portions as required by the PORT A and PORT B definitions. The ports are thus divided into two groups
Group A & Group B. All the output register, including the status flip-flop will be reset whenever the mode is
changed. Modes of the two group may be combined for any desired I/O operation e.g. Group A in mode ‘1’
and group B in mode ‘0’.
8251A-PROGRAMMABLE COMMUNICATION INTERFACE
(8251A-USART-Universal Synchronous/Asynchronous Receiver/Transmitter)

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A USART is also called a programmable communications interface (PCI).

The Intel 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter

(USART), designed for data communications with Intel microprocessor families such as 8080, 85, 86, 88 and
microcontroller 8051. The 8251A converts the parallel data received from the processor on the D7-0 data
pins into serial data, and transmits it on TxD (transmit data) output pin of 8251A. Similarly, it converts the
serial data received on RxD (receive data) input into parallel data, and the processor reads it using the data
pins D7-0.

The 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data
communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the
CPU and transmits serial data after conversion. This device also receives serial data from the outside and
transmits parallel data to the CPU after conversion. The internal block diagram of 8251A is shown in fig
below.

Data Bus Buffer: This bidirectional, 8-bit buffer used to interface the 8251A to the system data bus and also
used to read or write status, command word or data from or to the 8251A.

Read/Write control logic: The Read/Write Control logic interfaces the 8251A with microprocessor,
determines the functions of the 8251A according to the control word written into its control register and
monitors the data flow.
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Transmitter section: The transmitter section accepts parallel data from microprocessor and converts them
into serial data. The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel
data and another register called output register to convert the parallel data into serial bits. When output
register is empty, the data is transferred from buffer to output register.

Receiver Section: The receiver section accepts serial data and converts them into parallel data. The receiver
section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a
buffer register to hold the parallel data. When the RxD line goes low, the control logic assumes it as a
START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register
accepts the following bits, forms a character and loads it into the buffer register. The microprocessor reads
the parallel data from the buffer register.

MODEM Control: The MODEM control unit allows to interface a MODEM to 8251A and to establish data
communication through MODEM over telephone lines. This unit takes care of handshake signals for
MODEM interface.
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D0 to D7 (l/O terminal): This is bidirectional data bus which receives control words and transmits data from
the CPU and sends status words and received data to CPU.

RESET (Input terminal): A "High" on this input forces the 8251 into "reset status." The device waits for
the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of
CLK.

CLK (Input terminal): CLK signal is used to generate internal device timing. CLK signal is independent of
RXC or TXC.

WR (Input terminal): This is the "active low" input terminal which receives a signal for writing transmit
data and control words from the CPU into the 8251.

RD (Input terminal): This is the "active low" input terminal which receives a signal for reading receive
data and status words from the 8251.

C/ D (Input terminal): This is an input terminal which receives a signal for selecting data or command
words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D =
high, command word or status word will be accessed.

CS (Input terminal): This is the "active low" input terminal which selects the 8251 at low level when the
CPU accesses. Note: The device won‘t be in "standby status"; only setting CS = High.

TXD (output terminal): This is an output terminal for transmitting data from which serial- converted data is
sent out. The device is in "mark status" (high level) after resetting or during a status when transmit is
disabled. It is also possible to set the device in "break status" (low level) by a command.
TXRDY (output terminal): This is an output terminal which indicates that the 8251is ready to accept a
transmitted data character. But the terminal is always at low level if CTS = high or the device was set in "TX
disable status" by a command. Note: TXRDY status word indicates that transmit data character is receivable,
regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge
or WR signal.

TXEMPTY (Output terminal): This is an output terminal which indicates that the 8251 has transmitted all
the characters and had no data character. In "synchronous mode," the terminal is at high level, if transmit
data characters are no longer remaining and sync characters are automatically transmitted. If the CPU writes
a data character, TXEMPTY will be reset by the leading edge of WR signal.

TXC (Input terminal): This is a clock input signal which determines the transfer speed of transmitted data.
In "synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it
is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling
edge of TXC sifts the serial data out of the 8251.

RXD (input terminal): This is a terminal which receives serial data. RXRDY (Output terminal): This is a
terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU reads a data
character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character
before the next one is received completely, the preceding data will be lost. In such a case, an overrun error
flag status word will be set.

RXC (Input terminal): This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is
possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal): This is a terminal whose function changes according to mode. In
"internal synchronous mode." this terminal is at high level, if sync characters are received and synchronized.
If a status word is read, the terminal will be reset. In "external synchronous mode, "this is an input terminal.

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A "High" on this input forces the 8251 to start receiving data characters.

In "asynchronous mode," this is an output terminal which generates "high level ―output upon the detection
of a "break" character if receiver data contains a "low-level" space between the stop bits of two continuous
characters. The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be
output at low level.

DSR (Input terminal)"active low": This is an input port for MODEM interface. The input status of the
terminal can be recognized by the CPU reading status words.

DTR (Output terminal)"active low": This is an output port for MODEM interface. It is possible to set the
status of DTR by a command.

CTS (Input terminal)"active low": This is an input terminal for MODEM interface which is used for
controlling a transmit circuit. The terminal controls data transmission if the device is set in "TX Enable"
status by a command. Data is transmittable if the terminal is at low level.

RTS (Output terminal)"active low": This is an output port for MODEM interface. It is possible to set the
status RTS by a command.
Prior to starting a data transmission or reception, the 8251A must be loaded with a set of control words
generated by the microprocessor. These control signals define the complete functional definition of the
8251A and must immediately follow a reset operation (internal or external). The control words are split into
two formats.

1. Mode instruction 2. Command instruction

Mode instruction is used for setting the function of the 8251A. Mode instruction will be in "wait for write" at
either internal reset or external reset. That is, the writing of a control word after resetting will be recognized
as a "mode instruction."

Fig. Mode instruction format, Asynchronous mode

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Command Instruction: Command is used for setting the operation of the 8251. It is possible to
write a command whenever necessary after writing a mode instruction and sync characters.

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8259A Programmable Interrupt Controller

Intel 8259A Programmable Interrupt Controller is a circuit which controls interrupt handling.

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Data bus buffer:

This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control words
and status information from the microprocessor to PIC and from PIC to microprocessor respectively, are
transferred through the data bus buffer.

Read/Write & Control Logic:

The function of this block is to accept output commands sent from the CPU. It contains the initialization
command word (ICW) registers and operation command word (OCW) registers which store the various
control formats for device operation. This function block also allows the status of 8259A to be transferred
to the data bus.

Interrupt Request Register (IRR):

Interrupt request register (IRR) stores all the interrupt inputs that are requesting service. It is an 8-bit register
– one bit for each interrupt request. Basically, it keeps track of which interrupt inputs are asking for service.
If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will
be set. The content of this register can be read to know the status of pending interrupts.

Interrupt Mask Register (IMR):

The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-
bit register. Each bit in this register corresponds to the interrupt input with the same number. The IMR
operates on the IRR. Masking of higher priority input will not affect the interrupt request lines of lower
priority. To unmask any interrupt the corresponding bit is set ‘0’.
In-service Register (ISR):
The in-service register keeps track of which interrupt inputs are currently being serviced. For each input that
is currently being serviced the corresponding bit of in-service register (ISR) will be set. In 8259A, during the
service of an interrupt request, if another higher priority interrupt becomes active, it will be acknowledged
and the control will be transferred from lower priority interrupt service subroutine (ISS) to higher priority
ISS. Thus, more than one bit of ISR will be set indicating the number of interrupts being serviced. Each of
these 3-registers can be read as status register.

Priority Resolver:

This logic block determines the priorities of the interrupts set in the IRR. It takes the information from IRR,
IMR and ISR to determine whether the new interrupt request is having highest priority or not. If the new
interrupt request is having the highest priority, it is selected and processed. The corresponding bit of ISR will
be set during interrupt acknowledge machine cycle.

Cascade Buffer/Comparator:

This function block stores and compares the IDs of all 8259A’s in the system. The associated 3-I/O lines
(CAS 2 -CAS 0 ) are outputs when 8259A is used as a master and are inputs when 8259A is used as a slave.
As a master, the 8259A sends the ID of the interrupting slave device onto the CAS 2-0 lines. The slave
8259As compare this ID with their own programmed ID. Thus selected 8259A will send its pre-programmed
subroutine address on to the data bus during the next one or two successive INTA pulses.

PIN Diagram – 8259 A

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The pin diagram and internal block diagram of PIC is shown in figure. The pins are defined as follows:
CS (Chip Select signal): To access this chip, chip select signal CS is made low. A LOW on this pin enables
RD & WR communication between the CPU and the 8259A. This signal is made LOW by decoding the
addresses assigned to this chip. Therefore, this pin is connected to address bus through the decoder logic
circuit. Interrupt acknowledge functions to transfer the control to interrupt service subroutine are
independent of CS .

WR (Write signal): A low on this pin. When CS is low enables the 8259 A to accept command words from
CPU.

RD (Read signal): A low on this pin when CS is low enables this 8259A to release status (pending interrupts
or in-service interrupts or masked interrupts) on to the data bus for the CPU. The status includes the contents
of IMR (interrupt mask register) or ISR (interrupt service register) or IRR (interrupt request register) or a
priority level.

D 7 -D 0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information is transferred
via this data bus. This bus is connected to BDB of 8085A.

CAS 2 -CAS 0 (Cascade lines): The CAS 2-0 lines form a local 8259A bus to control multiple 8259As in
master-slave configuration, i.e., to identify a particular slave 8259A to be accessed for transfer of vector
information. These pins are automatically set as output pins for master 8259A and input pins for a slave
8259A once the chips are programmed as master or slave.

SP / EN (Salve Program/Enable Buffer): This is a dual function pin. When the chip is programmed in
buffered mode, the pin can be used as an output and when not in the buffered mode it is used as an input. In
non-buffered mode it is used as an input pin to determine whether the 8259A is to be used as a master ( SP /
EN = 1) or as a slave (SP / EN = 0). In buffered mode, normally data bus buffers are used. These buffers
need to be enabled or disabled during transfer of vector information depending upon whether 80259A is
connected before the buffer or after the buffer. To disable/enable the data bus transceivers (buffers) when
data are being transferred from the 8259A to the CPU, this pin is made low or high.

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INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It is used to
interrupt the CPU, thus it is connected to the CPU’s interrupt pin (INTR). In case of master-
slaveconfiguration, the interrupt pin of slave 8259A is connected to interrupt request input of master 8259A.

INTA (Interrupt Acknowledge): This pin is used to enable 8259A interrupt vector data on the data bus by a
sequence of interrupt acknowledge pulses issued by the CPU.

IR 0 -IR 7 (Interrupt Request inputs): These are asynchronous interrupt request input pins. An interrupt
request is executed by raising an IR input (low to high), and holding it high until it is acknowledged. (Edge
triggered mode) or just by a high level on an interrupt request input (Level triggered mode).

A 0 (A 0 address line): This pin acts in conjunction with the RD , WR & CS pins. It is used by the 8259A to
send various command words from the CPU and to read the status. It is normally connected to the CPU A 0
address line. Two addresses are assigned/ reserved in the I/O address space for each 8259A in the system-
one with A 0 =0 is called even address and other with A 0 = 1 is called odd address.
8279 Display and Keyboard Controller

The keyboard display controller chip 8279 provides: a set of four scan lines and eight return lines for

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interfacing keyboards and a set of eight output lines for interfacing display.

I/O Control and Data Buffers : The I/O control section controls the flow of data to/from the 8279. The data
buffers interface the external bus of the system with internal bus of 8279. The I/O section is enabled only if
CS is low. The pins A 0 , RD and WR select the command, status or data read/write operations carried out by
the CPU with 8279.

Control and Timing Register and Timing Control : These registers store the keyboard and display modes and
other operating conditions programmed by CPU. The registers are written with A 0 =1 and WR=0. The
Timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down
the operating frequency of 8279 to derive scan keyboard and scan display frequencies.

Scan Counter : The scan counter has two modes to scan the key matrix and refresh the display. In the
encoded mode, the counter provides binary count that is to be externally decoded to provide the scan lines
for keyboard and display (Four externally decoded scan lines may drive up to 16 displays). In the decode
scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan
on SL 0 -SL 3 ( Four internally decoded scan lines may drive upto 4 displays). The keyboard and display
both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control: This section for a key closure row wise. If a key closer
is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce
period, if the key continues to be detected. The code of key is directly transferred to the sensor RAM along
with SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic: In keyboard or strobed input mode, this block acts as 8-byte first-in-
first-out (FIFO) RAM. Each key code of the pressed key is entered in the order of the entry and in the mean
time read by the CPU, till the RAM become empty. The status logic generates an interrupt after each FIFO
read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM. Each
row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a
sensor changes its state, the IRQ line goes high to interrupt the CPU.

Display Address Registers and Display RAM : The display address register holds the address of the word
currently being written or read by the CPU to or from the display RAM. The contents of the registers are
automatically updated by 8279 to accept the next data entry by CPU.

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• DB 0 -DB 7 : These are bidirectional data bus lines. The data and command words to and from the CPU are
transferred on these lines.

• CLK : This is a clock input used to generate internal timing required by 8279.

• RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in sixteen 8-
bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31

.• CS : Chip Select – A low on this line enables 8279 for normal read or write operations. Other wise, this pin
should remain high.

• A 0 : A high on this line indicates the transfer of a command or status information. A low on this line
indicates the transfer of data. This is used to select one of the internal registers of 8279.

• RD, WR ( Input/Output ) READ/WRITE – These input pins enable the data buffers to receive or send data
over the data bus.

• IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt
lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key-code
entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.

• Vss, Vcc : These are the ground and power supply lines for the circuit.
• SL 0 -SL 3 -Scan Lines : These lines are used to scan the key board matrix and display digits. These lines
can be programmed as encoded or decoded, using the mode control register.

• RL 0 - RL 7 - Return Lines : These are the input lines which are connected to one terminal of keys, while
the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled
low when a key is pressed.

• SHIFT : The status of the shift input lines is stored along with each key code in FIFO, in scanned keyboard
mode. It is pulled up internally to keep it high, till it is pulled low with a key closure.

• BD – Blank Display : This output pin is used to blank the display during digit switching or by a blanking
closure.

• OUT A 0 – OUT A 3 and OUT B 0 – OUT B 3 – These are the output ports for two 16*4 or 16*8 internal
display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and
keyboard. The two 4-bit ports may also as one 8-bit port.

• CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as a control input and
stored in FIFO on a key closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed
input mode. It has an interrupt pull up. The lines is pulled down with a key closer.

The four major sections of 8279 are keyboard, scan, display and CPU interface.

Keyboard section:

• The keyboard section consists of eight return lines RL0 – RL7 that can be used to form the columns of a
keyboard matrix.

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• It has two additional input : shift and control/strobe. The keys are automatically debounced.

• The two operating modes of keyboard section are 2-key lockout and N-key rollover.

• In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

• In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.

• The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

• The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key
are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO.

• In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the
condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

Display section:

• The display section has eight output lines divided into two groups A0-A3 and B0-B3.

• The output lines can be used either as a single group of eight lines or as two groups of four lines, in
conjunction with the scan lines for a multiplexed display.

• The output lines are connected to the anodes through driver transistor in case of common cathode 7-
segment LEDs.

• The cathodes are connected to scan lines through driver transistors.

• The display can be blanked by BD (low) line.

• The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of
the display RAM.

Scan section:

• The scan section has a scan counter and four scan lines, SL0 to SL3.

• In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

• In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be
used to convert the binary count to decoded output.

• The scan lines are common for keyboard and display.

• The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a
multiplexed display, to turn ON/OFF.

CPU interface section:

• The CPU interface section takes care of data transfer between 8279 and the processor.

• This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU.

• It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of
8279.

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• The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

• It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

• The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock
by an internal prescaler.

• The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.
MODULE IV INTERFACING OF 8051

4.1.0 To know the applications of 8051 in display devices

4.1.1 To explain the pins of LCD display IC LM051
4.1.2 To explain the interfacing of LCD using time delay
4.1.3 To describe the commands in LCD
4.1.4 To illustrate the 7 segment display
4.1.5 To list the types of 7 segment display
4.1.6 To explain the interfacing of 7 segment display
4.2.0 To know the applications in A/D & D/A converters
4.2.1 To explain the pins of A/D converter IC ADC0804
4.2.2 To illustrate the interfacing of A/D converter
4.2.3 To describe the pins of D/A converter IC
4.2.4 To explain the interfacing of D/A converter
4.3.0 To understand the applications of 8051 in instrumentation.
4.3.1 To describe the interfacing of temperature IC LM 35.
4.4.0 To understand the applications in dc motors
4.4.1 To describe the interfacing of DC motor
4.5.0 To understand the applications in Stepper motors
4.5.1 To Define step angle
4.5.2 To Classification of stepper motor
4.5.3 To Describe the control circuits
4.5.4 To Describe the interfacing of stepper motors

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INTERFACING SEVEN SEGMENT DISPLAY TO 8051

A seven segment display consists of seven LEDs arranged in the form of a squarish’8′ slightly inclined to the
right and a single LED as the dot character. Different characters can be displayed by selectively glowing the
required LED segments. Seven segment displays are of two types, common cathode and common anode. In
common cathode type , the cathode of all LEDs are tied together to a single terminal which is usually
labeled as ‘com‘ and the anode of all LEDs are left alone as individual pins labeled as a, b, c, d, e, f, g & h
(or dot) . In common anode type, the anode of all LEDs are tied together as a single terminal and cathodes
are left alone as individual pins. The pin out scheme and picture of a typical 7 segment LED display is shown
in the image below.

Digit drive pattern of a seven segment LED display is simply the different logic combinations of its terminals
‘a’ to ‘h‘ in order to display different digits and characters. The common digit drive patterns (0 to 9) of a Sreejith KB
seven segment display are shown in the table below.
LCD Interfacing
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Interfacing of LCD using time delay

To send any of the commands to the LCD, make pin RS = 0. For data, make RS = 1. Then send a high-to-low
pulse to the E pin to enable the internal latch of the LCD.

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Interfacing ADC to 8051

ADC0804 is an 8 bit successive approximation analogue to digital converter from National semiconductors.
The features of ADC0804 are differential analogue voltage inputs, 0-5V input voltage range, no zero
adjustment, built in clock generator, reference voltage can be externally adjusted to convert smaller analogue
voltage span to 8 bit resolution etc.

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The voltage at Vref/2 (pin9) of ADC0804 can be externally adjusted to convert smaller input voltage spans to
full 8 bit resolution. Vref/2 (pin9) left open means input voltage span is 0-5V and step size is 5/255=19.6V.

Steps for converting the analogue input and reading the output from ADC0804.
• Make CS=0 and send a low to high pulse to WR pin to start the conversion.
• Now keep checking the INTR pin. INTR will be 1 if conversion is not finished and INTR will be 0 if
conversion is finished.
• If conversion is not finished (INTR=1) , poll until it is finished.
• If conversion is finished (INTR=0), go to the next step.
• Make CS=0 and send a high to low pulse to RD pin to read the data from the ADC.
The resolution of an A/D converter refers to the number of bits in the output binary word. An 8-bit converter
for example has a resolution of 1 part in 256.

Another important specification for an ADC is its conversion time. - the time it takes the converter to
produce a valid output binary code for an applied input voltage. When we refer to a converter as high speed,
it has a short conversion time.

For different Vref/2 voltages and corresponding analogue input voltage spans.

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DAC Interfacing with 8051
Digital to analog converters are used to convert digital quantity to analog quantity. They produce an output
current or voltage proportional to digital quantity apply to its input. They are used for the control of relay,
small motor, actuator etc. In communication system digital transmission is faster and convenient but the
digital signal have to be converted back to analog signal at the receiving terminal. D/A converter are also
used as a part of circuit tree of several A/D converter.

DAC contain a ladder network. The network has input prints for binary bits of the digital word. When MSB
of the digital word is 1 it produces an output current Iref/2. The bit next to MSB produces Iref/4 and so on.
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LM35 Temperature Sensor interfacing

The LM35 is a temperature sensor whose output voltage is linearly proportional to Celsius temperature. The
LM35 comes already calibrated hence requires no external calibration. It outputs 10mV for each degree of
Celsius temperature. LM35 sensor produces voltage corresponding to temperature. This voltage is converted
to digital (0 to 256) by ADC0804 and it is fed to 8051 microcontroller. 8051 microcontroller converts this
digital value into temperature in degree Celsius.

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Out put of the LM35 is connected to the +Vin (pin 6) of the ADC0804. Resistor R13 and preset R14 is used
to provide an external reference voltage of 1.28V to the Vref/2 pin ( pin 9) of the ADC0804 and with this
reference voltage, the step size of the ADC will be 10mV and span will be 0-1 V. This means that for a 10mV
input the digital out of ADC will be 1 (1 in decimal also), for 20mV it will be 10 (2 in decimal), for 30mV it
will be 11 (3 in decimal) and so on.

Digital out of the ADC (D0 to D7) are connected to P1 (P1.0 to P1.7) of the microcontroller. This is the line
through which the microcontroller accepts data from the ADC. The control pins CS, RD, WR and INTR are
connected to P3.7, P3.6, P3.5 and P3.4 of the microcontroller. This is the data path through which the
microcontroller sends chip select (CS), read (RD) write (WR) signals to the ADC and receives INTR signal
from the ADC.

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8051 doesn’t provide enough current to drive the coils so we need to use a current driver IC that is
ULN2003. ULN2003 is the array of seven NPN Darlington transistor pairs.
Some parameters of stepper motors:

• Step Angle -The step angle is the angle which the rotor moves when one pulse is applied as an input
of the stator. This parameter is used to determine the positioning of a stepper motor.

• Steps per Revolution -This is the number of step angles required for a complete revolution. So the
formula is 360° /Step Angle.

• Steps per Second -This parameter is used to measure a number of steps covered in each second.

• RPM -The RPM is the Revolution Per Minute. It measures the frequency of rotation. By this
parameter, we can measure the number of rotations in one minute.

Steps per Second = rpm x steps per revolution / 60

We are using Port P1 of 8051 for connecting the stepper motor. HereULN2003 is used. This is basically a
high voltage, high current Darlington transistor array. Each ULN2003 has seven NPN Darlington pairs. It
can provide high voltage output with common cathode clamp diodes for switching inductive loads.

The Unipolar stepper motor works in three modes.

Wave Drive Mode: In this mode, one coil is energized at a time. So all four coils are energized one
after another. This mode produces less torque than full step drive mode.

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The following table is showing the sequence of input states in different windings.

Full Drive Mode: In this mode, two coils are energized at the same time. This mode produces more torque.
Here the power consumption is also high

The following table is showing the sequence of input states in different windings.
Half Drive Mode: In this mode, one and two coils are energized alternately. At first, one coil is energized
then two coils are energized. This is basically a combination of wave and full drive mode. It increases the
angular rotation of the motor

The following table is showing the sequence of input states in different windings.

Types of Stepper Motor:

There are three main types of stepper motors, they are:
1. Permanent magnet stepper
2. Hybrid synchronous stepper
3. Variable reluctance stepper

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Permanent Magnet Stepper Motor: Permanent magnet motors use a permanent magnet (PM) in
the rotor and operate on the attraction or repulsion between the rotor PM and the stator
electromagnets.
Variable Reluctance Stepper Motor: Variable reluctance (VR) motors have a plain iron rotor and
operate based on the principle that minimum reluctance occurs with minimum gap, hence the rotor
points are attracted toward the stator magnet poles.
Hybrid Synchronous Stepper Motor: Hybrid stepper motors are named because they use a
combination of permanent magnet (PM) and variable reluctance (VR) techniques to achieve
maximum power in a small package size.

Applications:
1. Industrial Machines – Stepper motors are used in automotive gauges and machine tooling
automated production equipments.
2. Security – new surveillance products for the security industry.
3. Medical – Stepper motors are used inside medical scanners, samplers, and also found inside
digital dental photography, fluid pumps, respirators and blood analysis machinery.
4. Consumer Electronics – Stepper motors in cameras for automatic digital camera focus and
zoom functions.
And also have business machines applications, computer peripherals applications.
DC motor interfacing

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