austriamicrosystems AG

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D atas hee t

AS3992
UHF RFID Single Chip Reader EPC Class1 Gen2 Compatible
1 General Description 2 Key Features
The AS3992 UHF Reader chip is an integrated analog front-end and Supply voltage range 4.1V to 5.5V
provides protocol handling for ISO180006c/b 900MHz RFID reader Filters dedicated to 250kHz and 320kHz M4 and M8 DRM
systems. Equipped with multiple built-in programming options, the operation. Available RX modes:

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device is suitable for a wide range of UHF RFID applications.
- LF40kHz, 160kHz: FM0, M2, M4, M8
The AS3992 is pin to pin and firmware compatible with the previous - LF 250kHz, 320kHz, 640kHz: M4, M8
AS3990/91 IC's. It offers improved receive sensitivity to -86dB,

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ISO18000-6C (EPC Gen2) full protocol support
programmable Rx Dense Reader Mode (DRM) filters on chip and
pre-distortion. Fully scalable, the AS3992 is ideal for longer range ISO18000-6A,B compatibility in direct mode
and higher power applications. Programmable Dense Reader Mode filters on chip allowing a

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Offering DRM filtering on chip, combined with improved sensitivity true World Wide Shippable device
and pre-distortion allows the AS3992 to be the only true world wide Improved receive sensitivity to -86dBm
shippable IC. The reader configuration is achieved through setting
On chip pre-distortion meaning improved external PA efficiency

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control registers allowing fine tuning of different reader parameters.
The AS3992 complies with EPC Class 1 Generation 2 protocol (ISO Integrated low level transmission coding, Integrated low level

st
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18000-6C) and ISO 18000-6A/B (in direct mode).
Parallel or serial interface can be selected for communication
decoders
Integrated data framing, Integrated CRC checking
on A
between the host system (MCU) and the reader IC. When hardware Parallel 8-bit or serial 4-pin SPI interface to MCU using 24 bytes
coders and decoders are used for transmission and reception, data
nt
is transferred via 24 bytes FIFO register. In case of direct
FIFO

transmission or reception, coders and decoders are bypassed and Voltage range for communication to MCU between 1.8V and
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the host system can service the analog front end in real time. 5.5V

The transmitter generates 20dBm output power into 50Ω load and is Can be powered by USB with no need for step conversion from
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capable of ASK or PR-ASK modulation. The integrated supply 4.1V to 5.5V

voltage regulators ensure supply rejection of the complete reader Selectable clock output for MCU
system.
Integrated supply voltage regulator (20mA), which can be used
The transmission system comprises low level data coding. Automatic to supply MCU and other external circuitry
generation of FrameSync, Preamble, and CRC is supported.
Integrated supply voltage regulator for the RF output stage,
The receiver system allows AM and PM demodulation. The receiver providing rejection to supply noise
also comprises automatic gain control option (patent pending) and
selectable gain and signal bandwidth to cover a range of input link Internal power amplifier (20dBm) for short range applications
frequency and bit rate options. The signal strength of AM and PM Antenna driver using ASK or PR-ASK modulation
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modulation is measured and can be accessed in RSSI register. The

Adjustable ASK modulation index
receiver output is selectable between digitized sub-carrier signal and
any of integrated sub-carrier decoders. Selected decoders deliver bit AM & PM demodulation ensuring no “communication holes”
stream and data clock as outputs. with automatic I/Q selection
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The receiver system also comprises framing system. This system Selectable reception gain, Reception automatic gain control
performs the CRC check and organizes the data in bytes. Framed
AD converter for measuring TX power using external RF power
data is accessible to the host system through a 24 byte FIFO
detector
ch

register.
DA converter for controlling external power amplifier
To support external MCU and other circuitry a 3.3V regulated supply
and clock outputs are available. The regulated supply has 20mA Frequency hopping support
current capability.
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On-board VCO and PLL covering complete RFID frequency

The AS3992 is available in a 64-pin QFN (9mm x 9mm), ensuring range 840MHz to 960MHz
the smallest possible footprint.
Oscillator using 20MHz crystal
Power down, standby and active mode available

3 Applications
The device is an ideal solution for UHF RFID reader systems and
hand-held UHF RFID readers.

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AS3992
Datasheet - A p p l i c a t i o n s

Figure 1. AS3992 Block Diagram

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2xC
4xC

VDD_TXPAB

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VDD_5LFI

VDD_MIX
COMN_A
COMN_B
COMP_A
COMP_B

VEXT2
VEXT
CD1
CD2

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64 2 1 3 5 53 52 13 15 16 17 38 VDD_D
18 VDD_RF

Supply Regulators &

OAD 31
19 VDD_B

References
AS3992

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OAD_2 30 54 AGD
ADC 58 7xC
59 VDD_A

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DAC 4 63
61
VDDLF
VOSC
IQ Down- DRM Filter Gain Filter 34 VDD_RFP
on A
MIX_INP 7 Conversion Digitizer
Mixer
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MIX_INN 9 51 VDD_IO
MIXS_IN 10 Digitizer 41 IO0
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42 IO1
RFOUTN_1 27
Analog 43 IO2
RFOUTN_2 28
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RF Out Front-end RSSI 44 IO3

MCU Interface

RFOUTP_1 20
45 IO4
RFOUTP_2 21
46 IO5 Micro
RFONX 32
47 IO6 controller
Directional unit
RFOPX 33
48 IO7
EPC Gen 2 Protocol
56 Handling
EXT_IN 50 CLK
36 Oscillator GEN-2
OSCI & Timing 39 EN
System Frame Gen 24 Byte
37 FIFO 40 IRQ
OSCO CRC
VCO 60 49 CLSYS
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CP 62
6 8 11 12 14 22 23 24 25 26 29 35 55 57 65
VSN_4
VSN_MIX
VSS
VSS

CBIB

VSN_RFP
VSN_A
VSN_D

VSN_CP

EXP_PAD
CBV5
VSN_1
VSN_2
VSN_3

VSN_5
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AS3992
Datasheet - C o n t e n t s

Contents
1 General Description .................................................................................................................................................................. 1
2 Key Features............................................................................................................................................................................. 1
3 Applications............................................................................................................................................................................... 1
4 Pin Assignments ....................................................................................................................................................................... 5
4.1 Pin Descriptions.................................................................................................................................................................................... 5

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5 Absolute Maximum Ratings ...................................................................................................................................................... 8
6 Electrical Characteristics........................................................................................................................................................... 9
7 Detailed Description................................................................................................................................................................ 11

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7.1 Supply................................................................................................................................................................................................. 11
7.1.1 Power Modes............................................................................................................................................................................. 12

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7.2 Host Communication .......................................................................................................................................................................... 13
7.3 VCO and PLL ..................................................................................................................................................................................... 13
7.3.1 VCO and External RF Source.................................................................................................................................................... 13

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7.3.2 PLL ............................................................................................................................................................................................ 13

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7.4 Chip Status Control ............................................................................................................................................................................ 14
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7.5 Protocol Control.................................................................................................................................................................................. 14
7.6 Option Registers Preset ..................................................................................................................................................................... 14
on A
7.7 Transmitter.......................................................................................................................................................................................... 14
7.7.1
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Normal Mode ............................................................................................................................................................................. 14
7.7.2 Direct Mode ............................................................................................................................................................................... 16
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7.7.3 Modulator................................................................................................................................................................................... 16
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7.7.4 Amplifier..................................................................................................................................................................................... 17
7.7.5 TX Pre-Distortion ....................................................................................................................................................................... 17
7.8 Receiver ............................................................................................................................................................................................. 17
7.8.1 Input Mixer ................................................................................................................................................................................. 17
7.8.2 DRM RX Filter............................................................................................................................................................................ 18
7.8.3 RX Filter Calibration................................................................................................................................................................... 19
7.8.4 Fast AC Coupling....................................................................................................................................................................... 19
7.8.5 RX Gain ..................................................................................................................................................................................... 19
7.8.6 Received Signal Strength Indicator (RSSI)................................................................................................................................ 20
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7.8.7 Reflected RF Level Indicator ..................................................................................................................................................... 20

7.8.8 Normal Mode ............................................................................................................................................................................. 20
7.8.9 Direct Mode ............................................................................................................................................................................... 21
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7.8.10 Normal Mode With Mixer DC Level Output and Enable RX Output Available ......................................................................... 21
7.9 ADC / DAC ......................................................................................................................................................................................... 22
7.9.1 DA Converter ............................................................................................................................................................................. 22
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7.9.2 AD Converter ............................................................................................................................................................................. 22

7.10 Reference Oscillator ......................................................................................................................................................................... 22
8 Application Information ........................................................................................................................................................... 23
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8.1 Configuration Registers Address Space............................................................................................................................................. 23

8.2 Main Configuration Registers ............................................................................................................................................................. 25
8.3 Control Registers - Low Level Configuration Registers...................................................................................................................... 26
8.4 Status Registers ................................................................................................................................................................................. 30
8.5 Test Registers..................................................................................................................................................................................... 33
8.6 PLL, Modulator, DAC, and ADC Registers ......................................................................................................................................... 35

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AS3992
Datasheet - C o n t e n t s

8.7 RX Length Registers .......................................................................................................................................................................... 38

8.8 FIFO Control Registers....................................................................................................................................................................... 39
8.9 Direct Commands............................................................................................................................................................................... 40
8.9.1 Idle (80)...................................................................................................................................................................................... 41
8.9.2 Hop to Main Frequency (84) ...................................................................................................................................................... 41
8.9.3 Hop to Auxiliary Frequency (85) ................................................................................................................................................ 41
8.9.4 Trigger AD Conversion (87)....................................................................................................................................................... 41

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8.9.5 Trigger RX Filter Calibration (88)............................................................................................................................................... 41
8.9.6 Decrease RX Filter Calibration Data (89) .................................................................................................................................. 41
8.9.7 Increase RX Filter Calibration Data (8A) ................................................................................................................................... 41

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8.9.8 Reset FIFO (8F)......................................................................................................................................................................... 41
8.9.9 Transmission With CRC (90) ..................................................................................................................................................... 42
8.9.10 Transmission With CRC Expecting Header Bit (91) ................................................................................................................ 42

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8.9.11 Transmission Without CRC (92) .............................................................................................................................................. 42
8.9.12 Delayed Transmission With CRC (93)..................................................................................................................................... 42
8.9.13 Delayed Transmission Without CRC (94)................................................................................................................................ 42

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8.9.14 Block RX (96)........................................................................................................................................................................... 42
8.9.15 Enable RX (97) ........................................................................................................................................................................ 42

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8.10 EPC GEN2 Specific Commands ...................................................................................................................................................... 42
8.10.1 Query (98)................................................................................................................................................................................ 42
on A
8.10.2 QueryRep (99) ......................................................................................................................................................................... 42
8.10.3
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QueryAdjustUp (9A)................................................................................................................................................................. 42
8.10.4 QueryAdjustNic (9B) ................................................................................................................................................................ 43
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8.10.5 QueryAdjustDown (9C)............................................................................................................................................................ 43

8.10.6 ACK (9D) ................................................................................................................................................................................. 43
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8.10.7 NAK (9E).................................................................................................................................................................................. 43

8.10.8 ReqRN (9F) ............................................................................................................................................................................. 43
8.11 Reader Communication Interface ..................................................................................................................................................... 43
8.12 Parallel Interface Communication..................................................................................................................................................... 45
8.13 Serial Interface Communication ....................................................................................................................................................... 47
8.13.1 Timing Diagrams...................................................................................................................................................................... 48
8.13.2 Timing Parameters .................................................................................................................................................................. 49
8.14 FIFO ................................................................................................................................................................................................. 49
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9 Package Drawings and Markings ........................................................................................................................................... 50

10 Ordering Information............................................................................................................................................................. 52
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AS3992
Datasheet - P i n A s s i g n m e n t s

4 Pin Assignments
Figure 2. Pin Assignments (Top View)

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COMP_A

VSN_CP

VDD_IO
EXT_IN
VDD_A

CLSYS
VSN_A
VDDLF

VOSC

AGD
VCO

ADC

CD2
CD1

CLK
CP

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60
63

61
64

59

55
62

58

56

50
54
53

51
57

49
52
COMN_A 1 48 IO7
COMP_B 2 47 IO6

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COMN_B 3 46 IO5
DAC 4 45 IO4
VDD_5LFI 5 44 IO3
VSS 6 43 IO2

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MIX_INP 7 42 IO1
VSS 8 AS3992 41 IO0

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MIX_INN
MIXS_IN
9
10
40
39
IRQ
EN
VSN_MIX 11 38 VDD_D
on A
CBIB 12 37 OSCO
nt
VDD_MIX
CBV5
13
14
36
35
OSCI
VSN_RFP
VDD_TXPAB 15 34 VDD_RFP
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VEXT 16 33 RFOPX
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21
17
18

20

22

26
19

23

25

31
27
28

30
24

32
29

OAD
OAD2
VSN_3

VSN_D
VSN_2

RFONX
VSN_1

VSN_5
VDD_B

VSN_4
VEXT2
VDD_RF

RFOUTN_2
RFOUTN_1
RFOUTP_1
RFOUTP_2
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4.1 Pin Descriptions

Table 1. Pin Descriptions
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Pin Number Pin Name Pin Type Description

1 COMN_A Bidirectional
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2 COMP_B Bidirectional Connect de-coupling capacitor to VDD_5LFI

3 COMN_B Bidirectional
DAC output for external amplifier support, Output Resistance of DAC
4 DAC Output
pin is 1kΩ
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5 VDD_5LFI Supply Input Positive supply for LF input stage, connect to VDD_MIX
6 VSS Supply Input Substrate
7 MIX_INP Input Differential mixer positive input
8 VSS Supply Input Substrate
9 MIX_INN Input Differential mixer negative input

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AS3992
Datasheet - P i n A s s i g n m e n t s

Table 1. Pin Descriptions

Pin Number Pin Name Pin Type Description
10 MIXS_IN Input Single ended mixer input
11 VSN_MIX Supply Input Mixer negative supply
12 CBIB Bidirectional Internal node de-coupling capacitor to GND
13 VDD_MIX Supply Output Mixer positive supply, internally regulated to 4.8V

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14 CBV5 Bidirectional Internal node de-coupling capacitor to VDD_MIX
15 VDD_TXPAB Supply Input Power Amplifier Bias positive supply. Connect to VDD_MIX

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16 VEXT Supply Input Main positive supply input (5V to 5.5V)
17 VEXT2 Supply Input PA positive supply regulator input (2.5V to 5.5V)

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18 VDD_RF Supply Output PA positive supply regulator output, internally regulated to 2V-3.5V
19 VDD_B Supply Output PA buffer positive supply. Internally regulated to 3.4V
20 RFOUTP_1 Output PA positive RF output

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21 RFOUTP_2 Output RFOUT1 and RFOUT2 must be tied together

22 VSN_1 Supply Input

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23 VSN_2
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Supply Input
24 VSN_3 Supply Input PA negative supply
on A
25 VSN_4
nt
Supply Input
26 VSN_5 Supply Input
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27 RFOUTN_1 Output PA negative RF output or used in single ended mode.

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28 RFOUTN_2 Output RFOUT1 and RFOUT2 must be tied together

29 VSN_D Supply Output Digital negative supply

Analog or digital received signal output and MCU support mode sense
30 OAD2 Bidirectional
input
31 OAD Bidirectional Analog or digital received signal output
32 RFONX Output Low power linear negative RF output (~0dBm)
33 RFOPX Output Low power linear positive RF output (~0dBm)
34 VDD_RFP Supply Output RF path positive supply, internally regulated to 3.4V
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35 VSN_RFP Supply Input RF path negative supply

36 OSCI Input Crystal oscillator input
37 OSCO Bidirectional Crystal oscillator output or external 20MHz clock input
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38 VDD_D Supply Output Digital part positive supply, internally regulated to 3.4V
39 EN Input Enable input
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40 IRQ Output Interrupt output

41 IO0 Bidirectional
I/O pin for parallel communication
42 IO1 Bidirectional
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I/O pin for parallel communication

43 IO2 Bidirectional
EnableRX input in case of direct mode
I/O pin for parallel communication
44 IO3 Bidirectional
Modulation input in case of direct mode
I/O pin for parallel communication
45 IO4 Bidirectional
Slave select in case of serial communication (SPI)

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AS3992
Datasheet - P i n A s s i g n m e n t s

Table 1. Pin Descriptions

Pin Number Pin Name Pin Type Description
I/O pin for parallel communication
46 IO5 Bidirectional
Sub-carrier output in case of direct mode
I/O pin for parallel communication.
47 IO6 Bidirectional MISO in case of serial communication (SPI)
Sub-carrier output in case of direct mode

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I/O pin for parallel communication.
48 IO7 Bidirectional
MOSI in case of serial communication (SPI)
49 CLSYS Output Clock output for MCU operation

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50 CLK Input Clock input for MCU communication (parallel and serial)
Positive supply for peripheral communication, connect to host positive

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51 VDD_IO Supply Input
supply
52 CD2 Bidirectional
Internal node de-coupling capacitor
53 CD1 Bidirectional

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54 AGD Bidirectional Analog reference voltage

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55
56
VSN_A
EXT_IN
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Supply Input
Input
Analog part negative supply
RF input in case external VCO is used
on A
57 VSN_CP Supply Input Charge pump negative supply
58 ADC
nt Input ADC input for external power detector support
59 VDD_A Supply Output Analog part positive supply, internally regulated to 3.4V
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60 VCO Input VCO input

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61 VOSC Bidirectional Internal node de-coupling capacitor

62 CP Output Charge pump output
63 VDDLF Supply Input Positive supply for LF processing, internally regulated to 3.4
64 COMP_A Bidirectional Internal node, connect de-coupling capacitor to VDD_5LFI
65 EXP_PAD Supply Input Exposed paddle, must be tied to GND
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AS3992
Datasheet - A b s o l u t e M a x i m u m R a t i n g s

5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 9 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Min Max Units Comments
Electrical Parameters

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Supply voltage, VEXT, VEXT2 All voltage values are with respect to substrate ground
-0.3 6 V terminal VSS

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For pins EN, I07..IO0, CLK, IRQ, CLSYS, VDDIO,
VEXT+0.3 V VDD_MIX, VDD_5LFI, VDD_TXPAB, CBV5, DAC,
Positive Voltage OAD, OAD2

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4.5 V For other pins
Negative voltage -0.3 V For other pins
1
Latchup immunity , IO ±100 mA According to JEDEC 78

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Electrostatic Discharge

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ESD rating
2
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Other pins, HBM
RF pins, HBM
2
1
kV According to MIL 883 E method 3015
on A
Temperature Ranges and Storage Conditions nt
Maximum junction temperature, TJ The maximum junction temperature for continuous
120 ºC operation is limited by package constraints.
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Storage temperature range, Tstg -55 +150 ºC

The reflow peak soldering temperature (body
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temperature) specified is in accordance with IPC/

JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Lead temperature 1.6 mm (1/16 inch) from case Classification for non-hermetic Solid State Surface
260 ºC
for 10 seconds Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn)

1. The AGD (Pin 54) is excluded from Latch-up immunity test at EN (Pin 39) high. AGD is a reference voltage pin and must be kept at the
reference voltage level for proper chip operation. AGD must be connected to an external stabilization capacitor.

2. This integrated circuit can be damaged by ESD. We recommend that all integrated circuits are handled with appropriate precautions.
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Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance
degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric
changes could cause the device not to meet the published specifications. RF integrated circuits are also more susceptible to damage
due to use of smaller protection devices on the RF pins, which are needed for low capacitive load on these pins.
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AS3992
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

6 Electrical Characteristics
VEXT = 5.3V, typical values at 25ºC, unless otherwise noted.

Note: The difference between the external supply and the regulated voltage is higher than 250mV.
Table 3. Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
IVEXT Supply current without PA driver current VEXT Consumption 80 mA

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VEXT2 Consumption,
IVEXT2 Supply Current for internal PA 140 mA
VDD_RF = 2.5V

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ISTBY Standby current 3 mA

IPD All system disabled including supply

Supply current in power-down mode 2 10 µA
voltage regulators

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VAGD AGD voltage 1.5 1.6 1.7 V
VPOR Power on reset voltage (POR) 1.4 2.0 2.5 V

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VVDD Regulated supply for internal circuitry and 3.2 3.4 3.6 V
for external MCU

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VDD_RF
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Regulated supply for internal PA
Regulated supply for mixers,
1.9 2 2.1 V

VVDD MIX1 4.5 4.8 5.1 V

bit vext_low=L
on A
The difference between the external
VVDD MIX2
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Regulated supply for mixers,
bit vext_low=H
supply and the regulated voltage is 3.5 3.7 3.9 V
higher than 250mV
Rejection of external supply noise on the
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PPSSR 26 dB
supply regulators
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PRFAUX Auxiliary output power 0 dBm

PRFOUT Internal PA output power 20 dBm
RRFIN RFIN input resistance 100 Ω
VSENS-NOM Nominal mixer setting, PER = 0.1% -66 dBm
Input sensitivity
VSENS-GAIN Increased mixer gain, PER = 0.1% -76 dBm
VSENS-LBT LBT sensitivity Maximum LBT sensitivity -86 dBm
1dBCP Input 1dB compression point 10 dBm
Nominal mixer setting
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IP3 Third order intercept point 21 dBm

PN200 VCO Phase noise @ 200 kHz -118 dBc/Hz
PN400 VCO Phase noise @ 400 kHz -125 dBc/Hz
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TREC Recovery time after modulation Maximum LF selected 18 µs

Logic Input/Output
ch

Maximum CLK frequency 2 MHz

VLOW Input logic low 0.2 VDD_IO
VHIGH Input logic high 0.8 VDD_IO
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RIO Output resistance IO0…IO7 400 800 Ω

low_io = H for VDD_IO < 2.7V
RCL SYS Output resistance CL SYS 200 Ω

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AS3992
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

Table 4. Recommended Operating Conditions

Symbol Parameter Conditions Min Typ Max Units

Positive Supply Voltage 5.0 5.3 5.5 V

VEXT
Bit vext_low = 1 4.1 5.5 V
TJ Operating virtual junction temperature range -40 110 ºC
TAMB Ambient temperature -40 110 ºC

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- Rth junction to exposed die pad - 19 º/W

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on A
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AS3992
Datasheet - D e t a i l e d D e s c r i p t i o n

7 Detailed Description
The RFID reader IC comprises complete analog and digital functionality for reader operation including transmitter and receiver section with
complete EPC Gen2 or ISO18000-6C digital protocol support. To integrate as many components as possible, the device also comprises an on-
board PLL section with integrated VCO, supply section, DAC and ADC section, and host interface section. In order to cover a wide range of
possibilities, there is also Configuration registers section that configures operation of all blocks.
For operation, the device needs to be correctly supplied via. VEXT and VEXT2 pins and enabled via. EN pin (Refer Supply on page 11 for
connecting to supply and Power Modes on page 12 about operation of the EN pin). At power-up, the configuration registers are preset to a

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default operation mode. The preset values are described in the Configuration Registers Address Space on page 23 below each register
description table. It is possible to access and change registers to choose other options.
The communication between the reader and the transponder follows the reader talk first method. After power-up and configuring IC, the host

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system starts communication by turning on the RF field by setting option bit rf_on in the ‘Chip status control register’ (00) (see Table 13) and
transmitting the first protocol command (Select in EPC Gen2). Transmitting and receiving is possible in the following two modes:
1. Normal Data Mode: In this mode, the TX and RX data is transferred through the FIFO register and all protocol data processing is done

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internally.
2. Direct Data Mode: In this mode, the data processing is done by the host system.

7.1 Supply

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The effective supply system of the chip decreases the influence of the supply noise and interference and thus improves de-coupling between

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different building blocks. A set of 3.4V regulators is used for supplying the reference block, AD and DA converters, low frequency receiver cells,
the RF part, and digital part. It is possible to use the digital part supply VDD_D for supplying the external MCU with a current consumption up to
20mA. The input pin for the regulators is VEXT. The output pins for regulators are VDD_A, VDD_LF, VDD_D, VDD_RFP and VDD_B. Each of
on A
the pins require stabilizing capacitors to connected ground (2.2…10µF and 10…100nF) in parallel. Depending on quality of the capacitors,
100pF could be required.
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Figure 3. Mixer Supply
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VDD_TXPAB
VDD_5LFI
VDD_MIX

COMN_B
COMN_A
COMP_A

COMP_B
CBV5
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VEXT LDO
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Mixer

On
ch

receive
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An additional 4.8V regulator is used for the input RF mixers supply. The input of this regulator is VEXT, output is VDD_MIX pin. For correct
operation of the 4.8V regulator, the VEXT voltage needs to be between 5.3V and 5.5V. VDD_MIX needs de-coupling capacitors to VDD_MIX like
other VDD pins.

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AS3992
Datasheet - D e t a i l e d D e s c r i p t i o n

In case lower VEXT supply voltage is used (down to 4.1V), the vext_low option bit needs to be set to optimize the chip performance to the lower
supply. The vext_low in the ‘TRcal high and misc register’ (05) bit decreases VDD_MIX voltage to 3.7V to maintain the regulators PSSR and the
ir<1> bit in the ‘RX special setting 2’ (0A) adapts mixer’s internal operating point to lower supply. Adaptation to low supply is implemented in
differential mixer only. The consequence of the decreased supply is lower mixer’s input range.
VDD_5LFI and VDD_TXPAB pins are supply input pins and should be connected to VDD_MIX. The internal 20dBm power amplifier has an
internal regulator from 2…3.5V. The output voltage selection is done by reg2v1:0 option bits in the ‘Regulator and IO control register’ (0B) (see
Table 24).
The input pin is VEXT2 and output is VDD_RF. For optimum noise rejection performance, the input voltage at VEXT2 pin needs to be at least

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0.5V above the regulated supply output. Connecting VEXT2 directly to VEXT is possible only at the expense of increasing IC’s power dissipation
and decreasing the maximum operating temperature.
A separate I/O supply pin (VDD_IO) is used to supply the internal level shifters for communication interface to the host system (MCU). VDD_IO

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should be connected to MCU supply to ensure proper communication between the chip and MCU. In case the MCU is supplied by VDD_D from
the reader IC also VDD_IO should be connected to VDD_D.

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7.1.1 Power Modes
The chip has five power modes.

Power Down Mode. The power down mode is activated by EN pin low (EN=L). For correct operation, the OAD2 pin should not be connected.

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Normal Mode. The normal mode is entered by setting EN=H. In this case all supply regulators, reference voltage and bias system, crystal

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oscillator, RF oscillator and PLL are enabled. After the crystal oscillator stabilizes, the CLSYS clock becomes active (default frequency is 5MHz)
and the chip is ready to work with internal registers.
In case the crystal oscillator is used the time that the crystal stabilizes dependent on the crystal used. Typical time is 1.5-3ms. By reading the
on A
register 0E, the firmware can check the crystal status: register 0E:x1 (osc_ok=1, pll_ok=0, rf_ok=0) shows that crystal oscillator is stable and that
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device is ready to operate. In case the continuously running TCXO is used, only the OSCO pin DC level needs to be set before the internal clock
is ready. The same test with reg0E as above can be used.
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The bias and reference voltages after EN=H stabilize in 12ms typically. Then the chip is ready to switch on the RF field and start data
transmission.
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Standby Mode. The standby mode is entered from normal mode by option bit stby=H. In the standby mode the regulators, reference voltage
system, and crystal oscillator are operating in low power mode; but the PLL, transmitter output stages and receiver are switched off. All the
register settings are kept while switching between standby and normal mode.
The bias and reference voltages after stby=0 stabilize in 12ms typically. Then the chip is ready to switch on the RF field and start data
transmission.

MCU Support Mode. Power down with MCU support mode intends to support the MCU if the majority of the reader IC is in power down. This
mode is enabled by connecting 10kΩ resistor between OAD2 pin and ground. During EN=L period, the VDD_D regulator is enabled in low power
mode and the CLSYS frequency is 60kHz typically.
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Temporary Normal Mode. It is also possible to trigger temporary normal mode from power down mode (EN=L) by pulling shortly the OAD2
pin low via 10kΩ or less. After the crystal oscillator is stable and the CLSYS clock output is active, the chip waits for approximately 200µs and
then changes back to the power down mode. Using this function, the superior system can wake up the reader IC and MCU that are both in the
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power down mode. If the MCU during 200µs period finds out that the RFID system must react, it confirms the normal mode by setting EN high.
Table 5. AS3992 Power Modes
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Power Mode EN OAD2 Std by

Power down L - X
Power down
L 10k to GND X
SYSCLK of 60kHz
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Normal power H X X
Standby X H
Listen mode L 10k and falling edge X

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7.2 Host Communication

An 8-bit parallel interface (pins IO0 to IO7) with two control signals (CLK, IRQ) forms the main communication system. It can also be changed (by
hardwiring some of the 8 I/O pins) to a serial interface. The data handling is done by a 24 byte FIFO register used in both directions, transmission
and reception. For more details, refer Reader Communication Interface on page 43.
The signal level for communication between the host system (MCU) is defined by the supply voltage connected to VDD_IO pin. Communication
is possible in wide range between 1.8V and 5.5V. In case the pull-up output resistance at VDD_IO below 2.7V is to high, it can be decreased by
setting option bit vdd_io_low in the ‘TRcal High and Misc register’ (05). In case the MCU is supplied from the reader IC, then both the MCU
supply and VDD_IO pin need to be connected to VDD_D.

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CLSYS output level is defined by the VDD_IO voltage. It is also possible to configure CLSYS to open drain N-MOS output by setting the option
bit open_dr in the in the ‘TRcal high and misc register’ (05), (see Table 18). This function can be used to decrease amplitude and harmonic
content of the CLSYS signal and decrease the cross-talk effects that could corrupt operation of other parts of the circuit.

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7.3 VCO and PLL

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The PLL section is composed of a voltage control oscillator (VCO), prescaler, main and reference divider, phase-frequency detector, charge
pump, and loop filter. All building blocks excluding the loop filter are completely integrated. Operating range is 840MHz to 960MHz.

7.3.1 VCO and External RF Source

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Instead of the internal PLL signal, an external RF source can be used. The external source needs to be connected to EXT_IN pin and option bit
eext_in in the ‘PLL A/B divider auxiliary register’ (17) (see Table 39) needs to be set high. The EXT_IN input optimum level is 0dBm with a DC

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level between 0V and 2V.
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It is also possible to use external VCO and internal PLL circuitry. In this case, the output of the external VCO (0dBm) needs to be connected to
EXT_IN, option bits eext_in and epresc in the ‘PLL A/B divider auxiliary register’ (17) both need to be set high. The charge pump output pin CP
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needs to be connected to the external loop filter input and loop filter output to the external VCO input. This configuration is useful in case the
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application demands better phase noise performance than the completely integrated oscillator offers.
The internal on-board VCO is completely integrated including the variable capacitor and inductor. The control input is pin VCO; input range is
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between 0 and 3.3V. The option bits eosc<2:0> in the ‘CLSYS, analog out and CP control’ (14) (Table 36) can be used for oscillator noise and
current consumption optimization. Option bit lev_vco in the ‘PLL A/B divider auxiliary register’ (17) (see Table 39) is used to optimize the internal
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VCO output level to other RF circuitry demands. VCO and CP pin valid range is between 0.5V and 2.9V.
AS3992 has internal VCO set to a frequency range around 1800MHz, later internally divided by two for decreasing the VCO pulling effect. The
tuning curve of 1800MHz VCO is divided into 16 segments to decrease VCO gain and attain lowest possible phase noise.
Configuration of the 1800MHz VCO tuning range can be manual using option bits vco_r<3:0> in the ‘CL_SYS, analog out and CP control’
register (14) or automatic using L-H transition on option bit auto in the same register. The device allows measurement of the VCO voltage using
option bit mvco and reading out the 4 bits result of the automatic segment selection procedure, both in the ‘AGL/VCO/F_CAL status’ register
(10).

7.3.2 PLL
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The divide by 32/33 prescaler is controlled by the main divider. The main divider ratio is defined by the ‘PLL A/B divider main register’ (16). The
low ten bits in the three bytes deep register define A value and the next ten bits define B value. The A and B values define the main divider
division ratio to N=B*32+A*33. The reference clock is selectable by RefFreq<2:0> bits in the ‘PLL R, A/B divider main register’ (16) (see Table
38). The available values are 500 kHz, 250 kHz, 200 kHz, 100 kHz, 50 kHz and 25 kHz.
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Charge pump current is selectable between 150µA and 1200µA using option bits cp1:0 in the ‘CL_SYS, analog out and CP control register’ (14)
(see Table 36). The cp<3> is used to change the polarity (direction) of the charge pump output.
The frequency hopping is supported by direct commands ‘Hop to main frequency’ (84) and ‘Hop to auxiliary frequency’ (85). The hopping is
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controlled by host system (MCU) using two configuration registers for two frequencies. Before enabling the RF field, the host system needs to
configure the PLL by writing the ‘CL_SYS, analog out and PLL register’ (09) and the ‘PLL R, A/B divider main’ (16) registers. Any time during
operating at the first selected frequency, the external system can configure the three bytes deep ‘PLL A/B divider auxiliary (17)’ register. Hopping
to the second frequency is triggered, if direct command ‘Hop to auxiliary frequency’ is sent. Hop to the third frequency is similar: the register ‘PLL
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A/B divider main (16)’ can be written any time the external system has free resources and actual hop is triggered by direct command ‘Hop to
main frequency’.

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7.4 Chip Status Control

In the ‘Chip status control register’ (00) (see Table 13), main functionality of the chip is defined. By setting the rf_on bit in the ‘Chip control
register’ (00), the transmit and receive part are enabled. The initial RF field ramp-up is defined with the Tari1:0 option bits in the ‘Protocol control
register’ (01) (see Table 14). It is also possible to slow down the initial RF field ramp by option bits trfon1:0 in the ‘Modulator control register’ (15)
(see Table 37). The available values are 100µs, 200µs, and 400µs.
The host system can check whether the field ramp-up is finished via the rf_ok bit in the ‘AGC and internal status register’ (0E) (see Table 27),
which is set high when ramp-up is finished. By setting the rf_on bit low, the field will ramp-down similarly to the ramp-up transient. It is also
possible to enable receiver operation by setting rec_on bit. The agc_on and agl_on bits enables the (Automatic Gain Control) AGC and
(Automatic Gain Leveling) AGL functionality, dac_on enables DA converter, bit direct enables the direct data mode, and stby bit moves chip to

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the stand-by power mode.

7.5 Protocol Control

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In the ‘Protocol control register’ (01) (see Table 14), the main protocol parameters are selected (Tari value and RX coding for EPC Gen2
protocol). The Gen2 Protocol is configured by setting Prot<1:0> bits to low. The dir_mode<6> bit defines type of output signals in case the direct
mode is used. The rx_crc_n<7> bit high defines reception in case the user does not want to check CRC internally. In this case, the CRC is not

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checked but is just passed to the FIFO like other data bytes. In the EPC Gen2, this function is useful in case of truncated EPC reply where the
‘CRC’ transponder transmits is not valid CRC calculated over actual transmitted data.

7.6 Option Registers Preset

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After power up (EN low to high transition), the option registers are preset to values that allow default reader operation. Default transmission uses

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Tari 25µs, PW length is 0.5Tari, TX one length is 2 Tari, and RTcal is 133µs. Default reception uses FM0 coding with long preamble, link
frequency 160kHz. Default operation is set to internal PLL with internal VCO, differential input mixers, low power output (RFOPX, RFONX), and
DSB-ASK transmit modulation.
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7.7 Transmitter
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Transmitter section comprises of protocol processing digital part, shaping, modulator and amplifier circuitry. The RF carrier is modulated with the
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transmit data and amplified for transmission.

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7.7.1 Normal Mode

In normal mode, all signal processing (protocol coding, adding preamble or frame-sync and CRC, signal shaping, and modulation) is done
internally.
The external system (MCU) triggers the transmission and loads the transmit data into the FIFO register. The transmission is started by sending
the transmit command followed by information on the number of bytes that should be transmitted and the data. The number of bytes needs to be
written in the ‘TX length’ registers and the data to the FIFO register. Both can be done by a single continuous write. The transmission actually
starts when the first data byte is written into the FIFO.
The second possibility is to start transmission with one of the direct Gen2 commands (Query, QueryRep, QueryAdjust, ACK, NAK, ReqRN). In
this case, the transmission is started after receiving the command.
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In case the transmission data length is longer than the size of the FIFO, the host system (MCU) should initially fill the FIFO register with up to 24
bytes. The reader chip starts transmission and sends an interrupt request when only 3 bytes are left in the FIFO. When interrupt is received, the
host system needs to read the ‘IRQ status register’ (0C) (see Table 25). By reading this register, the host system is notified by the cause of the
interrupt and the same reading also clears the interrupt. In case the cause of the interrupt is low FIFO level and the host system did not put all
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data to the FIFO, the remaining data needs to be sent to FIFO, again according to the available FIFO size. In case all transmission data was
already sent to the FIFO, the host system waits until the transmission runs out. At the end of the transmit operation, the external system is
notified by another interrupt request with a flag in the IRQ register that signals the end of transmission.
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The two ‘TX length’ registers support in-complete bytes transmission. The high two nibbles in register 1D and the nibble composed of bits B4 ~
B7 in ‘TX length byte 2’ (1E) register (see Table 46) store the number of complete bytes that should be transmitted. Bit B0 (in register 1E) is a flag
that signals the presence of additional bits that do not form a complete byte. The number of bits are stored in bits B1~B3 of the same register
(1E).
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The protocol selection is done by the ‘Protocol control register’ (01) (see Table 14). As defined by selected protocol, the reader automatically
adds all the special signals like Preamble, Frame-Sync, and CRC bytes. The data is then coded to the modulation pulse level and sent to the
modulator. This means that the external system only has to load the FIFO with data and all the micro-coding is done automatically.
The EPC Gen 2 protocol allows some adjustment in transmission parameters. The reader IC supports three Tari values (25µs, 12.5µs, 6.25µs)
by changing Tari<1:0> option bits in the ‘Protocol control register’ (01). PW length and length of the logical one in the transmission protocol can
be adjusted by TxPW<1:0> and TxOne<1:0> option bits in the ‘TX options’ (02) register. Session that should be used in direct commands is
defined in the S1and S0 bits in the same register. The back scatter link frequency is defined by TRcal in the Query command transmission. The
TRcal is defined by option bits TRcal<11:0> in the ‘TRcal registers’ (04, 05).

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Table 6. Register Bits Settings

Protocol Setting Register Bits Individual Settings
Protocol
TARI 6.25µs (00) 12.5µs (01) 25µs
control<1:0>
PW length TX option
0.27TARI (00) 0.35TARI(01) 0.44TARI(10) 0.5TARI(11)
control <7:6>

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TX option
Data1 Tx 1.5TARI(00) 1.66TARI(01) 1.83TARI(10) 2TARI(11)
<5:4>

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Protocol
Coding FMO(00) M2(01) M4(10) M8(11)
control<4:3>
RX option 40 kHz 160 kHz 256 kHz 320 kHz 640 kHz

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Link frequency
<7:4> (0000) (0110) (1001) (1100) (1111)

The software designer needs to take care that actual TRcal (reg. 04, 05) and RxLF<3:0> (reg. 03) bits and DR bit in the transmission of the
Query command are matched. Precise description is in the EPC Gen2 or ISO18000-6C protocol description.

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The Transmit section contains a timer. The timer is used to issue a command in a specified time window after a transponder’s response. The

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timer’s time is defined in ‘TX reply in slot’ (06) register. The timer is enabled by using the command ‘Delayed transmission without CRC’ (92) or
‘Delayed transmission with CRC’ (93) and is actually started at the end of the reception.
Table 7. EPC_gen2 - Tari Combinations
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Forward Link

TARI Settings 25µs 12.5µs 6.25µs

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2.5 3 2.5 3 2.5 3

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Zero and one length (RT CAL)

LF Division TR cal
(kHz) Ratio (microseconds)
40 8 200.00 3.2 2.6667
160 64/3 133.33 2.1333 1.7778
256 64/3 83.33 1.3333 1.1111 2.6667 2.2222
320 64/3 66.67 2.1333 1.7778
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640 64/3 33.33 2.1333 1.7778

Backscatter Link

40 8 200.00
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160 8 50.00 1.6 1.3333

256 8 31.25 2 1.6667
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320 8 25.00 1.6 1.3333

640 8 12.50
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40 64/3 533.33
160 64/3 133.33 2.1333 1.7778
256 64/3 83.33 1.3333 1.1111 2.6667 2.2222
320 64/3 66.67 2.1333 1.7778
640 64/3 33.33 2.1333 1.7778

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7.7.2 Direct Mode

Direct mode is applied if the user wants to use analog functions only and bypass the protocol handling supported in the reader IC.

Direct Mode Using Parallel Interface. The reader IC enters the direct mode when option bit ‘direct’ is set to high in the ‘Chip status control
register’ (00). As the direct mode starts immediately, all the register settings that help to configure the operation of the chip needs to be done
prior to entering the direct mode. The ‘write’ command for direct mode should not be terminated by stop condition since the stop condition
terminates the direct mode. This is necessary as direct mode uses four IO pins (IO2, IO3, IO5, IO6) and normal parallel or serial communication
is not possible in direct mode. To terminate the direct mode, the user needs to send the stop condition. After stop condition, normal
communication via. interface and access to the registers are possible.

Direct Mode Using Serial Interface (SPI). To enter direct mode via SPI, bit direct should be set to high in the ‘Chip status control register’

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(00) and stop condition (IO4 L-to-H transition) has to be sent. As the direct mode starts immediately, all the register settings that help to configure
the operation of the chip needs to be done prior to entering the direct mode. The direct mode persists till writing bit direct to low (IO4 H-to-L, SPI
write to reg00). Since the direct mode uses four IO pins (IO2, IO3, IO5, IO6), it is not possible to read registers during the direct mode (IO6 which

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is MISO in SPI mode is used as direct mode data or subcarrier output). It is possible to write register 00 to terminate the direct mode. After direct
mode termination, normal communication via SPI interface and access to the registers are possible.

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For more information on transmit modulation input signal possibilities, refer to Modulator on page 16.
For more information on the receive output signal possibilities, refer to TX Pre-Distortion on page 17.
The digital modulation input in direct mode is IO3. RF field is set to high level if IO3 is high, and to low level if IO3 is low. IO2 is used as RX
enable. For correct operation, follow the instructions given below:

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1. Configuration registers should be defined, starting from reg01

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2.
3.
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Direct command Enable RX (97) should be sent
Bit direct should be written to reg00
4. IO2 should be low during data transmission via IO3
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5. IO2 should be changed to high level just before the reception is expected
6.
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IO3 should be maintained high during reception
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7.7.3 Modulator
For the modulation signal source, there are three possibilities:
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Normal data mode – Internally coded and internally shaped.

Externally coded and internally shaped modulation enabled by entering direct mode. For more information on entering and terminating the
direct mode, refer to Direct Mode on page 16.
Externally coded and externally shaped modulation is enabled by setting option bit e_amod in the ‘Modulator control register’ (15) and
entering direct mode. For more information on entering and terminating the direct mode, refer to Direct Mode on page 16. In this case, ADC
and DAC pins are differential modulator input. The DC level should be 2.2V, amplitude 600mVp. It is also possible to use CD1 and CD2 pins
as high and low reference for the external modulation shape circuitry.
The internal modulator is capable of DSB-ASK and PR-ASK modulation. Modulation shape is controlled with a double D/A converter. The first
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one defines the upper (un-modulated) signal level while the second one generates the modulation transient. The level defined by the first
converter is filtered by capacitors on CD1 and CD2 pins to decrease the noise level. The two levels are used as a reference for the shaping
circuitry that transforms the digital modulation signal to shaped analog modulation signal. Sinusoidal and linear shapes are available. The output
of the shaping circuit is interpolated and connected to the modulator input.
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The output level and modulation shape properties are controlled by the ‘Modulator control register’ (15). The level of the output signal is adjusted
by option bits tx_lev<4:0>. Modulation depth for ASK is adjusted by mod_dep<5:0> bits. Valid values for DSB-ASK are 01 to 3F. PR-ASK
modulation is selected by pr-ask bit high. In case of PR-ASK, the mod_dep<5:0> bits are used to adjust the delimiter/first zero timing. Linear
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modulation shape is selected by lin_mod bit. The rate of the modulation transient is automatically adjusted to selected Tari and can be adjusted
by ask_rate<1:0> bits. For smoother transition of the modulation signal, an additional low pass filter can be used. The Filter will be enabled by
e_lpf bit. The adjustment step is 1.6%, 3F gives 100% ASK modulation depth.
PR-ASK modulation is selected by pr-ask bit high. In case of PR-ASK the mod_dep<5:0> bits are used to adjust the delimiter/first zero timing in
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a range 9.6µs to 15.9µs. Linear modulation shape is selected by lin_mod bit. The rate of the modulation transient is automatically adjusted to
selected Tari and can be adjusted by ask_rate<1:0> bits. For smoother transition of the modulation signal, additional low pas filter can be used
by e_lpf bit.
In ASK modulation it is possible to adjust delimiter length by setting option bit ook_ask in the ‘Modulator control register’ (15). In this case,
ook_ask defines 100% ask modulation and the mod_dep<5:0> bits are used for delimiter length setting similar to the PR-ASK mode.
Bits aux_mod and main_mod define whether the modulation signal will be connected to the auxiliary low power output or to the main PA output.
In case one of the outputs are enabled by the etxp<3:0> bits and appropriate aux_mod or main_mod bit is low, the output is enabled but not
modulated.

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7.7.4 Amplifier
The following two outputs are available:
Low power high linear output (~0dBm) can be used for driving an external amplifier. This output uses RFOPX and RFONX pins and it has
nominal output impedance of 50Ω. It needs an external RF choke and de-coupling capacitor for operation. It is also possible to use differen-
tial output for driving balanced loads. The output is enabled by etx<1:0> bits in the ‘Regulator an IO control’ (0B) register (see Table 24).
With the help of these bits, it is also possible to adjust current capability of the output.
Higher output power output (~20dBm) can be used for antenna driving in case of short range applications. Internal higher power amplifier
is enabled by etx<3:2> bits in the ‘Regulator an IO control’ (0B) register (see Table 24). For operation it needs external RF choke and cor-

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rect impedance matching for operation in 50Ω system. It is also possible to use differential output by setting etx<4>. Bias current in the PA
stage can be increased by a factor of two or four using option bits ai2x and ai4x in registers 16 and 17. The differential outputs are
RFOUT_1 and RFOUT_2. Single ended output is RFOUT_1. UHF - power amplifiers (PAs) are generally sensitive to parasitics (layout,

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placement, routing, PCB material etc) and load conditions. We recommend to carefully investigate the specific system implementation on
inherent parasitic and load variations to avoid instabilities over production.

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7.7.5 TX Pre-Distortion
Transmission signal is modulated with the cosine shaped representation of the digital modulation signal. It is possible to tune the initial shape by
writing the correction data in the register 13 and setting option bit use_corr in register 15. Register 13 is 252 bytes deep register accessible in
continuous write mode. Bytes on positions 1 to 251 are used for pre-distortion. Byte on position 0 is not used for pre-distortion. The value on

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position 1 should be set to 0 and the value on position 251 should be set to 250 for smooth continuous transition. The values between positions
1 and 251 form the pre-distortion curve. In case the ramp with values 0-250 is written, the initial cosine shape is maintained.

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The pre-distortion data can be written and read during use_corr=0 period.
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7.8 Receiver nt
Receiver section comprises two input mixers followed by gain and filtering stages. The two receiving signals are fed to decision circuitry, bit
decoder and framer where preamble is removed and CRC is checked. The clean framed data is accessible to the host system (MCU) via. 24
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byte FIFO.
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7.8.1 Input Mixer

The two input mixer pairs are driven with 90º shifted LO signals and form IQ demodulator circuit. Using IQ architecture, the amplitude modulated
input signals are demodulated in the in-phase channel (I) while the phase modulated input signals are demodulated in the quadrature phase (Q)
channel. Mixed input modulation is demodulated in both receiving channels. This configuration allows reliable operation regardless the
transponders. Modulation presents amplitude or phase modulation at receiver’s input and suppresses communication holes that are caused by
modulation alternation.
One can use differential input mixer or single ended input mixer. The differential input is formed by pins MIX_INP and MIX_INN. Input should be
AC coupled. By default, differential mixers input is chosen. If the inputs are not used, then they should be unconnected.
The mixer with single ended mixers input is selected by s_mix bit in the ‘Rx special setting register’ (0A). The single ended mixers input is the
MIXS_IN pin. Input should be AC coupled. If the input is not used, then it should be unconnected.
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To optimize the receiver’s noise level and dynamic input range, the mixers have adjustable input range. Depending on expected level of the
reflected power the one can adapt mixer performance by internal attenuator or increasing mixer gain. Depending on the reflectivity of the
environment or antenna, the receiver’s input RF voltage can increase to a level that corrupts mixer operation. In such a case, the input range can
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be widened by internal input attenuator by setting option bit ir<0>. This is valid for both differential and single ended input mixer.
In case of low reflected power, the host system can increase the differential input mixer’s conversion gain and improve the overall sensitivity of
the receiver by setting option bit ir<1>. The drawback of this setting is decreased mixer’s input dynamic range. The single ended input mixer
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does not support the gain increase feature. The ir<1:0> bits are in the ‘RX special setting’ (0A) register.
In case lower supply voltage is used (low_vext=1, refer to Supply on page 11), the low_vext option bit adapts mixer’s operation point to
decreased supply. The consequence of low supply voltage is up to 1dB decreased performance in terms of sensitivity and input dynamic range.
The ir<1:0> bits are in the ‘RX special setting2 register’ (0A) (see Table 23).
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7.8.2 DRM RX Filter

The analog filtering is composed of four filter stages:
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4 -order elliptic low-pass with notch characteristic to suppress neighboring channel (500kHz or 600kHz). The filter can be set to have -1dB
point at 360kHz and 280kHz for ETSI and FCC channel spacing in DRM operation. It allows one non-DRM setting: 800kHz upper frequency
for 640kHz LF.
nd
2 -order high-pass Chebyshev filter with adjustable -1dB from 72kHz to 200kHz. The filter can also be switched off (only gain stage) for
lower LF frequencies.
nd
2 -order low-pass Chebyshev filter with -1dB frequencies at 360kHz and 280kHz for European and US channel spacing in DRM operation.

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It allows three non-DRM settings:
- 800kHz upper frequency for 640kHz LF,

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- 180kHz upper frequency for 160kHz LF and,
- 72kHz upper frequency for 40kHz LF.
nd st
2 -order high-pass Chebyshev filter with adjustable -1dB from 72kHz to 200kHz. The filter can also be reconfigured to 1 -order with -3dB

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frequency at 5.5kHz or 12kHz for lower LF and FM0 coding.
Filter setting is done via option bits setting in ‘RX Filter register’ 09. Available bit combinations are:
640kHz LF– (reg09:00…reg09:07)

il
Filter Setting -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 1.2MHz

st
reg09:00
te G 220kHz 770kHz -55dB -35dB
reg09:07 80kHz 770kHz -18dB -35dB
on A
nt
320kHz LF – DRM ETSI range filter (reg09:20…reg09:27)
lc s

-3dB high-pass -3dB low-pass

Filter Setting Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz
frequency frequency
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reg09:20 200kHz 380kHz -50dB -40dB -54dB

reg09:27 75kHz 380kHz -18dB -40dB -54dB

250kHz LF – DRM FCC range filter (reg09:30…reg09:37)

-3dB high-pass -3dB low-pass

Filter Setting Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz
frequency frequency
reg09:30 200kHz 320kHz -50dB -45dB -55dB
reg09:37 75kHz 320kHz -18dB -45dB -55dB
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160kHz – (reg09:3B…reg09:3F)

-3dB high-pass -3dB low-pass

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Filter Setting Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz

frequency frequency
reg09:3B 110kHz 245kHz NA -52dB -56dB
ch

reg09:3F 56kHz 255kHz NA -52dB -56dB

40kHz LF – (reg09:FF)
Te

-3dB high-pass -3dB low-pass

Filter Setting Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz
frequency frequency
reg09:FF 7kHz 80kHz NA -60dB -55dB

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Following filter settings for different link frequency and RX coding are proposed:
DRM modes:

Link frequency and RX coding Proposed reg09 setting

320kHz, M4, M8 24
250kHz, M4, M8 34

Other supported modes:

id
Link frequency and RX coding Proposed reg09 setting
40kHz, FM0, M2, M4, M8 FF

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160kHz, FM0 BF
160kHz, M2, M4, M8 3F

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640kHz, M4, M8 04

7.8.3 RX Filter Calibration

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The calibration procedure implemented in the chip helps to compensate the resistor and capacitor process and temperature variations.
Calibration procedure is triggered by ‘Trigger RX filter calibration’ (88) direct command. Calibration is finished in 5ms maximum. Calibration

st
te G
should be triggered prior to first reception after power down and from time to time, especially in cases wherein significant temperature changes
are expected.
The result of calibration is seen in the ‘AGL/VCO/F_CAL/PilotFreq status register’ (10) in case option bits r10page<2:0> in ‘Test setting’ register
on A
(12) are set to 2. Typical calibration result values are 88.
nt
The calibrated values can be changed automatically by using ‘Decrease RX filter calibration data’ (89) and ‘Increase RX filter calibration data’
(8A) direct command, together with f_cal_hp_cgh option bit in ‘Test setting’ register (12).
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Note: hp_cal<3:0> affects the high pass part of the filter characteristic and lp_cal<3:0> affects the low pass part of the filter characteristic,
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both in 4% steps.

7.8.4 Fast AC Coupling

The internal (patent pending) feedback AC coupling system prior to start of transmit modulation stores the DC operating points, and after data
transmission progressively adjusts the high pass time constant to allow very fast settling time prior to beginning of reception. Such a system is
needed to accommodate the short TX to RX time used at the highest bit rates in the EPC Gen 2 protocol.
It is possible to additionally speed up the first AC coupling time constant by setting option bit lf4_ac_su in the ‘Test register’ (12).

7.8.5 RX Gain
Gain in the receiving chain can be adjusted to optimize the signal to noise and interference ratio. There are three ways of adjusting: manual
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adjustment, AGC, and AGL.

Manual Adjustment is gain adjustable by setting option bits gain<5:0> in the ‘RX special setting 2 register’ (0A) (see Table 23) and ‘TRcal
high and misc register’ (05) (see Table 18). The low three bits decrease digitizer hysteresis by 3dB (7 steps), the high two bits change the
ni

amplifier gain by 3dB (3 steps). Gain<5:4> direction (increase or decrease) is defined by gd<3>.
AGC is automatic gain control. It can be enabled by option bit agc_on in the ‘Chip status control’ register (00) (see Table 13). AGC com-
prises of a system that decreases gain during the first periods of the incoming preamble. Gain is decreased equally for both channels to a
ch

level that results the stronger signal is just in the range. In this case, the ratio between I and Q channel amplitude is maintained. The
resulted status of the AGC can be seen in the ‘AGC and internal status’ register (0E) (see Table 27).
AGL is another possibility for adjusting the gain. AGL bit needs to be set high at the moment when there is no actual transponder response
at receiver input. It automatically decreases gain for each channel to the level that is just below the noise and interference level. The gain of
Te

the two channels is independent. The resulted status of the AGL for both channels can be seen in the ‘AGL status ‘register (10) (see Table
29).
Difference between the AGC and AGL functionality is that AGC is done each time at beginning of the receive telegram; while AGL is done only at
the moment when agl_on bit is set high, stored, and is valid till the agl_on bit is set low.
The two receiving signals are digitized and evaluated. The decision circuit selects the in-phase signal or quadrature signal for further processing,
whichever presents the better received signal. Which of the signals is chosen can be seen in the in_select bit in the ‘AGC and internal status’
register (0E). Bit is valid from preamble end till start of the next transmission.

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7.8.6 Received Signal Strength Indicator (RSSI)

The receiver section includes a double RSSI meter. The RSSI meters are connected to the outputs of both receiver chains to measure in real
time the peak to peak demodulated voltage of each receiving channel during the reception of each transponder response (from the end of RX
wait timer till the end of reception). The peak value of each RSSI meter is stored and presented in the ‘RSSI levels’ (0F) register (see Table 28).
The RSSI register is valid till start of next transmission.

7.8.7 Reflected RF Level Indicator

The receiver also comprises the input RF level indicator. It is used for diagnostic of circuitry or environment difficulties.

id
The reflection of poor antenna, reflection of reflective antenna’s environment, or directional device leakage (circulator) can cause that input
mixers are overdriven with the transmitting signal.
Overloading of the input mixers by reflected transmitting carrier can be notified by the host system (MCU) by measuring the RF input level via

al
internal AD converter. The reflected carrier that is seen on the two mixers input is down converted to zero frequency. The two DC levels on the
mixers outputs are proportional to the input RF level and dependant on the input phase and can be used for measuring the level of the reflected
carrier. They can be connected to the on-board ADC converter by setting option bits msel<2:0> in the ‘Test setting and measurement selection

lv
register’ (11). The appropriate settings for connecting two mixers’ DC levels to AD converter are 001 and 002. Conversion is started by direct
command ‘Trigger ADC conversion’ (87). Result in register 19 is valid 20µs after triggering.

7.8.8 Normal Mode

il
In the normal mode, the digitized output after decision circuit is connected to the input of the digital portion of the receiver. This input signal is the
sub-carrier coded signal, which is a digital representation of modulation signal on the RF carrier.

st
te G
The digital part of the receiver consists of two sections, which partly overlap. The first section comprises the bit decoders for the various
protocols. The bit decoders convert the sub-carrier coded signal to a bit stream and the data’s clock according to the protocol defined by option
on A
bits Rx-cod<1:0> in the ‘Protocol control’ (01) register (see Table 14) and Rx_LF<3:0> option bits in the ‘RX options’ (03) register. Preamble is
nt
truncated. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted
sub-carrier signals due to noise or interference. The receiver also supports transfer of incomplete bytes. The number of valid bits in the last
received byte is reported by Bb<2:0> bits in the ‘TX length byte 2’ (1E) register (see Table 46).
lc s

The second section comprises the framing logic for the protocols supported by the bit decoder section. In the framing section, the serial bit
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stream data is formatted in bytes. The preamble, FrameSync, and CRC bytes are checked and removed. The result is ‘clean’ data, which is sent
to the 24-byte FIFO register where it can be read out by the host system (MCU).
In the EPC Gen2 protocol, the decoder supports long RX preamble (TRext=1) for FM0, and all Miller coded signals and short RX preamble
(Trext=0) for Miller4 and Miller8 coded signals. In the EPC Gen2 protocol, the timing between transponders response and the subsequent
reader’s command is quite short. To relieve the host system (MCU) of reading RN16 (or handle) out of the FIFO and then writing it back into the
FIFO, there is a special register for storing last received RN16 during the Query, QueryRep, QueryAdjust or RegRN commands. The last stored
RN16 is automatically used in ACK command.
The start of the receive operation (successfully received preamble) sets the flags in the ‘IRQ and status’ register. The end of the receive
operation is signalled to the host system (MCU) by sending an interrupt request (pin IRQ). If the receive data packet is longer than 8 bytes, an
th
interrupt is sent to the MCU when the 18 byte is received to signal that the data should be removed from the FIFO.
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In case an error in data format or in CRC is detected, the external system is made aware of the error by an interrupt request pulse. The nature of
the interrupt request pulse is available in the ‘IRQ and status register’ (0C) (see Table 25).
The receive part comprises two timers.
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The RX wait time timer setting is controlled by the value in the ‘RX wait time’ (08) (see Table 21). This timer defines the time after the end
of transmit operation in which the receive decoders are not active (held in reset state). This prevents any incorrect detection that could be
caused as a result of transients that are caused by transmit operation or transients that are caused by noise or interference. The value of
ch

the ‘RX wait time register’ defines this time with increments of 6.4µs. This register is preset at every write to the ‘Protocol control’ register
(01) according to the minimum tag response time defined by default register definition.
The RX no response timer setting is controlled by the ‘RX no response wait time’ (07) (see Table 20). This timer measures the time from
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the start of slot in the anti-collision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt
request is sent and a flag is set in ‘IRQ status control’ register. This enables the external controller to be aware of empty slots. The wait time
is stored in the register with increments of 25.6µs. This register is automatically preset for every new protocol selection.

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‘RX length register’ (1A, 1B) defines the number of bits that the receiver should receive. The number of bits is taken into account only in case the
value is different than 0 00, otherwise receiver stops on pause at the end of reception. Since in noisy environment, the end of transponders
transmission is not precisely defined using the RX length registers improves the probability for successful receiving. For direct commands 98 to
9C, the RX length is internally set to 16 to receive RN16. For direct command 9F, the RX length is internally set to 32 to receive RN16 and CRC.
For other commands when the host system knows the expected RX length, it is recommended to write it in the RX length register. The only case
when RX length is not known in advance is reception of the PC+EPC.
AS3992 handles the issue mentioned above by using special RX mode. The idea is that reader chip generates an additional interrupt after two
bytes (PC part of the PC+EPC field) are received. MCU reads out the two bytes that define the length of the on going telegram and writes it in the
RX length register.

id
To use IRQ after the two received bytes, the fifo_dir_irq2 bit in the reg1A should be set and non-zero length (typical PC+EPC length) should be
written in the 1B register before start of reception. The fifo_dir_irq2 performs the following changes in the behavior of the logic:

al
All received bytes are directly transferred to FIFO.
Normally the receiving data is pipelined, causing that the two CRC bytes are not seen in the FIFO. If dir_fifo=1, then all bytes including CRC
are seen in the FIFO.

lv
Additional interrupt is generated after two bytes are received. In the IRQ status register, the ‘header/2byte’ (B3) bit is set. If the reception is
still in progress, IRQ status value is 48.
At this moment, the MCU needs to read out the first two bytes (PC part of the PC+EPC field) and set RX length accordingly. The
fifo_dir_irq2 bit should be maintained high.

il
At the end of reception, another IRQ is generated. Additional IRQ status bit ‘Irq_err3 – preamble/end’ (B1) is set. IRQ status is 42 if the inter-

st
te G
mediate 2nd_byte interrupt was read out and cleared, or 4A if the reception was over before the intermediate interrupt was read out and
cleared.
on A
7.8.9 Direct Mode
nt
The direct mode is applied in case the user wants to use analog functions only and bypass the protocol handling supported in the reader IC.
(Refer to Transmitter on page 14 for information on entering direct mode.)
lc s

Regarding receiving tag data in direct data mode, there are three possibilities depending on setting of option bits:
Internally decoded bit stream and bit clock according to the protocol defined by option bits Rx-cod<1:0> in the ‘Protocol control’ (01) register
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and Rx_LF<3:0> option bits in the ‘RX options’ (03) register is enabled by low level of option bit dir_mode in the ‘Protocol control’ (01) regis-
ter. Outputs are IO5 and IO6.
Digitized sub-carrier signals of both receiving channels are enabled by high level of option bit dir_mode in the ‘Protocol control’ (01) register.
Outputs are IO5 and IO6.
Analog sub-carrier signals of both receiving channels are enabled by high level of option bit e_anasupc in the ‘CLSYS, analog out, and CP
control’ (14) register. Outputs are OAD and OAD2.
In case MCU support mode is used, the OAD2 resistor to ground (the one that is needed for entering this mode) can be removed during
reception not to load the analog OAD2 output. Resistor is necessary only during EN=L, EN L-to-H transition and EN H-to-L transition. It is not
necessary during reception.
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7.8.10 Normal Mode With Mixer DC Level Output and Enable RX Output Available
One of the possibilities for achieving low reflected TX power is active tuning of the antenna or the directivity device. For correct tuning, the data
on the amplitude and phase of the incoming reflected power is available in the output DC level of the two mixers. The two voltages are available
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on the OAD and OAD2 inputs. For correct operation, the tuning circuitry needs to know when receiver is enabled and the two mixer output DC
levels are correct. This signal is available on ADC in case ‘Test setting’ low register (12l) is set to 1A, or on DAC pin in case ‘Test setting’ low
register (12l) is set to 1B. Tuning can be done on CW and also during telegram reception. In the first case, the receiver is enabled by ‘Enable RX’
ch

direct command. In the second case, the receiver is automatically enabled after data transmission.
Te

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7.9 ADC / DAC

Figure 4. ADC / DAC Section

id
ADC

Power
MCU Interface

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detector

RSSI

il lv
AS3992

st
te G
on A
nt
7.9.1 DA Converter
lc s

DA converter intends to support the TX power control function in cases that the external PA supports this function (typically named ramp input or
gain control input). The output level is stored in the DAC control register (18) (see Table 40) and the output pin is DAC. Output range is 0V to two
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times AGD voltage (3.2V). Input code 00 gives output level equal to AGD. The 7 LSB gives absolute output level and the MSB Bit is the sign. DA
converter is enabled by dac_on bit in the ‘Chip status control’ register (00). Output resistance on DAC pin is 1kΩ typically. For applications that
require current, a voltage follower needs to be included.

7.9.2 AD Converter
AD converter intends to support the external power detector placed before or after the circulator to measure actual output power. The analog
voltage from the power detector is connected to the ADC pin. AD conversion is triggered by the ‘Trigger AD conversion’ (87) command, and the
resulted value is available in the ‘ADC readout register’ (19) (see Table 41). AD converter can also be used for measuring the mixers DC output
levels. The source for the conversion is selected by msel<2:0> bits in the ‘Test setting 1 and measurement selection’ register (11) (see Table 33).
Input range is 0V to two times AGD voltage (3.2V). Input level equal to AGD gives output code 00. The 7 LSB bits give absolute output level, the
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MSB bit is a sign, H means positive, L means negative value. Result is valid 20µs after triggering. AD converter can be used to measure VEXT
voltage, and according to the result, the MCU can decide to use adaptation to low supply voltage (low_vext=1 and ir<1>=1 option bits) or inform
the superior system that supply needs to be fixed or just disable transmission. The value in ‘ADC readout register’ (19) is calculated accordingly
to the equation:
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ADCreg = [(VEXT-1.6)*0.8-1.6] / 0.0126 (EQ 1)

Where:
ADCreg is the value, sign should be considered as above
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VEXT is in volts

7.10 Reference Oscillator

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Reference frequency of 20MHz is needed for the chip. It is possible to use quartz crystal or external reference source (TCXO). In case the crystal
is used it should be connected between OSCI and OSCO pin with appropriate load capacitors between each oscillating pin and ground. Load
capacitance 15-20pF is proposed. Maximum series resistance in resonance is 30Ω. In case external reference source is used, it should be
connected to OSCO pin. The signal should be sinusoidal shape, 1Vpp, DC level 1.6V or AC coupled.

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8 Application Information
Figure 5. Application Example

Display

id
USB
Interface

al
microcontroller
device
LAN

lv
Optional
8 I/O IRQ CLK CLSYS VCC Tx
PA

UHF Reader AS3992 Rx

il
st
te G Optional VCO
on A
nt
8.1 Configuration Registers Address Space
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At power up, the configuration registers are preset to a value that allows default operation. The preset values are given after each register
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description table.
Table 8. Main Control Registers
Adr (hex) Register Length
00 Chip status control R/W 1
01 Protocol control R/W 1

Table 9. Protocol Sub-setting Registers

Adr (hex) Register Length
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02 TX options Gen2 R/W 1

03 RX options Gen2 R/W 1
TRcal L register Gen2
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04 R/W 1
05 TRcal H and misc R/W 1
06 TX reply in slot R/W 1
ch

07 RX no response wait R/W 1

08 RX wait time R/W 1
RX filter
Te

09 R/W 1
0A RX special setting2 R/W 1
0B Regulator and IO control R/W 1
13 TX pre-distortion (deep register) R/W
14 CL_SYS, analog out, and CP R/W 3
15 Modulator control (3 bytes deep) R/W 3

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Table 9. Protocol Sub-setting Registers

Adr (hex) Register Length
16 PLL main (3 bytes deep) R/W 3
17 PLL auxiliary (3 bytes deep) R/W 3
18 DAC register R/W 1
19 ADC register R 1

id
Table 10. Status Registers
Adr (hex) Register Length

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0C IRQ and status R 1
0D Interrupt mask register R/W 1

lv
0E AGC and internal status register R 1
0F RSSI levels R 1
10 AGL / VCO / F_CAL / PilotFreq status register R 1

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Table 11. Test Registers

st
Adr (hex)
te G Register Length
11 Measurement selection R/W 1
on A
12
nt
Test setting R/W 1

Table 12. FIFO Registers

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Adr (hex) Register Length

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1A RX length R/W 1
1B RX length R/W 1
1C FIFO status R 1
1D TX length byte1 R/W 1
R for RX
1E TX length byte2 1
W for TX
1F FIFO I/O register R/W 1
ca
ni
ch
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8.2 Main Configuration Registers

Chip Status Control (00) – Controls of the operation mode
1
Table 13. Chip Status Control (00)
Bit Signal Name Function Comments
0: normal mode
B7 stby Stand-by power mode
1: stby power mode

id
External modulation control for transmission and IQ or
B6 direct Direct data mode
bit stream output for reception
0: DAC off

al
B5 dac_on DA converter enable
1: DAC on
B4

lv
0: AGL off
B3 agl_on AGL mode enable
1: AGL on
0: AGC off
B2 agc_on AGC select

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1: AGC on
B1 rec_on Receiver enable Receiver is enabled

st
B0
te G
rf_on TX and RX enable TX RF field and receiver are enabled
on A
1. Reset to 00 at EN=L or POR=H nt
Protocol Control (01) – Controls the RFID protocol selection, operation of Tari10 bits is defined with Prot10 bits.
lc s

1
Table 14. Protocol Control (01)
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Bit Signal Name Function Comments

0: RX CRC (generate interrupt)
B7 rx_crc_n Receiving without CRC
1: No RX CRC (interrupt and no CRC truncation)
0: Output is bit stream and clock from the selected
B6 dir_mode Direct mode type decoder
1: Output is sub-carrier data.
B5 Prot1 00: EPC Gen2 / ISO18000-6C: Tari 6.26/12.5/25us,
FM0, M2, M4, M8
Protocol selection
B4 Prot0 01:
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10: ISO18000-6A/B:, A/B FM0 decoder in direct mode

B3 RX_cod1 00: FM0
01: Miller 2
RX decoding select (Gen2)
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B2 RX_cod0 10: Miller 4

11: Miller 8
B1 Tari1 00: Tari=6.25µs (Gen2, ISO-C)
ch

Tari (Gen2) 01: Tari=12.5µs (Gen2, ISO-C)

B0 Tari0 10: Tari=25µs (Gen2, ISO-C)

1. Preset to 06 (Gen2, Miller2, Tari=25µs) at EN=L or POR=H

Te

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8.3 Control Registers - Low Level Configuration Registers

TX Options (02) – Gen2
1
Table 15. TX Options (02)
Bit Signal Name Function Comments
B7 TxPw1 00: 0.27Tari
01: 0.35Tari
PW length control
10: 0.44Tari

id
B6 TxPw0
11: 0.50Tari
B5 TxOne1 00: 1.50Tari

al
01: 1.66Tari
TX one length control
B4 TxOne0 10: 1.83Tari
11: 2.00Tari

lv
0: CRC-16
B3 Tx-CRC TX CRC type
1: CRC-5
Normally TRcal is automatically transmitted when

il
Query (98) direct command is issued, according to
EPC Gen2 and ISO18000-6C.

st
B2 Force_TRcal TRcal period in normal transmission
te G In case Force_TRcal=1 the TRcal period is
transmitted also in normal data transmission (direct
commands 90, 91)
on A
B1 S1
nt Session bits Used for Gen 2 direct commands
B0 S0
lc s

1. Preset at POR=H or EN=L

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Gen2: F0 (TxPW=0.5 Tari, TxOne=2 Tari)

RX Options (03) - Gen 2

1
Table 16. RX Options (03)
Bit Signal Name Function Comments
B7 Rx_LF3 0000: 40kHz
B6 Rx_LF2 0110: 160kHz
Link frequency selection 1001: 256kHz
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B5 Rx_LF1 1100: 320kHz

B4 Rx_LF0 1111: 640kHz
B3 Shorten pilot measurement interval to 1/2, 1/4, 1/8.
pil_meas_sh<1:0> Shorter pilot measurement
ni

B2 Available intervals are 80, 40, 20, 10, 5 LF periods.

0: Short preamble
1: Long preamble
ch

B1 TRext RX preamble length

Short preamble is supported for Miller 4 and Miller 8
coding.
B0 don’t care Set to 0
Te

1. Preset at POR=H or EN=L

Gen2: 60 (160kHz)

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TRcal Low Register (04) – Gen2

1
Table 17. TRcal Low Register (04)
Bit Signal Name Function Comments
B7 TRcal7
Gen2: 17.2µs…225µs
B6 TRcal6
B5 TRcal5

id
B4 TRcal4
B3 TRcal3

al
B2 TRcal2 TRcal range 0.1µs…409µs (1…4096 steps)
B1 TRcal1 step size 0.1µs worst case relative resolution (0.1µs/
17.2µs=0.6%)

lv
B0 TRcal0

1. Preset at POR=H or EN=L

Gen2: 35 (1333 steps: 133.3µs, DR=64/3(bit DR=1) => LF=160µs)

il
st
TRcal High and Miscellaneous Register (05) – Gen 2
te G
Table 18. TRcal High and Miscellaneous Register (05)
1
on A
Bit Signal Name Function Comments
nt 0: Decrease
B7 gain<3> RX gain direction
1: Increase gain by option bits gain<5:4> in reg0A
lc s

0: 4.8V
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B6 vext_low Decrease VDD_MIX 1: 3.7V, also differential mixer adaptation to low

supply
When high decreases output resistance of logic
Supports low peripheral
B5 vdd_io_low outputs. Should be set high when VDD_IO voltage is
communication voltage
below 2.7V.
B4 open_dr Open drain N-MOS outputs Valid for CLSYS, OAD, OAD2 pins
B3 TRcal11
B2 TRcal10
(see Table 17 on page 27)
B1 TRcal9
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B0 TRcal8

1. Preset at POR=H or EN=L

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Gen2: 05
ch
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Delayed Transmission Wait Time (06)

1
Table 19. Delayed Transmission Wait Time (06)
Bit Signal Name Function Comments
B7 Txdel7
B6 Txdel6
TX reply range 6.4µs to 1632µs (1…255), Start at end of
B5 Txdel5
RX.
B4 Txdel4 00: Delayed transmission is disabled.

id
Delayed transmission wait time
B3 Txdel3
Gen2: T2=4.68µs…500µs after end of RX,
B2 Txdel2

al
Select T4>31.2…150µs after end of TX
B1 Txdel1
B0 Txdel0

lv
1. Preset at POR=H or EN=L
Gen2: 00

il
RX No Response Wait Time (07) – Defines the time when ‘No Response’ interrupt is sent.

st
Table 20. RX No Response Wait Time (07)
te G 1

Bit Signal Name Function Comments

on A
B7 NoResp7
nt Defines the time when ‘no response’ interrupt is sent. It
B6 NoResp6 starts from the end of TX.
lc s

B5 NoResp5
RX no response wait range is 25.6µs to 6528µs (1…255),
am

B4 NoResp4 Step size 25.6µs

No response wait time
B3 NoResp3
Interrupt is sent in case the time runs out before 6-10
B2 NoResp2 periods of link frequency is detected.
B1 NoResp1
B0 NoResp0 Gen2: T1max=23.6µs…262µs

1. Preset at POR=H or EN=L

Gen2: 07 (179.2µs > 54.25µs…84.5µs + 10 periods – LF:160kHz)
ca

RX Wait Time (08) – Defines the time after TX when the RX input is disregarded.
1
Table 21. RX Wait Time (08)
ni

Bit Signal Name Function Comments

B7 Rxw7 Defines the time during which the RX input is ignored. It
ch

B6 Rxw6 starts from the end of TX.

B5 Rxw5
RX wait range is 6.4µs to 1632µs (1…255),
B4 Rxw4 Step size 6.4µs,
RX wait time
Te

B3 Rxw3 00: receiver enabled immediately after TX.

ISO 1800-6C(Gen2)
B2 Rxw2
Gen2: T1min=11.28µs…262us,
B1 Rxw1 ISO 1800 - 6A: 150…1150µs
B0 Rxw0 ISO 1800 - 6B: 85…460µs

1. Preset at POR=H or EN=L

Gen2: 07(44.8µs < 54.25µs…84.5µs – LF:160kHz)

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Datasheet - A p p l i c a t i o n I n f o r m a t i o n

RX Filter (09)
1
Table 22. RX Filter (09)
Bit Signal Name Function Comments
B7 byp160 Bypass for 160kHz LF
B6 byp40 Bypass for 40kHz LF
B5 lp3

id
B4 lp2 Low pass setting
see DRM RX Filter on page 18
B3 lp1

al
B2 hp3
B1 hp2 High pass setting

lv
B0 hp1

1. Preset at POR=H or EN=L

Gen 2:41

il
st
RX Special Setting2 (0A)

Table 23. RX Special Setting2 (0A)

te G 1
on A
Bit Signal Name Function Comments
B7
nt
gain<5> Gain change, 3 steps by 3dB, Increase/decrease
RX gain setting
defined by gain<3> option bit in reg05
lc s

B6 gain<4>
B5 gain<2>
am

B4 gain<1> Digitizer hysteresis setting Hysteresis increase, 7 steps by 3dB

B3 gain<0>
0: differential input mixer
B2 s_mix Mixer input selection
1: single ended input mixer
B1 ir<1> Differential mixer gain increase 10dB gain increase
8dB attenuation using differential mixer,
B0 ir<0> Mixer input attenuation
5dB attenuation using single ended input mixer
ca

1. Preset to 01 (Max gain, mixer range) at POR=H or EN=L

ni
ch
Te

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Regulator and I/O Control (0B)

1
Table 24. Regulator and I/O Control (0B)
Bit Signal Name Function Comments
B7 reg for VDD_RF current source
B6 reg2v<1> 00: 2V
Internal power amplifier regulator 01: 2.5V
setting 10: 3V

id
B5 reg2v<0>
11: 3.5V
0: RFOUT1 only
B4 etx<4> PA2 enable

al
1: differential RFOUT1 and RFOUT2
B3 etx<3> 00: disabled
Enable for main PA and current for 01:7mA

lv
B2 etx<2> main PA pre-driver 10: 14mA
11: 22mA
B1 etx<1> 00: disabled

il
Enable for low power output and
01:7mA
current for auxiliary driver low power
B0 etx<0> 10: 14mA

st
te G output
11: 22mA

1. Preset to 02 (Medium driver current) at POR=H or EN=L

on A
nt
8.4 Status Registers
lc s

IRQ and status register (0C) displays the cause of IRQ and TX / RX status.
1
am

Table 25. IRQ and Status Register (0C)

Bit Signal Name Function Comments
Signals the TX is in progress. Interrupt when TX is
B7 Irq_tx IRQ set due to end of TX
finished.
Signals the RX was received and RX is in progress.
B6 Irg_srx IRQ set due to RX start
Interrupt when RX is finished.
Signals FIFO high or low (less than 6 or more than
B5 Irq_fifo Signals the FIFO is 3/4<FIFO <1/4
18)
B4 Irq_err1 CRC error Reception CRC
ca

Received header bit is high /

Irq_header / Header bit /
B3 nd Two bytes already in FIFO – in case
Irq_2 _byte 2 bytes
fifo_dir_irq2=1(reg1A)
ni

Signals to MCU that reception was shorter than

B2 Irq_err2 RX count error
expected (see RX length (1A, 1B) register definition)
ch

Signals to MCU that there was an error during

Irq_err3 / Preamble detect error /
B1 preamble detection /
Irq_RX_finished RX finished
Rx is finished – in case fifo_dir_irq2=1(reg1A)
B0 Irq_noresp No response interrupt Signals to MCU that next slot command can be sent.
Te

1. Preset to 00 at POR=H or EN=L. It is automatically reset at the end of read phase. The reset also removes the IRQ flag.

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Interrupt Mask Register (0D)

1
Table 26. Interrupt Mask Register (0D)
Bit Signal Name Function Comments
B7
IRQ enabled by default
B6
When enabled, AS3992 will generate an active high Interrupt when the FIFO is getting low (6
B5 e_irq_fifo

id
Bytes left to send on transmit operation) or is getting full over 18 bytes on receive operation.
When enabled, AS3992 will generate an active high Interrupt when the device detects an
B4 e_irq_err1
CRC error (This option will report no crc error when receive without crc is enabled).

al
When enabled, AS3992 will generate an active high Interrupt when the device detects an error
B3 e_irq_header
into the header Bit of the Tag reception.

lv
When enabled, AS3992 will generate an active high Interrupt when the length of the received
B2 e_irq_err2 Bit stream from the Tag has been shorter than expected in the RX length configuration. Such
event occurs, for example, if the Tag is not powered sufficiently.
When enabled, AS3992 will generate an active high Interrupt in case the device detects an

il
B1 e_irq_err3
error during preamble reception.

st
When enabled, AS3992 will generate an active high Interrupt in case no Tag has been
B0
te G
e_irq_noresp
answered.
on A
1. Preset to 37 at POR=H and EN=L
nt
AGC and Internal Status Register (0E)
lc s

Table 27. AGC and Internal Status Register (0E)

am

Bit Signal Name Function Comments

B7 rfu
B6 agc<2>
AGC status 7 steps, 3dB per step
B5 agc<1>
B4 agc<0>
0: REC_A
Shows the source of the subcarrier 1: REC_B
B3 in_select
signal that is used for decoding. Value is valid from reception start till start of next
ca

transmission
B2 rf_ok RF level stable
B1 pll_ok PLL locked
ni

B0 osc_ok Crystal oscillator stable

ch
Te

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RSSI Levels Register (0F) – Displays the signal strength on both reception channels.
1
Table 28. RSSI Levels Register (0F)
Bit Signal Name Function Comments
B7 rssi<7>
B6 rssi<6>
RSSI value of Q channel (REC_B) (16 steps, 2dB per step)
B5 rssi<5>

id
B4 rssi<4>
B3 rssi<3>

al
B2 rssi<2> RSSI value of I channel
(16 steps, 2dB per step)
B1 rssi<1> (REC_A)

lv
B0 rssi<0>

1. The RSSI values are valid from the start of reception till start of next transmission.

il
AGL / VCO / F_CAL / PilotFreq Status Register (10) – in case r10page<1:0>=00 (reg12) displays the status of the AGL.

st
te G
Table 29. AGL / VCO / F_CAL / PilotFreq Status Register (10)
Bit Signal Name Function Comments
on A
B7
B6
nt
lc s

B5 agl<5>
B4 agl<4> AGL status - REC_A 7 steps, 3dB per step
am

B3 agl<3>
B2 agl<2>
B1 agl<1> AGL status - REC_B 7 steps, 3dB per step
B0 agl<0>

AGL / VCO / F_CAL / PilotFreq Status Register (10) – in case r10page<1:0>=01 (reg12) displays the status of the internal VCO.
Table 30. AGL / VCO / F_CAL / PilotFreq Status Register (10)
ca

Bit Signal Name Function Comments

B7 vco_ri<7>
B6 vco_ri<6>
ni

VCO automatic range select result 16 steps

B5 vco_ri<5>
B4 vco_ri<4>
ch

0: 900 MHz VCO

B3 vco_ri<3> Internal VCO type
1: 1800 MHz VCO
B2 vco_ri<2>
Te

B1 vco_ri<1> VCO pin voltage measurement 7 steps, step size 0.4V

B0 vco_ri<0>

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AGL / VCO / F_CAL / PilotFreq Status Register (10) – in case r10page<2:0>=2 (reg12) displays the result of RX filter calibration.
Table 31. AGL / VCO / F_CAL / PilotFreq Status Register (10)
Bit Signal Name Function Comments
B7
B6
hp_cal<3:0> High pass calibration data 16 steps, step size 4%
B5
B4

id
B3
B2
lp_cal<3:0> Low pass calibration data 16 steps, step size 4%

al
B1
B0

lv
AGL / VCO / F_CAL / PilotFreq Status Register (10) – in case r10page<2:0>=3 (reg12) displays the result of RX filter calibration.
Table 32. AGL / VCO / F_CAL / PilotFreq Status Register (10)

il
Bit Signal Name Function Comments
B7

st
B6
te G
B5
on A
B4
nt
pilot_freq<7:0>
RX pilot frequency measurement
result
Typical value 160
B3
lc s

B2
B1
am

B0

Version Register (13)

30: AS3990
38: AS3991
51: AS3992

8.5 Test Registers

ca

Measurement Selection (11)

1
Table 33. Measurement Selection (11)
ni

Bit Signal Name Function Comments

B7
ch

B6
B5
B4
Te

B3 msel<3> rfu
B2 msel<2> 000: None
011: ADC pin
B1 msel<1>
ADC measurement selection 001: Rec. A mixer DC
B0 msel<0> 100: Internal RF level
111: VEXT level

1. Default: Reset to 00 at POR=H and EN=L

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Test Setting (12) – (three bytes deep)

Sets special connections for test or direct chip use. Should be low for normal operation.
1
Table 34. Test Setting (12)
Bit Signal Name Function Comments
Reserved for future use; set 0 for correct device
23:17 rfu
operation.

id
0: agl<5:0>
1: vco_r<7:0>
16 r10page<2> Page reg10 selection extension
2: hplp_cal<7:0>

al
3: pilot_freq
00: agl
15:14 r10page<1:0> Page reg10 selection
01: VCO range presented in reg10

lv
Reserved for future use; set 0 for correct device
13:0 rfu
operation.

il
1. Default: reset to 00 00 00 at POR=H and EN=L

st
TX Pre-Distortion (13), Deep register
te G
1
Table 35. TX Pre-Distortion (13)
on A
Bit Signal Name
nt Function Comments
Should be written in one continuous write,
lc s

251:1byte ramdat Pre-distortion shape including byte 0, byte1=0, byte 251=250, write at
use_corr=0 (reg15).
am

0 byte reg13_0 rfu First byte in register 13.

1. Default: First byte preset to 30/35/37/38/50/51 at POR=H and EN=L. Others bytes not cleared.
ca
ni
ch
Te

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8.6 PLL, Modulator, DAC, and ADC Registers

CL_SYS, Analog Out and CP Control (14) – (three bytes deep)
1
Table 36. CL_SYS, Analog Out and CP Control (14)
Bit Signal Name Function Comments
00 – normal operation with auto power saving
mode
23:22 xosc<1:0> Crystal oscillator adaptation
01 – External sinus TCXO AC coupled to OSCO

id
10 – Disable auto power saving mode
21 rfu rfu

al
cp<4> – disable ½ cp out – test, should be low for
20 rfu rfu
normal operation

lv
Manual selection of the VCO range segment.
19:16 vco_r Manual VCO range selection
Used in case auto=0
L-H transition triggers the automatic selection of
15 auto Automatic VCO range enable
the VCO range segment

il
14 h2 Auto range selection speed-up

st
13
12
h6
ozko
te G Auto range selection speed-up
Auto range selection mode
on A
11 mvco VCO measurement enable 7 steps, result in reg10
nt 00: min. bias current (~1.3mA)
10:9 eosc<2:1> Internal oscillator bias current
11: max. bias current (~5mA)
lc s

8 clsys2 000: Off

001: 5MHz
am

7 clsys1
CLSYS output frequency 010: 10MHz
6 clsys0 011: 20MHz
100: 4MHz
5 e_anamix Analog mixer DC output on OAD/OAD2
4 e_anasubc Analog sub-carrier out on OAD/OAD2
0: increasing with VCO voltage
3 cp<3> VCO frequency dependence
1: decreasing with VCO voltage
000: 150µA
ca

001: 300µA
010: 600µA
011: 1200µA
2:0 cp<2:0> Charge pump current
100: 1350µA
ni

101: 1500µA
110: 1800µA
111: 2350µA
ch

1. Preset at POR=H or EN=L

Default setting: 00 04 40 (Medium VCO bias, CLSYS: 5MHz, min. CP current)
Te

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Modulator Control Register (15) – (three bytes deep)

1
Table 37. Modulator Control Register (15)
Bit Signal Name Function Comments
0: IO3 is digital modulation input in direct mode.
23 e_amod Analog modulation 1: ADC is analog mod. input in direct mode (allowed
when ADC not used).
22 main_mod Modulation connected to main TX

id
21 aux_mod Modulation connected to aux. TX
20 tpreset Test bit Should be low for normal operation

al
19 use_corr TX pre-distortion enable
18 e_lpf Enable low pass filter

lv
00: Tari determined
01: Skip 2
17:16 ask-rate<1:0> ASK Modulation transient rate
10: Skip 4

il
11: Skip 8
Default is shaped modulation transient for ASK and

st
15 lin_mod
te G Selects linear modulation transient
PR-ASK modulation.
In case Tari is 25µs, the ook_ask bit defines delimiter
on A
transient in PRASK modulation mode: ook_ask=1
forces ASK shaped transient, ook_ask=0 forces
nt PRASK shaped transient. In case Tari is 12.5µs or
6.25µs, the ASK delimiter transient is used
lc s

14 pr-ask PR-ASK enable regardless ook_ask bit value.

ASK shaped delimiter transient offers correct and
am

adjustable delimiter length. The TX spectrum is not

affected to a visible level due to ASK delimiter
transient. Other field transitions are done in PRASK
mode.
in case pr_ask=0 and ook_ask=0: 00…3E: ASK
modulation depth, 3F: 100%
ASK modulation depth/
13:8 mod_dep<5:0> in case pr_ask=1 or ook_ask=1: Adjust delimiter
PR delimiter adjust
length, range 9.6µs to 15.9µs, step 0.1µs.
1D=12.5µs
ca

00: Tari determined

01: 100µs
7:6 trfon<1:0> RF on/off transition time
10: 200µs
11: 400µs
ni

100% ASK enable with variable delimiter Enforces 100% ASK modulation depth, bits <13:8>
5 ook_ask
length are used to adjust the delimiter length
ch

00: 0dB, nominal

4:3 tx_lev<4:3> TX output level coarse adjustment 10: -12dB
01: -6dB
2:0 tx_lev<2:0> TX output level fine adjustment 0: nominal, decrease: 1…7: -1dB...-7dB, step 1dB
Te

1. Preset at POR=H and EN=L

Default: set to 20 3F 00 (aux. modulation, ASK, level nominal)

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PLL R, A/B Divider Main Register (16) – (three bytes deep)

1
Table 38. PLL R, A/B Divider Main Register (16)
Bit Signal Name Function Comments
23 ai2x Increase internal PA bias Increase two times
000: 500kHz
001: 250kHz
100: 200kHz

id
22:20 RefFreq<2:0> PLL reference divider 010: 125kHz
101: 100kHz
110: 50kHz

al
111: 25kHz
19:10 B value Prescaler 32/33,
PLL main divider dividing ratio N=B*32+A*33, proposed A/B ratio: 1/

lv
9:0 A value 3…3

1. Preset at POR=H and EN=L

Default: set to 40 D8 4F (R: 200kHz, N: 4335: 54*32+79*33 =>867MHz)

il
st
te G
PLL A/B Divider Auxiliary Register (17) – (three bytes deep)
1
Table 39. PLL A/B Divider Auxiliary Register (17)
on A
Bit Signal Name Function Comments
nt
23 ai4x Increase internal PA bias Increase four times
lc s

0: normal VCO connection

22 lev_vco VCO signal adjustment
1: direct VCO connection
am

0: Internal VCO
21 eext_in Enable external RF input EXT_IN
1: External RF source is used.
20 epresc Enable divider and prescaler 1: In case internal PLL drives external VCO
19:10 B value Prescaler 32/33,
PLL main divider dividing ratio N=B*32+A*33, proposed A/B ratio: 1/
9:0 A value 3…3

1. Preset at POR=H and EN=L

Default: set to 01 18 46 (R: 200kHz, N: 4550: 70*32+70*33 =>910MHz)
ca

DAC Control Register (18)

1
Table 40. DAC Control Register (18)
ni

Bit Signal Name Function Comments

B7 dac<7>
ch

B6 dac<6>
B5 dac<5>
B4 dac<4>
Te

DAC control value

B3 dac<3>
B2 dac<2>
B1 dac<1>
B0 dac<0>

1. Default: reset to 00 at POR=H and EN=L

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ADC Readout Register (19)

Table 41. ADC Readout Register (19)
Bit Signal Name Function Comments
B7 adc<7>
Via ADC the two mixers output DC levels can be
B6 adc<6>
measured showing the reflectivity of the antenna or
B5 adc<5> the environment. Also DC level on ADC pin can be
B4 adc<4> measured. The later case can be used for checking

id
ADC readout the RF output power via external power detector. The
B3 adc<3> measurement is selected using msel<2:0> bits. The
B2 adc<2> measurement is triggered by the ‘Trigger ADC

al
conversion’ command (87). Result is valid 20µs after
B1 adc<1> triggering.
B0 adc<0>

lv
8.7 RX Length Registers
RX Length 1 (1A)

il
1
Table 42. RX Length 1 (1A)

st
Bit
te G
Signal Name Function Comments
Temporary receiving without CRC. Valid for a single
B7 rx_crc_n2 Receiving without CRC
on A
nt reception.
All bytes including CRC are transferred to FIFO,
nd nd
B6 fifo_dir_irq2 Direct FIFO and 2 byte IRQ irq_header is changed to irq_2 byte, irq_err3 is
lc s

changed to irq_RX_finished. For PC+EPC reception

B5
am

B4
B3
B2
B1 rxl<9>
RX length
B0 rxl<8>

1. Default: reset to 00 at POR=H, EN=L, at the end of reception.

ca

RX Length 2 (1B)
1
Table 43. RX Length 2 (1B)
ni

Bit Signal Name Function Comments

B7 rxl<7>
ch

B6 rxl<6>
B5 rxl<5>
B4 rxl<4>
RX length
Te

B3 rxl<3>
B2 rxl<2>
B1 rxl<1>
B0 rxl<0>

1. Default: reset to 00 at POR=H, EN=L, at the end of reception.

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8.8 FIFO Control Registers

FIFO status – adr 1C hex number of received bytes and FIFO flags.
1
Table 44. FIFO Status- adr 1C hex
Bit Signal Name Function Comments
B7 Fhil High FIFO level Indicates that 18 bytes are in FIFO already (for RX)
B6 Flol Low FIFO level Indicates that only 6 bytes are left in FIFO (for TX)

id
B5 Fove FIFO overflow error Several data is written to FIFO
B4 Fb4 FIFO bytes fb[4]

al
B3 Fb3 FIFO bytes fb[3]
B2 Fb2 FIFO bytes fb[2] How many bytes loaded in FIFO were not read out yet

lv
B1 Fb1 FIFO bytes fb[1]
B0 Fb0 FIFO bytes fb[0]

il
1. Default: reset to 00 at POR=H and EN=L

st
te G
TX length byte1 – adr 1D hex high 2 nibbles of complete bytes, which will be transferred through FIFO.
1
Table 45. TX Length Byte1 - adr 1D hex
on A
Bit Signal Name Function Comments
nt
B7 Txl11 Number of complete byte– bn[11]
lc s

B6 Txl10 Number of complete byte– bn[10] High nibble of complete bytes to be transmitted or
Number of complete byte– bn[9] received.
am

B5 Txl9
B4 Txl8 Number of complete byte– bn[8]
B3 Txl7 Number of complete byte– bn[7]
B2 Txl6 Number of complete byte– bn[6] Middle nibble of complete bytes to be transmitted
B1 Txl5 Number of complete byte– bn[5] or received.

B0 Txl4 Number of complete byte– bn[4]

1. Default: reset to 00 at POR=H and EN=L. It is also automatically reset at TX EOF

ca
ni
ch
Te

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TX Length Byte2 – adr 1E hex low nibbles of complete bytes, which will be transferred through FIFO and information if there is broken byte and
how many bits from it should be transferred.
1
Table 46. TX Length Byte2 - adr 1E hex
Bit Signal Name Function Comments
B7 Txl3 Number of complete byte– bn[3]
B6 Txl2 Number of complete byte– bn[2] Low nibble of complete bytes to be transmitted

id
B5 Txl1 Number of complete byte– bn[1] or received.

B4 Txl0 Number of complete byte– bn[0]

al
B3 Bb2 Broken byte number of bits bb[2] Number of bits in the last (broken) byte to be
transmitted or number of bits that is valid in the
B2 Bb1 Broken byte number of bits bb[1]
last (broken) received byte. It is taken into

lv
B1 Bb0 Broken byte number of bits bb[0] account only when broken byte flag is set.
1: indicates that last byte is not complete 8 bit
B0 Bbf Broken byte flag
wide.

il
1. Default: reset to 00 at pro=H and EN=L

st
te G
Note: For transmission, the register 1E is write only. The written value is used for the transmission but can not be read out by the micro con-
troller. For reception bits B0 to B4 are read only. The value read out is the number of valid bits in the last received byte. Bits B0 to B4
on A
are updated at the end of the last successful reception. In case the last received byte is not complete, the valid bits are on the LSB side.
nt
FIFO I/O Register – adr 1F hex 24 bytes FIFO register filled and read in cyclical way.
lc s

8.9 Direct Commands

Table 47 lists out the direct commands that are supported in the UHF reader IC.
am

Table 47. Command Codes

1 Command Comments
Cmd (hex)
80 Idle
84 Hop to main frequency
85 Hop to auxiliary frequency
87 Trigger AD conversion
ca

88 Trigger RX filter calibration

89 Decrease RX filter calibration data
8A Increase RX filter calibration data
ni

8F Reset FIFO
90 Transmission with CRC
ch

91 Transmission with CRC expecting header bit (Gen2 RX)

92 Transmission without CRC
93 Delayed transmission without CRC (not used in EPC Gen2)
Te

94 Delayed transmission with CRC (not used in EPC Gen2)

96 Block RX
97 Enable RX
98 Query (=TX with TX CRC5, no RX CRC)
99 QueryRep (=TX no TX CRC, no RX CRC)

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Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Table 47. Command Codes

1 Command Comments
Cmd (hex)
9A QueryAdjustUp (=TX no TX CRC, no RX CRC)
9B QueryAdjustNic (=TX no TX CRC, no RX CRC)
9C QueryAdjustDown (=TX no TX CRC, no RX CRC)
9D ACK (repeat) RN 16

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9E NAK
9F ReqRN

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1. Value in this column includes the command bit (MSB) high.

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8.9.1 Idle (80)
Command

8.9.2 Hop to Main Frequency (84)

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This command forces the PLL to use frequency setting in ‘PLL A/B divider main register’ (see Table 38). This is also the default setting.

st
8.9.3 Hop to Auxiliary Frequency (85)
te G
This command forces the PLL to use frequency setting in ‘PLL A/B divider auxiliary register’ (see Table 39).
on A
8.9.4 Trigger AD Conversion (87)
nt
This command triggers the analog to digital conversion with the internal 8-bit AD converter. Conversion result is available in the ‘ADC readout
register’ (19) (see Table 41). The source for the AD conversion is defined with msel<2:0> bits in the ‘Test setting 1 register’ (11) (see Table 33).
lc s

With this command it is possible to measure the both mixers output DC levels (msel<2:0>=001 and 010) and DC value on the pin ADC
(msel<2:0>=011). The first two possibilities are used for diagnostic purposes. Reflectivity of the antenna or antenna environment, or leakage of
am

the directional device causes reflection of the transmitted carrier towards receivers input. The mixers DC levels are defined with the amplitude
and phase of the incoming carrier. The ADC pin is direct input to the AD converter. The input can be used to connect the external power detector
for measuring the actual transmitted power. Other msel<2:0> combinations are used for test purposes.

8.9.5 Trigger RX Filter Calibration (88)

The command triggers the RX filter calibration cycle. The calibration cycle is finished after t.b.d. Result is available in reg10.

8.9.6 Decrease RX Filter Calibration Data (89)

After RX filter calibration (88), the host system (MCU) can decrease the automatically selected time constant by sending direct command 89 to
fine adjust the filters. The option bit f_cal_hp_chg in reg12 defines whether the calibration data change triggered by command 89 will affect the lp
ca

or hp part of the filter. Sending one command 89 decreases calibration data for one step. There are 16 steps available, step size is 4%. Result is
available in reg10.

8.9.7 Increase RX Filter Calibration Data (8A)

ni

After RX filter calibration (8A), the host system (MCU) can increase the automatically selected time constant by sending direct command 8A to
fine adjust the filters. The option bit f_cal_hp_chg in reg12 defines whether the calibration data change triggered by command 89 will affect the lp
or hp part of the filter. Sending one command 8A increases calibration data for one step. There are 16 steps available, step size is 4%. Result is
ch

available in reg10.

8.9.8 Reset FIFO (8F)

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The reset command clears the FIFO pointers and all IRQ flags. It also clears the register storing the error (collision) location.

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8.9.9 Transmission With CRC (90)

The transmission commands are used to transmit data from the reader to the transponders. First the registers ‘Tx length’ (1D, 1E) need to be set
with the number of bytes for transmission, including data on broken bytes. Then transmission data can be loaded to FIFO register (1F).
Transmission starts when the third byte is written in the FIFO. Transmission of short messages (less than three bytes) is started when complete
data is in the FIFO. When the command is received the reader starts transmitting. CRC-16 is included in the transmitted sequence. In this mode
the micro controller has control on precise timing.
Optimal way to load transmission data is use of Continuous Write mode, starting from address 1D. Example 90 3D 00 30 AA BB CC operates as
follows: Transmit with CRC, write 00 to 1D and 30 to 1E (three bytes are going to be transmitted), and write AA, BB, CC to address 1F (FIFO,

id
data that will be transmitted). Continuous write command must be terminated by ‘Continuous stop condition’. Transmission starts when the data
is in the FIFO.

8.9.10 Transmission With CRC Expecting Header Bit (91)

al
This command functions similar to Transmission with CRC (90), but also informs RX decoding logic that header bit is expected in the response
(Gen 2).

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8.9.11 Transmission Without CRC (92)
This command functions similar to Transmission with CRC (90), but CRC is excluded.

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8.9.12 Delayed Transmission With CRC (93)
Delayed transmission is used in case the transmission needs to be started in a quite narrow time window after end of reception. The time

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between end of reception and start of transmission is set in register ‘Delayed transmission wait time’ (06) (see Table 19). The register 06 needs
to be set prior to the reception after which the delayed transmit should be done. After sending the ‘Delayed transmission with CRC’ the TX length
bytes must be set and transmission data needs to be loaded in the FIFO. The reader transmitting is triggered by the TX timer.
on A
Example: 93 3D 00 40 AA BB CC DD will transmit AA BB CC DD and CRC. Transmission will start after delayed defined in reg 06. The delay
nt
time will start at the end of previous reception - despite the command is sent during the delay is already running out.
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8.9.13 Delayed Transmission Without CRC (94)

This command functions similar to Delayed transmission with CRC, but CRC is excluded.
am

8.9.14 Block RX (96)

The block RF command puts the digital part of receiver (bit decoder and framer) in reset. The reset of the receiver is useful in case the system
operates in an extremely noisy environment, causing a constant switching of the sub-carrier input of the digital part of the receiver. The receiver
(if not in reset) would try to ‘catch’ a Preamble and in case the noise pattern matches the expected signal pattern, an interrupt is sent. A constant
flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders
in reset mode. The reset mode can be terminated in two ways. One possibility is that the external system sends the ‘Enable RX’ command. The
reset mode is also automatically terminated at the end of TX operation. The receiver can stay in reset also after end of TX if the ‘RX wait time’
registers (address 08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation.
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8.9.15 Enable RX (97)

This command clears the reset mode in the digital part of the receiver, if the reset mode was entered on the request by the ‘Block RX’ command.

8.10 EPC GEN2 Specific Commands

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8.10.1 Query (98)

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The Query command must be followed by 3F (continuous FIFO write) and two bytes of query data (00, DR, M, TRext, Sel, Session, Target, Q).
Since this gives 15 applicable bits the last LSB bit is disregarded. Transmitter issues preamble, command, TX data and CRC-5. The received
RN16 is stored in an internal register for further communication (ACK…). RN 16 is also achievable from the FIFO.

8.10.2 QueryRep (99)

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The QueryRep command issues the command followed by two session bits. The session bits are taken from ‘TX options’ (02) register. The
received RN16 is stored in an internal register for further communication (ACK). RN 16 is also achievable from the FIFO.

8.10.3 QueryAdjustUp (9A)

The QueryAdjustUp command issues the command QueryAdjust followed by two session bits and ‘up’ parameter (increase number of slots Q).
The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK…).
RN 16 is also achievable from the FIFO.

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8.10.4 QueryAdjustNic (9B)

The QueryAdjustNic command issues the command QueryAdjust followed by two session bits and ‘no change’ parameter. The session bits are
taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK). RN 16 is also
achievable from the FIFO.

8.10.5 QueryAdjustDown (9C)

The QueryAdjustUp command issues the command QueryAdjust followed by two session bits and ‘down’ parameter (decrease number of slots
Q). The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK,
ReqRN). RN 16 is also achievable from the FIFO.

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8.10.6 ACK (9D)
The ACK command issues the command followed by RN16 (or handle) that was stored in the internal register. The stored RN16 was acquired in
last successful Query command.

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8.10.7 NAK (9E)
The direct NAK command issues the NAK command to tags.

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8.10.8 ReqRN (9F)
The direct ReqRN command issues the ReqRN command to the tag. The last received RN is used as a parameter and the received new RN16

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(handle) is stored in an internal register for further communication (ACK, ReqRN…). New RN 16 is also achievable from the FIFO.

st
8.11 Reader Communication Interface
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The basic interface is a parallel 10-pin bus, which can be also configured and used as a serial peripheral interface (SPI) also. Both modes are
exclusive and one can not switch between them in a single application. The parallel mode is selected if all IO pins are low during low to high
on A
transition of the EN pin (enable).
nt
When the serial interface is selected in an application, the unused IO1 and IO0 pins should be hard wired according to Table 48. Upon power-up
(EN low to high transition), the reader looks for the status of these three pins and as given in Table 48, it enters parallel or serial mode.
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The reader will always behave as the “slave” connected to the host system (MCU), which behaves as the “master” device. The host system
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initiates all communications with the reader and is used for communication to the higher levels towards the host station, which can typically be a
personal computer. The reader has an IRQ pin to ask for host system attention.
Table 48. Pin Assignment in Parallel and Serial Interface Connection and in Case of Direct Mode

Parallel normal mode, 1

Pin SPI with SS ,
Direct mode Direct mode
CLK CLK SCLK from master
A/D[7] 2
IO7 MOSI (data in)
A/D[6], 3
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IO6 MISO (data out),

Direct mode out (sub-carrier) Direct mode out (sub-carrier)
A/D[5],
IO5 Direct mode out (sub-carrier)
Direct mode out (sub-carrier)
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IO4 A/D[4] SS – Slave Select

A/D[3]
IO3 Direct mode modulation input
ch

Direct mode modulation input

A/D[2]
IO2 Direct mode enable RX input
Direct mode enable RX input
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IO1 A/D[1] Hard wire to VDD_IO

IO0 A/D[0] Hard wire to ground
IRQ IRQ interrupt IRQ interrupt

1. SS – Slave Select pin active low

2. MOSI – Master Output, Slave Input
3. MISO – Master Input, Slave Output

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Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Communication is initialized by a Start condition, which should be followed by an Address or Command word. The Address and Command words
are 8-bits long. Their format is shown in Table 49. Communication is closed by an appropriate stop condition. Three different communication
modes are available – Continuous address mode, non-continuous address mode, and command mode. Continuous address mode needs to be
closed by StopCont condition, while the other two modes need to be terminated by StopSgl condition.
Table 49. Address / Command Word Bit Distribution
Bit Description Bit Function Address Command
7 Command control bit 0=Address, 1=Command 0 1

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6 Read/Write 1=Read, 0=Write R/W Not used
5 Continuous address mode 1=Cont., 0=Non-cont mode Cont Not used

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4 Address/Command bit 4 Adr 4 Cmd 4
3 Address/Command bit 3 Adr 3 Cmd 3

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2 Address/Command bit 2 Adr 2 Cmd 2
1 Address/Command bit 1 Adr 1 Cmd 1
0 Address/Command bit 0 Adr 0 Cmd 0

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The MSB (Bit 7) determines if the word is to be used as a command or address. The last two columns in Table 49 show the function of the

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separate bits in the event that either address or command is written. Data is expected once the address word is sent. In the event of continuous
address mode (Cont mode=1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the
address is incremented by one. This continuous mode can be used to write part of the control registers in a single stream without changing the
on A
address: for instance, set-up of the pre-defined standard control registers from the MCU’s non-volatile memory to the reader. In the case of non-
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continuous address, only one data word is expected after the address. The two address modes are used to write or read the configuration
registers or the FIFO. When writing or reading more than one byte the Continuous address mode should be used. The Command mode is used
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to enter a command resulting in reader action (initialize transmission, frequency hop…). Examples of expected communication between MCU
and reader chip are shown below:
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Continuous Address Mode

Start Adrc x Data (x) Data (x+1) Data (x+2) Data (x+3) Data (x+4) … Data (x+n) StopCont

Non-continuous Address Mode (Single Address Mode)

Start Adr x Data (x) Adr y Data (y) … Adr z Data (z) StopSgl

Command Mode
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Start Cmd x Cmd y … StopSgl

Where:
Start = start condition
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Adr = address with Cont bit low

Adrc = address with the Cont bit high
Cmd = command byte
ch

Data = data byte

StopSgl = stop condition for termination of the command or non-continuous address mode
StopCont = stop condition for termination of the continuous address mode
Te

There are also combinations of different communication modes allowed in a single stream between the start and stop condition. Some examples
of combined communication are presented below:
Non-continuous Address Mode and Command Mode

Start Adr x Data (x) Adr y Data (y) … Cmd z Cmd w StopSgl

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Command and Continuous Address Mode

Start Cmd x Cmd y … Adrc z Data (z) Data (z+1) … Data (z+n) StopCont

Non-continuous, Command, and Continuous Address Mode

Start Adr x Data (x) … Cmd y … Adrc z Data (z) Data (z+1) … Data (z+n) … StopSgl

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Non-continuous address mode and Command mode can be continued by any mode including the Continuous address mode. The Continuous
address mode should be terminated by StopCont condition. Changing from Continuous address mode to the other two modes can be done only
by StopCont condition followed by start condition.

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Majority of the registers in the reader IC are 8-bit long. They can be accessed by continuous or non-continuous address mode.
Registers 12, 14, 15, 16, and 17 are three bytes deep. They can be accessed by Continuous address mode only. The least significant byte is
accessed first. It is possible to access only deep register in a single communication stream, more of them, or combination of normal and deep

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registers. Example is presented below:

Start Adrc x 1 2 3 StopCont

Data0 (x) Data1 (x) Data2 (x)

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1. Least significant byte

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2. Middle byte
3. Most significant byte
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on A
Continuous access is possible for registers 00 to the end of the register 12. Register 13 is deep register and prevents continuous access over it
nt
to register 14. Continuous access is again possible from register 14 to the end of FIFO (address 1F).
The 24 bytes deep FIFO register can be accessed by Continuous address mode only. It is allowed to use communication stream combined of
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command mode and address mode. Example is combination needed for transmission composed of Reset FIFO, Transmit, write to 1D, 1E for
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transmission length, and continuously to 1F for filling FIFO with transmission data.

Start ResetFIFO Transmit Write Cont. to 1D Data (1D) Data (1E) Data FIFO (0) Data FIFO (1) … StopCont
8F 90 3D TX length TX data

8.12 Parallel Interface Communication

In parallel mode, the Start condition is triggered by rising edge of the IO7 pin while the CLK pin is high and IO6-IO0 are low. This is used to reset
the interface logic. Communication is terminated by StopSgl condition or StopCont condition. StopSgl condition is triggered by falling edge on
IO7 pin while CLK pin is high and IO6-IO0 are low. StopCont condition is triggered by successive rising and falling edge on IO7 pin while CLK
and IO6-IO0 are low. The ‘StopSgl’ condition is used to terminate the direct mode.
ca

Figure 6. Parallel Interface Communication with Single Stop Condition “StopSgl”

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Start condition StopSgl

ch

CLK

IO7 a1[7] d1[7] a2[7] d2[7] aN[7] dN[7]

Te

IO[6:0] a1[6:0] d1[6:0] a2[6:0] d2[6:0] aN[6:0] dN[6:0]

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Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Figure 7. Parallel Interface Communication with Continuous Stop Condition “StopCont”

Start condition Stop Cont

continuous mode

CLK

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IO7 a0[7] d0[7] d1[7] d2[7] d3[7] dN[7]

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IO[6:0] a0[6:0] d0[6:0] d1[6:0] d2[6:0] d3[6:0] dN[6:0]

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Figure 8. Data Output Only when CLK is High

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Stop Cont
Start condition
continuous mode
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CLK
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a0[7] d0[7] d1[7] d2[7] d3[7] dN[7]

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IO7

IO[6:0] a0[6:0] d0[6:0] d1[6:0] d2[6:0] d3[6:0] dN[6:0]

internal OE

Output Data
ca

valid Output data

ni
ch

Timing Requirements for Parallel Interface. While using parallel interface, there must always be a separation between CLK transitions
and IO0…IO7 transitions. Minimum time interval between transition on CLK and data lines is 100ns.
Minimum CLK high time interval is 300ns in periods when IO0…IO7 pins are used as data outputs (see Figure 8) or 100ns in periods when
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IO0…IO7 pins are used as inputs (address, command, or register write).

To decrease interferences between MCU communication and RF part of the chip, the output resistance of IO0…IO7 lines is 400Ω typical and
800Ω maximum. The firmware designer should be aware of the fact that in case higher capacitance are connected to these pins, then possibly
longer CLK high intervals are needed to allow settling of the output level.

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8.13 Serial Interface Communication

In serial interface IO4 pin enables the communication, CLK pin is serial data clock, IO7 is serial data input, and IO6 is serial data output.
The interface is in reset as long the IO4 pin is high. Communication is started by falling edge on the IO4 pin. Data coming from the host system
is sampled on the falling of the CLK pin. When reading out the data from the UHF chip, the data is set on the rising edge of the CLK pin. Host
system (MCU) should sample the data on the falling edge on the CLK pin. Communication is terminated by rising edge on the IO4 pin. All words
are 8-bits long with the MSB transmitted first.

Figure 9. Serial Interface Communication

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Start Stop
condition condition

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CLK

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IO7 x b7 b6 b5 b4 b3 b2 b1 b0 x

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IO4
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IO6 z7 z6 z5 z4 z3 z2 z1 z0 x
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In this mode the serial interface is in reset while the IO4 signal is high. CLK pin is serial data clock, IO7 is serial data in, and IO6 is serial data
output. Communication is terminated when IO4 signal goes high again.

Timing Requirements for Serial Interface. Minimum time interval between IO4 falling edge and first CLK change is 100ns.
Minimum CLK high time interval is 300ns in periods IO6 pin is used as data output (like register reading – data from UHF chip to MCU) or 100ns
in periods when IO7 pin is used as input (address, command, or register write – data from MCU to UHF chip). Minimum CLK low interval is
100ns.
ca

To decrease interferences between MCU communication and RF part of the chip the output resistance of IO6 line is 400Ω typical and 800Ω
maximum. The firmware designer should be aware that in case of higher capacitance is connected to this pin possibly longer CLK high interval is
needed to allow settling of the output level.
Minimum hold time (time in which IO6 output data is valid after the CLK fall edge) is 130ns.
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Minimum time interval between bytes is 200ns.

Minimum time interval between last CLK falling edge and IO4 rising edge is 200ns.
ch

Minimum IO4 high time interval is 200ns.

Te

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8.13.1 Timing Diagrams

Figure 10. Write Data

ENABLE - IO4

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tEH
tCHD tCH tCL

CLK

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tDIS tDIH

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MOSI - IO7 DATAI DATAI DATAI

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DATAO

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on A
Figure 11. Read Data
nt
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ENABLE - IO4

tCH tCL

CLK tDOD

MOSI - IO7 DATAI DATAI

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tDOH tDOD

MISO - IO6 DATAO (D7N) DATAO (D00)

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ch
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8.13.2 Timing Parameters

Table 50. Timing Parameters
Symbol Parameter Condition Min Typ Max Units
General
BRSDI Bit rate 2 Mbps
tCH Clock high time 250 ns

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tCL Clock low time 250 ns
Write timing

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tDIS Data in setup time 20 ns
tDIH Data in hold time 10 ns

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tEH Enable hold time 300 ns
Read timing
tDOH Data out hold time 150 ns

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tDOD Data out delay 150 ns

st
8.14 FIFO
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The FIFO is loaded in a cyclical manner. The FIFO and its pointers should be cleared by the Reset FIFO command (0F) prior each FIFO write for
on A
transmission. Data coming from the MCU is stored in the FIFO at address 1F hex from location 0 to 23. When the bytes are loaded in the reader,
nt
the input FIFO counter is counting the number of bytes loaded into the FIFO. When data is read from the FIFO, an output FIFO counter is
incremented and it follows the status of the bytes read.
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The input and output counters are 12 bits each. They are used to control the data flow in and out of the FIFO. This control sends an interrupt
request if the number of bytes in the FIFO is less than 6 and if number of bytes increases to above 18 so that MCU can send new data or remove
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the data as necessary. It additionally checks that the number of data bytes to be sent does not surpass the value defined in ‘TX length’ bytes. It
also signals the transmit logic when the last data to be sent was moved from FIFO to the transmit logic. The number of bytes in the FIFO is
available in the FIFO status register. This register also contains three status flags:
Fove bit is set in case of FIFO overflow
Flol bit is set in case of low FIFO level during transmission
Fhil bit is set in case of high FIFO level during reception
ca
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ch
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Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s

9 Package Drawings and Markings

The device is available in a 64-pin QFN (9mm x 9mm) package.

Figure 12. Drawings and Dimensions

id
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AS3992
YYWWXZZ

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st
te G Symbol Min Nom Max
A 0.80 0.90 1.00
on A
A1 0 0.02 0.05
nt A3 - 0.20 REF -
L 0.35 0.40 0.45
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L1 0 - 0.15
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b 0.18 0.25 0.30

D 9.00 BSC
E 9.00 BSC
e 0.50 BSC
D2 5.90 6.00 6.10
E2 5.90 6.00 6.10
aaa - 0.15 -
bbb - 0.10 -
ccc - 0.10 -
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ddd - 0.05 -
eee - 0.08 -
fff - 0.10 -
N 64
ni

- REF: Reference Dimension, usually without

Notes: tolerance, for information purposes only.
- BSC: Basic Dimension. Theoretically exact
ch

1. Dimensions and Tolerancing conform to ASME Y14.5M-1994.

value shown without tolerances.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension b applies to metalized terminal and is measured between 0.25mm and 0.30mm from terminal tip.
Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable.
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4. Coplanarity applies to the exposed heat slug as well as the terminal.

5. Radius on terminal is optional.
6. N is the total number of terminals

Marking: YYWWXZZ.

YY WW X ZZ
Year (i.e. 10 for 2010) Manufacturing Week Assembly plant identifier Assembly traceability code

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Revision History

Revision Date Owner Description

1.0 Dec 21, 2009 Initial revision
tlu Updated current consumption, Key Features, Package Drawings and
1.1 Nov 24, 2010
Markings, Ordering Information

Note: Typos may not be explicitly mentioned under revision history.

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Datasheet - O r d e r i n g I n f o r m a t i o n

10 Ordering Information
The devices are available as the standard products shown in Table 51.
Table 51. Ordering Information

Ordering Code Description 1 Package

Delivery Form
Tape and Reel in
AS3992-BQFP Internal DRM compatible VCO, pre-distortion 64-pin QFN (9mm x 9mm)
dry pack

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1. Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels.

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Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect

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Technical Support is availableat http://www.austriamicrosystems.com/Technical-Support

For further information and requests, please contact us mailto: [email protected]

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or find your local distributor at http://www.austriamicrosystems.com/distributor

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Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding

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the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,

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unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
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www.austriamicrosystems.com/AS3992 Revision 1.1 53 - 53

AS3992 (V6) Errata Sheet
Known issues in the digital section:

No. Issue description Comment Workaround

P1 clsys<2:0>=000b enables As a consequence a Set the bit open_dr in
60kHz on the CLSYS -62dBc TX spur at 60kHz register 0x05 to high.
output can be seen.
This problem can be
considered as non-
critical.
By using the proposed
workaround, the spur
disappears.

No. Issue description Comment Workaround

P2 In case exactly two bytes The data length Read out only the first
are received in the FIFO information is contained FIFO byte which contains
and both bytes are read in the first received byte – the EPC length
out during reception, the therefore it is sufficient to information upon
subsequent ReqRN read only one byte. receiving Irq_2nd_byte
command is corrupted.
Any other number of
The case happens when bytes (1, 3, 4, …) can be
2byte_irq is used. read out without any
problems.

No. Issue description Comment Workaround

P5 In case BlockRX is used An alternative to the Skip the direct command
after receiving the RN16 Block RX command, BlockRX. In case the
the IRQstatus register reg03:0A can be used as issue still happen act as
(0x0C) reports 0x00 well. in case of a collision.
instead of 0x4x.
(Select, NAK)

No. Issue description Comment Workaround

P6 In case BlockRX is used An alternative to the Skip the direct command
after receiving the RN16 Block RX command, BlockRX. In case the
the IRQstatus register reg03:0A can be used as issue still happen act as
(0x0C) reports 0xC0 well. in case of a collision.
instead of 0x4x.
(Select, NAK)

No. Issue description Comment Workaround

P7 After corrupted reception There are two EN H-L-H transition is
of RN16 with IRQstatus possibilities to identify needed.
register (0x0C) = 0x40 this condition:
the reception remains (1) Read IRQstatus just
enabled, TX is blocked after subsequent TX
and consequently the TX command
IRQ is missing. (IRQstatus=0x80 is
expected)
(2) Watch dog timer
action when waiting
on the missing IRQ
pulse at the end of
transmission.

STRICTLY CONFIDENTIAL 1/3 20 Sept. 12

 No. Issue description Comment Workaround
P8 After EPC reception the This case does not Continue inventory round
IRQstatus register indicate that a collision as if a corrupted EPC
contains 0X00. has happened. There is was received.
no need to increase the
number of slots in the
subsequent inventory.

No. Issue description Comment Workaround

P9 After any reception the Continue inventory round
IRQstatus register as if a corrupted
contains 0x41. reception has happened
(collision on RN, error
EPC…)

No. Issue description Comment Workaround

P10 SPI: Direct command Send the direct command
Reset FIFO (0x8F) Reset FIFO after the TX
should not be sent before IRQ, before the receiving
the direct command the HANDLE.
ReqRN (0x9F).

No. Issue description Comment Workaround

G5d SPI: Reading the FIFO Read the FIFO status
register 0x1F should not register in single byte
be done right after an IO4 mode before reading the
H-L transition. contents of the FIFO
register.

Known issues in the analogue section:

No. Issue description Comment Workaround
A4b MCU support current not Issue is less critical since
stable and higher than MCU current in operation
expected (400uA- is typically much higher
1000uA). than the unwanted
Should be 400-500uA 500uA.
typ.

No. Issue description Comment Workaround

H3 The internal PA cannot Use low power RF
be used in majority of the output.
applications due to
insufficient linearity and
stability.

STRICTLY CONFIDENTIAL 2/3 20 Sept. 12

Important Notes & Hints
No. Issue description Comment Recommendation
P3 QueryRep and Not critical in a normal Use Reset FIFO
QueryAdj need a Reset inventory round in case command before
FIFO (0x8F) direct an access operation QueryRep and
command for correct (read/write) is done in the QueryAdj.
operation. same round.
The issue decreases tag
inventory rate in case
only the EPCs are read
and no read or write
operation is planned.

No. Issue description Comment Recommendation

P3A Direct commands for Use Reset FIFO before
transmission (0x90, 0x91, transmission commands.
0x92) require a Reset
FIFO direct command for
correct operation.

No. Issue description Comment Recommendation

P4 To meet a StopSgl Previously also the stop Use correct StopSgl.
condition a IO7 transition condition met by a
at CLK=H is needed. transition of all IO lines at
IO6:0 should be stable CLK=H was allowed.
during StopSgl.

No. Issue description Comment Recommendation

G8 A FIFO read operation Read FIFO contents in
requires the continuous the continuous read
read mode for correct mode.
status of the pointers.

STRICTLY CONFIDENTIAL 3/3 20 Sept. 12