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21-Jun to 25-Jun 2021

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Mixed Signal Design

Lecture 1 on June 21, 2021

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About me Course Plan

§ Introduction to DATA Converters § ADC Continued:
§ Dr G S VISWESWARAN
§ Performance Metrics § Serial ADC (Low Speed)
§ Working in VLSI Design for more than 41 yrs
§ Codes Used in Data Converters § Successive Approximation ADC
§ >35 yrs at IIT Delhi (Medium Speed)
§ Multiple patents and papers § Digital to Analog Converters (Nyquist
Rate) § Algorithmic or Cyclic ADC
§ Areas of research/ interest § Pipelined ADC with Error
§ Analog and Mixed Signal Circuit Design
§ Current Scaling and Steering DAC
Correction.
§ Memory Design § Voltage and Charge Scaling DAC. § Flash ADC
§ Other interests § Extending Resolution of DAC § Oversampled Data Converters:
§ Student Counselling and Mentorship § Serial and Algorithmic DAC § Sigma-Delta Modulators
§ Physical Coordinates § Some Design Analysis § Sigma-Delta ADC
§ A-303, Academic § Analog to Digital Converters (Nyquist § Sigma-Delta DAC
Block Rate) § Comparators
§ Email § Recollection of Basic Characteristics § Delay Constraints
§ [email protected] § Sample and Hold Circuits. § Sequential Circuits
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Reference Material Evaluations

1. Rudy van de Plassche, “CMOS Integrated Analog-to- and Digital-to-Analog § DESIGN PROJECT
Converters”, Kluwer Academic Publishers. § ONE HOUR SHORT ANSWER EXAM ON TE LAST DAY.
2. Behzad Razavi, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN”,
§ CLASS INTERACTION.
Wiley Interscience.
3. Philip E. Allen and Douglas R Holberg, “CMOS ANALOG CIRCUIT DESIGN”,
Indian Second Edition, Oxford University Press. (Chapter 10)
4. Tony Chan Carusone, David A. Johns and Kenneth W. Martin, “Analog
Integrated Circuit Design”, Second Edition, John Wiley & Sons, Inc.
5. Willy M. C. Sansen, “Analog Design Essentials”, Springer International
Edition.

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Class Logistics Rules of the Online Game

§ Platform § Please plan to be in the class for 3.0 hrs (with a 10mts. break after 1.5hrs.)
§ Classes on Zoom
§ Please sit in a manner and place where you don’t get distracted by others
§ Google Classroom as repository § “NOT” facing the door/ room where other people may be moving around
§ Structure § Focus on understanding
§ Start with a quick re-cap § Equations are used to model the understanding
§ Close with a quick review § Ask Questions when you have doubts
§ If desperately needed, you can un-mute and interrupt me
§ Lab Hours – daily 6 to 8pm
§ Metaphors will be used to help in developing understanding
§ Teaching Assistants § Do not limit understanding to them
§ Akshat Saxena § Spend as much time on the daily assignment as needed
§ Mohd Shadman Ahmad § Don’t limit to how the problem is defined
§ Sayan Adhikari
§ Attend Office Hours
§ Swapnil Bansal § TAs have extensive experience with the EDA tools
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Transfer Characteristics:

Analog Output

Analog Input
DATA CONVERTERS

Digital Input Digital Output

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Performance Metrics: (Static Characteristics) OFFSET, DNL and INL:

• Differential Non-Linearity (DNL) is the maximum deviation in the output
step size from the ideal value for adjacent code change.
Gain Error
• Integral Non-Linearity (INL) is the maximum deviation of the input/output
characteristics from a straight line passed through its end points. The
difference between the ideal and actual characteristics will be called the INL
profile.
• Offset is the vertical intercept of the straight line passed through the end
points from its ideal value.
• Gain Error is the deviation of the slope of the line passed through the end
points from its ideal value.
• Monotonicity of a converter means that the output never decreases with an
increase in digital output.

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Nonlinearity Calculations: Graphic Look at some of the Errors:

For an n-bit binary weighted converter, the weight of the m th bit will have a value

𝑏" = 2%&("()) 𝐿𝑆𝐵 + 𝜀" (m = 0 is the MSB)

The full-scale value, B, will be calculated as
%&) %&)

𝐵 = 0 2%&("()) 𝐿𝑆𝐵 + 𝜀" = 2% − 1 𝐿𝑆𝐵 + 0 𝜀"

"12 "12

The ideal quantization step S and the linearity error of the kth bit are given by
𝐵 ∑ %&)
"12 𝜀"
𝑆= = 𝐿𝑆𝐵 + and the error ∆7 = 2%&(7()) 𝑆 − (2%& 7()
LSB + 𝜀7 )
2% −1 2% − 1
%&) %&)
1
𝐼𝑁𝐿 = 0 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒∆7 − 0 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒∆7 ≤ 𝐿𝑆𝐵 = ∆2
2
712 712
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Quantization Noise: Performance Metrics: (Dynamic Characteristics)

• Settling time is the time required for the output to experience full scale
transition and settle within a specified error band around its final value.
• Latency is the total delay from the time the digital input changes to the time
the analog output has settled within a specified error band around its final
value. Latency may include a multiples of clock period if the digital logic in
Analog Output

the DAC is pipelined.

In a Nyquist converter, the maximum signal to • Glitch impulse area is the maximum area under any extraneous glitch that
noise ratio that can be obtained for a sinusoidal appears at the output after the input code changes. This is called “glitch
input with a peak voltage of V is given by: energy”.
𝑆KL 𝑆KL
𝑆𝑁𝑅 = 10𝑙𝑜𝑔 = 10𝑙𝑜𝑔 + 4.77 + 6.02𝑁 (𝑑𝐵) • Signal to Noise Ration (SNR) or Dynamic Range (DR) is the ratio of the
𝑆ML L
𝑉OPQ maximum signal power to the power in the quantization Noise -----------
\ Every additional bit Þ 6dB of SNR. Digital Input
SNR = 6.02N dB + 1.76 dB.

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Performance Metrics: (Dynamic Characteristics) -- Continued Settling Time and Glitch:

• Spurious Free Dynamic Range (SFDR) is the ratio between the maximum
signal component and the largest distortion component.

• Effective Number of Bits (ENOB) is an alternative way of stating SNDR of a

data converter and is given by
𝑆𝑁𝐷𝑅"MZ[\]M^ − 1.76
𝐸𝑁𝑂𝐵 =
6.02

• Signal-to-Noise plus Distortion Ratio (SNDR or SINAD)is the ratio of the

signal power to the total noise and harmonic distortion at the output when
the input is a sinusoid. This includes Total Harmonic Distortion (THD) along
with the quantization noise.

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SFDR (Spurious Free Dynamic Range) from the Spectrum: SINAD in a DAC:

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Digital Codes Used in DAC: Digital to Analog Converters

Decimal 0 1 2 3
Binary 00 01 10 11
Thermometer 0 0 0 0
0 0 0 1
0 0 1 0
0 1 1 0
1-of-n 0 0 0 1
0 0 1 0
0 1 0 0 Notation: For an n-bit number we will use notation b0, b1 ⋯ ⋯ ⋯ bn-2, bn-1 with
1 0 0 0 b0 representing MSB and bn-1 representing LSB.

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Currrent Scaling DAC with Binary Weighted Resistance Network: Currrent Scaling DAC with R-2R Ladder Network:

Switch Si will be controlled by bit b i Switch Si will be controlled by bit b i

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Current Sourced Based Currrent Scaling DAC : Current Steering DAC:

Solution is the Current Steering Architecture, consumes more power but
better behaved.

Switch Si will be controlled by bit b i

Issues: When switch Si is turned OFF the corresponding Current source is
turned also turned OFF till it is turned ON again. This adds to unnecessary
Issue: We see glitches at the output.
delay in the conversion.
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Binary and Thermometer Coded DAC:

Binary coded DAC Thermometer coded DAC

DNLmax = 2% − 1 𝜎a DNLmax = 𝜎a

DNLmax = 2%bcd − 1 𝜎a

INLmax = 0.5 2%&) 𝜎a

Solution: Ensure that both b0 and 𝑏2 have overlapping periods of high.
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Segmented DAC: Voltage Scaling DAC:

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Voltage Scaling DAC: Voltage Scaling DAC:

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Evaluation of Nonlinearity in Voltage Scaling DAC: Charge Scaling DAC:

2% − 𝑖 𝑅
𝑣f = 𝑉
2% − 𝑖 𝑅 + 𝑖𝑅 OPQ
Assumptions:
• The worst scale INL occurs at the midpoint where 𝑖 = 2% − 1
• 𝑅"ZK = 𝑅 + ∆𝑅 𝑎𝑛𝑑 𝑅"fg = 𝑅 − ∆𝑅
• Resistors below are all 𝑅"ZK and those below are all 𝑅"fg .

𝐼𝑁𝐿 = 𝑣Lhij 𝑎𝑐𝑡𝑢𝑎𝑙 − 𝑣Lhij 𝑖𝑑𝑒𝑎𝑙

2%&) 𝑅 + ∆𝑅 𝑉OPQ 𝑉OPQ ∆𝑅 ∆𝑅
= − = 𝑉 = 2%&) 𝐿𝑆𝐵 ≤ 0.5𝐿𝑆𝐵
2%&) 𝑅 + ∆𝑅 + 2%&) 𝑅 − ∆𝑅 2 2𝑅 OPQ 𝑅
∆𝑅
𝐷𝑁𝐿 = ± 𝐿𝑆𝐵 ≤ 0.5𝐿𝑆𝐵
𝑅

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Charge Scaling DAC: Charge Scaling DAC:

𝐶Mo 𝑉OPQ − 𝑣p\q = 2𝐶 − 𝐶Mo 𝑣p\q

𝐶Mo 𝑉OPQ = 2𝐶𝑣p\q

𝐶Mo 𝑉OPQ
∴ 𝑣p\q =
2𝐶

𝐶Mo = 𝑏2 𝐶 + 𝑏) 2&) 𝐶 + 𝑏L 2&L 𝐶 + … … … + 𝑏%&) 2& %&)

𝐶

𝑏2 𝐶 + 𝑏) 2&) 𝐶 + 𝑏L 2&L 𝐶 + … … … + 𝑏%&) 2& %&)

𝐶
𝑣p\q = 𝑉OPQ
2𝐶
𝑏2 + 𝑏) 2&) + 𝑏L 2&L + … … … + 𝑏%&) 2& %&)
𝑣p\q = 𝑉OPQ
2
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Evaluation of INL for a Charge Scaled DAC: Evaluation of DNL for a Charge Scaled DAC:

𝐷𝑁𝐿 = 𝑣[qMu 𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒 − 𝑣[qMu 𝑖𝑑𝑒𝑎𝑙

𝐶 ⁄2f&) 2%
𝑣p\q 𝑖𝑑𝑒𝑎𝑙 = 𝑉OPQ = f 𝐿𝑆𝐵
2𝐶 2
= 𝑣p\q 1000000 … … − 𝑣p\q 0111111 … … − 𝐿𝑆𝐵
Let us consider 𝐶"ZK = 𝐶 + ∆𝐶 and 𝐶"fg = 𝐶 − ∆𝐶
2
𝐶 + ∆𝐶 𝐶 − ∆𝐶 1−
= 𝑉OPQ − 2% 𝑉OPQ − 𝐿𝑆𝐵
𝐶 ± ∆𝐶 ⁄2f&) 2% ∆𝐶
𝑣p\q 𝑎𝑐𝑡𝑢𝑎𝑙 = 𝑉OPQ = 𝐿𝑆𝐵 ± 2%&f 𝐶 + ∆𝐶 + 𝐶 − ∆𝐶 𝐶 + ∆𝐶 + 𝐶 − ∆𝐶
2𝐶 2f 𝐶
∆𝐶 ∆𝐶
∴ 𝐼𝑁𝐿 = ±2%&f and the worst case is when 𝑖 = 1 = 2% − 1 𝐿𝑆𝐵
𝐶 𝐶
∆𝐶
𝐼𝑁𝐿"ZK == ±2%&)
𝐶

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Extending Resolution of Parallel DAC:

Comparison of Different DAC Approaches: Combining Identically Scaled DAC

DAC Type Advantage Disadvantage

Current Scaling Fast, Insensitive to Large Element Spread,
Switch Parasitic. Nonmonotonic
Voltage Scaling Monotonic, Equal Large Area, Sensitive to
Resistors Parasitic Capacitors.
Charge Scaling Fast, Good Large Element Spread,
Component Accuracy:
Accuracy Nonmonotonic. 𝑉OPQ
𝑊𝑒𝑖𝑔ℎ𝑡𝑖𝑛𝑔 𝑓𝑎𝑐𝑡𝑜𝑟 𝑜𝑓 𝑖 q{ 𝑏𝑖𝑡 = = 2%&f&) 𝐿𝑆𝐵
2f()
±0.5𝐿𝑆𝐵 100
𝐴𝑐𝑐𝑢𝑟𝑎𝑐𝑦 𝑜𝑓 𝑡ℎ𝑒 𝑖 q{ 𝑏𝑖𝑡 = %&f&) = %
2 𝐿𝑆𝐵 2%&f

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Effect of Error in the Division Factor: Tolerance on the Scaling Factor for proper functioning of the DAC:

For the example considered with M=2 and K=2, the multiplication factor 𝑥 = 1⁄4.

Consider a small error in the multiplication factor and 𝑥 → 𝑥 + ∆𝑥. Considering

the LSB two bits that get multiplied by 𝑥, we require

𝑏L 𝑏• 𝑏L 𝑏• 1
1⁄4 + ∆𝑥 + 1⁄4 + ∆𝑥 ≤ + ±
2 4 8 16 32

Consider a system with M=2=K 𝑏L 𝑏• 1 3 1 1

+ ∆𝑥 ≤ 𝑓𝑜𝑟 𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒 ∆𝑥 ≤ −−→ ∆𝑥 ≤
i.e., the LSB DAC output is to be 2 4 32 4 32 24
divided by 4. Consider an error in
the design that causes the LSB The multiplication factor must be accurate within 16.66%
DAC output to be multiplied by
(3/8).
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Current Steering DAC: Charge Scaling DAC:

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Charge Scaling DAC: Charge Scaling DAC:

1 1⁄2 1⁄4 1⁄8 16 𝑏2 𝑏) 𝑏L 𝑏•

𝑉) = 𝑏 + 𝑏 + 𝑏 + 𝑏 𝑉 = + + + 𝑉
15⁄8 2 15⁄8 ) 15⁄8 L 15⁄8 2 OPQ 15 2 4 8 16 OPQ

𝑏… 𝑏† 𝑏‡ 𝑏ˆ
𝑉L = + + + 𝑉
2 4 8 16 OPQ
1 1 8 2𝐶
+ = −−−→ 𝐶„ = 15 1 𝑏2 𝑏) 𝑏L 𝑏• 𝑏… 𝑏† 𝑏‡ 𝑏ˆ
𝐶„ 2𝐶 𝐶 15
𝑣‰Š‹ = 𝑉) + 𝑉L = + + + + + + + 𝑉OPQ
16 16 2 4 8 16 32 64 128 256
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Alternate Charge Scaling Structure: Combining Differently Scaled DAC:

MSB Voltage Scaled subDAC and LSB Charge Scaled subDAC.

Bus A is the higher Voltage and Bus B is the lower voltage.

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MSB Voltage Scaled subDAC and LSB Charge Scaled subDAC. MSB Voltage Scaled subDAC and LSB Charge Scaled subDAC.
• The MSB subDAC is guaranteed to be monotonic.
• The accuracy of the LSB will be greater than MSB as it is determined by
capacitors.
• The capacitor spread is determined by 2Œ&)
• Due to the inaccuracies in the resistors, the nonmonotonicity caused in the
LSB subDAC may make the over all DAC nonmonotonic when combined.

2% ∆𝑅 ∆𝑅 ∆𝑅
𝐼𝑁𝐿 𝑅 = 2•&) 𝐿𝑆𝐵 = 2%&) 𝐿𝑆𝐵; 𝐷𝑁𝐿 𝑅 = 2Œ 𝐿𝑆𝐵
2• 𝑅 𝑅 𝑅
∆𝐶 ∆𝑅 ∆𝐶
𝐼𝑁𝐿 𝐶 = 2Œ&) 𝐿𝑆𝐵 = 2%&) 𝐿𝑆𝐵; 𝐷𝑁𝐿 𝑅 = 2Œ − 1 𝐿𝑆𝐵
𝐶 𝑅 𝐶

𝐼𝑁𝐿 = 𝐼𝑁𝐿 𝑅 + 𝐼𝑁𝐿 𝐶 ; 𝐷𝑁𝐿 = 𝐷𝑁𝐿 𝑅 + 𝐷𝑁𝐿(𝐶)

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MSB Charge Scaled subDAC and LSB Voltage Scaled subDAC MSB Charge Scaled subDAC and LSB Voltage Scaled subDAC

• LSBs are guaranteed to be Monotonic.

• Accuracy of the MSBs are greater than that of the LSBs.
• The DNL is less for this DAC due to the increased accuracy of the MSBs.
• The component spread determined by the binary weighted capacitors and
is 2•&) .

∆𝑅 ∆𝐶
𝐼𝑁𝐿 = 𝐼𝑁𝐿 𝑅 + 𝐼𝑁𝐿 𝐶 = 2•&) + 2%&) 𝐿𝑆𝐵
𝑅 𝐶
∆𝑅 ∆𝐶
𝐷𝑁𝐿 = 𝐷𝑁𝐿 𝑅 + 𝐷𝑁𝐿 𝐶 = + 2% − 1 𝐿𝑆𝐵
𝑅 𝐶

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Serial DAC: Algorithmic DAC:

𝑣‰Š‹ 𝑧 = 𝑏2 𝑧 &) + 2&) 𝑏) 𝑧 &L + … … + 2&f 𝑏f 𝑧 & f()

+ … … + 2&(%&)) 𝑏%&) 𝑧 &%
Convert 1101

S1 Redistribution Switch; S 2 Charging Switch and S 3 Discharging Switch

ON for bi =1, Start switching from LSB ON for bi =0

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