M28010

1 Mbit (128K x 8) Parallel EEPROM

With Software Data Protection
PRELIMINARY DATA

■ Fast Access Time: 100 ns

■ Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
32
■ Low Power Consumption
■ Fast BYTE and PAGE WRITE (up to 128 Bytes)
1
■ Enhanced Write Detection and Monitoring:
– Data Polling PDIP32 (BA)

– Toggle Bit
– Page Load Timer Status
■ JEDEC Approved Bytewide Pin-Out
■ Software Data Protection
■ Hardware Data Protection
■ Software Chip Erase TSOP32 (NA)
PLCC32 (KA) 8 x 20 mm
■ 100000 Erase/Write Cycles (minimum)
■ Data Retention (minimum): 10 Years

DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with Figure 1. Logic Diagram
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
VCC
time, with low power dissipation, and require a sin-
gle voltage supply (5V, 3V or 2V, depending on the
option chosen).
17 8
A0-A16 DQ0-DQ7
Table 1. Signal Names
A0-A16 Address Input
W M28010
DQ0-DQ7 Data Input / Output
E
W Write Enable
G
E Chip Enable

G Output Enable

VCC Supply Voltage

VSS
AI02221

VSS Ground

January 1999 1/22

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28010

Figure 2A. DIP Connections Figure 2C. TSOP Connections

DU 1 32 VCC A11 1 32 G
A16 2 31 W A9 A10
A15 3 30 DU A8 E
A12 4 29 A14 A13 DQ7
A7 5 28 A13 A14 DQ6
A6 6 27 A8 DU DQ5
A5 7 26 A9 W DQ4
A4 8 M28010 25 A11 VCC 8 25 DQ3
M28010
A3 9 24 G DU 9 24 VSS
A2 10 23 A10 A16 DQ2
A1 11 22 E A15 DQ1
A0 12 21 DQ7 A12 DQ0
DQ0 13 20 DQ6 A7 A0
DQ1 14 19 DQ5 A6 A1
DQ2 15 18 DQ4 A5 A2
VSS 16 17 DQ3 A4 16 17 A3
AI02222
AI02224

Note: 1. DU = Do Not Use Note: 1. DU = Do Not Use

Figure 2B. PLCC Connections data retention. The organization of the data in a 4
byte (32-bit) “word” format leads to significant sav-
ings in power consumption. Once a byte has been
VCC
A12
A15
A16
DU

DU

read, subsequent byte read cycles from the same

W

“word” (with addresses differing only in the two

1 32 least significant bits) are fetched from the previ-
A7 A14 ously loaded Read Buffer, not from the memory ar-
A6 A13 ray. As a result, the power consumption for these
A5 A8 subsequent read cycles is much lower than the
A4 A9 power consumption for the first cycle. By careful
design of the memory access patterns, a 50% re-
A3 9 M28010 25 A11
duction in the power consumption is possible.
A2 G
A1 A10 SIGNAL DESCRIPTION
A0 E The external connections to the device are sum-
DQ0 DQ7 marized in Table 1, and their use in Table 3.
17 Addresses (A0-A16). The address inputs are
used to select one byte from the memory array
VSS
DQ1
DQ2

DQ3
DQ4
DQ5
DQ6

during a read or write operation.

AI02223 Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
Note: 1. DU = Do Not Use through the Data I/O pins.
Chip Enable (E). The chip enable input must be
The device has been designed to offer a flexible held low to enable read and write operations.
microcontroller interface, featuring both hardware When Chip Enable is high, power consumption is
and software hand-shaking, with Data Polling and reduced.
Toggle Bit. The device supports a 128 byte Page Output Enable (G). The Output Enable input con-
Write operation. Software Data Protection (SDP) trols the data output buffers, and is used to initiate
is also supported, using the standard JEDEC algo- read operations.
rithm.
Write Enable (W). The Write Enable input controls
The M28010 is designed for applications requiring whether the addressed location is to be read, from
as much as 100,000 write cycles and ten years of or written to.

2/22
 M28010

Table 2. Absolute Maximum Ratings 1

Symbol Parameter Value Unit
TA Ambient Operating Temperature –40 to 85 °C
T STG Storage Temperature –65 to 150 °C

VCC Supply Voltage –0.3 to VCCMAX+1 V

VIO Input or Output Voltage (except A9) –0.3 to V CC+0.6 V

VI Input Voltage –0.3 to 4.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 2000 V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

Figure 3. Block Diagram

X DECODE

ADDRESS
A7-A16 1Mbit ARRAY
LATCH
(Page Address)

ADDRESS
A0-A6
LATCH
LATCH PAGE

Y DECODE
REFERENCES

VPP GEN

VREAD GEN SENSE PAGE & DATA LATCH

E
PROGRAMMING
CONTROL
G STATE ECC (1) & MULTIPLEXER
LOGIC
MACHINE
W

I/O BUFFERS

DQ0-DQ7
AI02225

3/22
M28010

Table 3. Operating Modes 1

Mode E G W DQ0-DQ7

Read VIL V IL VIH Data Out

Write VIL VIH VIL Data In

Stand-by / Write Inhibit V IH X X Hi-Z

Write Inhibit X X VIH Data Out or Hi-Z

Write Inhibit X V IL X Data Out or Hi-Z

Output Disable X VIH X Hi-Z

Note: 1. X = VIH or VIL.

DEVICE OPERATION Further protection against data corruption is of-

In order to prevent data corruption and inadvertent fered by the E and W low pass filters: any glitch,
write operations, an internal VCC comparator in- on the E and W inputs, with a pulse width less than
hibits the Write operations if the VCC voltage is 10 ns (typical) is internally filtered out to prevent
lower than VWI (see Table 4A to Table 4C). Once inadvertent write operations to the memory.
the voltage applied on the VCC pin goes over the Read
VWI threshold (VCC>VWI), write access to the The device is accessed like a static RAM. When E
memory is allowed after a time-out tPUW, as spec- and G are low, and W is high, the contents of the
ified in Table 4A to Table 4C. addressed location are presented on the I/O pins.

Table 4A. Power-Up Timing1 for M28010 (5V range)

(TA = -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol Parameter Min. Max. Unit
tPUR Time Delay to Read Operation 5 ms

tPUW Time Delay to Write Operation (once VCC ≥ VWI) 5 ms

VWI Write Inhibit Threshold 3.0 4.2 V

Note: 1. Sampled only, not 100% tested.

Table 4B. Power-Up Timing1 for M28010-W (3V range)

(TA = -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol Parameter Min. Max. Unit
tPUR Time Delay to Read Operation 5 ms

tPUW Time Delay to Write Operation (once VCC ≥ VWI) 5 ms

VWI Write Inhibit Threshold 2.0 2.6 V

Note: 1. Sampled only, not 100% tested.

Table 4C. Power-Up Timing1 for M28010-R (2V range)

(TA = -40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol Parameter Min. Max. Unit
tPUR Time Delay to Read Operation 5 ms

tPUW Time Delay to Write Operation (once VCC ≥ VWI) 5 ms

VWI Write Inhibit Threshold 1.2 1.7 V

Note: 1. Sampled only, not 100% tested.

4/22
 M28010

Otherwise, when either G or E is high, the I/O pins ter a delay, tWLQ5H, that cannot be shorter than the
revert to their high impedance state. value specified in Table 9A to Table 9C, the inter-
Write nal write cycle starts. It continues, under internal
timing control, until the write operation is complete.
Write operations are initiated when both W and E
The commencement of this period can be detect-
are low and G is high. The device supports both
ed by reading the Page Load Timer Status on
W-controlled and E-controlled write cycles (as
DQ5. The end of the internal write cycle can be de-
shown in Figure 12 and Figure 13). The address is
tected by reading the status of the Data Polling
latched during the falling edge of W or E (which
and the Toggle Bit functions on DQ7 and DQ6.
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-

Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
SDP is Disabled and Application SDP is Disabled and
needs to Enable it, and Write Data Application needs to Enable it

Write AAh in Write AAh in

Address 5555h Address 5555h

Page Write Write 55h in Write 55h in

Timing Address 2AAAh Address 2AAAh

Page Write
Write A0h in Timing Write A0h in
Address 5555h Address 5555h
Write
is enabled
Time Out (tWLQ5H)
Write data
in any addresses
Wait for write completion (tQ5HQ5X) within one page

SDP is set
Time Out (tWLQ5H)

Write AAh in
Address 5555h Wait for write completion (tQ5HQ5X)

Write 55h in DATA has been written

Address 2AAAh and SDP is Enabled

Page Write
Timing Write A0h in
Address 5555h
Write
is enabled

Write data
in any addresses
within one page

Time Out (tWLQ5H)

Wait for write completion (tQ5HQ5X)

DATA has been written

and SDP is Enabled AI02227B

5/22
M28010

Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write)
SDP is Enabled and SDP is Enabled and
Application needs to Disable it Application needs to Write Data

Write AAh in Write AAh in

Address 5555h Address 5555h

Write 55h in Write 55h in

Address 2AAAh Address 2AAAh

Write 80h in Write 80h in

Address 5555h Address 5555h
Page Write Page Write
Timing Timing
Write AAh in Write AAh in
Address 5555h Address 5555h

Write 55h in Write 55h in

Address 2AAAh Address 2AAAh

Write 20h in Write 20h in

Address 5555h Address 5555h

Time Out (tWLQ5H) Physical Write data

Write in any addresses
Instructions within one page
Wait for write completion (tQ5HQ5X)

Time Out (tWLQ5H)

SDP is Disabled

Wait for write completion (tQ5HQ5X)

DATA has been written

and SDP is Disabled

AI02226B

Page Write All bytes must be located on the same page ad-
The Page Write mode allows up to 128 bytes to be dress (A16-A7 must be the same for all bytes).
written on a single page in a single go. This is Otherwise, the Page Write operation is not execut-
achieved through a series of successive Write op- ed. The Page Write Abort event is indicated to the
erations, no two of which are separated by more application via DQ1 (as described on page 8).
than the tWLQ5H value (as specified in Table 9A to As with the single byte Write operation, described
Table 9C). above, the DQ5, DQ6 and DQ7 lines can be used
The page write can be initiated during any byte to detect the beginning and end of the internally
write operation. Following the first Byte Write in- controlled phase of the Page Write cycle.
struction, the host may send another address and Software Data Protection (SDP)
data with a minimum data transfer rate of: The device offers a software-controlled write-pro-
1/t WLQ5H. tection mechanism that allows the user to inhibit all
The internal write cycle can start at any instant af- write operations to the device, including chip
ter tWLQ5H. Once initiated, the write operation is in- erase. This can be useful for protecting the mem-
ternally timed, and continues, uninterrupted, until ory from inadvertent write cycles that may occur
completion. during periods of instability (uncontrolled bus con-
ditions when excessive noise is detected, or when

6/22
 M28010

Figure 6. Software Chip Erase Algorithm Figure 7. Status Bit Assignment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Write AAh in
Address 5555h
DP TB PLTS X X X PWA SDP

Write 55h in
Address 2AAAh DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Write 80h in X = undefined
Address 5555h PWA = Page Write Abort
Page Write
Timing SDP = Software Data Protection

Write AAh in AI02486B

Address 5555h

Write 55h in Figure 8. Software Data Protection Status Read

Address 2AAAh
Algorithm

Write 10h in
Address 5555h Write AAh in
Address 5555h

Time Out (tWLQ5H)

Page Write Write 55h in
Timing Address 2AAAh
Wait for write completion (tQ5HQ5X)

Write 20h in
Whole Array has been Set to FFh Address 5555h

AI02236C Read SDP

on DQ0

power supply levels are outside their specified val- Write xxh in
Address xxxxh
ues).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely Normal User Mode
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are AI02237B
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft- chance of inadvertent enabling or disabling of the
ware Data Protection disable sequence is re- Software Data Protection mechanism.
ceived. The device reverts to its “unprotected” When SDP is enabled, the memory array can still
state. have data written to it, but the sequence is more
The status of the Software Data Protection (en- complex (and hence better protected from inad-
abled or disabled) is represented by a non-volatile vertent use). The sequence is as shown in Figure
latch, and is remembered across periods of the 5. This consists of an unlock key, to enable the
power being off. write action, at the end of which the SDP continues
The Software Data Protection Enable command to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
consists of the writing of three specific data bytes
(tWC).
to three specific memory locations (each location
being on a different page), as shown in Figure 4. Software Chip Erase
Similarly, to disable the Software Data Protection, The device can be erased (with all bytes set to
the user has to write specific data bytes into six dif- FFh) by using a six-byte software command code.
ferent locations, as shown in Figure 5. This com- This operation can be initiated only if the user
plex series of operations protects against the loads, with a Page Write addressing mode, six

7/22
M28010

specific data bytes to six specific locations (as cessive Write operations, up to tWLQ5H (defined in
shown in Figure 6). The complexity of the se- Table 9A to Table 9C). The DQ5 line is held low to
quence has been designed to guard against inad- show when this timer is running (hence showing
vertent use of the command. that the device has received one write operation,
Status Bits and is waiting for the next). The DQ5 line is held
high when the counter has overflowed (hence
The devices provide five status bits (DQ7, DQ6,
showing that the device is now starting the internal
DQ5, DQ1 and DQ0) for use during write opera-
write to the memory array).
tions. These allow the application to use the write
time latency of the device for getting on with other Page Write Abort bit (DQ1). During a page write
work. These signals are available on the I/O port operation, the A16 to A7 signals should be kept
bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only dur- constant. They should not change while succes-
ing the internal write cycle, tQ5HQ5X). sive data bytes are being transferred to the inter-
nal latches of the memory device. If a change
Data Polling bit (DQ7). The internally timed write
occurs on any of the pins, A16 to A7, during the
cycle starts as soon as tWLQ5H (defined in Table
page write operation (that is, before the falling
9A to Table 9C) has elapsed since the previous
edge of W or E, which ever occurs later), the inter-
byte was latched in to the memory. The value of
nal write cycle is not started, and the internal cir-
the DQ7 bit of this last byte, is used as a signal cuitry is completely reset.
throughout this write operation: it is inverted while
the internal write operation is underway, and is in- The abort signal can be observed on the DQ1 pin,
verted back to its original value once the operation using a normal read operation. This can be per-
is complete. formed at any time during the byte load cycle,
tWLQ5H, or while the W input is being held high be-
Toggle bit (DQ6). The device offers another way
tween two load cycles. The default value of DQ1 is
for determining when the internal write cycle is
initially set to ’0’ and changes to ’1’ if the internal
running. During the internal write cycle, DQ6 tog-
circuitry has detected a change on any of the ad-
gles from ’0’ to ’1’ and ’1’ to ’0’ (the first read value dress pins A16 to A7. This PWA bit can be
being ’0’) on subsequent attempts to read any byte
checked regardless of whether Software Data
of the memory. When the internal write cycle is
Protection is enabled or disabled.
complete, the toggling is stopped, and the values
read on DQ7-DQ0 are those of the addressed Software Data Protection bit (DQ0). Reading the
memory byte. This indicates that the device is SDP bit (DQ0) allows the user to determine wheth-
again available for new Read and Write opera- er the Software Data Protection mode has been
tions. enabled (SDP=1) or disabled (SDP=0). The SDP
bit (DQ0) can be read by using a dedicated algo-
Page Load Timer Status bit (DQ5). An internal
rithm (as shown in Figure 8), or can be combined
timer is used to measure the period between suc-

Table 5A. Read Mode DC Characteristics for M28010 (5V range)

(TA = -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0 V ≤ V IN ≤ VCC 5 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC 5 µA

E = VIL, G = VIL, f = 0.1 MHz 2 mA

ICC 1 Supply Current (CMOS inputs) E = VIL, G = VIL, f = 5 MHz 22 mA

E = VIL, G = VIL , f = 10 MHz 40 mA

ICC1 1 Supply Current (Stand-by) CMOS E > VCC – 0.3 V 30 µA

V IL Input Low Voltage –0.3 0.8 V

V IH Input High Voltage 2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1 mA 0.4 V

VOH Output High Voltage IOH = –400 µA 2.4 V

Note: 1. All inputs and outputs open circuit.

8/22
 M28010

Table 5B. Read Mode DC Characteristics for M28010-W (3V range)

(TA = -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current 0 V ≤ V IN ≤ VCC 5 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC 5 µA

E = VIL, G = VIL, f = 0.1 MHz 2 mA

ICC 1 Supply Current (CMOS inputs) E = VIL, G = VIL, f = 5 MHz 15 mA

E = VIL, G = VIL , f = 10 MHz 26 mA

ICC1 1 Supply Current (Stand-by) CMOS E > VCC – 0.3 V 30 µA

V IL Input Low Voltage –0.3 0.6 V

V IH Input High Voltage 2 VCC + 0.3 V

VOL Output Low Voltage IOL = 1.6 mA 0.45 V

VOH Output High Voltage IOH = –100 µA 2.4 V

Note: 1. All inputs and outputs open circuit.

Table 5C. Read Mode DC Characteristics for M28010-R (2V range)

(TA = -40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol Parameter Test Conditio n Min. Max. Unit

ILI Input Leakage Current 0 V ≤ VIN ≤ V CC 5 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC 5 µA

E = V IL, G = VIL, f = 0.1 MHz, VCC = 2.4 V 2 mA

ICC 1 Supply Current (CMOS inputs)
E = VIL, G = VIL, f = 5 MHz, VCC = 2.4 V 12 mA

ICC1 1 Supply Current (Stand-by) CMOS E > VCC – 0.3 V 30 µA

V IL Input Low Voltage - 0.3 0.2 V

V IH Input High Voltage VCC - 0.3 VCC + 0.3 V

VOL Output Low Voltage IOL = 0.4 mA 0.15 V

VOH Output High Voltage I OH = –100 µA VCC - 0.15 V

Note: 1. All inputs and outputs open circuit.

with the reading of the DP bit (DQ7), TB bit (DQ6)

and PLTS bit (DQ5).

9/22
M28010

Table 6. Input and Output Parameters1 (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min. Max. Unit
C IN Input Capacitance V IN = 0 V 6 pF

C OUT Output Capacitance VOUT = 0 V 12 pF

Note: 1. Sampled only, not 100% tested.

Table 7. AC Measurement Conditions Figure 10. AC Testing Equivalent Load Circuit

Input Rise and Fall Times ≤ 5 ns
Input Pulse Voltages 0 V to VCC

Input and Output Timing Ref. Voltages VCC/2

IOL

Figure 9. AC Testing Input Output Waveforms DEVICE

UNDER OUT
TEST

VCC IOH
CL = 30pF
VCC/2

0V

AI02228
CL includes JIG capacitance
AI02578

Table 8A. Read Mode AC Characteristics for M28010 (5V range)

(TA = -40 to 85 °C; VCC = 4.5 to 5.5 V)
M28010
Test
Symbol Alt. Parameter Condi t -10 -12 Unit
ion
Min Max Min Max
E = VIL,
tAVQV tACC Address Valid to Output Valid 100 120 ns
G = VIL

tELQV tCE Chip Enable Low to Output Valid G = VIL 100 120 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL 40 45 ns

tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 40 0 45 ns

tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 40 0 45 ns

Address Transition to Output E = VIL,

tAXQX tOH 0 0 ns
Transition G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

10/22
 M28010

Table 8B. Read Mode AC Characteristics for M28010-W (3V range)

(TA = -40 to 85 °C; VCC = 2.7 to 3.6 V)
M28010-W
Test
Symbol Alt. Parameter Condi t -10 -12 -15 Unit
ion
Min Max Min Max Min Max
E = VIL,
tAVQV tACC Address Valid to Output Valid 100 120 150 ns
G = VIL

tELQV tCE Chip Enable Low to Output Valid G = VIL 100 120 150 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL 70 80 100 ns

tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60 0 70 ns

tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 60 0 70 ns

Address Transition to Output E = VIL,

tAXQX tOH 0 0 0 ns
Transition G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Table 8C. Read Mode AC Characteristics for M28010-R (2V range)

(TA = -40 to 85 °C; VCC = 1.8 to 2.4 V)
M28010-R
Test
Symbol Alt. Parameter Condi t -20 -25 Unit
ion
Min Max Min Max
E = VIL,
tAVQV tACC Address Valid to Output Valid 200 250 ns
G = VIL

tELQV tCE Chip Enable Low to Output Valid G = VIL 200 250 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL 80 90 ns

tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60 ns

tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 60 ns

Address Transition to Output E = VIL,

tAXQX tOH 0 0 ns
Transition G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

11/22
M28010

Figure 11. Read Mode AC Waveforms (with Write Enable, W, high)

A0-A16 VALID

tAVQV tAXQX

tGLQV tEHQZ

tELQV tGHQZ
Hi-Z
DQ0-DQ7 DATA OUT

AI02229

Note: 1. Write Enable (W) = VIH

Table 9A. Write Mode AC Characteristics for M28010 (5V range)

(TA = -40 to 85 °C; VCC = 4.5 to 5.5 V)
M28010
Symbol Alt. Parameter Test Condit ion Unit
Min Max
tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH, W= VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 70 ns

tELAX tAH Chip Enable Low to Address Transition 70 ns

tELEH tWP Chip Enable Low to Chip Enable High 100 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

tWHGL tOEH Write Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 50 ns

tWLWH tWP Write Enable Low to Write Enable High 100 ns

tWLQ5H tBLC Time-out after the last byte write 150 µs

Byte Write Cycle time 5 ms

tQ5HQ5X tWC
Page Write Cycle time (up to 128 bytes) 10 ms
tDVWH tDS Data Valid before Write Enable High 50 ns

tDVEH tDS Data Valid before Chip Enable High 50 ns

12/22
 M28010

Table 9B. Write Mode AC Characteristics for M28010-W (3V range)

(TA = -40 to 85 °C; VCC = 2.7 to 3.6 V)
M28010-W
Symbol Alt. Parameter Test Condit ion Unit
Min Max
tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH, W= VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 70 ns

tELAX tAH Chip Enable Low to Address Transition 70 ns

tELEH tWP Chip Enable Low to Chip Enable High 100 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

tWHGL tOEH Write Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 50 ns

tWLWH tWP Write Enable Low to Write Enable High 100 ns

tWLQ5H tBLC Time-out after the last byte write 150 µs

Byte Write Cycle time 5 ms

tQ5HQ5X tWC
Page Write Cycle time (up to 128 bytes) 10 ms
tDVWH tDS Data Valid before Write Enable High 50 ns

tDVEH tDS Data Valid before Chip Enable High 50 ns

13/22
M28010

Table 9C. Write Mode AC Characteristics for M28010-R (2V range)

(TA = -40 to 85 °C; VCC = 1.8 to 2.4 V)
M28010-R
Symbol Alt. Parameter Test Condit ion Unit
Min Max
tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH, W= VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 120 ns

tELAX tAH Chip Enable Low to Address Transition 120 ns

tELEH tWP Chip Enable Low to Chip Enable High 120 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

tWHGL tOEH Write Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 100 ns

tWLWH tWP Write Enable Low to Write Enable High 120 ns

tWLQ5H tBLC Time-out after the last byte write 150 µs

Byte Write Cycle time 5 ms
tWHRH tWC
Page Write Cycle time (up to 128 bytes) 10 ms
tDVWH tDS Data Valid before Write Enable High 120 ns
tDVEH tDS Data Valid before Chip Enable High 120 ns

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 M28010

Figure 12. Write Mode AC Waveforms (Write Enable, W, controlled)

A0-A16 VALID

tAVWL tWLAX

tELWL tWHEH

tGHWL tWLWH tWHGL

tWHWL

DQ0-DQ7 DATA IN

tDVWH tWHDX

AI02230

Figure 13. Write Mode AC Waveforms (Chip Enable, E, controlled)

A0-A16 VALID

tAVEL tELAX

tGHEL tELEH

tWLEL tEHGL

tEHWH

DQ0-DQ7 DATA IN

tDVEH tEHDX

AI02231

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M28010

Figure 14. Page Write Mode AC Waveforms (Write Enable, W, controlled)

A0-A12 Addr 0 Addr 1 Addr 2 Addr n

tWHWL

tWLWH

DQ0-DQ7 (in) Byte 0 Byte 1 Byte 2 Byte n

DQ5 (out)

tWLQ5H
tQ5HQ5X

AI02829

Figure 15. Software Protected Write Cycle Waveforms

A0-A6 Byte Add 0 Byte Add n

5555h 2AAAh 5555h

1
A7-A16 Page Add

tWHWL

tWLWH tDVWH tWHDX

DQ0-DQ7 AAh 55h A0h Byte 0 Byte n

AI02233B

Note: 1. A16 to A7 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.

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 M28010

Figure 16. Data Polling Sequence Waveforms

A0-A16 Address of the last byte of the Page Write instruction

tWHGL

DQ7

DQ7 DQ7 DQ7 DQ7 DQ7

LAST BYTE INTERNAL WRITE SEQUENCE READY

LOADED OR AFTER INTERNAL
TIME BETWEEN TWO CONSECUTIVE WRITE SEQUENCE
BYTES LOADING
AI02234

Figure 17. Toggle Bit Sequence Waveforms

A0-A16 Address of the last byte of the Page Write instruction

DQ6 (1)

LAST BYTE TOGGLE READY

LOADED INTERNAL WRITE SEQUENCE AFTER INTERNAL
OR WRITE SEQUENCE
TIME BETWEEN TWO CONSECUTIVE
BYTES LOADING
AI02235

Note: 1. The Toggle Bit is first set to ‘0’.

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M28010

Table 10. Ordering Information Scheme

Example: M28010 -10 W KA 6 T

Option
T Tape & Reel Packing

Speed

-10 100 ns Temperature Range

-12 120 ns 11 0 to 70 °C
-15 150 ns 6 –40 to 85 °C
-20 200 ns
-25 250 ns

Operating Voltage Package

blank 4.5 V to 5.5 V BA PDIP32
W 2.7 V to 3.6 V KA PLCC32
R 1.8 V to 2.4 V NA TSOP32: 8 x 20mm

Note: 1. This temperature range on request only.

ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 10. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.

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 M28010

Table 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N 32 32

Figure 18. PDIP32 (BA)

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Note: 1. Drawing is not to scale.

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M28010

Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004

Figure 19. PLCC32 (KA)

D A1
D1 A2

1 N
B1

Ne E1 E D2/E2 e
F
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Note: 1. Drawing is not to scale.

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 M28010

Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.20 0.047
A1 0.05 0.17 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 32 32
CP 0.10 0.004

Figure 20. TSOP32 (NS)

A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L

Note: 1. Drawing is not to scale.

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M28010

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
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