CAT22C10

256-Bit Nonvolatile CMOS Static RAM

FEATURES
■ Single 5V Supply ■ Low CMOS Power Consumption:
■ Fast RAM Access Times: –Active: 40mA Max.
–200ns –Standby: 30 µA Max.
–300ns ■ JEDEC Standard Pinouts:
2
■ Infinite E PROM to RAM Recall –18-pin DIP
–16-pin SOIC
■ CMOS and TTL Compatible I/O
■ 10 Year Data Retention
■ Power Up/Down Protection
■ Commercial, Industrial and Automotive
■ 100,000 Program/Erase Cycles (E2PROM) Temperature Ranges

DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory writes or internal recalls from E2PROM. Internal false
organized as 64 words x 4 bits. The high speed Static store protection circuitry prohibits STORE operations
RAM array is bit for bit backed up by a nonvolatile when VCC is less than 3.0V.
E2PROM array which allows for easy transfer of data
from RAM array to E2PROM (STORE) and from The CAT22C10 is manufactured using Catalyst’s ad-
E2PROM to RAM (RECALL). STORE operations are vanced CMOS floating gate technology. It is designed
completed in 10ms max. and RECALL operations typi- to endure 100,000 program/erase cycles (E2PROM)
cally within 1.5µs. The CAT22C10 features unlimited and has a data retention of 10 years. The device is
RAM write operations either through external RAM available in JEDEC approved 18-pin plastic DIP and 16-
pin SOIC packages.

PIN CONFIGURATION PIN FUNCTIONS

DIP Package (P) SOIC Package (J) Pin Name Function
A0–A5 Address
A4 1 16 Vcc
NC 1 18 Vcc I/O0–I/O3 Data In/Out
A3 2 15 A5
A4 2 17 NC
A2 3 14 I/O4 WE Write Enable
A3 3 16 A5
A1 4 13 I/O3
A2 4 15 I/O3 CS Chip Select
A0 5 12 I/O2
A1 5 14 I/O2
CS 6 11 I/O1 RECALL Recall
A0 6 13 I/O1
Vss 7 10 WE
CS 7 12 I/O0
9
STORE Store
STORE 8 RECALL
Vss 8 11 WE
VCC +5V
STORE 9 10 RECALL
VSS Ground
22C10 F01 22C10 F02
NC No Connect

© 1998 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice 6-1
CAT22C10

BLOCK DIAGRAM

E2PROM ARRAY

A0 ROW STATIC RAM

STORE
A1
A2 SELECT ARRAY
RECALL
A3
A4 COLUMN SELECT
A5

STORE CONTROL READ/WRITE

LOGIC CIRCUITS
RECALL

CS WE I/O0 I/O1 I/O2 I/O3

5153 FHD F02

MODE SELECTION(1)(2)(3)
Input
Mode CS WE RECALL STORE I/O
Standby H X H H Output High-Z
RAM Read L H H H Output Data
RAM Write L L H H Input Data
(E2PROM→RAM) X H L H Output High-Z RECALL
(E2PROM→RAM) H X L H Output High-Z RECALL
(RAM→E2PROM) X H H L Output High-Z STORE
(RAM→E2PROM) H X H L Output High-Z STORE

POWER-UP TIMING(4)
Symbol Parameter Min. Max. Units
VCCSR VCC Slew Rate 0.5 0.005 V/ms

Note:
(1) RECALL signal has priority over STORE signal when both are applied at the same time.
(2) STORE is inhibited when RECALL is active.
(3) The store operation is inhibited when VCC is below ≈ 3.0V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.

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 CAT22C10

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
Voltage on Any Pin with of the device at these or any other conditions outside of
Respect to Ground(2) .............. -2.0 to +VCC +2.0V those listed in the operational sections of this specifica-
VCC with Respect to Ground ................ -2.0V to +7.0V tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation mance and reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND(1) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(1) Data Retention 10 Years MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Unit Conditions
ICC Current Consumption 40 mA All Inputs = 5.5V
(Operating) TA = 0°C
All I/O’s Open
ISB Current Consumption 30 µA CS = VCC
(Standby) All I/O’s Open
ILI Input Current 10 µA 0 ≤ VIN ≤ 5.5V
ILO Output Leakage Current 10 µA 0 ≤ VOUT ≤ 5.5V
VIH High Level Input Voltage 2 VCC V
VIL Low Level Input Voltage 0 0.8 V
VOH High Level Output Voltage 2.4 V IOH = –2mA
VOL Low Level Output Voltage 0.4 V IOL = 4.2mA
VDH RAM Data Holding Voltage 1.5 5.5 V VCC

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Parameter Max. Unit Conditions
CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.

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CAT22C10

A.C. CHARACTERISTICS, Write Cycle

VCC = +5V ±10%, unless otherwise specified.

22C10-20 22C10-30
Symbol Parameter Min. Max. Min. Max. Unit Conditions
tWC Write Cycle Time 200 300 ns
tCW CS Write Pulse Width 150 150 ns
tAS Address Setup Time 50 50 ns CL = 100pF
tWP Write Pulse Width 150 150 ns +1TTL gate
tWR Write Recovery Time 25 25 ns VOH = 2.2V
tDW Data Valid Time 100 100 ns VOL = 0.65V
tDH Data Hold Time 0 0 ns VIH = 2.2V
tWZ(1) Output Disable Time 100 100 ns VIL = 0.65V
tOW Output Enable Time 0 0 ns

A.C. CHARACTERISTICS, Read Cycle

VCC = +5V ±10%, unless otherwise specified.

22C10-20 22C10-30
Symbol Parameter Min. Max. Min. Max. Unit Conditions
tRC Read Cycle Time 200 300 ns CL = 100pF
tAA Address Access Time 200 300 ns +1TTL gate
tCO CS Access Time 200 300 ns VOH = 2.2V
tOH Output Data Hold Time 0 0 ns VOL = 0.65V
tLZ(1) CS Enable Time 0 0 ns VIH = 2.2V
tHZ(1) CS Disable Time 100 100 ns VIL = 0.65V

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

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 CAT22C10

A.C. CHARACTERISTICS, Store Cycle

VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Units Conditions
tSTC Store Time 10 ms
tSTP Store Pulse Width 200 ns CL = 100pF + 1TTL gate
tSTZ(1) Store Disable Time 100 ns VOH = 2.2V, VOL = 0.65V
tOST(1) Store Enable Time 0 ns VIH = 2.2V, VIL = 0.65V

A.C. CHARACTERISTICS, Recall Cycle

VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Units Conditions
tRCC Recall Cycle Time 1.4 µs
tRCP Recall Pulse Width 300 ns CL = 100pF + 1TTL gate
tRCZ Recall Disable Time 100 ns VOH = 2.2V, VOL = 0.65V
tORC Recall Enable Time 0 ns VIH = 2.2V, VIL = 0.65V
tARC Recall Data Access Time 1.1 µs

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

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CAT22C10

DEVICE OPERATION into the Static RAM. When the STORE input is taken low,
it initiates a store operation which transfers the entire
The configuration of the CAT22C10 allows a common Static RAM array contents into the E2PROM array.
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be Standby Mode
directly connected to a common I/O bus if the bus has The chip select (CS) input controls all of the functions of
less than 1 TTL load and 100pF capacitance. If not, the the CAT22C10. When a high level is supplied to the CS
I/O path should be buffered. pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
When the chip select (CS) pin goes low, the device is power consumption is drastically reduced. With ISB less
activated. When CS is forced high, the device goes into than 100µA in standby mode, the designer has the
the standby mode and consumes very little current. With flexibility to use this part in battery operated systems.
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a Read
write operation when WE is low and a read operation When the chip is enabled (CS = low), the nonvolatile
when WE is high. In either of these modes, an array byte functions are inhibited (STORE = high and RECALL =
(4 bits) can be addressed uniquely by using the address high). With the Write Enable (WE) pin held high, the data
lines (A0–A5), and that byte will be read or written to in the Static RAM array may be accessed by selecting an
through the Input/Output pins (I/O0–I/O3). address with input pins A0–A5. This will occur when the
The nonvolatile functions are inhibited by holding the outputs are connected to a bus which is loaded by no
STORE input and the RECALL input high. When the more than 100pF and 1 TTL gate. If the loading is greater
RECALL input is taken low, it initiates a recall operation than this, some additional buffering circuitry is recom-
which transfers the contents of the entire E2PROM array mended.

Figure 1. Read Cycle Timing

tRC

ADDRESS
tAA
tCO

CS

tLZ tOH tHZ

HIGH-Z
DATA I/O DATA VALID

5153 FHD F06

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 CAT22C10

Write
With the chip enabled and the nonvolatile functions cluding the write pulse width time (tWP) are met, the data
inhibited, the Write Enable (WE) pin will select the write will be written to the specified location in the Static RAM.
mode when driven to a low level. In this mode, the A write function may also be initiated from the standby
address must be supplied for the byte being written. mode by driving WE low, inhibiting the nonvolatile func-
After the set-up time (tAS), the input data must be tions, supplying valid addresses, and then taking CS low
supplied to pins I/O0–I/O3. When these conditions, in- and supplying input data.

Figure 2. Write Cycle Timing

tWC

ADDRESS

tCW

CS

tAS tWP tWR

WE

tDW tDH

DATA IN DATA VALID

tWZ tOW
HIGH-Z
DATA OUT

5153 FHD F04

Figure 3. Early Write Cycle Timing

tWC

ADDRESS

tCW

CS
tAS
tWR
tWP
WE

tDW tDH

DATA IN DATA VALID

HIGH-Z
DATA OUT

5153 FHD F05

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CAT22C10

Recall place independent of the state of CS, WE or A0–A5. The

At anytime, except during a store operation, taking the STORE pin must be held low for the duration of the Store
RECALL pin low will initiate a recall operation. This is Pulse Width (tSTP) to ensure that a store operation is
independent of the state of CS, WE, or A0–A5. After the initiated. Once initiated, the STORE pin becomes a
RECALL pin has been held low for the duration of the “Don’t Care”, and the store operation will complete its
Recall Pulse Width (tRCP), the recall will continue inde- transfer of the entire contents of the Static RAM array
pendent of any other inputs. During the recall, the entire into the E2PROM array within the Store Cycle time
contents of the E2PROM array is transferred to the Static (tSTC). If a store operation is initiated during a write cycle,
RAM array. The first byte of data may be externally the contents of the addressed Static RAM byte and its
accessed after the recalled data access time from end of corresponding byte in the E2PROM array will be un-
recall (tARC) is met. After this, any other byte may be known.
accessed by using the normal read mode. During the store operation, the outputs are in a high
If the RECALL pin is held low for the entire Recall Cycle impedance state. A minimum of 100,000 store opera-
time (tRCC), the contents of the Static RAM may be tions can be performed reliably and the data written into
immediately accessed by using the normal read mode. the E2PROM array has a minimum data retention time
A recall operation can be performed an unlimited num- of 10 years.
ber of times without affecting the integrity of the data. DATA PROTECTION DURING POWER-UP AND
The outputs I/O0–I/O3 will go into the high impedance POWER-DOWN
state as long as the RECALL signal is held low. The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when VCC falls below
Store 3.0V typ. This function eliminates the potential hazard of
At any time, except during a recall operation, taking the spurious signals initiating a store operation when the
STORE pin low will initiate a store operation. This takes system power is below 3.0V typ.

Figure 4. Recall Cycle Timing

tRCC

ADDRESS

tRCP

RECALL

tARC

CS

tORC
HIGH-Z
DATA I/O DATA UNDEFINED DATA VALID

tRCZ 5153 FHD F08

Figure 5. Store Cycle Timing

tSTC
tSTP

STORE

tSTZ tOST
HIGH-Z
DATA I/O

5153 FHD F07

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 CAT22C10

ORDERING INFORMATION

Prefix Device # Suffix

CAT 22C10 J I -20 -TE13

Optional Product Temperature Range Tape & Reel

Company ID Number Blank = Commercial (0˚ - 70˚C) TE13: 2000/Reel
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*

Package Speed
P: PDIP 20: 200ns
J: SOIC (JEDEC) 30: 300ns

* -40˚ to +125˚C is available upon request

22C10 F08

Notes:
(1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel)

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CAT22C10

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