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    System Clock and Clock Options

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    System Clock and Clock Options

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    salar
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    no2

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    Atmel_0024

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    no2

    Copyright:

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    56 views1 page

    System Clock and Clock Options

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    salar
    no2

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 1

    8.

    System Clock and Clock Options

    8.1 Clock Systems and their Distribution


    Figure 8-1 presents the principal clock systems in the AVR® and their distribution. All of the clocks need not be active at a
    given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different
    sleep modes, as described in Section 9. “Power Management and Sleep Modes” on page 34. The clock systems are detailed
    below.

    Figure 8-1. Clock Distribution

    Asynchronous General I/O Flash and


    ADC CPU Core RAM
    Timer/Counter Modules EEPROM

    clkADC

    clkI/O clkCPU
    AVR Clock
    Control Unit
    clkASY clkFLASH

    System Clock
    Reset Logic Watchdog Timer
    Prescaler

    Source clock Watchdog clock

    Clock Watchdog
    Multiplexer Oscillator

    Timer/Counter Crystal Low-frequency Calibrated RC


    External Clock
    Oscillator Oscillator Crystal Oscillator Oscillator

    8.1.1 CPU Clock – clkCPU


    The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are
    the general purpose register file, the status register and the data memory holding the stack pointer. Halting the CPU clock
    inhibits the core from performing general operations and calculations.

    8.1.2 I/O Clock – clkI/O


    The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by
    the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such
    interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried
    out asynchronously when clkI/O is halted, TWI address recognition in all sleep modes.

    8.1.3 Flash Clock – clkFLASH


    The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock.

    24 ATmega328P [DATASHEET]
    7810D–AVR–01/15

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