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8.2 Clock Sources: 8.1.4 Asynchronous Timer Clock - CLK

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41 views1 page

8.2 Clock Sources: 8.1.4 Asynchronous Timer Clock - CLK

no2

Uploaded by

salar
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8.1.

4 Asynchronous Timer Clock – clkASY


The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an
external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when
the device is in sleep mode.

8.1.5 ADC Clock – clkADC


The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.

8.2 Clock Sources


The device has the following clock source options, selectable by flash fuse bits as shown below. The clock from the selected
source is input to the AVR® clock generator, and routed to the appropriate modules.

Table 8-1. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0


Low power crystal oscillator 1111 - 1000
Full swing crystal oscillator 0111 - 0110
Low frequency crystal oscillator 0101 - 0100
Internal 128kHz RC oscillator 0011
Calibrated internal RC oscillator 0010
External clock 0000
Reserved 0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.2.1 Default Clock Source


The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz
system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = “0010”, SUT = “10”,
CKDIV8 = “0”). The default setting ensures that all users can make their desired clock source setting using any available
programming interface.

8.2.2 Clock Startup Sequence


Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be
considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by
all other reset sources. Section 10. “System Control and Reset” on page 40 describes the start conditions for the internal
reset. The delay (tTOUT) is timed from the watchdog oscillator and the number of cycles in the delay is set by the SUTx and
CKSELx fuse bits. The selectable delays are shown in Table 8-2. The frequency of the watchdog oscillator is voltage
dependent as shown in Section 29. “Typical Characteristics” on page 268.

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0ms 0ms 0
4.1ms 4.3ms 512
65ms 69ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the
actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or
external brown-out detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and
the time-out delay can be disabled. Disabling the time-out delay without utilizing a brown-out detection circuit is not
recommended.

ATmega328P [DATASHEET] 25
7810D–AVR–01/15

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