Low Voltage Cmos Quad 2-Input or Gate With 5V Tolerant Inputs
Low Voltage Cmos Quad 2-Input or Gate With 5V Tolerant Inputs
Low Voltage Cmos Quad 2-Input or Gate With 5V Tolerant Inputs
■ 5V TOLERANT INPUTS
■ HIGH SPEED:
tPD = 5.2ns (MAX.) at VCC = 3V
■ POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V SOP TSSOP
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: Table 1: Order Codes
tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE: PACKAGE T&R
VCC(OPR) = 2.0V to 3.6V (1.5V Data
SOP 74LCX32MTR
Retention)
TSSOP 74LCX32TTR
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32
■ LATCH-UP PERFORMANCE EXCEEDS technology. It is ideal for low power and high
500mA (JESD 17) speed 3.3V applications; it can be interfaced to 5V
■ ESD PERFORMANCE: signal environment for inputs.
HBM > 2000V (MIL STD 883 method 3015); It has same speed performance at 3.3V than 5V
MM > 200V AC/ACT family, combined with a lower power
consumption.
DESCRIPTION All inputs and outputs are equipped with
The 74LCX32 is a low voltage CMOS QUAD protection circuits against static discharge, giving
2-INPUT OR GATE fabricated with sub-micron them 2KV ESD immunity and transient excess
silicon gate and double-layer metal wiring C2MOS voltage.
Rev. 6
September 2004 1/11
74LCX32
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
2/11
74LCX32
Table 6: DC Specifications
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
3/11
74LCX32
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
4/11
74LCX32
5/11
74LCX32
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
e 1.27 0.050
k 0° 8° 0° 8°
0016019D
6/11
74LCX32
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
K 0˚ 8˚ 0˚ 8˚
A A2
K L
A1 b e c E
E1
PIN 1 IDENTIFICATION
1
0080337D
7/11
74LCX32
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
D 20.2 0.795
N 60 2.362
T 22.4 0.882
8/11
74LCX32
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
D 20.2 0.795
N 60 2.362
T 22.4 0.882
9/11
74LCX32
10/11
74LCX32
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
11/11