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Computer Organisation and Architecture MCQ Part 1

This document contains 30 multiple choice questions about computer organization and architecture. The questions cover topics like memory types, addressing modes, instruction cycles, registers, buses, and logic gates. They test understanding of concepts like memory hierarchy, cache memory, instruction fetching, and basic computer components like ALU, registers, and buses.

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Vimeno Dolie
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1K views5 pages

Computer Organisation and Architecture MCQ Part 1

This document contains 30 multiple choice questions about computer organization and architecture. The questions cover topics like memory types, addressing modes, instruction cycles, registers, buses, and logic gates. They test understanding of concepts like memory hierarchy, cache memory, instruction fetching, and basic computer components like ALU, registers, and buses.

Uploaded by

Vimeno Dolie
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Computer Organisation and architecture MCQ Part 1


1: A combinational logic circuit which sends data coming from a single source to two or more
separate destinations is
(A) Decoder.
(B) Encoder.
(C) Demultiplexer.
Ans: D

2: In which addressing mode the operand is given explicitly in the instruction


(A) Immediate.
(B) Indirect.
(C) Direct.
Ans: B

3: The average time required to reach a storage location in memory and obtain its contents is
called
(A)Latency
(B) Access time.
(C) Turnaround time.
(D) Response time.
Ans: B

4: The memory unit that communicates directly with the CPU is called the
(A) Main memory
(B) Secondary memory
(C) Shared memory
(D) Auxiliary memory.
Ans: A

5: The maximum addressing capacity of a microprocessor which uses 16 bit database & 32 bit
address base is
(A) 64 K.
(B) 4 GB.
(C) Both (A) & (B).
(D) None of these.
Ans: B

6: In Assembly language programming, minimum number of operands required for an


instruction is/are
(A) Three
(B) One.
(C) Two.
(D) Both (B) & (C).
Ans: A
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7: Which of the following is a main memory


(A) Secondary Memory
(B) Auxiliary memory.
(C) Cache memory.
(D) Virtual memory.
Ans: C

8: What is the content of Stack Pointer (SP)?


(A) Address of the current instruction
(B) Address of the next instruction
(C) Address of the top element of the stack
(D) Size of the stack
Ans: C

9: A register capable of shifting its binary information either to the right or the left is called
(A) Parallel register
(B) Serial register.
(C) Shift register.
(D) Storage register.
Ans: C

10: An interface that provides I/O transfer of data directly to and from the memory unit and
peripheral is termed as
(A) Serial interface.
(B) BR.
(C) DMA.
Ans: C

11.Which of the memory holds the information when the Power Supply is switched off?
(A) Static RAM
(B) Dynamic RAM
(C) EEROM
(D) None of the above
Ans: C

12.     In computers, subtraction is generally carried out by


(A) 9’s complement
(B) 10’s complement
(C) 1’s complement
(D) 2’s complement
Ans: D

13.     Which logic is known as universal logic?


(A) PAL logic.
(B) NAND logic.
(C) MUX logic.
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(D) Decoder logic.


Ans: B

14.     Minimum of NAND gate required to implement a Ex-OR function is


(A) 2
(B) 3
(C) 4
(D) 5
Ans: C

15.     When an instruction is read from the memory, it is called


(A) Memory Read cycle
(B) Fetch cycle
(C) Instruction cycle
(D) Memory write cycle
Ans: B

16.     A demultiplexer can be used as


(A) Encoder
(B) Decoder
(C) Multiplexer
(D) None of the above
Ans: B

17.     An interrupt for which hardware automatically transfers the program to a specific memory
location is known as
(A) Software interrupt
(B) Hardware interrupt
(C) Maskable interrupt
(D) Vector interrupt
Ans:B

18.     The idea of cache memory is based


(A) on the property of locality of reference
(B) on the heuristic 90-10 rule
(C) on the fact that references generally tend to cluster
(D) all of the above
Ana: A

19.     Synchronous means


(A) At irregular intervals
(B) At same time
(C) At variable time
(D) None of these
Ans: B
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20.   Cache memory works on the principle of


(A) Locality of
(B) Locality of reference
(C) Locality of memory
(D) Locality of reference & memory
Ans: B

21.    Which activity does not take place during execution cycle?
 (A) ALU performs the arithmetic & logical
(B) Effective address is
(C) Next instruction is
(D) Branch address is calculated & Branching conditions are checked.
Ans: D

22.   The average time required to reach a storage location in memory and obtain its contents is
called the
(A) seek time
(B) Turnaround time
(C) access time
(D) transfer time
Ans: C

23.   Computers use addressing mode techniques for.


(A) giving programming versatility to the user by providing facilities as pointers to memory
counters for loop control
(B) to reduce no. of bits in the field of instruction
(C) specifying rules for modifying or interpreting address field of the instruction
(D) All the above
Ans: D

24.   What characteristic of RAM memory makes it not suitable for permanent storage?
(A) too slow
(B) unreliable
(C) it is volatile
(D) too bulky
Ans: C

25.   The circuit used to store one bit of data is known as


(A) Register
(B) Encoder
(C) Decoder
(D) Flip Flop
Ans:D

26.   Register keeps track of the instructions stored in program stored in


(A) AR (Address Register)
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(B) XR (Index Register)


(C) PC (Program Counter)
(D) AC (Accumulator)
Ans:C

27.   Cache memory acts between


(A) CPU and RAM
(B) RAM and ROM
(C) CPU and Hard Disk
(D) None of these
Ans:A

28.   Which of the following is not a weighted code?


(a) Decimal Number system
(B) Excess 3-code
(C) Binary number System
(D) None of these
Ans:B

29.   Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data.
The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to
125 nsecs and the number of cycles required for transfer stayed the same what would the
bandwidth of the bus?
(A) 1 Megabyte/sec
(B) 4 Megabytes/sec
(C) 8 Megabytes/sec
(D) 2 Megabytes/sec
Ans:D

30.  What is always true for a n bit processor?


(A) Data bus has n line
(B) Address bus has n lines
(C) CPU register is made of n bits
(D) A and B
Ans:A

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