SmartVoltage FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT

E BYTE-WIDE
SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology n High-Density 64-Kbyte Symmetrical

 2.7 V (Read-Only), 3.3 V or 5 V V CC Erase Block Architecture
and 3.3 V, 5 V, or 12 V V PP  4 Mbit: Eight Blocks
n High-Performance  8 Mbit: Sixteen Blocks
 4, 8 Mbit 85 ns Read Access Time  16 Mbit: Thirty-Two Blocks
 16 Mbit 95 ns Read Access Time n Extended Cycling Capability
n Enhanced Data Protection Features  100,000 Block Erase Cycles
 Absolute Protection with V PP = GND n Low Power Management
 Flexible Block Locking  Deep Power-Down Mode
 Block Write Lockout during Power  Automatic Power Savings Mode
Transitions Decreases ICC in Static Mode
n Enhanced Automated Suspend Options n Automated Program and Block Erase
 Program Suspend to Read  Command User Interface
 Block Erase Suspend to Program  Status Register
 Block Erase Suspend to Read n SRAM-Compatible Write Interface
n Industry-Standard Packaging n ETOX™ V Nonvolatile Flash
 40-Lead TSOP, 44-Lead PSOP Technology
and 40 Bump µBGA* CSP
Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997 Order Number: 290600-003

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004SC, 28F008SC, 28F016SC may contain design defects or errors known as errata. Current characterized errata are
available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493

E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5 6.0 ELECTRICAL SPECIFICATIONS..................30

1.1 New Features...............................................5 6.1 Absolute Maximum Ratings ........................30
1.2 Product Overview.........................................5 6.2 Commercial Temperature Operating
1.3 Pinout and Pin Description ...........................6 Conditions .................................................30
6.3 Capacitance ...............................................30
2.0 PRINCIPLES OF OPERATION .....................12 6.4 DC Characteristics—Commercial
2.1 Data Protection ..........................................13 Temperature..............................................31
6.5 AC Characteristics—Read-Only
3.0 BUS OPERATION .........................................13 Operations—Commercial Temperature .....35
3.1 Read ..........................................................13 6.6 AC Characteristics—Write Operations—
3.2 Output Disable ...........................................13 Commercial Temperature..........................37
3.3 Standby......................................................13 6.7 Block Erase, Program, and Lock-Bit
3.4 Deep Power-Down .....................................13 Configuration Performance—Commercial
Temperature..............................................39
3.5 Read Identifier Codes Operation ................14
6.8 Extended Temperature Operating
3.6 Write ..........................................................14 Conditions .................................................40
4.0 COMMAND DEFINITIONS ............................14 6.9 DC Characteristics—Extended
Temperature..............................................40
4.1 Read Array Command................................17
6.10 AC Characteristics—Read-Only Operations
4.2 Read Identifier Codes Command ...............17 — Extended Temperature .........................40
4.3 Read Status Register Command................17
4.4 Clear Status Register Command................17 7.0 ORDERING INFORMATION..........................41
4.5 Block Erase Command ..............................17 8.0 ADDITIONAL INFORMATION .......................42
4.6 Program Command....................................18
4.7 Block Erase Suspend Command................18
4.8 Program Suspend Command .....................19
4.9 Set Block and Master Lock-Bit Commands 19
4.10 Clear Block Lock-Bits Command..............20
5.0 DESIGN CONSIDERATIONS ........................28

5.1 Three-Line Output Control..........................28
5.2 RY/BY# Hardware Detection ......................28
5.3 Power Supply Decoupling ..........................28
5.4 VPP Trace on Printed Circuit Boards...........28
5.5 VCC, VPP, RP# Transitions .........................28
5.6 Power-Up/Down Protection ........................28
5.7 VPP Program and Erase Voltages on Sub-
0.4µ SC Memory Family............................29
3
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
REVISION HISTORY
E
Number Description
-001 Original version
-002 Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP.
Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under ILO Test Conditions, previously read V IN = VCC
or GND, corrected to VOUT = VCC or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
-003 Added µBGA* CSP pinout and corrected error in PSOP pinout.
Added Design Consideration for VPP Program and Erase Voltages on future sub-0.4µ
devices.
4
PRELIMINARY
E
1.0 INTRODUCTION
1.2 Product Overview

This datasheet contains 4-, 8-, and 16-Mbit The byte-wide SmartVoltage FlashFile memory
SmartVoltage FlashFile memory specifications. family provides density upgrades with pinout
Section 1.0 provides a flash memory overview. compatibility for the 4-, 8-, and 16-Mbit densities.
Sections 2.0, through 5.0 describe the memory The 28F004SC, 28F008SC, and 28F016SC are
organization and functionality. Section 6.0 covers high-performance memories arranged as
electrical specifications for commercial and 512 Kbyte, 1 Mbyte, and 2 Mbyte of 8 bits. This
extended temperature product offerings. Section data is grouped in eight, sixteen, and thirty-two
7.0 contains ordering information. Finally, the byte- 64-Kbyte blocks which are individually erasable,
wide SmartVoltage FlashFile memory family lockable, and unlockable in-system. Figure 4
documentation also includes application notes and illustrates the memory organization.
design tools which are referenced in Section 8.0.
SmartVoltage technology enables fast factory
programming and low-power designs. These
1.1 New Features components support read operations at 2.7 V (read-
only), 3.3 V, and 5 V VCC and block erase and
The byte-wide SmartVoltage FlashFile memory program operations at 3.3 V, 5 V, and 12 V VPP.
family maintains backwards-compatibility with The 12 V VPP option renders the fastest program
Intel’s 28F008SA and 28F008SA-L. Key and erase performance which will increase your
enhancements include: factory throughput. With the 3.3 V and 5 V VPP
option, VCC and VPP can be tied together for a
• SmartVoltage Technology simple and voltage flexible design. This voltage
flexibility is key for removable media that need to
• Enhanced Suspend Capabilities operate in a 3 V to 5 V system. In addition, the
• In-System Block Locking dedicated VPP pin gives complete data protection
when VPP ≤ VPPLK.
They share a compatible status register, software
commands, and pinouts. These similarities enable Table 1. SmartVoltage Flash
a clean upgrade from the 28F008SA and VCC and VPP Voltage Combinations
28F008SA-L to byte-wide SmartVoltage FlashFile
VCC Voltage VPP Voltage
products. When upgrading, it is important to note
the following differences: 2.7 V(1) 
• Because of new feature and density options, 3.3 V 3.3 V, 5 V, 12 V

the devices have different device identifier 5V 5 V, 12 V
codes. This allows for software optimization.
NOTE:
• VPPLK has been lowered from 6.5 V to 1.5 V to
1. Block erase, program, and lock-bit configuration
support low VPP voltages during block erase, operation with VCC, 3.0 V are not supported.
program, and lock-bit configuration operations.
Designs that switch VPP off during read Internal VCC and VPP detection circuitry
operations should transition VPP to GND. automatically configures the device for optimum
performance.
• To take advantage of SmartVoltage tech-
nology, allow VPP connection to 3.3 V or 5 V. A Command User Interface (CUI) serves as the
interface between the system processor and
For more details see application note AP-625, internal operation of the device. A valid command
28F008SC Compatibility with 28F008SA (order sequence written to the CUI initiates device
number 292180). automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
5
PRELIMINARY
A block erase operation erases one of the device’s

E
the WSM is performing a block erase, program, or
64-Kbyte blocks typically within 1 second lock-bit configuration operation. RY/BY#-high
(5 V VCC, 12 V VPP), independent of other blocks. indicates that the WSM is ready for a new
Each block can be independently erased 100,000 command, block erase is suspended (and program
times (1.6 million block erases per device). A block is inactive), program is suspended, or the device is
erase suspend operation allows system software to in deep power-down mode.
suspend block erase to read data from or write data
to any other block. The Automatic Power Savings (APS) feature
substantially reduces active current when the
Data is programmed in byte increments typically device is in static mode (addresses not switching).
within 6 µs (5 V VCC, 12 V VPP). A program In APS mode, the typical ICCR current is 1 mA at
suspend operation permits system software to read 5 V VCC.
data or execute code from any other flash memory
array location. When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
To protect programmed data, each block can be RP# to GND enables a deep power-down mode
locked. This block locking mechanism uses a which significantly reduces power consumption,
combination of bits, block lock-bits and a master provides write protection, resets the device, and
lock-bit, to lock and unlock individual blocks. The clears the status register. A reset time (tPHQV) is
block lock-bits gate block erase and program required from RP# switching high until outputs are
operations, while the master lock-bit gates block valid. Likewise, the device has a wake time (tPHEL)
lock-bit configuration operations. Lock-bit config- from RP#-high until writes to the CUI are
uration operations (Set Block Lock-Bit, Set Master recognized.
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
1.3 Pinout and Pin Description
The status register and RY/BY# output indicate
whether or not the device is busy executing or The family of devices is available in 40-lead TSOP
ready for a new command. Polling the status (Thin Small Outline Package, 1.2 mm thick) and
register, system software retrieves WSM feedback. 44-lead PSOP (Plastic Small Outline Package) and
The RY/BY# output gives an additional indicator of 40-bump µBGA* CSP (28F008SC and 28F016SC
WSM activity by providing a hardware status signal. only). Pinouts are shown in Figures 2, 3 and 4.
Like the status register, RY/BY#-low indicates that
6
PRELIMINARY
DQ 0 - DQ 7
Output Input
Buffer Buffer
Identifier
I/O Logic VCC
Register
CE#
Status Command WE#
Register Register
OE#
RP#
Data
Comparator
4-Mbit: A0 - A18 , Y
Input Y Gating RY/BY#
8-Mbit: A 0 - A19 , Decoder Write State
Buffer
16-Mbit: A0 - A 20 Machine Program/Erase VPP
Voltage Switch
Address X 4-Mbit: Eight VCC

Latch Decoder 8-Mbit: Sixteen GND
16-Mbit: Thirty-Two
64-Kbyte Blocks
Address
Counter
Figure 1. Block Diagram
Table 2. Pin Descriptions

Sym Type Name and Function
A0–A20 INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit → A0–A18
8 Mbit → A0–A19
16 Mbit → A0–A20
DQ0–DQ7 INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at VHH enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = V HH overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V IH < RP# < VHH produce
spurious results and should not be attempted.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
7
PRELIMINARY
Table 3. Pin Descriptions (Continued)

E
Sym Type Name and Function
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, programming data, or configuring lock-bits.
SmartVoltage Flash → 3.3 V, 5 V, and 12 V V PP
With VPP ≤ VPPLK, memory contents cannot be altered. Block erase, program, and
lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious
results and should not be attempted.
VCC SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
for optimized read performance. Do not float any power pins.
SmartVoltage Flash → 2.7 V (Read-Only), 3.3 V, and 5 V V CC
With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. Device
operations at invalid VCC voltages (see DC Characteristics) produce spurious
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with VCC < 3.0 V are not supported.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
8
PRELIMINARY
28F016SC
28F008SC
28F004SC
A19 A19 NC 1 40 NC NC A 20
A18 A18 A18 2 39 NC NC NC
A17 A17 A17 3 38 WE# WE# WE#
A16 A16 A16 4 37 OE# OE# OE#
A15 A15 A15 5 36 RY/BY# RY/BY# RY/BY#
A14 A14 A14 6 35 DQ7 DQ7 DQ7
A13 A13 A13 7 34 DQ6 DQ6 DQ6
A12 A12 A12 8 40-LEAD TSOP 33 DQ5 DQ5 DQ5
CE# CE# CE# 9 STANDARD PINOUT 32 DQ 4 DQ 4 DQ 4
VCC VCC VCC 10 10 mm x 20 mm 31 VCC VCC VCC
VPP VPP VPP 11 30 GND GND GND
TOP VIEW
RP# RP# RP# 12 29 GND GND GND
A11 A11 A11 13 28 DQ3 DQ3 DQ3
A10 A10 A10 14 27 DQ2 DQ2 DQ2
A9 A9 A9 26 DQ1 DQ1 DQ1
15
A8 A8 A8 16 25 DQ0 DQ0 DQ0
A7 A7 A7 17 24 A0 A0 A0
A6 A6 A6 18 23 A1 A1 A1
A5 A5 A5 19 22 A2 A2 A2
A4 A4 A4 20 21 A3 A3 A3
Figure 2. TSOP 40-Lead Pinout
9
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
Figure 3. PSOP 44-Lead Pinout
10
PRELIMINARY
8 7 6 5 4 3 2 1
A
A7 A9 RP# VPP VCC A12 A15 A17
B
A6 A10 A11 CE# A13 A14 A16 A18
C
A4 A5 A3 A8 NC A19 RY/BY# A20
D
A2 A0 D1 D3 GND D4 D6 WE#
E
A1 D0 D2 GND VCC D5 D7 OE#
Bottom View - Bump Side Up

Pin #1
Indicator 1 2 3 4 5 6 7 8
A
A17 A15 A12 VCC VPP RP# A9 A7
B
A18 A16 A14 A13 CE# A11 A10 A6
C
NC RY/BY# A19 NC A8 A3 A5 A4
D
WE# D6 D4 GND D3 D1 A0 A2
E
OE# D7 D5 VCC GND D2 D0 A1
Top View - Bump Side Down

This is the view of the package as surface mounted on the board.
Note that the signals are mirror images of bottom view.
NOTES:
1. Figures are not drawn to scale.
2. Address A20 is not included in the 28F008SC.
3. More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4. µBGA* CSP 40-Ball Pinout (28F008SC and 28F016SC)
11
PRELIMINARY
2.0 PRINCIPLES OF OPERATION
1FFFFF
The byte-wide SmartVoltage FlashFile memories 64-Kbyte Block 31
1F0000
include an on-chip WSM to manage block erase, 1EFFFF
program, and lock-bit configuration functions. It 1E0000
64-Kbyte Block 30
1DFFFF
allows for: 100% TTL-level control inputs, fixed 64-Kbyte Block 29
1D0000
power supplies during block erasure, program, and 1CFFFF
64-Kbyte Block 28
lock-bit configuration, and minimal processor 1C0000
1BFFFF
overhead with RAM-like interface timings. 1B0000
64-Kbyte Block 27
1AFFFF
64-Kbyte Block 26
After initial device power-up or return from deep 1A0000
19FFFF
power-down mode (see Bus Operations), the 190000
64-Kbyte Block 25
device defaults to read array mode. Manipulation of 18FFFF
64-Kbyte Block 24
external memory control pins allow array read, 180000
17FFFF
standby, and output disable operations. 170000
64-Kbyte Block 23
16FFFF
64-Kbyte Block 22
Status register and identifier codes can be 160000
15FFFF
accessed through the CUI independent of the VPP 150000
64-Kbyte Block 21
voltage. High voltage on VPP enables successful 14FFFF
64-Kbyte Block 20
140000
block erasure, program, and lock-bit configuration. 13FFFF
All functions associated with altering memory 130000
64-Kbyte Block 19
contents—block erase, program, lock-bit 12FFFF
64-Kbyte Block 18
120000
configuration, status, and identifier codes—are 11FFFF
accessed via the CUI and verified through the 110000
64-Kbyte Block 17
10FFFF
status register. 64-Kbyte Block 16
100000 16-Mbit
0FFFFF
Commands are written using standard micro- 0F0000
64-Kbyte Block 15
0EFFFF
processor write timings. The CUI contents serve as 64-Kbyte Block 14
0E0000
input to the WSM that controls block erase, 0DFFFF
program, and lock-bit configuration operations. The 0D0000
64-Kbyte Block 13
0CFFFF
internal algorithms are regulated by the WSM, 0C0000
64-Kbyte Block 12
including pulse repetition, internal verification, and 0BFFFF
64-Kbyte Block 11
margining of data. Addresses and data are 0B0000
0AFFFF
internally latched during write cycles. Writing the 0A0000
64-Kbyte Block 10
appropriate command outputs array data, accesses 09FFFF
64-Kbyte Block 9
the identifier codes, or outputs status register data. 090000
08FFFF 8-Mbit
080000
64-Kbyte Block 8
Interface software that initiates and polls progress 07FFFF
64-Kbyte Block 7
of block erase, program, and lock-bit configuration 070000
06FFFF
can be stored in any block. This code is copied to 060000
64-Kbyte Block 6
and executed from system RAM during flash 05FFFF
64-Kbyte Block 5
memory updates. After successful completion, 050000
04FFFF
reads are again possible via the Read Array 040000
64-Kbyte Block 4
command. Block erase suspend allows system 03FFFF 4-Mbit
030000
64-Kbyte Block 3
software to suspend a block erase to read or write 02FFFF
data from any other block. Program suspend allows 020000
64-Kbyte Block 2
system software to suspend a program to read data 01FFFF

64-Kbyte Block 1
010000
from any other flash memory array location. 00FFFF
000000
64-Kbyte Block 0
Figure 5. Memory Map
12
PRELIMINARY
E
2.1 Data Protection
3.2 Output Disable

Depending on the application, the system designer With OE# at a logic-high level (VIH), the device
may choose to make the VPP power supply outputs are disabled. Output pins DQ0–DQ7 are
switchable (available only when memory block placed in a high-impedance state.
erases, programs, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates either design practice and 3.3 Standby
encourages optimization of the processor-memory
interface. CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
When VPP ≤ VPPLK, memory contents cannot be power consumption. DQ0–DQ7 outputs are placed
altered. When high voltage is applied to VPP, the in a high-impedance state independent of OE#. If
two-step block erase, program, or lock-bit deselected during block erase, program, or
configuration command sequences provides pro- lock-bit configuration, the device continues
tection from unwanted operations. All write functioning and consuming active power until the
functions are disabled when VCC voltage is below operation completes.
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability provides
additional protection from inadvertent code or data 3.4 Deep Power-Down
alteration by gating erase and program operations.
RP# at VIL initiates the deep power-down mode.
3.0 BUS OPERATION In read mode, RP#-low deselects the memory,

places output drivers in a high-impedance state,
The local CPU reads and writes flash memory and turns off all internal circuits. RP# must be held
in-system. All bus cycles to or from the flash low for time tPLPH. Time tPHQV is required after
memory conform to standard microprocessor bus return from power-down until initial memory access
cycles. outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
3.1 Read 80H.
Block information, identifier codes, or status register During block erase, program, or lock-bit
can be read independent of the VPP voltage. RP# configuration, RP#-low will abort the operation.
can be at either VIH or VHH. RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
The first task is to write the appropriate read-mode longer valid; the data may be partially erased or
command (Read Array, Read Identifier Codes, or written. Time tPHWL is required after RP# goes to
Read Status Register) to the CUI. Upon initial logic-high (VIH) before another command can be
device power-up or after exit from deep power- written.
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow As with any automated device, it is important to
in and out of the component: CE#, OE#, WE#, and assert RP# during system reset. When the system
RP#. CE# and OE# must be driven active to obtain comes out of reset, it expects to read from the flash
data at the outputs. CE# is the device selection memory. Automated flash memories provide status
control, and when active enables the selected information when accessed during block erase,
memory device. OE# is the data output (DQ0–DQ7) program, or lock-bit configuration modes. If a CPU
control and when active drives the selected reset occurs with no flash memory reset, proper
memory data onto the I/O bus. WE# must be at VIH CPU initialization may not occur because the flash
and RP# must be at VIH or VHH. Figure 18 memory may be providing status information
illustrates a read cycle. instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
13
PRELIMINARY
3.5 Read Identifier Codes

E
Operation
1FFFFF
Block 31 The read identifier codes operation outputs the
Reserved for manufacturer code, device code, block lock
Future Implementation configuration codes for each block, and master lock
configuration code (see Figure 6). Using the
1F0002 Block 31 Lock Configuration
manufacturer and device codes, the system
Reserved for
1F0000 Future Implementation
software can automatically match the device with its
proper algorithms. The block lock and master lock
(Blocks 16 through 30) configuration codes identify locked and unlocked
0FFFFF
blocks and master lock-bit setting.
Block 15
Reserved for
Future Implementation 3.6 Write
0F0002 Block 15 Lock Configuration The CUI does not occupy an addressable memory
Reserved for location. It is written when WE# and CE# are active
0F0000 Future Implementation
and OE# = VIH. The address and data needed to
(Blocks 8 through 14) execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
07FFFF 16-Mbit
Block 7 Standard microprocessor write timings are used.
Figure 18 illustrates a write operation.
Reserved for
Future Implementation
070002 Block 7 Lock Configuration 4.0 COMMAND DEFINITIONS

Reserved for
070000 Future Implementation
8-Mbit When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
(Blocks 2 through 14)
are enabled. Placing VPPH1/2/3 on VPP enables
01FFFF
Block 1 successful block erase, program, and lock-bit
configuration operations.
Reserved for
Future Implementation 4-Mbit
Device operations are selected by writing specific
010002 Block 1 Lock Configuration commands into the CUI. Table 4 defines these
Reserved for commands.
010000 Future Implementation
00FFFF Block 0
Reserved For
Future Implementation
000003 Master Lock Configuration
000002 Block 0 Lock Configuration
000001 Device Code
000000 Manufacturer Code
Figure 6. Device Identifier Code Memory Map
14
PRELIMINARY
Table 3. Bus Operations

Mode Notes RP# CE# OE# WE# Address VPP DQ0–7 RY/BY#
Read 1,2,3 VIH or VIL VIL VIH X X DOUT X
VHH
Output Disable 3 VIH or VIL VIH VIH X X High Z X
VHH
Standby 3 VIH or VIH X X X X High Z X
VHH
Deep Power-Down 4 VIL X X X X X High Z VOH
Read Identifier Codes VIH or VIL VIL VIH See X Note 5 VOH
VHH Figure 5
Write 3,6,7 VIH or VIL VIH VIL X X DIN X
VHH
NOTES:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for VPPLK and
VPPH1/2/3 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH
when the WSM is not busy, in block erase suspend mode (with program inactive), program suspend mode, or deep power-
down mode.
4. RP# at GND ± 0.2 V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and
VCC = VCC2/3 (see Section 6.2 for operating conditions).
7. Refer to Table 4 for valid DIN during a write operation.
15
PRELIMINARY
Table 4. Command Definitions(9)

E
Bus Cycles First Bus Cycle Second Bus Cycle
Command Req’d. Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Program 2 5,6 Write PA 40H Write PA PD
or
10H
Block Erase and Program 1 5 Write X B0H
Suspend
Block Erase and Program 1 5 Write X D0H
Resume
Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H
Set Master Lock-Bit 2 7 Write X 60H Write X F1H
Clear Block Lock-Bits 2 8 Write X 60H Write X D0H
NOTES:
1. Bus operations are defined in Table 3.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 7 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
16
PRELIMINARY
E
4.1 Read Array Command
4.3 Read Status Register

Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read The status register may be read to determine when
array mode. This operation is also initiated by a block erase, program, or lock-bit configuration is
writing the Read Array command. The device complete and whether the operation completed
remains enabled for reads until another command successfully. It may be read at any time by writing
is written. Once the internal WSM has started a the Read Status Register command. After writing
block erase, program or lock-bit configuration, the this command, all subsequent read operations
device will not recognize the Read Array command output data from the status register until another
until the WSM completes its operation unless the valid command is written. The status register
WSM is suspended via an Erase Suspend or contents are latched on the falling edge of OE# or
Program Suspend command. The Read Array CE#, whichever occurs first. OE# or CE# must
command functions independently of the VPP toggle to VIH to update the status register latch. The
voltage and RP# can be VIH or VHH. Read Status Register command functions
independently of the VPP voltage. RP# can be VIH
or VHH.
4.2 Read Identifier Codes
Command
4.4 Clear Status Register
The identifier code operation is initiated by writing Command
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown Status register bits SR.5, SR.4, SR.3, and SR.1 are
in Figure 5 retrieve the manufacturer, device, block set to “1”s by the WSM and can only be reset by
lock configuration and master lock configuration the Clear Status Register command. These bits
codes (see Table 5 for identifier code values). To indicate various failure conditions (see Table 7). By
terminate the operation, write another valid allowing system software to reset these bits,
command. Like the Read Array command, the several operations (such as cumulatively erasing or
Read Identifier Codes command functions locking multiple blocks or writing several bytes in
independently of the VPP voltage and RP# can be sequence) may be performed. The status register
VIH or VHH. Following the Read Identifier Codes may be polled to determine if an error occurred
command, the subsequent information can be read. during the sequence.
Table 5. Identifier Codes To clear the status register, the Clear Status
Register command (50H) is written. It functions
Code Address Data independently of the applied VPP voltage. RP# can
Manufacturer Code 000000 89 be VIH or VHH. This command is not functional
during block erase or program suspend modes.
4 Mbit 000001 A7
Device Code 8 Mbit 000001 A6
16 Mbit 000001 AA 4.5 Block Erase Command
Block Lock Configuration XX0002(1)
Erase is executed one block at a time and initiated
• Block Is Unlocked DQ0 = 0
by a two-cycle command. A block erase setup is
• Block Is Locked DQ0 = 1 written first, followed by a block erase confirm. This
• Reserved for Future Use DQ1–7 command sequence requires appropriate se-
Master Lock Configuration 000003 quencing and an address within the block to be
erased (erase changes all block data to FFH).
• Device Is Unlocked DQ0 = 0 Block preconditioning, erase, and verify are handled
• Device Is Locked DQ0 = 1 internally by the WSM (invisible to the system).
• Reserved for Future Use DQ1–7 After the two-cycle block erase sequence is written,
the device automatically outputs status register
NOTE: data when read (see Figure 67). The CPU can
1. X selects the specific block lock configuration code to detect block erase completion by analyzing the
be read. See Figure 6 for the Device Identifier Code RY/BY# pin or status register bit SR.7.
Memory Map.
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PRELIMINARY
When the block erase is complete, status register

E
Successful program also requires that the
bit SR.5 should be checked. If a block erase error is corresponding block lock-bit be cleared or, if set,
detected, the status register should be cleared that RP# = VHH. If program is attempted when the
before system software attempts corrective actions. corresponding block lock-bit is set and RP# = VIH,
The CUI remains in read status register mode until program will fail, and SR.1 and SR.4 will be set to
a new command is issued. “1.” Program operations with VIH < RP# < VHH
produce spurious results and should not be
This two-step command sequence of set-up attempted.
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status 4.7 Block Erase Suspend
register bits SR.4 and SR.5 being set to “1.” Also, Command
reliable block erasure can only occur when
VCC = VCC2/3 and VPP = VPPH1/2/3. In the absence of The Block Erase Suspend command allows
this high voltage, block contents are protected block-erase interruption to read or write data in
against erasure. If block erase is attempted while another block of memory. Once the block erase
VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” process starts, writing the Block Erase Suspend
Successful block erase requires that the command requests that the WSM suspend the
corresponding block lock-bit be cleared or, if set, block erase sequence at a predetermined point in
that RP# = VHH. If block erase is attempted when the algorithm. The device outputs status register
the corresponding block lock-bit is set and data when read after the Block Erase Suspend
RP# = VIH, the block erase will fail, and SR.1 and command is written. Polling status register bits
SR.5 will be set to “1.” Block erase operations with SR.7 and SR.6 can determine when the block erase
VIH < RP# < VHH produce spurious results and operation has been suspended (both will be set to
should not be attempted. “1”). RY/BY# will also transition to VOH.
Specification tWHRH2 defines the block erase
suspend latency.
4.6 Program Command
At this point, a Read Array command can be written
Program is executed by a two-cycle command to read data from blocks other than that which is
sequence. Program setup (standard 40H or suspended. A Program command sequence can
alternate 10H) is written, followed by a second write also be issued during erase suspend to program
that specifies the address and data (latched on the data in other blocks. Using the Program Suspend
rising edge of WE#). The WSM then takes over, command (see Section 4.8), a program operation
controlling the program and write verify algorithms can also be suspended. During a program operation
internally. After the program sequence is written, with block erase suspended, status register bit
the device automatically outputs status register SR.7 will return to “0” and the RY/BY# output will
data when read (see Figure 8). The CPU can detect transition to VOL. However, SR.6 will remain “1” to
the completion of the program event by analyzing indicate block erase suspend status.
the RY/BY# pin or status register bit SR.7.
The only other valid commands while block erase is
When program is complete, status register bit SR.4 suspended are Read Status Register and Block
should be checked. If program error is detected, the Erase Resume. After a Block Erase Resume
status register should be cleared. The internal WSM command is written to the flash memory, the WSM
verify only detects errors for “1”s that do not will continue the block erase process. Status
successfully write to “0”s. The CUI remains in read register bits SR.6 and SR.7 will automatically clear
status register mode until it receives another and RY/BY# will return to VOL. After the Erase
command. Resume command is written, the device
automatically outputs status register data when
Reliable programs only occurs when VCC = VCC2/3 read (see Figure 9). VPP must remain at VPPH1/2/3
and VPP = VPPH1/2/3. In the absence of this high (the same VPP level used for block erase) while
voltage, memory contents are protected against block erase is suspended. RP# must also remain at
programs. If program is attempted while VIH or VHH (the same RP# level used for block
VPP ≤ VPPLK, the operation will fail, and status erase). Block erase cannot resume until program
register bits SR.3 and SR.5 will be set to “1.” operations initiated during block erase suspend
have completed.
18
PRELIMINARY
E
4.8 Program Suspend Command
master lock-bit is set, subsequent setting of block

lock-bits requires both the Set Block Lock-Bit
The Program Suspend command allows program command and VHH on the RP# pin. See Table 6 for
interruption to read data in other flash memory a summary of hardware and software write
locations. Once the program process starts, writing protection options.
the Program Suspend command requests that the
WSM suspend the program sequence at a Set block lock-bit and master lock-bit are initiated
predetermined point in the algorithm. The device using two-cycle command sequence. The set block
continues to output status register data when read or master lock-bit setup along with appropriate
after the Program Suspend command is written. block or device address is written followed by either
Polling status register bits SR.7 and SR.2 can the set block lock-bit confirm (and an address within
determine when the program operation has been the block to be locked) or the set master lock-bit
suspended (both will be set to “1”). RY/BY# will also confirm (and any device address). The WSM then
transition to VOH. Specification tWHRH1 defines the controls the set lock-bit algorithm. After the
program suspend latency. sequence is written, the device automatically
outputs status register data when read (see
At this point, a Read Array command can be written Figure 11). The CPU can detect the completion of
to read data from locations other than that which is the set lock-bit event by analyzing the RY/BY# pin
suspended. The only other valid commands while output or status register bit SR.7.
program is suspended are Read Status Register
and Program Resume. After Program Resume When the set lock-bit operation is complete, status
command is written to the flash memory, the WSM register bit SR.4 should be checked. If an error is
will continue the program process. Status register detected, the status register should be cleared. The
bits SR.2 and SR.7 will automatically clear and CUI will remain in read status register mode until a
RY/BY# will return to VOL. After the Program new command is issued.
Resume command is written, the device
automatically outputs status register data when This two-step sequence of setup followed by
read (see Figure 10). VPP must remain at VPPH1/2/3 execution ensures that lock-bits are not accidentally
(the same VPP level used for program) while in set. An invalid Set Block or Master Lock-Bit
program suspend mode. RP# must also remain at command will result in status register bits SR.4 and
VIH or VHH (the same RP# level used for program). SR.5 being set to “1.” Also, reliable operations
occur only when VCC = VCC2/3 and VPP = VPPH1/2/3.
In the absence of this high voltage, lock-bit contents
4.9 Set Block and Master Lock-Bit are protected against alteration.
Commands
A successful set block lock-bit operation requires
A flexible block locking and unlocking scheme is that the master lock-bit be cleared or, if the master
enabled via a combination of block lock-bits and a lock-bit is set, that RP# = VHH. If it is attempted with
master lock-bit. The block lock-bits gate program the master lock-bit set and RP# = VIH, the operation
and erase operations while the master lock-bit will fail, and SR.1 and SR.4 will be set to “1.” A
gates block-lock bit modification. With the master successful set master lock-bit operation requires
lock-bit not set, individual block lock-bits can be set that RP# = VHH. If it is attempted with RP# = VIH,
using the Set Block Lock-Bit command. The Set the operation will fail, and SR.1 and SR.4 will be set
Master Lock-Bit command, in conjunction with to “1.” Set block and master lock-bit operations with
RP# = VHH, sets the master lock-bit. After the VIH < RP# < VHH produce spurious results and
should not be attempted.
19
PRELIMINARY
4.10 Clear Block Lock-Bits

E
This two-step sequence of set-up followed by
Command execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
All set block lock-bits are cleared in parallel via the Lock-Bits command sequence will result in status
Clear Block Lock-Bits command. With the master register bits SR.4 and SR.5 being set to “1.” Also, a
lock-bit not set, block lock-bits can be cleared using reliable clear block lock-bits operation can only
only the Clear Block Lock-Bits command. If the occur when VCC = VCC2/3 and VPP = VPPH1/2/3. If a
master lock-bit is set, clearing block lock-bits clear block lock-bits operation is attempted while
requires both the Clear Block Lock-Bits command VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” In the
and VHH on the RP# pin. See Table 6 for a absence of this high voltage, the block lock-bits
summary of hardware and software write protection content are protected against alteration. A suc-
options. cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
Clear block lock-bits operation is initiated using a bit is set, that RP# = VHH. If it is attempted with the
two-cycle command sequence. A clear block master lock-bit set and RP# = VIH, SR.1 and SR.5
lock-bits setup is written first. Then, the device will be set to “1” and the operation will fail. A clear
automatically outputs status register data when block lock-bits operation with VIH < RP# < VHH
read (see Figure 12). The CPU can detect produce spurious results and should not be
completion of the clear block lock-bits event by attempted.
analyzing the RY/BY# pin output or status register
bit SR.7. If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP#
When the operation is complete, status register bit active transition, block lock-bit values are left in an
SR.5 should be checked. If a clear block lock-bit undetermined state. A repeat of clear block lock-
error is detected, the status register should be bits is required to initialize block lock-bit contents to
cleared. The CUI will remain in read status register known values. Once the master lock-bit is set, it
mode until another command is issued. cannot be cleared.
Table 6. Write Protection Alternatives

Master Block
Operation Lock-Bit Lock-Bit RP# Effect
Block Erase or 0 VIH or VHH Block Erase and Program Enabled
Program X 1 VIH Block is Locked. Block Erase and Program Disabled
VHH Block Lock-Bit Override. Block Erase and Program
Enabled
Set Block 0 X VIH or VHH Set Block Lock-Bit Enabled
Lock-Bit 1 X VIH Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH Master Lock-Bit Override. Set Block Lock-Bit
Enabled
Set Master X X VIH Set Master Lock-Bit Disabled
Lock-Bit VHH Set Master Lock-Bit Enabled
Clear Block 0 X VIH or VHH Clear Block Lock-Bits Enabled
Lock-Bits 1 X VIH Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
VHH Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
20
PRELIMINARY
Table 7. Status Register Definition

WSMS ESS ECLBS PSLBS VPPS PSS DPS R
7 6 5 4 3 2 1 0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS Check RY/BY# or SR.7 to determine block erase,
1 = Ready program, or lock-bit configuration completion.
0 = Busy SR.6–0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS If both SR.5 and SR.4 are “1”s after a block erase or
STATUS lock-bit configuration attempt, an improper
1 = Error in Block Erasure or Clear Lock-Bits command sequence was entered.
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in Program or Set Master/Block
Lock-Bit
0 = Successful Program or Set Master/Block
Lock-Bit
SR.3 = VPP STATUS SR.3 does not provide a continuous indication of
1 = VPP Low Detect, Operation Abort VPP level. The WSM interrogates and indicates the
0 = VPP OK VPP level only after a block erase, program, or lock-
bit configuration operation. SR.3 is not guaranteed
to reports accurate feedback only when VPP ≠
VPPH1/2/3.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS SR.1 does not provide a continuous indication of
1 = Master Lock-Bit, Block Lock-Bit and/or master and block lock-bit values. The WSM
RP# Lock Detected, Operation Abort interrogates the master lock-bit, block lock-bit, and
0 = Unlock RP# only after a block erase, program, or lock-bit
configuration operation. It informs the system,
depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or
RP# ≠ VHH.
SR.0 = RESERVED FOR FUTURE SR.0 is reserved for future use and should be
ENHANCEMENTS masked out when polling the status register.
21
PRELIMINARY
Start Bus
Command Comments
Operation
Write Erase Setup Data = 20H

Write 20H,
Addr = Within Block to Be Erased
Block Address
Write Erase Data = D0H

Confirm Addr = Within Block to Be Erased
Write D0H,
Block Address
Read Status Register Data

Read Status
Register
Suspend Block
Erase Loop Standby Check SR.7
No 1 = WSM Ready
0 0 = WSM Busy
Suspend
SR.7 =
Block Erase
Yes Repeat for subsequent block erasures.
Full status check can be done after each block erase, or after a
1
sequence of block erasures.
Full Status Write FFH after the last operation to place device in read array mode.
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus

Command Comments
Data (See Above) Operation
Standby Check SR.3

1 = VPP Error Detect
1
SR.3 = VPP Range Error
Check SR.1
Standby 1 = Device Protect Detect
0 RP# = V IH , Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
1
SR.1 = Device Protect Error
Standby Check SR.4,5
Both 1 = Command Sequence Error
0
1 Command Sequence Standby Check SR.5

SR.4,5 = Error 1 = Block Erase Error
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple blocks are erased
1 Block Erase before full status is checked.
SR.5 = Error If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
Block Erase
Successful
Figure 7. Automated Block Erase Flowchart

22
PRELIMINARY
Start Bus
Operation Command Comments
Write Setup Data = 40H

Write 40H, Program Addr = Location to Be Programmed
Address
Write Program Data = Data to Be Programmed

Write Byte Addr = Location to Be Programmed
Data and Address

Read
Status Register
Suspend Standby Check SR.7
Program Loop 1 = WSM Ready
No
0 = WSM Busy
0
Suspend
SR.7 =
Program
Yes
Repeat for subsequent byte writes.
1 SR full status check can be done after each program, or after a
sequence of program operations.
Full Status Write FFH after the last program operation to reset device to
Check if Desired read array mode.
Program Complete

Command Comments
Standby Check SR.3

1 1 = VPP Error Detect
Check SR.1
0 Standby 1 = Device Protect Detect
RP# = V IH , Block Lock-Bit Is Set
1 Only required for systems
SR.1 = Device Protect Error implementing lock-bit configuration
0 Standby Check SR.4

1 = Program Error
1
SR.4 = Program Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
0
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Program Successful
Figure 8. Automated Program Flowchart
23
PRELIMINARY
Start Bus Command Comments
Operation
Write Erase Data = B0H

Write B0H Suspend Addr = X

Read Addr = X
Status Register
Standby Check SR.7
1 = WSM Ready
0 0 = WSM Busy
SR.7 =
Standby Check SR.6
1 = Block Erase Suspended
1 0 = Block Erase Completed
Write Erase Data = D0H
0 Resume Addr = X
SR.6 = Block Erase Completed
Read Read or Program

Program
?
Read Array No Program

Data Loop
Done?
Yes
Write D0H Write FFH
Block Erase Resumed Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
24
PRELIMINARY
Start Bus
Command Comments
Operation
Write Program Data = B0H

Write B0H Suspend Addr = X

Addr = X
Read
Status Register
Standby Check SR.7
1 = WSM Ready
0 = WSM Busy
0
SR.7 = Standby Check SR.2
1 =Program Suspended
0 = Program Completed
1
Write Read Array Data = FFH
0 Addr = X
SR.2 = Program Completed
Read Read array locations other
than that being data written.
1
Write Program Data = D0H

Write FFH Resume Addr = X
Read Array Data
Done No
Reading
Yes
Write D0H Write FFH
Program Resumed Read Array Data
Figure 10. Program Suspend/Resume Flowchart
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PRELIMINARY
Start Bus
Command Comments
Operation
Write 60H, Write Set Data = 60H

Block/Device Address Block/Master Addr = Block Address (Block),
Lock-Bit Setup Device Address (Master)
Write Set Data = 01H (Block),

Write 01H/F1H, Block or Master F1H (Master)
Block/Device Address Lock-Bit Confirm Addr = Block Address (Block),
Device Address (Master)
Read Status Read Status Register Data

Register
Check SR.7
Standby 1 = WSM Ready
0 0 = WSM Busy
SR.7 =
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
1 a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
Full Status read array mode.
Check if Desired
Set Lock-Bit Complete

Command Comments
Standby Check SR.3

1
SR.3 = V PP Range Error
Check SR.1
0 RP# = V IH ,
(Set Master Lock-Bit Operation)
RP# = VHH , Master Lock-Bit Is Set
1 (Set Block Lock-Bit Operation)
SR.1 = Device Protect Error
Standby Check SR.4,5

0 Both 1 = Command Sequence Error
1 Standby Check SR.4

Command Sequence
SR.4,5 = 1 = Set Lock-Bit Reset Error
Error
0 SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
1 If error is detected, clear the Status Register before attempting retry
SR.4 = Set Lock-Bit Error
or other error recovery.
Set Lock-Bit Successful
Figure 11. Set Block and Master Lock-Bit Flowchart

26
PRELIMINARY
Start Bus
Command Comments
Operation
Clear Block Data = 60H

Write
Write 60H Lock-Bits Setup Addr = X
Clear Block Data = D0H

Write Lock-Bits Confirm Addr = X
Write D0H

Read Status
Register
Check SR.7
Standby 1 = WSM Ready
0 0 = WSM Busy
SR.7 =
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
1
Full Status
Check if Desired
Clear Block Lock-Bits

Complete

Command Comments
Standby Check SR.3

1
Check SR.1
0
RP# = VIH, Master Lock-Bit Is Set
1 Check SR.4,5
SR.1= Device Protect Error
Standby Both 1 = Command Sequence Error
0
Check SR.5
Standby
1 Command Sequence 1 = Clear Block Lock-Bits Error
SR.4,5 = Error
0 SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
1 retry or other error recovery.
SR.5 = Error

Successful
Figure 12. Clear Block Lock-Bits Flowchart
27
PRELIMINARY
5.0 DESIGN CONSIDERATIONS 5.4 VPP Trace on Printed Circuit

E
Boards
5.1 Three-Line Output Control Updating flash memories that reside in the target
system requires that the printed circuit board
Intel provides three control inputs to accommodate designer pay attention to the VPP power supply
multiple memory connections: CE#, OE#, and RP#. trace. The VPP pin supplies the memory cell current
Three-line control provides for: for byte writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
a. Lowest possible memory power dissipation. power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
b. Data bus contention avoidance. overshoots.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be 5.5 VCC, VPP, RP# Transitions
connected to all memory devices and the system’s
READ# control line. This assures that only selected Block erase, program and lock-bit configuration are
memory devices have active outputs while de- not guaranteed if VPP or VCC fall outside of a valid
selected memory devices are in standby mode. voltage range (VCC2/3 and VPPH1/2/3) or RP# ≠ VIH or
RP# should be connected to the system VHH. If VPP error is detected, status register bit
POWERGOOD signal to prevent unintended writes SR.3 is set to “1” along with SR.4 or SR.5,
during system power transitions. POWERGOOD depending on the attempted operation. If RP#
should also toggle during system reset. transitions to VIL during block erase, program, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
5.2 RY/BY# Hardware Detection will abort and the device will enter deep power-
down. The aborted operation may leave data
RY/BY# is a full CMOS output that provides a partially altered. Therefore, the command sequence
hardware method of detecting block erase, program must be repeated after normal operation is
and lock-bit configuration completion. This output restored.
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to VOH when it is finished 5.6 Power-Up/Down Protection
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at The device is designed to offer protection against
VOH. accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
5.3 Power Supply Decoupling supply (VPP or VCC) powers-up first. Internal
circuitry resets the CUI to read array mode at
Flash memory power switching characteristics power-up.
require careful device decoupling. System
designers are interested in three supply current A system designer must guard against spurious
issues: standby current levels, active current levels writes for VCC voltages above VLKO when VPP is
and transient peaks produced by falling and rising active. Since both WE# and CE# must be low for a
edges of CE# and OE#. Two-line control and proper command write, driving either input signal to VIH will
decoupling capacitor selection will suppress inhibit writes. The CUI’s two-step command
transient voltage peaks. Each device should have a sequence architecture provides an added level of
0.1 µF ceramic capacitor connected between its protection against data alteration.
VCC and GND and between its VPP and GND.
These high-frequency, low-inductance capacitors In-system block lock and unlock renders additional
should be placed as close as possible to package protection during power-up by prohibiting block
leads. Additionally, for every eight devices, a 4.7 µF erase and program operations. The device is
electrolytic capacitor should be placed at the array’s disabled while RP# = VIL regardless of its control
power supply connection between VCC and GND. inputs state.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
28
PRELIMINARY
E
5.7 VPP Program and Erase
Voltages on Sub-0.4µ SC
Memory Family
Intel's SmartVoltage FlashFile™ memory family
provides in-system program/erase at 3.3 V VPP and
5V VPP as well as faster factory program/erase at
12 V VPP.
Future sub-0.4µ lithography SmartVoltage FlashFile

memory products will also include a backward-
compatible 12 V programming feature. This mode,
however, is not intended for extended use. A 12 V
program/erase VPP can be applied for 1000 cycles
maximum per block or 80 hours maximum per
device. To ensure compatibility with future sub-0.4µ
SmartVoltage FlashFile memory products, present
designs should not permanently connect VPP to
12 V. This will avoid device over-stressing that may
cause permanent damage.
29
PRELIMINARY
6.0 ELECTRICAL SPECIFICATIONS

E
NOTICE: This datasheet contains information on new
products in production. Do not finalize a design with this
information. Revised information will be published when
6.1 Absolute Maximum Ratings* the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
Temperature under Bias ................ –10°C to +80°C design.
Storage Temperature....................–65°C to +125°C
Voltage on Any Pin *WARNING: Stressing the device beyond the “Absolute
(except VPP, and RP#) ......... –2.0 V to +7.0 V(1) Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
VPP Voltage ........................... –2.0 V to +14.0 V (1,2) Conditions” is not recommended and extended exposure
RP# Voltage ........................ –2.0 V to +14.0 V(1,2,4) beyond the “Operating Conditions” may affect device
reliability.
Output Short Circuit Current ....................100 mA(3)
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC, RP#,
and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on
input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.
2. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods <20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
6.2 Commercial Temperature Operating Conditions

Commercial Temperature and VCC Operating Conditions
Symbol Parameter Notes Min Max Unit Test Condition
TA Operating Temperature 0 +70 °C Ambient Temperature
VCC1 VCC Supply Voltage (2.7 V–3.6 V) 1 2.7 3.6 V
VCC2 VCC Supply Voltage (3.3 V ± 0.3 V) 3.0 3.6 V
VCC3 VCC Supply Voltage (5 V ± 5%) 4.75 5.25 V
VCC4 VCC Supply Voltage (5 V ± 10%) 4.5 5.5 V
NOTE:
1. Block erase, program, and lock-bit configuration with VCC < 3.0 V should not be attempted.
6.3 Capacitance(1)
TA = +25°C, f = 1 MHz
Symbol Parameter Typ Max Unit Condition

CIN Input Capacitance 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
30
PRELIMINARY
E
6.4
DC Characteristics—Commercial Temperature
2.7V VCC 3.3V VCC 5V VCC Test
Sym Parameter Notes Typ Max Typ Max Typ Max Unit Conditions
ILI Input Load Current 1 ±0.5 ±0.5 ±1 µA VCC = VCC Max, VIN = VCC or GND
ILO Output Leakage Current 1 ±0.5 ±0.5 ±10 µA VCC = VCC Max, VOUT = VCC or GND
ICCS VCC Standby Current 1,3,6 20 100 20 100 25 100 µA CMOS Inputs
VCC = VCC Max
CE# = RP# = VCC ± 0.2 V
0.1 2 0.2 2 0.4 2 mA TTL Inputs
VCC = VCC Max, CE# = RP# = VIH
ICCD VCC Deep Power- 1 10 10 10 µA RP# = GND ± 0.2 V
Down Current IOUT (RY/BY#) = 0 mA
ICCR VCC Read Current 1,5,6 6 12 7 12 17 35 mA CMOS Inputs

VCC = VCC Max, CE# = GND
f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V)
IOUT = 0 mA
7 18 8 18 20 50 mA TTL Inputs
VCC = VCC Max, CE# = GND
f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V)
IOUT = 0 mA
ICCW VCC Program or 1,7   17   mA VPP = 3.3 V ± 0.3 V
Set Lock-Bit Current   17 35 mA VPP = 5 V ± 10%
  12 30 mA VPP = 12 V ± 5%
ICCE VCC Block Erase or 1,7   17   mA VPP = 3.3 V ± 0.3 V
Clear Block   17 30 mA VPP = 5 V ± 10%
Lock-Bits Current   12 25 mA VPP = 12 V ± 5%
ICCWS VCC Program or Block 1,2   1 6 1 10 mA CE# = VIH
ICCES Erase Suspend Current
IPPS VPP Standby Current 1 ±2 ±15 ±2 ±15 ± 2 ±15 µA VPP ≤ VCC
IPPR VPP Read Current 1 10 200 10 200 10 200 µA VPP > VCC
IPPD VPP Deep Power-Down 1 0.1 5 0.1 5 0.1 5 µA RP# = GND ± 0.2 V
Current
IPPW VPP Program/ Set 1,7   40   mA VPP = 3.3 V ± 0.3 V
Lock-Bit Current   40 40 mA VPP = 5 V ± 10%
  15 15 mA VPP = 12 V ± 5%
IPPE VPP Block Erase/Clear 1,7   20   mA VPP = 3.3 V ± 0.3 V
Block Lock-Bits   20 20 mA VPP = 5 V ± 10%
Current   15 15 mA VPP = 12 V ± 5%
IPPWS VPP Program/ Block Erase 1   10 200 10 200 µA VPP = VPPH1/2/3
I Suspend Current
PPES
31
PRELIMINARY
6.4 DC Characteristics—Commercial Temperature(Continued)

E
2.7 V VCC 3.3 V VCC 5 V VCC Test
Sym Parameter Notes Min Max Min Max Min Max Unit Conditions
VIL Input Low Voltage 7 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
VIH Input High Voltage 7 2.0 VCC 2.0 VCC 2.0 VCC V
+ 0.5 + 0.5 + 0.5
VOL Output Low Voltage 3,7 0.4 0.4 0.45 V VCC = VCC Min
IOL = 2 mA (2.7V, 3.3V)
5.8 mA (5V)
VOH1 Output High Voltage (TTL) 3,7 2.4 2.4 2.4 V VCC = VCC Min
IOH = –2.5 mA
VOH2 Output High Voltage 3,7 0.85 0.85 0.85 V VCC = VCC Min
(CMOS) VCC VCC VCC IOH = –2.5 mA
VCC VCC VCC V VCC = VCC Min
–0.4 –0.4 –0.4 IOH = –100 µA
VPPLK VPP Lockout Voltage 4,7 1.5 1.5 1.5 V
VPPH1 VPP Voltage   3.0 3.6   V
VPPH2 VPP Voltage   4.5 5.5 4.5 5.5
VPPH3 VPP Voltage   11.4 12.6 11.4 12.6 V
VLKO VCC Lockout Voltage 2.0 2.0 2.0 V
VHH RP# Unlock Voltage 8,9   11.4 12.6 11.4 12.6 V Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2. ICCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of ICCWS or ICCES and ICCR or ICCW.
3. Includes RY/BY#.
4. Block erases, programs, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), between VPPH2 (max) and VPPH3 (min), and
above VPPH3 (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with VIH < RP# < VHH.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
32
PRELIMINARY
2.7
INPUT 1.35 TEST POINTS 1.35 OUTPUT
0.0
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35
V. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V
3.0
INPUT 1.5 TEST POINTS 1.5 OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V and V CC = 5.0 V ± 5%
(High Speed Testing Configuration)
2.4
2.0 2.0
INPUT TEST POINTS OUTPUT
0.8 0.8
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for VCC = 5.0 V ± 10%
(Standard Testing Configuration)
Test Configuration Capacitance Loading Value

1.3V
Test Configuration CL (pF)
1N914
VCC = 3.3 V ± 0.3 V, 2.7 V−3.6 V 50
R L = 3.3 K VCC = 5 V ± 5% 30
DEVICE
UNDER OUT
VCC = 5 V ± 10% 100
TEST
CL
NOTE:
CL includes Jig Capacitance
Figure 16. Transient Equivalent Testing

Load Circuit
33
PRELIMINARY
VIH
RY/BY# (R)
VIL
P2
VIH
RP# (P)
VIL
P1
Figure 17. AC Waveform for Reset Operation
Table 8. Reset Specifications

2.7 V VCC 3.3 V VCC 5 V VCC
# Sym Parameter Notes Min Max Min Max Min Max Unit
P1 tPLPH RP# Pulse Low Time (If RP# is tied to VCC, 100 100 100 ns
this specification is not applicable)
P2 tPLRH RP# Low to Reset during Block Erase, 2,3  20 12 µs
Program, or Lock-Bit Configuration
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted when the WSM is not busy (RY/BY# = “1”), the reset will complete within 100 ns.
3. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid.
34
PRELIMINARY
E
6.5
AC Characteristics—Read-Only Operations(1)—Commercial Temperature

TA = 0°C to +70°C
5 V ± 5% VCC -85/-95(5)    
Versions(4) 5 V ± 10% VCC  -90/-100(6) -120   Unit
3.3 V ± 0.3 V VCC   -120 -150 
2.7 V−3.6 V VCC    -150 -170
# Sym Parameter Notes Min Max Min Max Min Max Min Max Min Max
R1 tAVAV Read Cycle 4, 8 Mbit 85 90 120 150 170 ns
Time 16 Mbit 95 100 120 150 170 ns
R2 tAVQV Address to 4, 8 Mbit 85 90 120 150 170 ns
Output Delay 16 Mbit 95 100 120 150 170 ns
R3 tELQV CE# to Output 4, 8 Mbit 2 85 90 120 150 170 ns
Delay 16 Mbit 2 95 100 120 150 170 ns
R4 tGLQV OE# to Output Delay 2 40 45 50 55 55 ns
R5 tPHQV RP# High to Output 400 400 400/ 600 600 ns
Delay 600(7)
R6 tELQX CE# to Output in Low Z 3 0 0 0 0 0 ns
R7 tGLQX OE# to Output in Low Z 3 0 0 0 0 0 ns
R8 tEHQZ CE# High to Output in 3 55 55 55 55 55 ns
High Z
R9 tGHQZ OE# High to Output in 3 10 10 15 20 25 ns
High Z
R10 tOH Output Hold from 3 0 0 0 0 0 ns
Address, CE# or OE#
Change, Whichever
Occurs First
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characteristics.
7. Valid for 3.3 V VCC read operations.
35
PRELIMINARY
Device Data
VIH Standby Address Selection Valid
ADDRESSES (A) Address Stable
VIL
R1
VIH
CE# (E)
VIL
R2 R8
VIH
OE# (G)
VIL
R3 R9
VIH
WE# (W)
R4
VIL
R5 R10
VOH
R6
DATA (D/Q) High Z High Z
(DQ0-DQ7) Valid Output
VOL R7
V CC
VIH
RP# (P)
VIL
Figure 18. AC Waveform for Read Operations
36
PRELIMINARY
E
6.6
AC Characteristics—Write Operations(1,2)—Commercial Temperature

TA = 0°C to +70°C
5 V ± 5%, Valid for All 

5 V ± 10% VCC Speeds
3.3 V ± 0.3 V,  Valid for All
Versions 2.7 V−3.6 V VCC Speeds Unit
# Sym Parameter Notes Min Max Min Max
W1 tPHWL (tPHEL) RP# High Recovery to WE# (CE#) Going 3 1 1 µs
Low
W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Going 7 0 0 ns
Low
W3 tWP Write Pulse Width 7 50 70 ns
W4 tDVWH (tDVEH) Data Setup to WE# (CE#) Going High 4 40 50 ns
W5 tAVWH (tAVEH) Address Setup to WE# (CE#) Going High 4 40 50 ns
W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 0 ns
W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 5 5 ns
W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 5 5 ns
W9 tWPH Write Pulse Width High 9 25 25 ns
W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CE#) Going High 3,8 100 100 ns
W11 tVPWH (tVPEH) VPP Setup to WE# (CE#) Going High 3,8 100 100 ns
W12 tWHGL (tEHGL) Write Recovery before Read 0 0 ns
W13 tWHRL (tEHRL) WE# (CE#) High to RY/BY# Going Low 8 90 90 ns
W14 tQVPH RP# VHH Hold from Valid SRD, RY/BY# 3,5,8 0 0 ns
High
W15 tQVVL VPP Hold from Valid SRD, RY/BY# High 3,5,8 0 0 ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
4. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration.
5. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, program,
or lock-bit configuration success (SR.1/3/4/5 = 0).
7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to tWP – 10 ns for 5 V VCC and tWP – 20 ns for 2.7 V and 3.3 V VCC writes.
8. Block erase, program, and lock-bit configuration with VCC < 3.0 V should not be attempted.
9. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
37
PRELIMINARY
A B C D E F
VIH
ADDRESSES [A] AIN AIN
VIL
W5 W8
VIH
CE# (WE#) [E(W)]
VIL
W1 W6 W12
VIH
OE# [G]
VIL
W2 W9 W16
VIH
WE# (CE#) [W(E)]
VIL
W3
W4
W7
VIH High Z
DATA [D/Q] DIN Valid DIN
DIN
VIL SRD
W13
VIH
RY/BY# [R]
VIL
W10 W14
VHH
VIH
RP# [P]
VIL
W11 W15
V PPH2,1
VPP [V]
VPPLK
VIL
NOTES:
A. VCC power-up and standby.
B. Write block erase or program setup.
C. Write block erase confirm or valid address and data..
D. Automated erase or program delay.
E. Read status register data.
F. Write Read Array command.
Figure 19. AC Waveform for Write Operations
38
PRELIMINARY
E
6.7
Block Erase, Program, and Lock-Bit Configuration Performance(3, 4, 5)—

Commercial Temperature
VCC = 3.3 V ± 0.3 V, T A = 0°C to +70°C
3.3 V VPP 5 V VPP 12 V VPP

# Sym Parameter Notes Typ(1) Max Typ(1) Max Typ(1) Max Unit
W16 tWHRH1, Program Time 2 19 300 10 150 7 125 µs
tEHRH1
Block Write Time 2 1.2 4 0.7 2 0.5 1.5 sec
W16 tWHRH2, Block Erase Time 2 0.8 6 0.4 5 0.3 4 sec
tEHRH2
W16 tWHRH3, Set Lock-Bit Time 2 21 TBD 13.3 TBD 11.6 TBD µs
tEHRH3
W16 tWHRH4, Clear Block Lock- 2 1.8 TBD 1.2 TBD 1.1 TBD sec
tEHRH4 Bits Time
W16 tWHRH5, Program Suspend 7.1 10 6.6 9.3 7.4 10.4 µs
tEHRH5 Latency Time to
Read
W16 tWHRH6, Erase Suspend 15.2 21.1 12.3 17.2 12.3 17.2 µs
tEHRH6 Latency Time to
Read
VCC = 5 V ± 5%, 5 V ± 10%, T A = 0°C to +70°C
5 V VPP 12 V VPP
# Sym Parameter Notes Typ(1) Max Typ(1) Max Unit
W16 tWHRH1, Program Time 2 8 150 6 100 µs
tEHRH1
Block Write Time 2 0.5 1.5 0.4 1 sec
W16 tWHRH2, Block Erase Time 2 0.4 5 0.3 4 sec
tEHRH2
W16 tWHRH3, Set Lock-Bit Time 2 12 TBD 10 TBD µs
tEHRH3
W16 tWHRH4, Clear Block Lock-Bits Time 2 1.1 TBD 1.0 TBD sec
tEHRH4
W16 tWHRH5, Program Suspend Latency Time to 5.6 7 5.2 7.5 µs
tEHRH5 Read
W16 tWHRH6, Erase Suspend Latency Time to 9.4 13.1 9.8 12.6 µs
tEHRH6 Read
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested.
5. Reference the AC Waveform for Write Operations, Figure 19.
39
PRELIMINARY
6.8 Extended Temperature Operating Conditions

E
Except for the specifications given in this section, all DC and AC characteristics are identical to those give in
commercial temperature specifications. See the Section 6.2 for commercial temperature specifications.
Extended Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Unit Test Condition
TA Operating Temperature –40 +85 °C Ambient Temperature
6.9 DC Characteristics—Extended Temperature

2.7V VCC 3.3V VCC 5V VCC Test
Sym Parameter Notes Typ Max Typ Max Typ Max Unit Conditions
ICCD VCC Deep Power-Down 1 20 20 20 µA RP# = GND ± 0.2 V
Current IOUT (RY/BY#) = 0 mA
NOTE:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.
6.10 AC Characteristics—Read-Only Operations(1) — Extended Temperature

TA = –40°C to +85°C
5 V ± 10% VCC -100/-110  

Versions(3) 3.3 V ± 0.3 V VCC  -150  Unit
2.7 V−3.6 V VCC   -170
# Sym Parameter Notes Min Max Min Max Min Max
R1 tAVAV Read Cycle Time 4, 8 Mbit 100 150 170 ns
16 Mbit 110 150 170 ns
R2 tAVQV Address to Output 4, 8 Mbit 100 150 170 ns
Delay 16 Mbit 110 150 170 ns
R3 tELQV CE# to Output Delay 4, 8 Mbit 2 100 150 170 ns
16 Mbit 2 110 150 170 ns
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
40
PRELIMINARY
E
7.0 ORDERING INFORMATION
Product line designator for all Intel Flash products
E2 8 F0 0 4 SC- 0 8 5
Operating Temperature/Package Access Speed (ns)

E = Comm. Temp. 40-Lead TSOP 85 ns (5 V, 30 pF), 90 ns (5 V)
TE = Extended Temp. 40-Lead TSOP 120 ns (3.3 V), 150 ns (2.7 V)
PA = Comm. Temp 44-Lead PSOP
TB = Ext. Temp 44-Lead PSOP
G = Comm. Temp. 40-Ball µBGA* CSP Voltage Options (V CC/VPP)
C = SmartVoltage Flash
(2.7 V, 3.3 V and
5 V/3.3 V, 5 V and 12 V)
Device Density
004 = 4 Mbit Product Family
008 = 8 Mbit S = FlashFile™ Memory
016 = 16 Mbit
Valid Operational Combinations

Order Code by Density 5V VCC
2.7V VCC, 3.3V VCC, 10% VCC, 5% VCC,
4-Mbit 8-Mbit 16-Mbit 50pF load 50pF load 100pF load 30pF load
Commercial Temperature
E28F004SC-85 E28F008SC-85 E28F016SC-95 -150 -120 -90/-100(1) -85/95(1)
E28F004SC-120 E28F008SC-120 E28F016SC-120 -170 -150 -120
PA28F004SC-85 PA28F008SC-85 PA28F016SC-95 -150 -120 -90/-100(1) -85/95(1)
PA28F004SC-120 PA28F008SC-120 PA28F016SC-120 -170 -150 -120
G28F008SC-120 G28F016SC-120 -170 –150 –120
G28F008SC-150 G28F016SC-150 -170 –150 –120
Extended Temperature
TE28F004SC-100 TE28F008SC-100 TE28F016SC-110 -170 -150 -100/-110(1)
TB28F004SC-100 TB28F008SC-100 TB28F016SC-110 -170 -150 -100/-110(1)
NOTE:
1. Valid access time for 16-Mbit byte-wide FlashFile memory.
41
PRELIMINARY
8.0 ADDITIONAL INFORMATION

E
Order Number Document/Tool
290598 Byte-Wide Smart3 FlashFile Memory Family Datasheet
290597 Byte-Wide Smart5 FlashFile Memory Family Datasheet
292183 AB-64 4-, 8-, 16-Mbit Byte-Wide FlashFile™ Memory Family Overview
292094 AP-359 28F008SA Hardware Interfacing
292099 AP-364 28F008SA Automation and Algorithms
292123 AP-374 Flash Memory Write Protection Techniques
292180 AP-625 28F008SC Compatibility with 28F008SA
292182 AP-627 Byte-Wide FlashFile™ Memory Family Software Drivers
297729 Byte-Wide SmartVoltage FlashFile™ Memory Family Specification Update
Contact Intel/Distribution 4-, 8-, and 16-Mbit Schematic Symbols
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit TimingDesigner* Files
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit VHDL and Verilog Models
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit iBIS Models
Sales Office
NOTE:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
42
PRELIMINARY
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

SmartVoltage FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT

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SmartVoltage FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT

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E BYTE-WIDE

SmartVoltage FlashFile™ MEMORY FAMILY

n SmartVoltage Technology n High-Density 64-Kbyte Symmetrical

December 1997 Order Number: 290600-003

COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493

1.0 INTRODUCTION .............................................5 6.0 ELECTRICAL SPECIFICATIONS..................30

5.0 DESIGN CONSIDERATIONS ........................28

1.2 Product Overview

• Because of new feature and density options, 3.3 V 3.3 V, 5 V, 12 V

A block erase operation erases one of the device’s

Address X 4-Mbit: Eight VCC

Figure 1. Block Diagram

Table 2. Pin Descriptions

Table 3. Pin Descriptions (Continued)

Figure 2. TSOP 40-Lead Pinout

Figure 3. PSOP 44-Lead Pinout

Bottom View - Bump Side Up

Top View - Bump Side Down

system software to suspend a program to read data 01FFFF

Figure 5. Memory Map

3.2 Output Disable

3.0 BUS OPERATION In read mode, RP#-low deselects the memory,

3.5 Read Identifier Codes

070002 Block 7 Lock Configuration 4.0 COMMAND DEFINITIONS

Figure 6. Device Identifier Code Memory Map

Table 3. Bus Operations

Table 4. Command Definitions(9)

4.3 Read Status Register

When the block erase is complete, status register

master lock-bit is set, subsequent setting of block

4.10 Clear Block Lock-Bits

Table 6. Write Protection Alternatives

Table 7. Status Register Definition

Write Erase Setup Data = 20H

Write Erase Data = D0H

Read Status Register Data

FULL STATUS CHECK PROCEDURE

Read Status Register Bus

Standby Check SR.3

1 Command Sequence Standby Check SR.5

Figure 7. Automated Block Erase Flowchart

Write Setup Data = 40H

Write Program Data = Data to Be Programmed

Read Status Register Data

FULL STATUS CHECK PROCEDURE

Read Status Register Bus

Standby Check SR.3

0 Standby Check SR.4

Figure 8. Automated Program Flowchart

Write Erase Data = B0H

Read Status Register Data

Read Read or Program

Read Array No Program

Write D0H Write FFH

Block Erase Resumed Read Array Data

Figure 9. Block Erase Suspend/Resume Flowchart

Write Program Data = B0H

Read Status Register Data

Write Program Data = D0H

Read Array Data