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NALLA MALLA REDDY ENGINEERING COLLEGE

(An Autonomous Institute)
M.Tech. in VLSISD
COURSE STRUCTURE & SYLLABUS (R21)
Applicable From 2021-22 Admitted Batch

I YEAR I – SEMESTER
Course Code Course Title L T P Credits
Professional DIGITAL DESIGN AND VERIFICATION
3 0 0 3
Core - I
Professional VLSI Technology and Design
3 0 0 3
Core - II
Professional 1. Communication Buses and Interface
Elective - I 2. CPLD and FPGA architectures and applications 3 0 0 3
3. Design of ASICs

Professional 1. Physical Design and Automation

Elective - II 4. IOT and its Applications 3 0 0 3
2. Embedded RTOS
Lab - I HDL simulation and Verification Lab 0 0 3 2
Lab - II IOT/Spice simulation Lab 0 0 3 2

Research Methodology & IPR 2 0 0 2

Audit - I Audit Course - I 2 0 0 0
Total Credits 16 0 6 18

I YEAR II – SEMESTER
Course Code Course Title L T P Credits
Professional 1. Analog IC Design
3 0 0 3
Core - III
Professional 2. Low power VLSI system Design
3 0 0 3
Core - IV
Professional 3. SOC Design
Elective - III 4. VLSI Signal Processing 3 0 0 3
5. DSP architecture

Professional 1. Optimization techniques in VLSI Design

Elective - IV 6. Digital CMOS Design 3 0 0 3
7. Design for Testability
Lab - III Analog IC Design Lab 0 0 3 2
Lab - IV Digital CMOS Lab 0 0 3 2
Mini project with Seminar 0 0 4 2
Audit - II Audit Course- II 2 0 0 0
Total Credits 14 0 10 18
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III – SEMESTER
Course Code Course Title L T P Credits
1. CAD for VLSI
Professional
2. AI and Machine Learning 3 0 0 3
Elective - V
3. Memory Technologies
Open Elective Open Elective 3 0 0 3
Dissertation Dissertation Work Review - II 0 0 12 6
Total Credits 6 0 12 12

II YEAR II - SEMESTER
Course Code Course Title L T P Credits
Dissertation Dissertation Work Review - III 0 0 12 6
Dissertation Dissertation Viva-Voce 0 0 28 14
Total Credits 0 0 40 20

*For Dissertation Work Review - I, Please refer 7.8 in R19 Academic

Regulations. Audit Course I & II:
1. English for Research Paper Writing
2. Disaster Management
3. Sanskrit for Technical Knowledge
4. Value Education
5. Constitution of India
6. Pedagogy Studies
7. Stress Management by yoga
8. Personality Development Through Life Enlightenment Skills
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DIGITAL DESIGN AND VERIFICATION

(PC – I)

M.Tech (VLSISD) I Year-I Semester L/T/P/C: 3/0/0/3

Course Outcomes: At the end of this course, students will be able to

1. Familiarity of Front end design and verification techniques and create reusable test
environments.
2. Verify increasingly complex designs more efficiently and effectively.
3. Use EDA tools like Cadence, Mentor Graphics.

UNIT-I
Revision of basic Digital systems: Combinational Circuits, Sequential Circuits, Logic families
Synchronous FSM and asynchronous design, Metastability, Clock distribution and issues,
basicbuilding blocks like PWM module, pre-fetch unit, programmable counter, FIFO, Booth's
multiplier,ALU, Barrel shifter etc.

UNIT-II
Verilog/VHDL Comparisons and Guidelines, Verilog: HDL fundamentals, simulation, and
test- bench design, Examples of Verilog codes for combinational and sequential logic, Verilog
AMS

UNIT-III
System Verilog and Verification: Verification guidelines, Data types, procedural statements
androutines, connecting the test bench and design, Assertions, Basic OOPS concepts,
Randomization,Introduction to basic scripting language: Perl, Tcl/Tk

UNIT-IV
Current challenges in physical design: Roots of challenges, Delays: Wire load models Generic
PD flow, Challenges in PD flow at different steps, SI Challenge - Noise & Crosstalk, IR Drop,
Process effects: Process Antenna Effect & Electromigration

UNIT-V
Programmable Logic Devices: Introduction, Evolution: PROM, PLA, PAL, Architecture of
PAL's, Applications, Programming PLD's, FPGA with technology: Antifuse, SRAM, EPROM,
MUX, FPGAstructures, and ASIC Design Flows, Programmable Interconnections, Coarse
grained reconfigurable devices

TEXTBOOKS:
1. Douglas Smith, “HDL Chip Design: A Practical Guide for Designing, Synthesizing &
Simulating ASICs & FPGAs Using VHDL or Verilog”, Doone publications, 1998.
2. Samir Palnitkar, “Verilog HDL: A guide to Digital Design and Synthesis”, Prentice Hall,
2nd
Edition, 2003.
REFERENCES:
1. Doug Amos, Austin Lesea, Rene Richter, “FPGA based Prototyping Methodology
Manual”,
Synopsys Press, 2011.
2. Christophe Bobda, “Introduction to Reconfigurable Computing, Architectures, Algorithms
and Applications”, Springer, 2007.
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3. Janick Bergeron, “Writing Testbenches: Functional Verification of HDL Models”, Second

Edition, Springer, 2003.
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VLSI TECHNOLOGY AND DESIGN

(Professional Core -II)
M.Tech (VLSISD) I Year-I Semester L/T/P/C: 3/0/0/3

COURSE OBJECTIVES
• To enable the student to visualize MOS fabrication technologies and to understand electrical
properties of MOS, CMOS and Bi CMOS circuits.
• To train the student to draw integrated circuit layouts following design rules.
• To enable the student design combinational circuit, do verification, power optimization and
network testing.
• To enable the student to use power optimization techniques, design validation procedures
and testing of sequential circuits.
• To train the student to use different floor planning methods and different low power
architectures.

COURSE OUTCOMES: Graduate student will be able to

• Visualize the steps taken for MOS fabrication technologies.
• Analyze electrical behavior of MOS, CMOS and Bi-CMOS circuits.
• Draw the layout of integrated circuits following design rules.
• Design combinational circuit.
• Design sequential circuits using different clocking disciplines.
• Carry out power optimization techniques, design validation procedure and testing of
circuits.
• Carry out floor planning for different low power architectures.

UNIT I
Review of Microelectronics and Introduction to MOS Technologies:
MOS, CMOS, BiCMOS Technology. Basic Electrical Properties of MOS, CMOS &
BiCMOS Circuits: Ids – Vds relationships, Threshold Voltage VT, Gm, Gds and ωo.
Pass Transistor, MOS, CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit
model, Latch-up in CMOS circuits.

UNIT II
Layout Design and Tools: Transistor structures, Wires and Vias, Scalable Design rules,
Layout Design tools.
Logic Gates & Layouts: Static Complementary Gates, Switch Logic, Alternative Gate
circuits, Low power gates, Resistive and Inductive interconnect delays.

UNIT III
Combinational Logic Networks: Layouts, Simulation, Network delay, Interconnect design
Power optimization, Switch logic networks, Gate and Network testing.

UNIT IV
Sequential Systems: Memory cells and Arrays, Clocking disciplines, Design, Power
optimization, Design validation and testing.

UNIT V
Floor Planning: Floor planning methods, Global Interconnect, Floor Plan Design, Off-chip
connections.
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TEXT BOOKS
1. Essentials of VLSI Circuits and Systems, K. Eshraghian Eshraghian. D, A. Pucknell, 2005,
PHI.
2. Modern VLSI Design – Wayne Wolf, 3rd Ed., 1997, Pearson Education.
REFERENCE BOOKS
1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin,
CRC
Press, 2011.
2. Principals of CMOS VLSI Design – N.H.E Weste, K. Eshraghian, 2nd Ed., Addison
Wesley.
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CPLD AND FPGA ARCHITECURES AND APPLICATIONS

(Program Elective -I)
L/T/P/C:3/0/0/3

M.Tech (VLSISD) I Year-I Semester

COURSE OBJECTIVES
• To understand the concept of Programmable Logic Device architectures and technologies.
• Underlying FPGA architectures and technologies in detail.
• To understand the difference between CPLDs and FPGAs
• To provide knowledge about SRAM Programmable FPGA Device architecture.
• To comprehend knowledge about Anti-Fuse Programmable FPGA Device architecture.

COURSE OUTCOMES: After going through this course the student will be able to
• To know the concept of programmable architectures.
• Perceiving CPLD and FPGA technologies
• Study and compare the different architectures of CPLDs and FPGAs
• An ability to know the SRAM Technology based FPGAs
• An ability to know the Anti-Fuse Technology based FPGAs

UNIT I
Introduction to Programmable Logic Devices: Introduction, Simple Programmable Logic
Devices – Read Only Memories, Programmable Logic Arrays, Programmable Array Logic,
Programmable Logic Devices/Generic Array Logic;
Complex Programmable Logic Devices – Architecture of Xilinx Cool Runner XCR3064XL
CPLD, CPLD Implementation of a Parallel Adder with Accumulation.

UNIT II
Field Programmable Gate Arrays: Organization of FPGAs, FPGA Programming
Technologies, Programmable Logic Block Architectures,
Programmable Interconnects, and Programmable I/O blocks in FPGAs, Dedicated
Specialized Components of FPGAs, Applications of FPGAs.

UNIT III
SRAM Programmable FPGAs: Introduction, Programming Technology, Device
Architecture
The Xilinx XC2000, XC3000 and XC4000 Architectures.

UNIT IV
Anti-Fuse Programmed FPGAs: Introduction, Programming Technology, Device
Architecture,
The Actel ACT1, ACT2 and ACT3 Architectures.

UNIT V
Design Applications: General Design Issues, Counter Examples, A Fast Video Controller, A
Position Tracker for a Robot Manipulator
A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and
Accumulators with the ACT Architecture.
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TEXT BOOKS:
1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer
International Edition.
2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage Learning.

REFERENCE BOOKS:
1. Field Programmable Gate Arrays - John V. Oldfield, Richard C. Dorf, Wiley India.
2. Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/Samiha Mourad,
Pearson Low Price Edition.
3. Digital Systems Design with FPGAs and CPLDs - Ian Grout, Elsevier, Newnes.
4. FPGA based System Design - Wayne Wolf, Prentice Hall Modern Semiconductor Design
Series.
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Design of ASICs
(Program Elective -I)
L/T/P/C:3/0/0/3

Course Learning Objectives

-level industrial standard ASIC or FPGA designer.

implementation.

design.

Course outcomes At the end of the course student will be able

CO1: demonstrate VLSI tool-flow and appreciate FPGA and CPLD architectures.
CO2: understand the issues involved in ASIC design, including technology choice, design
management and tool-flow.
CO3: understand the algorithms used for ASIC construction.
CO4: understand Full Custom Design Flow and Tool used.
CO5: understand Semicustom Design Flow and Tool used - from RTL to GDS and Logical to
Physical Implementation.

Unit-1

Introduction to Technology, Types of ASICs, VLSI Design flow, Design and Layout Rules,
Programmable ASICs - Antifuse, SRAM, EPROM, EEPROM based ASICs. Programmable
ASIC logic cells and I/O cells. Programmable interconnects. Advanced FPGAs and CPLDs
and Soft-core processors
Unit-II

ASIC physical design issues, System Partitioning, Floorplanning and Placement. Algorithms:
K-L, FM, Simulated annealing algorithms. Full Custom Design: Basics, Needs &
Applications. Schematic and layout basics, Full Custom Design Flow
Unit-III

Semicustom Approach: Synthesis (RTL to GATE netlist) - Introduction to Constraints

(SDC), Introduction to Static Timing Analysis (STA). Place and Route (Logical to Physical
Implementation): Floorplan and Power-Plan, Placement, Clock Tree Synthesis (clock
planning), Routing, Timing Optimization, GDS generation.
Unit-IV

Extraction, Logical equivalence and STA: Parasitic Extraction Flow, STA: Timing Flow,
LEC: Introduction, flow and Tools used. Physical Verification: Introduction, DRC, LVS and
basics of DFM.
Unit-V

System-On-Chip Design - SoC Design Flow, Platform-based and IP based SoC Designs,
Basic Concepts of Bus-Based Communication Architectures. High performance algorithms
for ASICs/ SoCs as case studies – Canonic Signed Digit Arithmetic, KCM, Distributed
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Arithmetic, High performance digital filters for sigma-delta ADC

Text Books
1. M.J.S. Smith, “Application Specific Integrated Circuits”, Pearson, 2003.
2. SudeepPasricha&NikilDutt, “On-Chip Communication Architectures System on Chip
Interconnect”, Elsevier, 2008.
Reference Books
1. H.Gerez, “Algorithms for VLSI Design Automation”, John Wiley, 1999.
2. Jan.M.Rabaey et al, “Digital Integrated Circuit Design Perspective”, 2nd Edition, PHI
2003.
3. David A.Hodges, “Analysis and Design of Digital Integrated Circuits”, 3rd Edition, MGH
2004.
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M.TECH.- I YEAR- I SEMESTER

VLSI SYSTEM DESIGN

(Professional Elective – II)

L/T/P/C:3/0/03

IOT AND ITS APPLICATIONS

(PE – II) Course Outcomes: At the end of this course,students

will be able to
1. Study the security and privacy issues in IOT.
2. Study IOT architecture and applications in various fields
3. Write the basic level programs in Python
4. Understand the applications of Internet of Things
5. Understand the Raspberry Pi interfacing with sensors
Unit-I
IoT& Web Technology The Internet of Things Today, Time for Convergence, Towards the
IoT Universe, Internet of Things Vision, IoT Strategic Research and Innovation Directions,
IoT Applications, Future Internet Technologies, Infrastructure, Networks and
Communication, Processes, Data Management, Security, Privacy & Trust, Device Level
Energy Issues, IoT Related Standardization, Recommendations on Research Topics.

UNIT II
IoT Architecture -State of the Art – Introduction, State of the art, Architecture Reference
Model- Introduction, Reference Model and architecture, IoT reference Model, IoT Reference
Architecture- Introduction, Functional View, Information View, Deployment and
Operational View, Other Relevant architectural views.

UNITIII
Introduction to Python - Language features of Python, Data types, data structures, Control
of flow, functions, modules, packaging, file handling, data/time operations, classes,
Exception handling. Python packages - JSON, XML, HTTP Lib, URL Lib, SMTP Lib.

UNIT-IV
IoT Applications for Value Creations Introduction, IoT applications for industry: Future
Factory Concepts, Brownfield IoT, Smart Objects, Smart Applications, Four Aspects in your
Business to Master IoT, Value Creation from Big Data and Serialization, IoT for Retailing
Industry, IoT For Oil and Gas Industry, Opinions on IoT Application and Value for Industry,
Home Management, eHealth.

UNIT-V
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IoT Physical Devices and Endpoints - Introduction to Raspberry PI - Interfaces (serial, SPI,
I2C). Programming – Python program with Raspberry PI with focus of interfacing external
gadgets, controlling output, reading input from pins.

TEXTBOOKS

1. Vijay Madisetti and Arshdeep Bahga, “Internet of Things (A Hands-on-

st
Approach)”, 1 Edition, VPT, 2014.
2 . Francis daCosta, “Rethinking the Internet of Things: A Scalable Approach to
C onnecting Everything”, 1st Edition, Apress Publications, 2013.
3. Cuno Pfister, “Getting Started with the Internet of Things”, O Reilly Media, 2011.
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Embedded RTOS

(Program Elective -II)

L/T/P/C:3/0/0/3

UNIT – I : Introduction: Introduction to UNIX/LINUX, Overview of Commands, File I/O,(

open, create, close, lseek, read, write), Process Control ( fork, vfork, exit, wait, waitpid, exec).

UNIT – II : Real Time Operating Systems: Brief History of OS, Defining RTOS, The
Scheduler, Objects, Services, Characteristics of RTOS, Defining a Task, asks States and
Scheduling, Task Operations, Structure, Synchronization, Communication and Concurrency.
Defining Semaphores, Operations and Use, Defining Message Queue, States, Content,
Storage, Operations and Use

UNIT – III : Objects, Services and I/O: Pipes, Event Registers, Signals, Other Building
Blocks, Component Configuration, Basic I/O Concepts, I/O Subsystem

UNIT – IV : Exceptions, Interrupts and Timers: Exceptions, Interrupts, Applications,

Processing of Exceptions and Spurious Interrupts, Real Time Clocks, Programmable Timers,
Timer Interrupt Service Routines (ISR), Soft Timers, Operations.

UNIT – V : Case Studies of RTOS: RT Linux, Micro C/OS-II, Vx Works, Embedded Linux,
and Tiny OS.

TEXT BOOK:

 Qing Li, “Real Time Concepts for Embedded Systems”, 2011, Elsevier.

REFERENCE BOOKS:

 Rajkamal, “Embedded Systems- Architecture, Programming, and Design”, 2007,

TMH.
 W. Richard Stevens, Stephan A. Rago, “Advanced UNIX Programming”, 2006, 2nd
Edition, Pearson.
 Dr. Craig Hollabaugh, “Embedded Linux: Hardware, Software and Interfacing”,
2008, 1st Edition, Pearson.
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IOT/Spice simulation Lab

Course Outcomes: At the end of the laboratory work, students will be able to:
1. Design digital and analog Circuit using CMOS.
2. Use EDA tools like Cadence, Mentor Graphics and other open source software tools like
Ngspice

Lab experiments to be included for Internet of Things Lab:

Part A

1..Start Raspberry Pi and try various Linux commands in command terminal window: ls, cd,
touch, mv, rm, man, mkdir, rmdir, tar, gzip, cat, more, less, ps, sudo, cron, chown, chgrp, ping
etc

2.Practice Linux commands and simple python programs on Rpi2

a) Write a Program for arithmetic operation in Python

b) Write a Program for looping statement in Python

3.Programming and Interfacing GPIOs – Blink LED Start/Stop with Switch

4.Weather monitoring with DHT11 and data storage on cloud (Thing Speak)

Part B Spice simulation

1) Use VDD=1.8V for 0.18um CMOS process, VDD=1.3V for 0.13um CMOS Process and
VDD=1V for 0.09um CMOS Process.
a) Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
b) Plot ID vs. VGS at particular drain voltage (low) for NMOS, PMOS and determine Vt.
c) Plot log ID vs. VGS at particular gate voltage (high) for NMOS, PMOS and determine
IOFF
and sub-threshold slope.
d) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel
length
modulation factor.
e) Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS =
30mV
To extract Vth use the following procedure.
i. Plot gm vs VGS using NGSPICE and obtain peak gm point.
ii. Plot y=ID/(gm)1/2 as a function of VGS using Ngspice.
iii. Use Ngspice to plot tangent line passing through peak gm point in y (VGS) plane
and determine Vth.
f) Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and
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calculate gm, gds, gm/gds, and unity gain frequency.

Tabulate your result according to technologies and comment on it.

2) Use VDD=1.8V for 0.18um CMOS process, VDD=1.2V for 0.13um CMOS Process and
VDD=1V for 0.09um CMOS Process.
a) Perform the following
i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine
transition voltage and gain g. Calculate VIL, VIH, NMH, NML for the inverter.
ii. Plot VTC for CMOS inverter with varying VDD.
iii. Plot VTC for CMOS inverter with varying device ratio.
b) Perform transient analysis of CMOS inverter with no load and with load and determine
tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload = 50fF)
c) Perform AC analysis of CMOS inverter with fanout 0 and fanout 1. (Use Cin= 0.012pF,
Cload = 4pF, Rload = k)

3) Use Ngspice to build a three stage and five stage ring oscillator circuit in 0.18um and
0.13um
technology and compare its frequencies and time period.

4) Perform the following

a) Draw small signal voltage gain of the minimum-size inverter in 0.18um and 0.13um
technology as a function of input DC voltage. Determine the small signal voltage gain at the
switching point using Ngspice and compare the values for 0.18um and 0.13um process.
b) Consider a simple CS amplifier with active load, as explained in the lecture, with NMOS
transistor MN as driver and PMOS transistor MP as load, in 0.18um technology
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I YEAR II – SEMESTER

Analog IC Design
(Program Elective -I)
L/T/P/C:3/0/0/3

Course outcomes At the end of the course student will be able

CO1: draw the equivalent circuits of MOS based Analog VLSI and analyse their
performance.
CO2: design analog VLSI circuits for a given specification.
CO3: analyse the frequency response of the different configurations of an amplifier.
CO4: understand the feedback topologies involved in the amplifier design.
CO5: appreciate the design features of the differential amplifiers.
Unit-1
Basic MOS Device Physics – General Considerations, MOS I/V Characteristics, Second Order
effects, MOS Device models. Short Channel Effects and Device Models. Single Stage
Amplifiers – Basic Concepts, Common Source Stage, Source Follower, Common Gate Stage,
Cascade Stage.
Unit-II
Differential Amplifiers – Single Ended and Differential Operation, Basic Differential Pair,
Common Mode Response, Differential Pair with MOS loads, Gilbert Cell. Passive and Active
Current Mirrors – Basic Current Mirrors, Cascode Current Mirrors, Active Current Mirrors.
Unit-III
Frequency Response of Amplifiers – General Considerations, Common Source Stage, Source
Followers, Common Gate Stage, Cascode Stage, Differential Pair. Noise – Types of Noise,
Representation of Noise in circuits, Noise in single stage amplifiers, Noise in Differential Pairs.
Unit-IV
Feedback Amplifiers – General Considerations, Feedback Topologies, Effect of Loading.
Operational Amplifiers – General Considerations, One Stage Op Amps, Two Stage Op Amps,
Gain Boosting, Common – Mode Feedback, Input Range limitations, Slew Rate, Power Supply
Rejection, Noise in Op Amps. Stability and Frequency Compensation.
Unit-V
Bandgap References, Introduction to Switched Capacitor Circuits, Nonlinearity and
Mismatch.
Text Books
1. B.Razavi, “Design of Analog CMOS Integrated Circuits” 2 nd Edition, McGraw Hill
Edition 2016.
2. 2. Paul. R.Gray&Robert G. Meyer, “Analysis and Design of Analog Integrated
Circuits”, Wiley, 5th Edition, 2009.
Reference Books
1. T. C. Carusone, D. A. Johns & K. Martin, “Analog Integrated Circuit Design”, 2nd
Edition, Wiley, 2012.
2. P.E.Allen&D.R. Holberg, “CMOS Analog Circuit Design”, 3rd Edition, Oxford
University Press, 2011.
3. R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 3rd Edition,
Wiley, 2010.
4. Recent literature in Analog IC Design.
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OPTIMIZATION TECHNIQUES IN VLSI DESIGN

(Program Elective -IV)
M.Tech (VLSISD) I Year-II Semester
L/T/P/C: 3/0/0/3

COURSE OBJECTIVES
• To understand the trade offs among various design styles given a set of design constraints in
physical design automation and to understand performance/area trade offs in a chip design
process.
• To learn the various statistic modeling methods like Monte Carlo techniques and Pelgroms
model etc.,
• To learn the implementation issues for digital design automation including optimization
techniques.
• To understand concept of design optimization algorithms and their application to physical
design automation.
• To understand the latest design techniques as practiced in the Industry for design layout
optimization.

COURSE OUTCOMES
After going through this course the student will be able to
• Apply the appropriate design practices, emerging technologies, state-of-the-art design
techniques, software tools, and research methods for IC design.
• Design the systems by using concepts of High level statistical, Gate level statistical analysis
methods.
• Design the low power digital systems by applying appropriate partitioning and Floor
planning algorithms.
• Design the real time applications using optimization techniques like Genetic Algorithms.
• Understand the concepts of geometric programming and convex functions.

UNIT –I
Statistical Modeling:
Modeling sources of variations, Monte Carlo techniques, Process variation modeling-
Pelgrom‟s model, Principle component based modeling
Quad tree based modeling, Performance modeling-Response surface methodology, delay
modeling, interconnect delay models
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UNIT –II Statistical Performance, Power and Yield Analysis:

Statistical timing analysis, parameter space techniques, Bayesian networks Leakage models,
High level statistical analysis, Gate level statistical analysis
dynamic power, leakage power, temperature and power supply variations, High level yield
estimation and gate level yield estimation.
UNIT –III
Convex Optimization:
Convex sets, convex functions, geometric programming, trade-off and sensitivity analysis,
Generalized geometric programming, geometric programming applied to digital circuit gate
sizing, Floor planning
wire sizing, Approximation and fitting- Monomial fitting, Maxmonomial fitting, Posynomial
fitting.
UNIT –IV
Genetic Algorithm:
Introduction, GA Technology-Steady State Algorithm-Fitness Scaling-Inversion GA for
VLSI Design, Layout and Test automation- partitioning-automatic placement, routing
technology, Mapping for FPGA
Automatic test generation- Partitioning algorithm Taxonomy-Multi-way Partitioning Hybrid
genetic-encoding-local improvement-WDFR Comparison of CAS-Standard cell placement-
GASP algorithm-unified algorithm.
UNIT –V
GA Routing Procedures and Power Estimation:
Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame
work-test generation procedures
Power estimation-application of GA-Standard cell placement-GA for ATG-problem
encoding- fitness function-GA Vs Conventional algorithm.
TEXT BOOKS / REFERENCE BOOKS:
1. Statistical Analysis and Optimization for VLSI: Timing and Power - Ashish Srivastava,
Dennis Sylvester, David Blaauw, Springer, 2005.
2. Genetic Algorithm for VLSI Design, Layout and Test Automation - Pinaki Mazumder,
E.Mrudnick, Prentice Hall,1998.

3. Convex Optimization - Stephen Boyd, Lieven Vandenberghe, Cambridge University Press,

2004.
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Digital CMOS Design

UNIT-I
Review: Basic MOS structure and its static behavior, Quality metrics of a digital design:
Cost,
Functionality, Robustness, Power, and Delay, Stick diagram and Layout, Wire delay models.
Inverter:
Static CMOS inverter, Switching threshold and noise margin concepts and their evaluation,
Dynamic
behavior, Power consumption.
UNIT-II:Physical design flow: Floor planning, Placement, Routing, CTS, Power analysis
and IR dropestimation-static and dynamic, ESD protection-human body model, Machine
model.
Combinational logic: Static CMOS design, Logic effort, Ratioed logic, Pass transistor logic,
Dynamic
logic, Speed and power dissipation in dynamic logic, Cascading dynamic gates, CMOS
transmission
gate logic.
UNIT-III:Sequential logic: Static latches and registers, Bi-stability principle, MUX based
latches, Static SR flipflops,
Master-slave edge-triggered register, Dynamic latches and registers, Concept of pipelining,
Pulse registers, Non-bistable sequential circuit.
Advanced technologies: Giga-scale dilemma, Short channel effects, High–k, Metal Gate
Technology,
FinFET, TFET etc
Unit-IV: Designing Arithmetic Building Blocks: Introduction, The Adder, The Binary Adder:
Definitions, The Full Datapaths in Digital Processor Architectures, Adder: Circuit Design
Considerations, The Binary Adder: Logic Design Considerations, The Multiplier, The
Multiplier: Definitions, Partial- Product Generation, Partial Product Accumulation, Final
Addition, Multiplier Summary, The Shifter, Barrel Shifter, Logarithmic Shifter

Unit-V:Designing Memory and Array Structures: Introduction, Memory Classification,

Memory Architectures and Building Blocks, The Memory Core, Read Only Memories,
Nonvolatile Read-Write Memories, Read-Write Memories (RAM), Contents Addressable or
Associative Memory (CAM), Memory Peripheral Circuitry, The Address Decoders, Sense
Amplifiers, Voltage References, Drivers/Buffers, Timing and Control

TEXTBOOKS
1.Kamran Ehraghian, Dauglas A. Pucknell and Sholeh Eshraghiam, “Essentials of VLSI
Circuits and Systems” – PHI, EEE, 2005 Edition.
2.Neil H. E. Weste and David. Harris Ayan Banerjee,, “CMOS VLSI Design” - Pearson
Education.
REFERENCES
1. Sung-Mo Kang, Yusuf Leblebici,”CMOS Digital Integrated Circuits” TMH 2003
2. Jan M. Rabaey, “Digital Integrated Circuits” Pearson Education, 2003
3. Wayne Wolf, “Modern VLSI Design ", 2nd Edition, Prentice Hall,19
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Analog IC Design Laboratory

List of Experiments
1. Characteristics of NMOS & PMOS Transistor
2. Design of Common Source Amplifier with different Loads
3. Design of Common Gate Amplifier
4. Design of Common Drain Amplifier
5. Design of Single stage Cascode Amplifiers
6. Design of Current Mirrors
7. Design of Differential Amplifiers with Different Loads
8. Design of Two stage Opamp
9. Design of Telescopic CascodeOpamp
10. Design of Folded CascodeOpamp
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Digital CMOS LAB (Lab – IV)

COURSE OBJECTIVES
• To describe over view about evolution of CMOS integrated circuits.
• To provide knowledge about Combinational, Sequential MOS logic circuits
• To introduce and familiarize with the various logic circuits.
• To prepare them to face the challenges in dynamic logic circuits.
• To prepare them to design various building blocks in combinational and sequential circuits.

COURSE OUTCOMES: After going through this course the student will be able to
• An ability to know about the various Combinational and Sequential MOS logic circuits.
• An in-depth knowledge of applying the concepts on real time applications
• An ability to understand the basic concepts of Boolean expressions.
• Able to design different Combinational logic blocks.
• Able to analyze and implement various memory elements.

Note: All the following digital circuits are to be designed and implemented using
Cadence/ Mentor Graphics/ Synopsys/ equivalent CAD Tools.

1. Design and Draw layout for CMOS Inverter gate and perform DRC, LVS, RC Extraction.
2. Design and Draw layout for CMOS NOR/ NAND gate and perform DRC, LVS, RC
Extraction.
3. Design and Draw layout for CMOS XOR gate using Transmission Gates and perform DRC,
LVS, RC Extraction.
4. Design and Draw layout for Full Adder using CMOS logic and perform DRC, LVS, RC
Extraction.
5. Design and Draw layout for Latch using CMOS logic and perform DRC, LVS, RC Extraction.
6. Design and Draw layout for SRAM Design using CMOS logic and perform DRC, LVS, RC
Extraction.