Scribd
Upload
75 views5 pages

Programmable Digital Signal Processors Commercial DSP Devices

The document discusses programmable digital signal processors (DSPs). It summarizes the key features of commercial DSPs, including Harvard architecture, hardware multipliers, and on-chip memory. It then provides details about the architecture and instruction set of the Texas Instruments TMS320C54xx DSP, including its memory system, central processing unit, accumulators, barrel shifter, and addressing modes.

Uploaded by

sannidhiguruprasad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
75 views5 pages

Programmable Digital Signal Processors Commercial DSP Devices

The document discusses programmable digital signal processors (DSPs). It summarizes the key features of commercial DSPs, including Harvard architecture, hardware multipliers, and on-chip memory. It then provides details about the architecture and instruction set of the Texas Instruments TMS320C54xx DSP, including its memory system, central processing unit, accumulators, barrel shifter, and addressing modes.

Uploaded by

sannidhiguruprasad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

PROGRAMMABLE DIGITAL SIGNAL PROCESSORS

Commercial DSP devices:

Most of the commercial DSP devices have


harvard architecture
single-cycle hardware multiplier
address generation unit
dedicated address registers
special addressing modes
on-chip memories
hardware support for loops.
The first programmable DSP was TMS32010 in 1982 by Texas instruments.
The first widely used P-DSP was TMS320C25 in 1985.
Motorola introduced DSP56000.
Analog devices introduced ADSP2100.

Data addressing modes of TMS320C54XX DSP’s:

They retain the basic Harvard structure.


They have one program and 3 data memory with separate buses.
They help provide simultaneous access to program instruction and two data operands and
enable writing of result at same time.
Memory implementation
on-chip
ROM
dual-access RAM
single-access RAM
Transfers between the memory spaces are also possible.
The cpu of TMS320C54XX contains
40-bit ALU
Two 40-bit accumulators
Barrel shifter
17x17 multiplier
40-bit adder
Data address generation logic (DAGEN)
Program address generation logic (PAGEN)
The instruction set includes
Hardware support
Single instruction repeat
Block repeat
Block memory move
Instructions that pack 2 or 3 simultaneous reads
Arithmetic instructions with parallel store and load.
On-chip peripherals include
Clock generator
Hardware timer
Wait state generator
Parallel I/O ports.
Serial I/O ports.

Bus structure:

Multiple buses enhance the performance of processor.


The 54XX architecture is build around four pairs of 16-bit buses.
Each bus contains an address bus and a data bus.
The program bus pair (PAB, PB) carries the instruction code from program memory.
The three data bus pairs (CAB, CB; DAB,DB; EAB,EB) interconnect various units within t he CPU.
The pairs CAB, CB and DAB, DB are used to read from the data memory
The pair EAB,EB carry the data to be written to the memory.
The C54xx can generate upto 2 data memory addresses per cycle using 2 auxi9liary registger
arithmetic units (ARAU 0) and (ARAU1) in the DAGEN block
This enables accessing two operands simultaneously.

Central processing Unit (CPU):

The ‘54xx CPU is commonly to all ‘54xx devices .


The ALU performs 2’s complement arithmetic operations.
It also performs bit-leve Boolean operations on 16,32 and 40 bit words.
It can perform as 2-separate 16-bit ALU’s and perform two 16-bit operations simultaneously.

Accumulators:

Accumulators A and B store output form the ALU (or) the multiplier/adder block and provide a
second input to the ALU
Each accumulator is divided into 3 parts.
Guard bits (bits 32-39)
High order word (bits 31-16)
Low order word (bits 15-0)
These 3 parts can be stored or retrieved individually.

Barrel shifter:

The barrel shifter provides the capability to scale the data during an operand read (or) write.
The 54xx barrel can produce a left shift of 0-31 bits and right shift of 0to 16 bits on the input
data.
The shift details are defined in the shift count field of the instruction, the shift count field of the
status register (ST1) or the temporary register T.
The barrel shifter and the exponent encoder normalize the values in an accumulator in a single
cycle.
The LSB’s of the output are filled with 0’s.
The MSB’s can be either zero filled or sign extended.
It depends on the sign- extension mode bit in the status register ST1.

Multiplier/adder unit:

It is the kernel of the DSP device architecture


The MAU performs 17x17 2’s complement multiplication with a 40-biut addition effectively in
single instruction cycle.
The unit also consists of control logic for integer and fractional computations.
It also consists of 16-bit temporary storage register T.

Compare, select and store Unit (CSSU):

It is a hardware unit specifically incorporated to accelerate the add/compare/select option.


This operation is essential to implement the viterbi algorithm.

Exponent encoder unit:

It supports Exp instruction, which stores the number of leading redundant bits in the T register.

Internal memory & memory mapped registers:

The 54xx memory is organized into 3 individually selectable spaces


Program
Data
I/O space
All ‘54xx devices contain both RAM and ROM
RAM can be either dual-access RAM (DARAM) or single-access RAM (SARAM).
The on-chip RAM of these processors is orgainzied into pages having 128 word locations on
page.
The cpu registers and peripheral registers are all located on page O of the data memory.
The processor mode status (PMST) register is used ti configure the processor.
It is memory mapped register located at address IDH on page O of the RAM.

Data addressing modes of TMS320C54xx processors:

The ‘54xx devices offer seven basic addressing modes.


Immediate addressing
Accumulator addressing
Indirect addressing
Stack addressing
Absolute addressing
Direct addressing
Memory mapped register addressing

Immediate addressing mode:

Here the instruction contains specific value of the operand


The operand can be short (3,5,8,9) (or) long (16-bit)
The instruction syntax for short operands occupies one-memory location.
For long operands, it occupies 2 memory locations.
It can be used to initialize registers and memory locations.
Eg: LD #20, DP #20H --------> DP
RPT #0FFFFH 0FFFF--------->RC

Absolute addressing:

Here, the instruction contains a specific address.


The address may be
Data address location (dmad addressing)
Program address location (pmad addressing)
Port address (PA addressing)
Location in data space specified directly (*(lk) addressing)

Eg: MVKD 1000H,*AR5 : 1000H ---------> AR5


MVPD 1000H,*AR7 : 1000H ---------->*AR7
PORTR 05H, *AR3 : 05H -------------> *AR3
LD *(1000)H, A : *(1000H)--------->A

Accumulator addressing:

It uses accumulator contents as the address.


It is used to move data between program memory location and at memory location
READ A transfers a word from program memory location specified by A to data memory
location.
WRIT A transfers a word from data memory location to the program memory location specified
by A
Eg: READA *AR2 *A --------> *AR2

Direct addressing:

Here, the 16-bit address of the data – memory location is formed by combining the lower 7-bits
of the data memory address contained in the instructions with the base address give by data-
page pointer (DP) or the stack pointer(SP).
We can access a page of 128 contiguous locations without changing the DP (or) SP.
The compiler mode bit (CPL) located in status register ST1 selects between the two pointers.
CPL=0 Selects DP
CPL=1 selects SP.
When CPL=0, to add the contents of memory location on page 4 in the data memory to
accumulator to accumulator B,
LD #4, DP : DP=4=upper a bits of address
ADD=0, B : lower 7 bits of the address.
When SP is used instead of DP the effective address is computed by adding 7-bit offset to SP.

Indirect addressing:

Any location in the data space can be accessed by means of address contained in an auxiliary
register.
54xx devices have 8 16-bit auxiliary registers (AR0-AR7)
It is to be used when there is need to step through a sequence of locations in the memory in the
fixed size steps.
Two auxiliary register arithmetic units (ARAU 0 & ARAU1) are used to modify the contents of
auxiliary registers.
They perform unsigned, 16-bit arithmetic operations.
They can be loaded with an immediate value.
Loaded via the data bus.
Modified by indirect addressing field of any instruction.
Modify auxiliary register (MAR) instruction.
Used as loop counters.

Generating address using ARAU:

Address can be modified before (or) after accessing the location or can be left unchanged.
We can increment (or) decrement the address by 1
We can add a 16-bit offset.
We can index with the value in AR0.
These modifications can be carried out either before after accessing the memory location.

Circular addressing:

Real time algorithms like convolution, correlation, FIR filters require implementation of circular
buffer.
A circular buffer is a sliding window containing the most recent data.
As new data come in, the buffer overwrites the oldest data.
An indirect addressing mode with circular buffer address modification allows implementation of
circular buffers.
The circular buffer size register (BK) specifies the size of the circular buffers.

You might also like