INTEL 8086 - Pin Diagram

UCS1502
MICROPROCESSORS AND INTERFACING

By
S. Angel Deborah
AP/CSE
 Learning Objective
• To understand the pin details of 8086
• To understand the purpose of each pins.
 Overview
• Pin Diagram
• Modes of Operation
• Memory bank
• Control signals
INTEL 8086 - Pin Diagram

4
 INTEL 8086 - Pin Details
Power Supply
5V ± 10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
5
 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.

6
 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request

7
INTEL 8086 - Pin Details
Direct
Memory
Access

Hold

Hold
acknowledge

8
INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3

9
 INTEL 8086 - Pin Details

BHE#, A0: Bus High Enable/S7

1,1: No selection

10
 INTEL 8086 - Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

11
Minimum Mode- Pin Details

Read Signal

Write Signal

Memory or I/0

Data
Transmit/Recei
ve
Data Bus
Enable 12
 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.

Microprocessor &
13
Microcontroller
 Maximum Mode - Pin Details

Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the Request/Grant
LOCK: prefix on any
instruction
Lock Output

Microprocessor &
14
Microcontroller
 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)

15
 Test
• TEST pin is examined by the "WAIT" instruction.
• If the TEST pin is Low, execution continues.
• Otherwise the processor waits in an "idle" state.
• This input is synchronized internally during each clock
cycle on the leading edge of CLK.
CLK
 Lock
• It indicates to another system bus master, not to gain
control of the system bus while LOCK is active Low.
• The LOCK signal is activated by the "LOCK" prefix
instruction and remains active until the completion of the
instruction.
instruction
• This signal is active Low and floats to tri-state OFF
during 'hold acknowledge'.
 Memory Banking

RCET 18
Interface 8086 to 6116 Static RAM
A0, BHE*
6116 (2K x8)
20 21 A(11-1)
A A(10-0)
____ Latch D(7-0)
BHE D(7-0) __
ALE A(19-12) R/W Low byte
D OE* (Even Bank)
16 CS*
Addr
Decoder RAMCS*
8086
__ A0 A(11-1) A(10-0)
MEM* D(7-0)
M/IO
___ D(15-8) __
WR
___ R/W High byte
RD OE* (Odd Bank)
BHE* CS*

19
8086 Control Signals
1. ALE
2. BHE
3. M/IO
4. DT/R
5. RD
6. WR
7. DEN

20
 Summary
• Pin Diagram
• Modes of Operation
• Memory bank
• Control signals
 Reference
• Doughlas V Hall, “Microprocessors and Interfacing,
Programming and Hardware”, TMH, 2012.
Thank you