IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO.

8, AUGUST 2019 2255

A Low-Noise Chopper Amplifier Designed for

Multi-Channel Neural Signal Acquisition
Deng Luo, Student Member, IEEE, Milin Zhang , Senior Member, IEEE, and Zhihua Wang, Fellow, IEEE

Abstract— This paper proposed the design of a low-noise, distributes from sub-Hz to about 200 Hz, and APs occupy a
low total harmonic distortion (THD) chopper amplifier for frequency band from 200 Hz to 5 kHz [6], [7].
neural signal acquisition. A dc servo loop (DSL) based on In order to perform the LFPs and APs acquisition with
active Gm-C integrator is proposed to reject the electrode-dc-
offset (EDO). Architecture of a complementary input very low- high precision, an analog-front-end (AFE) features input-
transconductance (VLT) operational transconductance amplifier referred noise (IRN) as low as to μV level is required.
(OTA) was proposed and integrated in the active Gm-C integrator In addition, the performance of low-power consumption is
to improve the linearity as well as to reduce the noise, featuring a also expected to extend the battery life, as well as to reduce
transconductance ranging from 45 pS to a few nS. The proposed self-heating of the implanted device for safety [8]. However,
amplifier was fabricated in a TSMC 0.18-µm CMOS process,
occupying an area of 0.2 mm2 , featuring a power consumption there is a tradeoff between the noise and power, which is
of 3.24 µW/channel under a 1.8-V supply voltage. The THD typically quantitatively measured in terms of noise-efficiency
for a 5-mVpp input is lower than −61 dB. An input-referred √ factor (NEF). The traditional capacitive-coupled instrumental
thermal noise power spectral density (PSD) of 39 nV/ Hz is amplifier (CCIA) features a low NEF, as well as a simple struc-
measured. The measured input-referred noise is 0.65 µVrms in ture [9]. Different techniques, such as current splitting, source
the 0.3–200-Hz frequency band and 2.14 µVrms in the 200-Hz– degeneration, complementary input, current reuse, and partial
5-kHz frequency band, respectively, leading to a noise-efficiency
factor of 2.37 (0.3–200 Hz) and 1.56 (0.2 k–5 kHz). In addition, operational transconductance amplifier (OTA) sharing archi-
the high-pass corner frequency can be precisely configured and tecture [10]–[13] have been reported in the literature to reduce
linearly adjusted with the external bias current from 0.35 to the NEF of a capacitive-coupled amplifier. In [10], an NEF
54.5 Hz. of 3.09 is achieved by employing current scaling, current
Index Terms— Active Gm-C integrator, chopper amplifier, splitting, and bottom-transistor source degeneration to reduce
complementary input operational transconductance amplifier the IRN. A complementary input-based OTA [14] can double
(OTA), high linearity, low-noise amplifier, very low transconduc- the effective transconductance without increasing the bias
tance (VTL) OTA.
current. Reference [12] proposed the current reuse technique
enabling a reduction of NEF to 1.07 or even further by a stack-
I. I NTRODUCTION
ing inverter. However, the capacitive-coupled amplifiers suffer

B RAIN–machine-interface (BMI) has been widely used

in neuroprosthetics and neuromodulatory system, tak-
ing the advantages of the development in microelectrode,
from flicker noise, greatly reducing the performance of LFP
signal acquisition. In order to obtain less than 1 μVrms IRN,
the chopper-stabilized technique can be utilized, which pushes
microelectronics, and computing technologies [1], [2]. Neural the 1/ f frequency corner to sub-Hz [15].
signal acquisition plays a critical role in a BMI system to One of the main challenges in chopper-stabilized amplifier
close the loop [3]–[5]. The target signal varies while different design, as proposed in [15], is how to create a high-pass corner
electrodes are used or different detection locations are applied. to filter out the electrode-dc-offset (EDO). Different from
Typically, local field potentials (LFPs) and action potentials the capacitive-coupled amplifier, which features a high toler-
(APs) are captured using an invasive penetrating electrode. ance to the EDO rail-to-rail inherently, the chopper-stabilized
The amplitude of LFP and AP is typically in the order of amplifier cancels EDO by integrating an active feedback loop,
tens of microvolts to a few millivolts. The frequency of LFPs denoted as dc servo loop (DSL). Reference [15] proposed
a switched-capacitor integrator-based DSL design, realizing
Manuscript received November 16, 2018; revised March 15, 2019; accepted
April 12, 2019. Date of publication June 25, 2019; date of current version up to ±50-mV EDO cancellation, but requiring an 800-pF
July 23, 2019. This paper was approved by Associate Editor Hoi-Jun Yoo. large on-chip capacitor with high silicon area consumption
This work was supported in part by the Beijing Innovation Center for Future to achieve sub-Hz high-pass corner. A modified design is
Chip, in part by the Beijing National Research Center for Information Science
and Technology, in part by the National Natural Science Foundation of China reported in [16] to reduce the silicon area, but sacrificing
under Grant 61674095, and in part by the Thousand Youth Talents Plan. the IRN of the overall system by 6.7 uVrms (11.1×) in the
(Corresponding author: Milin Zhang.) band of 0.5–100 Hz, which is unacceptable for the application
D. Luo and Z. Wang are with the Institute of Microelectronics, Tsinghua
University, Beijing 100084, China. of LFP signal acquisition. The back-to-back pseudoresistor is
M. Zhang is with the Department of Electronic Engineering, Tsinghua widely used as an area-efficient method to create low high-
University, Beijing 100084, China (e-mail: [email protected]). pass corner while achieving low noise [17], [18]. However,
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. the value of the pseudoresistor is extremely sensitive to
Digital Object Identifier 10.1109/JSSC.2019.2913101 process–voltage–temperature (PVT) variations, which can be
0018-9200 © 2019 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted,
but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2256 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019

varied by a factor of 100 [7]. In addition, the nonlinearity

of the pseudoresistor causes poor performance with large
output swing. For LFPs and APs acquisition applications,
with an expectation of μV level IRN for the amplifier
and approximately 10-bit ADC resolution [19], up to 60-dB
dynamic range is required, which is almost impossible for
the pseudoresistor-based structure, even with an elaborate bias
scheme [20]. In [21], a digital low-pass filter is used for
EDO cancellation. The quantization noise was successfully
suppressed below the 1-μV thermal noise level, but a digital-
to-analog converter (DAC) with higher than 17-bit resolution
is required, which will greatly increase the complexity of Fig. 1. (a) Schematic of the chopper-stabilized amplifier, consisting of a low-
noise OTA and a DSL. (b) Active Gm-C integrator used in DSL. (c) Transfer
the system. In addition, a total harmonic distortion (THD) of function of the chopper amplifier using the active Gm-C integrator.
only −48 dB at 1-mVpp input voltage is reported in [21].
To summarize, solutions to achieve a low-frequency high-
pass corner have been reported in the literature, but a few can
realize a good balance among noise, linearity, and accuracy.
Pseudoresistor is low noise, but suffering from poor linearity
and inaccuracy due to its high sensitivity to PVT variations.
The switch-capacitor integrator features higher accuracy with
high linearity but suffers from a poor noise performance due
to noise aliasing [16].
This paper proposed an architecture of a chopper-stabilized
amplifier designed for a multi-channel neural recording sys-
tem, featuring a good balance between power, noise, and
linearity, by employing an active Gm-C-based DSL. The pro- Fig. 2. Symmetrical OTA with series–parallel current division to reduce
posed active Gm-C-based DSL achieves high linearity while transconductance.
maintaining low noise. The rest of this paper is organized as
follows. Section II reviews the state of the art of very low
transconductance (VLT) OTA designs, which is the key mod- For LFP recoding, smaller than 0.5 Hz f hp is required.
ule in the chopper-stabilized amplifier. Section III introduces According to (1), f int,ugb of around 0.25 Hz is expected, which
the proposed complementary input VLT OTA design. By using means that a very large time constant integrator is needed.
the proposed complementary VLT OTA, a low-noise chopper- The integrator capacitance Cint is set to 40 pF to achieve a
stabilized neural signal amplifier was proposed in Section IV, good balance between the area consumption and noise. Thus,
including the detailed architecture design of each module and gm,VLT must be smaller than 63 pS, which places a great
a noise analysis. Section V illustrates the experimental results, challenge for on-chip implement. Consider the scenario of
while Section VI concludes the entire work. invasive neural signal acquisition, the input linear range of the
chopper-stabilized amplifier should be at least 4 mVpp , and
the closed-loop gain of the amplifier is set to 40 dB, which
II. D ESIGN R EQUIREMENTS A NALYSIS means that a linear input range of 400 mVpp is required for
AND R EVIEW OF VLT OTA D ESIGNS the VLT OTA design.
A. Design Requirements Analysis
Fig. 1(a) shows an overview of the proposed chopper B. Review of VLT OTA Designs
stabilization-based neural signal amplifier design. It consists Various VLT OTA topologies have been reported in the liter-
of a differential low-noise OTA and an active Gm-C integrator- ature. An extremely low bias current is applied in [22], leading
based DSL. The proposed DSL features a very large time to an extremely low transconductance. However, the input
constant integrator based on the active Gm-C structure by linear range is limited to 100 mVpp , as the input transis-
implementing a VLT OTA, as shown in Fig. 1(b). The require- tors operate in the subthreshold region. Current cancellation
ments of the VLT OTA are discussed as follows. technique is utilized to divide the OTA transconductance by
The transfer function of the proposed chopper amplifier is a desired factor [23]. However, it is very sensitive to the
shown in Fig. 1(c). The high-pass corner frequency fhp can mismatch and noise, leading to a limited reduction factor of
be calculated as about 20. Current division is an alternative method to realize
f int,ugb Chp low transconductance, which simply uses current mirrors with
fhp = (1) large division factors [24]. However, it is area hungry. The
Cfb
active area of the VLT OTA is roughly 0.25 mm2 . The area
where f int,ugb is the unity-gain bandwidth of the integrator, efficiency can be improved by using a series–parallel current
which is defined by gm,VLT/2πCint , and Chp is approximately division in OTA, as shown in Fig. 2. An OTA features a
equal to twice the capacitance of C f b . transconductance of 89 pS with a linear range of ±500 mV
LUO et al.: LOW-NOISE CHOPPER AMPLIFIER DESIGNED FOR MULTI-CHANNEL NEURAL SIGNAL ACQUISITION 2257

Fig. 4. Body effect is used in the proposed design to generate equivalent

bias offset voltage of the source degeneration transistors.

Fig. 3. (a) Classical differential nMOS pair OTA input stage. (b) Differential
pMOS pair OTA input stage with source degeneration transistors. (c) Proposed
complementary OTA input stage.

are reported in [25] by employing the series–parallel current

division scheme with a division factor of 784 and consuming
an area of 0.15 mm2 . Although the area efficiency is obviously
improved, there is still room for further improvement to
better fit the requirement rising from multi-channels neural
acquisition applications. In this paper, a low-noise, low-power
Fig. 5. Schematic of the proposed VLT OTA with a complementary input
consumption amplifier is proposed. A complementary input, stage.
weak inversion region biased VLT OTA with extremely low
bias current is applied in the proposed design. A much lower
division factor is achieved with the same transconductance off. Comparing Fig. 3(a) and (b), the linear input point of
while compared with the design reported in the literature the classical differential nMOS pair is around zero, while the
(see [25]). The noise is greatly reduced since higher gm /Id linear input point of the pMOS pair with source degeneration
is applied. In addition, the silicon area efficiency and power transistors is shifted to ±V .
consumption are also improved in the proposed design. This paper proposed a complementary input stage design
technology for OTA, as shown in Fig. 3(c). It combines the
III. D ESIGN OF A VLT OTA W ITH nMOS pair with the pMOS pair with a proper ratio to extend
C OMPLEMENTARY I NPUT S TAGE the input linear range. An equivalent offset voltage of the
source degeneration transistors is generated by applying a
A. Design of a Complementary Input Stage for OTA
threshold of the source degeneration transistors larger than that
The differential nMOS pair is widely used in the classical of the input differential pair, as shown in Fig. 4. If a larger
OTA design as the input stage, as shown in Fig. 3(a). A very threshold is applied, a larger input voltage is required to turn
low tail current is used to achieve VTL. The nMOS pair is on the device with the same function of the offset voltage. The
biased in a weak inversion region. The input linear range is bulks of the differential pair are connected to the source, while
limited to 100 mVpp . Fig. 3(b) shows a differential pMOS the bulks of source degeneration transistors are connected to
pair OTA input stage with a source degeneration technique. the power line. The threshold voltage is given by
Different from the traditional source degeneration technique,  
V , as shown in Fig. 3(b), is employed as the input bias VTH = VTH0 + γ ( |2φ F | − |2φ F + VSB |) (2)
offset of the source degeneration transistors to provide an where VTH0 is the threshold voltage with VSB = 0, γ is the
extra degree of freedom. The input pair and the source body-effect constant, φ F is the Fermi potential of the substrate,
degeneration transistors, featuring the same size, are biased in and VSB is the voltage between the source and the bulk. The
the deep subthreshold region. When the input voltage is lower equivalent offset voltage V can be given by
than V , the current passing through the source degeneration  
transistors is very small due to the bias offset voltage V . V = γ ( |2φ F + VSB | − |2φ F |). (3)
The source degeneration transistors act as an extremely large
In the proposed design, a simulated V value of 0.149 V
resistor. Considering the source negative feedback effect,
is achieved by biasing the source degeneration transistors
the effective transconductance of the input differential pair is
with VDD .
nearly zero. When the input voltage increases to be closed
to V , the effective impedance of the source degeneration
transistors decreases dramatically, which means that the source B. Architecture of a Complementary Input VLT OTA
degeneration transistors work normally to extend the linear Based on the proposed complementary input stage,
range around an input voltage of V . When the input voltage the architecture of a complementary input VLT OTA is pro-
further increases, one of the input transistors will be turned posed, as shown in Fig. 5. The series–parallel current division
2258 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019

scheme is used in the proposed design. It also employed the

proposed linearizing method to extend the input linear range
while reducing the noise and area consumption. The output
current of the VLT OTA is contributed by the nMOS pair and
the pMOS pair together. The ratio between the bias current
of the nMOS input pair and that of the pMOS input pair is
denoted as β. The series–parallel current division scheme is
applied to the nMOS pair and the pMOS pair separately. There
are ten transistors connected in parallel and ten transistors
connected in series to divide the input current by a ratio of 100.
Thus, a VTL can be achieved.
Assuming that the two input transistors match perfectly and
ignoring the channel length modulation effects, the output
differential current of pMOS pair can be calculated as
 κ Vd
−κ V −κ Vd 
e e VT − e VT
VT
Id ≈ 2Ib −κ V  κ Vd −κ Vd 
(4)
ζ + e VT 2 + e VT + e VT
where Vd is the input differential voltage, Ib is the bias current
for each transistor in the differential pair, V is defined by (3),
Fig. 6. Plot of (a) linear input voltage versus the achievable minimum
VT is the thermal voltage of 26 mV at room temperature, ζ is nonlinearity e. (b) e versus β and ζ .
the ratio between the W/L of the pMOS pair and the source
degeneration transistors, and κ is the subthreshold slope factor
that depends on the progress. The output current of the nMOS
pair can be expressed as
κ Vd
e VT − 1
Id = 2β Ib κ Vd
. (5)
e VT +1
Based on (4) and (5), the output differential current of the
proposed OTA is expressed as
⎛ κ Vd −κ V  κ Vd −κ Vd  ⎞
2Ib ⎝ e VT − 1 e VT e VT −e VT
Id = β κ Vd + ⎠ (6)
−κ V  κ Vd −κ Vd 
N
e +1 ζ + e
VT VT
2 + e +e
VT VT

where N is the current division factor, which is set to 100.

Ib is the bias current for each transistor of the pMOS input
pair, which is set to 0.5 nA. In (6), β, ζ , and V are the three
independent variables. The goal of the proposed design is to
achieve a high linearity with a larger linear input range. The
Fig. 7. Simulation results of (a) V versus process variations, (b) e versus
nonlinearity of Id can be qualified as process variations, (c) e versus supply voltage, and (d) e versus temperature.

Id,max 2
−Id,max Id d Id The value of e can be optimized by tuning β and ζ with a
e =
(7)
Id,max 2 dI fixed Id,max value. As mentioned earlier, V is set to 0.149 by
I
−Id,max d d
biasing source degeneration transistors with supply voltage.
where Id is the deviation of Id to an ideal one, which is Fig. 6(b) shows the relationship between e and β and ζ .
also called residual, while Id,max represents the linear input A minimum e value of 1.6% is achieved with a β value
range. There is a tradeoff between the nonlinearity and the of 0.46 and a ζ value of 0.82, respectively.
linear input range, which is shown in Fig. 6(a). It is calculated PVT sensitivity is important to the performance of the pro-
according to (6) by sweeping β, ζ , and V . In this paper, posed design. V varies with the process variations, as shown
the maximum target signal is 2.5 mVp. With a gain of 40 dB, in Fig. 7(a). With 1000 runs of Monte Carlo simulation,
the input of the VLT OTA can be 250 mVp. However, V features a standard deviation of 1.6 mV. Fig. 7(b) shows
according to the simulation, THD is smaller than −60 dB, the nonlinearity factor e with process variations. An average e
when Id,max is set to 250 mVp. To meet the requirement value of 2.35% is achieved. According to (3), V is sensitive to
of THD, Id,max is set to 200 mVp. A voltage divider is the supply voltage. Fig. 7(c) shows the simulated relationship
employed to enhance the linear range from 200 mVp to between V or e and supply voltage, respectively. In order to
250 mVp, as addressed in Section IV-C. achieve less than 2% of e, the supply voltage should be in the
LUO et al.: LOW-NOISE CHOPPER AMPLIFIER DESIGNED FOR MULTI-CHANNEL NEURAL SIGNAL ACQUISITION 2259

Fig. 9. Schematic of the proposed two-stage chopper-stabilized amplifier.

Compared with thermal noise, the flicker noise of the VLT

OTA can be ignored. The corner frequency of the flicker
noise is lower than 0.1 mHz according to the simulation.
Fig. 8. (a) Simulation results of the output current of the VLT OTA versus By applying the thermal model in the deep subthreshold
the input voltage. Compared with the OTA with a single nMOS pair as the region, the output current noise in Fig. 5 can be calculated
input stage, the proposed one with a complementary input stage increases
the linear range by four times, from ±50 to ±200 mV. (b) Monte Carlo as
simulation with 1000 runs. The simulation results show a high robustness of
 
8kT 1 2
the proposed VLT OTA against the process variation. 2
i n,out = Ib + 2 . (8)
VT N N
According to (6), when the input voltage is zero, the transcon-
range of 1.75–1.88 V. A power supply insensitive bias circuit ductance of the proposed VLT OTA in Fig. 5 can be given by
can be designed to enlarge the supply voltage range. Fig. 7(d) βκ Ib
shows the simulated relationship between e and temperature. gm = . (9)
N VT
It clearly shows that the proposed design is not very sensitive
to the changes in temperature under the room temperature. According to (8) and (9), the IRN in Fig. 5 can be expressed
The simulated output current of the proposed VLT OTA as
versus the differential input voltage is plotted, as shown 2
i n,out 8kT
in Fig. 8(a). When β is set to 0.5, the linear range is v n,in
2 = ≈ . (10)
2
gm βκgm
enhanced by four times, from ±50 to ±200 mV by using
the proposed complementary input stage. The implementation IV. D ESIGN OF THE P ROPOSED L OW-N OISE
of the common-mode (CM) feedback loop is shown in Fig. 5 C HOPPER -S TABILIZED A MPLIFIER
as well. The current flowing through the nMOS in the output
branch is larger than that of the pMOS since the bias current of A. System Overview of the Proposed Chopper Amplifier
the pMOS pair is larger than that of the nMOS pair. The CM The proposed chopper-stabilized neural recording amplifier
feedback loop integrates a pair of pMOS branch to compensate is shown in Fig. 9. It consists of: 1) a two-stage Miller-
for the current gap between the output nMOS and pMOS. compensated OTA; labeled as gm1 and gm2 ; 2) an input
Two pMOS transistors worked in the triode region are used impedance boosting loop; 3) an active Gm-C integrator-based
to sense the output of the VLT OTA to adjust the current DSL using the proposed VLT OTA, labeled as gmVLT; and
of the compensating pMOS branch. Thus, the CM output of 4) a capacitive feedback loop.
the VLT OTA can be set to a proper value. In this design, the The two-stage Miller-compensated OTA dominates the lin-
CM output is set to 1.4 V. Note that the output of the proposed earity performance in the high-frequency band, while in the
VLT OTA is connected to a virtual ground node, which is the low-frequency band, the linearity performance is decided by
input of an OTA. Thus, the CM feedback loop performs little the active Gm-C integrator. As mentioned earlier, a com-
influence on the linearity. plementary input scheme was employed in the proposed
The proposed VLT OTA features high robustness against Gm-C integrator to enhance the linear range. In addition,
the process. A Monte Carlo simulation with 1000 runs is the resistance divider is utilized as a pre-stage to further
performed, as shown in Fig. 8(b). The simulated gmVLT value improve the linearity performance.
is 45 pS with a standard deviation of only 0.3 pS. The active In the proposed design, Cin is set to 5 pF, while f clk is
area of the proposed VLT OTA is only 0.0055 mm2 . Com- set to 20 kHz. The equivalent input impedance is calculated
pared with the state-of-the-art series–parallel current-based as 5 M . A positive feedback loop as addressed in [16],
OTA design [25], the area consumption is reduced by a factor which can provide required current to the input switched-
of 27.3. capacitor resistor, is also integrated into the proposed work.
2260 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019

When ignoring the noise contributed from the second stage,

the IRN PSD of the two-stage OTA can be expressed as
2
i ni VT
v ni
2 =4 = 2kT 2 . (13)
(2gm )2 κ ID
According to (13), the complementary
√ input structure can
reduce the IRN by a factor of 2 while compared with one
without such a structure [10]. In this proposed design, the bias
current of the input pairs are√ set to 1 μA (2I D = 1 μA).
A theoretical IRN of 30 nV/ Hz is expected.

Fig. 10. Detailed schematic of the two-stage low-noise OTA in the chopper- C. Design of the DC Servo Loop
stabilized amplifier, which is labeled as gm1 and gm2 in Fig. 9.
The DSL integrates a very large time constant integra-
tor based on the active Gm-C structure, which is imple-
mented by the proposed VLT OTA as discussed earlier. The
The capacitance of C p f is set to 53 fF according to the post-
EDO cancellation range is directly determined by Chp as
layout simulation to eliminate the parasitic capacitor effect.
Thus, the differential input impedance is boosted to 440 M V D D Chp
VEDO = . (14)
at 50 Hz. Cin
The input capacitance Cin is set to 5 p F with a supply voltage
of 1.8 V. In order to achieve a maximum VEDO value up
B. Design of the Low-Noise Two-Stage OTA to 50 mV, according to (14), Chp should be at least 139 fF.
Fig. 10 shows the architecture of the low-noise two-stage A voltage divider shown in Fig. 11(a) is used as the input
Miller-compensated OTA. A pair of capacitors Cdc , as shown stage of the integrator to improve the linearity. The high-pass
in Fig. 9, is used to block the dc-offset, which may propagate frequency can then be calculated as
to the output ripple. A large resistor connected the input αChp gmVLT
and output of the first stage is used as a dc-feedback loop, f hp = (15)
2πC f b Cint
as well as to establish a stable dc bias for the input pairs [26].
To secure the stability, the Miller-compensated capacitor with where α is the voltage division factor. In this proposed design,
an adjusting zero resistor is employed. the voltage division factor of α is set to 0.8, while gmVLT
In the second stage, a back-to-back pseudoresistor is used to is 45 pS. A high-pass frequency corner of 0.4 Hz can be
bias the input pairs. It is important to note that the input swing achieved. With the voltage divider, the linear range can be
of the second stage is small enough to achieve high linearity. further enhanced from ±200 to ±250 mV. There is a tradeoff
Since the noise of the second stage is much smaller than between the linearity and the noise. In order to enable a higher
the first stage, the second stage can be biased to a relatively linear range, the noise will increase by a factor of 1/α.
low current for better power efficiency. However, the resistive The output of the DSL generates large spikes caused by
sensing scheme is employed for the CM feedback to improve the charge and discharge of the capacitor Chp when the EDO
the linearity. The bias current of the second stage must be high generated at the electrodes is quite large. These spikes cause
enough to meet the driving capability requirement. A tradeoff two problems: 1) the spikes pass from the output of the DSL
is performed to balance the power-efficiency requirement and to the output of the LNA. The spikes with an amplitude
the linearity requirement, and the bias current is set to 400 nA. of 500 mVpp can be observed at the output of the LNA
A complementary input-based OTA is used to double the according to simulation with an EDO of 50 mV and 2) the
effective transconductance without increasing the bias current. spikes at the DSL output can be kicked back to the input
√
The theoretical NEF limit can be reduced by a factor of 2. of gmDSL through the integral capacitor Cint due to which
Since the flicker noise of the two-stage OTA is removed from gmDSL may be unstable or even out of work. To solve this
the baseband due to the chopper structure, leaving only the problem, a bypass capacitor Cbp of 10 pF is connected to
thermal noise. For low-noise design, the input transistors are the DSL output to provide the current when charging and
biased in the deep subthreshold region. The transconductance discharging Chp . The bypass capacitor ensures that gmDSL
of a subthreshold MOSFET can be expressed as works properly and reduces the spikes at the output of LNA
to about 20 mVpp .
κ ID The bias current of gmVLT can be switched between two
gm ≈ (11)
VT modes. In the integrator mode, the bias current is 0.5 nA.
At this situation, the high-pass frequency corner is 0.4 Hz.
where I D is the drain current of the input transistor. The It will take a long time for the LNA to resume. To shorten the
current-noise power spectral density (PSD) of the subthreshold setting time, the bias current is switched to 100 nA to push the
MOSFET can be modeled as DSL working in the setting mode when the LNA is turned on.
1 Fig. 11(b) shows the schematic of the OTA used in DSL.
2 = 4kT
i ni gm . (12)
2κ A class-AB structure is used to enhance the driveability.
LUO et al.: LOW-NOISE CHOPPER AMPLIFIER DESIGNED FOR MULTI-CHANNEL NEURAL SIGNAL ACQUISITION 2261

Fig. 11. (a) Architecture of the dc servo loop based on the Gm-C structure. A voltage divider is used as the input stage of the integrator to improve the
linearity. (b) Schematic of the OTA gmDSL used in DSL. A class-AB structure is used.

The total current of gmDSL is only 200 nA, including the

CM feedback loop.
The setting mode may cause instability of the design. The
loop transfer function can be expressed as

2π AC f b f hp 1 + 2πsf h p
Ls =   (16)
sCin 1 + 2πsf p1 1 + 2πsf p2

where A is the dc gain of the two-stage OTA, as shown

in Fig. 10. f p1 and f p2 are the poles of the two-stage OTA.
A Miller compensation scheme is employed to realize an f p2
value much higher than f p1 , so as to reduce the correlation Fig. 12. Schematic of the proposed amplifier for noise calculation.
between f p2 and the circuit stability. A pole and a zero are
introduced by the DSL. In order to achieve a phase margin
of 60◦ , a relationship of is the high-pass corner of the amplifier. According to (18),
fhp < 2 f p1 (17) the ratio of the noise contribution to the IRN PSD between the
core OTA and gmDSL is equal to (Cin +C f b +Chp )/Chp 2 . Thus,
is expected. The simulated f p1 value is 170 Hz. A maximum the noise origins from gmDSL can be omitted when compared
f hp of 340 Hz is expected according to (17). The simulated f hp with the noise from the core OTA.
value in the integrator mode and the setting mode is 0.4 and Substituting (13) and (10) into (18), the total input-referred
180 Hz, respectively. Thus, a phase margin of nearly 90◦ can integrated noise from high-pass cutoff frequency fhp to the
be achieved in both the modes. low-pass filter cutoff frequency flp , which is typically 200 Hz
for the LFP signal recording and 5 kHz for the AP signal
D. Noise Analysis recording, can be calculated as follows:
A noise equivalent model is built to analyze the noise Vni,rms
performance, as shown in Fig. 12. The IRN PSD of the 
flp
chopper-stabilized amplifier is calculated using the output = v n,in
2 df
noise PSD divided by the mid-band gain as follows: fh p
 2 
 2
Cin + C f b + Chp 1 VT Cin + C f b + Chp kT VEDO
v n,in = v ni,core
2 2 = 2kT flp +
Cin 2π f κ 2 ID Cin Aαβκ V D D Cint
1 + Shp
 2 (20)
Chp 1
+ v ni,gmDSL
2
where A is the closed-loop gain of the chopper-stabilized
Cin 1 + 2π fh p
S amplifier, defined as A = Cin /C f p . According to (20),
⎛ ⎞2
the total input-referred integrated noise consists of two parts:
1 C 1
+ v ni,g
2 ⎝ f b ⎠ (18) 1) the thermal noise from the core OTA and 2) the noise
mVLT α Cin 1 + 2πSf associated with the EDO cancellation range, the supply volt-
hp
age, the closed-loop gain, the integration capacitance, and
where
the voltage division factor. It resources from the VLT OTA.
αgm Chp As mentioned earlier, a smaller voltage division factor α
fhp = (19)
2πCint C f b always leads to better linearity. However, according to (20),
2262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019

Fig. 13. Microphotography of the proposed chip, which has been fabricated in
a TSMC 180-nm CMOS process, occupying a silicon area of 2.6 mm×2 mm.

Fig. 15. (a) Comparison between the measured IRN (blue line) and the
theoretically derived noises calculated by (13) (green line) and (20) (red line).
(b) Input-referred peak-to-peak voltage noise in the frequency band
of 0.3–200 Hz. 4.5 μV is achieved. (c) Input-referred peak-to-peak voltage
noise in the frequency band of 200 Hz–5 kHz. 14 μV is achieved.

Fig. 14. (a) Measured frequency response of the fabricated chopper amplifier
with adjustable high-pass corner frequency. (b) High-pass corner frequency
versus the bias current.

Fig. 16. (a) Measured harmonic distortion of the amplifier for a 5-mVpp
a small voltage division factor may significantly increase the input at 5 Hz. (b) Measured harmonic distortion of the amplifier for a 5-mVpp
noise. A tradeoff between the noise performance and the input at 1 kHz.
linearity must be performed. For this application, VEDO and
VDD are set to 50 mV and 1.8 V, respectively. Thus, the closed-
loop gain A is set to 40 dB. The integration capacitor Cint
is set to 40 pF as a tradeoff between the area consumption
and the noise. The IRN resourced from the VLT OTA can be
calculated as 0.31 uVrms.

V. E XPERIMENTAL R ESULTS
The proposed work has been fabricated in the TSMC
180-nm CMOS process, occupying a silicon area of 2.6 mm×
2 mm. Fig. 13 shows the microphotography of the proposed Fig. 17. Measured THD versus electrode offset for a 5-mVpp input at 5 Hz
chip. The 16 integrated chips proposed low-noise chopper and 1 kHz separately.
amplifiers for the neural signal acquisition of 16 indepen-
dent channels. A programmable gain amplifier (PGA), an
SAR ADC, and an serial peripheral interface (SPI) encoder integrated noise is 0.65 and 2.14 μVrms in the frequency
are integrated as well for further signal amplifying, digitizing, band of 0.3–200 Hz and 0.2 k–5 kHz, respectively. An input-
and readout. referred peak-to-peak voltage noise of 4.5 μV (0.3–200 Hz)
During the bench test, the chopping clock frequency is set and 14 μV (0.2 k–5 kHz) are measured, as shown
to 20 kHz. The measured mid-band gain is 40 dB with a in Fig. 15(b) and (c), respectively.
high-pass cutoff frequency of 0.35 Hz and a low-pass cutoff Fig. 16 presents the harmonic distortion for a 5-mVpp input
frequency of 5.4 kHz, as shown in Fig. 14. at different frequencies. In the frequency band of 200–5 kHz,
The high-pass corner frequency can be precisely set and the THD is dominated by the core two-stage OTA, while DSL
linearly adjusted by tuning the bias current of the Gm-C dominates in the frequency band from near dc to 200 Hz.
integrator-based DSL. Fig. 15(a) compares the theoretical According to the experimental results, a THD of lower than
noise density derived from Section III with the measured −61 dB is achieved. Fig. 17 shows the measured THD versus
results. It clearly shows that the theoretical analysis and the electrode offset with a 5-mVpp input at 5 Hz and 1 kHz,
measured results perfectly match. According to Fig. 15(a), respectively. THD decreases slightly while the electrode offset
the DSL dominates the noise density in the low-frequency is increased, especially at the low-frequency band. Neural
band, and a noise corner frequency of 5.5√Hz is achieved. The signal acquisition suffers from CM interference (CMI). Thanks
input-referred thermal noise is 39 nV/ Hz. The measured to the chopping scheme, a high common-mode rejection ratio
LUO et al.: LOW-NOISE CHOPPER AMPLIFIER DESIGNED FOR MULTI-CHANNEL NEURAL SIGNAL ACQUISITION 2263

TABLE I
P ERFORMANCE AND C OMPARISON OF THE P ROPOSED N EURAL A MPLIFIERS

Fig. 18. Measured CMRR and PSRR.

Fig. 20. Raw data of the in vivo LFP recording.

Fig. 19. Time-domain response of a 50-mV step input in the integrator mode
and the setting mode, respectively.

(CMRR) can be achieved. The measured CMRR and power

supply rejection ratio (PSRR) are shown in Fig. 18. A CMRR
of 100 dB is achieved under a CMI of 200 mVpp .
To test the response time in the integrator mode and the
setting mode, a step input of 50 mV is performed, as shown
in Fig. 19. The response time in the integrator mode can be
larger than 10 s. While in the setting mode, less than 20 ms is
needed for a full setting, once the setting switch is trigged.
Fig. 20 shows the measured in vivo LFP without filtering
Fig. 21. Comparison with state-of-the-art AFE designs (see
recording from freely moving mice. [12], [21], [29]–[45]) of the input-referred rms noise versus the supply
Table I compares the proposed work with state-of-the- current of the amplifier.
art designs in the literature. Three different topologies of
AFEs were compared. The traditional CCIA structure features However, the input impedance is relatively small, and the
high input impedance and rail-to-rail EDO but suffers from bandwidth is limited. The chopper amplifiers are widely used
high flicker noise. The -based AFE designs feature high with low flicker noise and high CMRR. However, the tra-
area efficiency, high tolerance of large EDO, and low noise. ditional DSL structures used in chopper amplifiers introduce
2264 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019

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[34] S.-Y. Park, J. Cho, K. Na, and E. Yoon, “Modular 128-channel - Milin Zhang (S’06–M’11–SM’17) received the B.S.
analog front-end architecture using spectrum equalization scheme for and M.S. degrees in electronic engineering from
1024-channel 3-D neural recording microsystems,” IEEE J. Solid-State Tsinghua University, Beijing, China, in 2004 and
Circuits, vol. 53, no. 2, pp. 501–514, Feb. 2018. 2006, respectively, and the Ph.D. degree from the
[35] S.-Y. Park, J. Cho, and E. Yoon, “3.37 μW/Ch modular scalable Electronic and Computer Engineering Department,
neural recording system with embedded lossless compression for The Hong Kong University of Science and Technol-
dynamic power reduction,” in Proc. Symp. VLSI Circuits, Jun. 2017, ogy (HKUST), Hong Kong.
pp. C168–C169. She was a Post-Doctoral Researcher with the
[36] U. Ha et al., “A 25.2 mW EEG-NIRS multimodal SoC for accurate University of Pennsylvania, Philadelphia, PA, USA.
anesthesia depth monitoring,” in IEEE Int. Solid-State Circuits Conf. In 2016, she joined the Department of Electronic
(ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 450–451. Engineering, Tsinghua University, as an Assistant
[37] K. A. Ng and Y. P. Xu, “A multi-channel neural-recording amplifier Professor. Her research interests include designing traditional and various
system with 90 dB CMRR employing CMOS-inverter-based OTAS with nontraditional imaging sensors, such as polarization imaging sensors and
CMFB through supply rails in 65 nm CMOS,” in IEEE Int. Solid-State focal-plane compressive acquisition image sensors. She is also interested in
Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 1–3. analog and mixed-signal circuit designs oriented for various applications.
[38] H. Chandrakumar and D. Markovic, “A 2.8 μW 80 mVpp -linear-input- Dr. Zhang has been serving as a Technology Program Committee Member
range 1.6Gω-input impedance bio-signal chopper amplifier tolerant to of the IEEE Asian Solid-State Circuits Conference (A-SSCC) since 2019,
common-mode interference up to 650 mVpp ,” in IEEE Int. Solid-State the IEEE Custom Integrated Circuits Conference (CICC) since 2018, and the
Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 448–449. IEEE International Solid-State Circuits Conference Student Research Preview
[39] H. Chandrakumar and D. Marković, “A 2μW 40 mVpp linear- (ISSCC SRP) Committee. She received the Best Paper Award of the BioCAS
input-range chopper-stabilized bio-signal amplifier with boosted input Track of the 2014 International Symposium on Circuits and Systems (ISCAS)
impedance of 300 Mω and electrode-offset filtering,” in IEEE Int. and the Best Paper Award (first place) of the 2015 Biomedical Circuits and
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, Systems Conference (BioCAS).
pp. 96–97.
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[41] U. Ha and H.-J. Yoo, “An EEG-NIRS ear-module SoC for wearable Zhihua Wang (M’99–SM’04–F’17) received the
drowsiness monitoring system,” in Proc. IEEE Asian Solid-State Circuits B.S., M.S., and Ph.D. degrees in electronic engi-
Conf., Nov. 2016, pp. 193–196. neering from Tsinghua University, Beijing, China,
[42] W. A. Smith, J. P. Uehlin, S. I. Perlmutter, J. C. Rudell, and V. S. Sathe, in 1983, 1985, and 1990, respectively.
“A scalable, highly-multiplexed delta-encoded digital feedback ECoG He was a Visiting Scholar with Carnegie Mel-
recording amplifier with common and differential-mode artifact suppres- lon University, Pittsburgh, PA, USA, from 1992 to
sion,” in Proc. Symp. VLSI Circuits, Jun. 2017, pp. C172–C173. 1993 and Katholieke Universiteit Leuven, Leuven,
[43] S.-J. Kim, L. Liu, L. Yao, W. L. Goh, Y. Goh, and M. Je, “A 0.5-V Belgium, from 1993 to 1994. He has been serving
sub-μW/channel neural recording IC with delta-modulation-based spike as a Full Professor and the Deputy Director of the
detection,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2014, Institute of Microelectronics, Tsinghua University,
pp. 189–192. since 1997 and 2000, respectively. He was a Visiting
[44] U. Ha et al., “A wearable EEG-HEG-HRV multimodal system with real- Professor with The Hong Kong University of Science and Technology,
time tES monitoring for mental health management,” in IEEE Int. Solid- Hong Kong, from 2014 to 2015. He has coauthored 12 books/chapters,
State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 1–3. over 197 (514) papers in international journals (conferences), and over
[45] J. Xu et al., “A 0.6 V 3.8 μW ECG/bio-impedance monitoring IC for 246 (29) papers in Chinese journals (conferences). He holds 118 Chinese
disposable health patch in 40 nm CMOS,” in Proc. IEEE Custom Integr. and 9 U.S. patents. His current research mainly focuses on CMOS radio
Circuits Conf., Apr. 2018, pp. 1–4. frequency integrated circuit (RFIC) and biomedical applications, involving
radio frequency identification (RFID), phase-locked loop, low-power wireless
transceivers, and smart clinic equipment combined with leading-edge RFIC
and digital image processing techniques.
Dr. Wang has been a Steering Committee Member of the IEEE Asian
Deng Luo (S’16) received the B.S. degree in elec- Solid-State Circuits Conference (A-SSCC) since 2005. He served as the
tronic engineering from the Huazhong University of Chairman for the IEEE SSCS Beijing Chapter from 1999 to 2009, an AdCom
Science and Technology, Wuhan, China, in 2014. He Member of the IEEE Solid-State Circuits Society (SSCS) from 2016 to 2019,
is currently pursuing the Ph.D. degree with Tsinghua a Technology Program Committee Member of the IEEE International Solid-
University, Beijing, China, focusing on low-noise, State Circuits Conference from 2005 to 2011, the Technical Program Chair
low-power, and low-voltage analog circuit design. for A-SSCC 2013, a Guest Editor of the IEEE J OURNAL OF S OLID -S TATE
His research interests include analog and mixed- C IRCUITS special issues in 2006, 2009, and 2014, an Associate Editor of
signal circuit designs, especially for biomedical the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS I AND II and the
applications. IEEE T RANSACTIONS ON B IOMEDICAL C IRCUITS AND S YSTEMS , and other
administrative/expert committee positions in China’s national science and
technology projects.