MCQ – MICROPROCESSOR AND MICROCONTROLLER

1. The mnemonic that is placed before the arithmetic operation is performed is

a) AAA
b) AAS
c) AAM
d) AAD
View Answer

Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.

2. The Carry flag is undefined after performing the operation

a) AAA
b) ADC
c) AAM
d) AAD
View Answer

Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the
carry flag, auxiliary flag and overflow flag are undefined.

3. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
View Answer

Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is
not stored but flags are affected.

4. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
View Answer

Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into
LSB and the MSB of the operand is pushed into carry flag.
5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
View Answer

Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register
becomes zero. When CX becomes zero, the execution proceeds to the next instruction in
sequence.

6. Match the following

A) MOvSB/SW 1) loads AL/AX register by content of a string

B) CMPS 2) moves a string of bytes stored in source to destination
C) SCAS 3) compares two strings of bytes or words whose length is
stored in CX register
D) LODS 4) scans a string of bytes or words

a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
View Answer

Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.

7. The instructions that are used to call a subroutine from the main program and return to the
main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
View Answer

Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the
stack, before the control is transferred to the procedure. At the end of the procedure, the RET
instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.

8. The instruction that unconditionally transfers the control of execution to the specified address
is
a) CALL
b) JMP
c) RET
d) IRET
View Answer

Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are
not affected by this instruction.

9.Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
View Answer

Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the
‘halt’ state.

10. NOP instruction introduces

a) Address
b) Delay
c) Memory location
d) None of the mentioned
View Answer

Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the
clock cycle and thus there exists a delay.

11. Which of the following is not a machine controlled instruction?

a) HLT
b) CLC
c) LOCK
d) ESC
View Answer

Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry
Flag.

11. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
View Answer

Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears
in the form of successive byte or bytes.

12. The instruction, MOV AX, 1234H is an example of

a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
View Answer

Answer: c
Explanation: Since immediate data is present in the instruction.

13. The instruction, MOV AX, [2500H] is an example of

a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
View Answer

Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.

14. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
View Answer

Answer: b
Explanation: Since register is used to refer the address.

15. The instruction, MOV AX,[BX] is an example of

a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
View Answer

Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
16. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
View Answer

Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of
them, address is stored.

17. The addressing mode that is used in unconditional branch instructions is

a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
View Answer

Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a
register or a memory location.

18. If the location to which the control is to be transferred lies in a different segment other than
the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
View Answer

Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.

19. The instruction, JMP 5000H:2000H;

is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
View Answer

Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be
transferred is in a different segment.
20. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
View Answer

Answer: d
Explanation: The effective address is formed by adding the contents of both base and index
registers to a default segment.

21. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
View Answer

Answer: a
Explanation: These instructions are used to copy and transfer the instructions.

22. Which of the following is not a data copy/transfer instruction?

a) MOV
b) PUSH
c) DAS
d) POP
View Answer

Answer: c
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

23. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
View Answer

Answer: d
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.

24. Which of the following instruction is not valid?

a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
View Answer

Answer: b
Explanation: Both the source and destination operands cannot be memory locations except for
string instructions.

25. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: d
Explanation: The actual current stack-top is always occupied by the previously pushed data. So,
the push operation decrements SP by 2 and then stores the two bytes contents of the operand
onto the stack.

26. The instruction that pushes the contents of the specified register/memory location on to the
stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
View Answer

Answer: c
Explanation: Since PUSH operation transfers data to stack from a register or memory location.

27. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: c
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to by
SP are copied to AH & SP.

28. The instructions that are used for reading an input port and writing an output port
respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
View Answer

Answer: d
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address
is in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.

29. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
View Answer

Answer: b
Explanation: The translate(XLAT) instruction is used to find codes.

30. The instruction that loads effective address formed by destination operand into the specified
source register is
a) LEA
b) LDS
c) LES
d) LAHF
View Answer

Answer: a
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.

31. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
View Answer

Answer: c
Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe
the status of all the condition code flags(except overflow flag) at a time.
32. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer

Answer: c
Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.
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33. The instruction that loads the flag register completely from the word contents of the memory
location is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer

Answer: d
Explanation: POPF is pop flags to stack.

34. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
View Answer

Answer: b
Explanation: ADD instruction adds the data.

35. The instruction that supports addition when carry exists is

a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
View Answer

Answer: b
Explanation: ADC(Add with Carry) instruction performs the same operation as ADD operation,
but adds the carry flag bit to the result.
36. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
View Answer

Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.

37. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
View Answer

Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory
location by 1.

38. The instruction that enables subtraction with borrow is

a) DEC
b) SUB
c) SBB
d) None of the mentioned
View Answer

Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.

39. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
View Answer

Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.

40. In general, the source operand of an instruction can be

a) memory location
b) register
c) immediate data
d) all of the mentioned
View Answer

Answer: d
Explanation: The source operand is the element which is data or data stored memory location on
which operation is performed.

41. In general, the destination operand of an instruction can be

a) memory location
b) register
c) immediate data
d) memory location and register
View Answer

Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.

42. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
View Answer

Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.

43. During comparison operation, the result of comparing or subtraction is stored in

a) memory
b) registers
c) stack
d) no where
View Answer

Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.

44. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
View Answer
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are
called as “Unpacked BCD arithmetic instructions”.

45. Which of the following is a mnemonic?

a) ADD
b) ADC
c) AAA
d) ADD & ADC
View Answer

Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

46. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
View Answer

Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits.

47. The expansion of DAA is

a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
View Answer

Answer: c
Explanation: This instruction performs conversion operation.
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48. The instruction that is used to convert the result of the addition of two packed BCD numbers
to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
View Answer

Answer: a
Explanation: In this conversion, the result has to be only in AL.
49. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
View Answer

Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.

50. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
View Answer

Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is
not stored but flags are affected.

51. The assembler directives which are the hints using some predefined alphabetical strings are
given to
a) processor
b) memory
c) assembler
d) processor & assembler
View Answer

Answer: c
Explanation: These directives help the assembler to correctly understand the assembly language
programs to prepare the codes.

52. The directive used to inform the assembler, the names of the logical segments to be assumed
for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
View Answer

Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.

53. Match the following

a) DB 1) used to direct the assembler to reserve only 10-bytes

b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1

b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
View Answer

Answer: d
Explanation: These directives are used for allocating memory locations in the available memory.

54. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer

Answer: b
Explanation: The directive END is used to denote the completion of the program.

55. The directive that marks the end of a logical segment is

a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer

Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is used to
end the program.

56. The directive that updates the location counter to the next even address while executing a
series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
View Answer
Answer: b
Explanation: The directive updates location counter to next even address if the current location
counter contents are not even.

57. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
View Answer

Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.

58. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
View Answer

Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.
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59. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
View Answer

Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.

60. The labels or constants that can be used by any module in the program is possible when they
are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
View Answer
Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by
any module in the program.

61. The Stack follows the sequence

a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
View Answer

Answer: c
Explanation: The stack follows last-in-first-out sequence.

62. If the processor is executing the main program that calls a subroutine, then after executing
the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
View Answer

Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.

63. The stack is useful for

a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
View Answer

Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory locations,
status of registers.

64. The Stack is accessed using

a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
View Answer

Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS registers.
65. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.

66. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
View Answer

Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At that
time, the stack pointer is incremented by 2.

67. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
View Answer

Answer: c
Explanation: The data is pushed into the stack while loading the stack.

68. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
View Answer

Answer: d
Explanation: The data retrieved from stack is called popping off.

69. The books arranged one on the other on a table is an example of

a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
View Answer

Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will be
the first out.

70. The PID temperature controller using 8086 has

a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
View Answer

Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving control
signals and applying the control signal to control flow of energy.

71. While CPU is executing a program, an interrupt exists then it

a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
View Answer

Answer: c
Explanation: An interrupt function is to break the sequence of operation.

72. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
View Answer

Answer: a
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing
ISR, the control is transferred back again to the main program.

73. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
View Answer

Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing the
interrupt, if one more interrupt occurs again, then it is called a nested interrupt.

74. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
View Answer

Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.

75. NMI stands for

a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
View Answer

Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.

77. If any interrupt request given to an input pin cannot be disabled by any means then the input
pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
View Answer

Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at
NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.

78. The INTR interrupt may be

a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
View Answer

Answer: a
Explanation: the INTR (interrupt request) is maskable or can be disabled.
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79. The Programmable interrupt controller is required to

a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
View Answer

Answer: b
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip
called programmable interrupt controller is required to handle them.

80. The INTR interrupt may be masked using the flag

a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
View Answer

Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If
interrupt flag, IF=0, then the processor ignores the service.

81. If a number of instructions are repeating through the main program, then to reduce the length
of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
View Answer

Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when
macro is defined then the code of a program is reduced by placing the name of the macro at
which the set of instructions are needed to be repeated.

82. The process of assigning a label or macroname to the string is called

a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
View Answer

Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.

83. A macro within a macro is called

a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
View Answer

Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.

84. A macro can be defined as

a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
View Answer

Answer: d
Explanation: A macro can be defined anywhere in a program.

85. A macro can be used as ________

a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
View Answer

Answer: d
Explanation: A macro may be used in data segment and can also be used to represent statements
and directives.

86. The end of a macro can be represented by the directive.

a) END
b) ENDS
c) ENDM
d) ENDD
View Answer
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.

87. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
View Answer

Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the program,
is known as calling a macro.

88. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
View Answer

Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does
not contain CALL and RET instructions as the procedures do.

89. Which of the following statements is incorrect?

a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
View Answer

Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.

90. The beginning of the macro can be represented as

a) START
b) BEGIN
c) MACRO
d) None of the mentioned
View Answer

Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive
MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.

91. In the I/O mode, the 8255 ports work as

a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
View Answer

Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.

92. In BSR mode, only port C can be used to

a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
View Answer

Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port
bits.

93. The feature of mode 0 is

a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
View Answer

Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.

94. The strobed input/output mode is another name of

a) mode 0
b) mode 1
c) mode 2
d) none
View Answer

Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.
95. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
View Answer

Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded
into input latches.

96. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
View Answer

Answer: c
Explanation: This signal indicates that the printer is selected.

97. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
View Answer

Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.

98. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
View Answer

Answer: d
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
the Paper end state, Offline state and Error state.

99. The signals that are provided to maintain proper data flow and synchronization between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
View Answer

Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.

100. The feature of mode 2 of 8255 is

a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
View Answer

Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.

101. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the
active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
View Answer

Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.

102. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
View Answer

Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.

103. The procedure of algorithm for interfacing ADC contain

a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
View Answer

Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end
of a conversion process, reading digital data output of ADC as equivalent digital output.

104. Which is the ADC among the following?

a) AD 7523
b) 74373
c) 74245
d) ICL7109
View Answer

Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is
transceiver and ICL7109 is an ADC.

105. The conversion delay in a successive approximation of an ADC 0808/0809 is

a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
View Answer

Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.

106. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
View Answer

Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.

107. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
View Answer

Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.

108. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
View Answer

Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three phases
of total conversion cycle.

109. Which of the following phase contain feedback loop in it?

a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
View Answer

Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.

110. In the signal integrate phase, the differential input voltage between IN LO(input low) and
IN HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
View Answer

Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.

111. DAC (Digital to Analog Converter) finds application in

a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
View Answer

Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.

112. To save the DAC from negative transients the device connected between OUT1 and OUT2
of AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)
View Answer

Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.

113. An operational amplifier connected to the output of AD 7523 is used

a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
View Answer

Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert the
current output to output voltage and also provides additional driving capability to the DAC.

114. The DAC 0800 has a settling time of

a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
View Answer

Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.

115. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
View Answer

Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.

116. The internal schematic of a typical stepper motor has

a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
View Answer

Answer: d
Explanation: The internal schematic of a typical stepper motor has 4 windings.

117. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
View Answer

Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.

118. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
View Answer

Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.

119. The firing angles of thyristors are controlled by

a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
View Answer
Answer: d
Explanation: In early days, the firing angles were controlled by a pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.

120. The Isolation transformers are generally used for

a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
View Answer

Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary.

121. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.

122. The operation that can be performed on control word register is

a) read operation
b) write operation
c) read and write operations
d) none
View Answer

Answer: b
Explanation: The control word register can only be written and cannot be read.

123. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
View Answer

Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
124. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low
for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
View Answer

Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is
reloaded and again the output becomes high and remains so for (N-1) clock pulses.

125. The generation of a square wave is possible in the mode

a) mode 1
b) mode 2
c) mode 3
d) mode 4
View Answer

Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains
high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse
decrements it by 1 resulting in an even count value.

126. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
View Answer

Answer: b
Explanation: SC denotes select counter.

127. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
View Answer

Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

128. If BCD=0, then the operation is

a) decimal count
b) hexadecimal count
c) binary count
d) octal count
View Answer

Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

129. The counter starts counting only if

a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
View Answer

Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

130. The control word register contents are used for

a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
View Answer

Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.

131. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer

Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins
were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an
external device was supposed to hand over the type of the interrupt to the microprocessor.
132. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
View Answer

Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register
internally.

133. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
View Answer

Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the
direction of the Priority Resolver.

134. The interrupt control logic

a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
View Answer

Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the
interrupts like accepting and managing interrupt acknowledge signals, interrupts.

135. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4
b) 8
c) 16
d) 64
View Answer

Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored
interrupts can be provided.
136. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can
be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
View Answer

Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to
control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to
designate whether the chip is used as a master or a slave.

137. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
View Answer

Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
advertisement

138. When non-specific EOI command is issued to 8259A it will automatically

a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
View Answer

Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the
highest ISR.

139. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
View Answer
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices
are of equal priority.

140.The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
View Answer

Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.

141. The registers that store the keyboard and display modes and operations programmed by
CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
View Answer

Answer: b
Explanation: The control and timing register to store the keyboard and display modes and other
operations programmed by CPU.

142. The sensor RAM acts as 8-byte first-in-first-out RAM in

a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
View Answer

Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.

143. The registers that hold the address of the word currently being written by the CPU from the
display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
View Answer
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.

144. When a key is pressed, a debounce logic comes into operation in

a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
View Answer

Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.

145. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
View Answer

Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.

146. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
View Answer

Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard
scans and then checks whether the key is still depressed. If it is still depressed, the code is
entered in FIFO RAM.

147. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
View Answer
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode, as
in a type-writer the first character typed appears at the left-most position, while the subsequent
characters appear successively to the right of the first one.

148. The FIFO status word is used to indicate the error in

a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
View Answer

Answer: c
Explanation: Overrun error occurs when an already full FIFO has attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.

149. The flag that increments automatically after each read or write operation to the display
RAM is
a) IF
b) RF
c) AI
d) WF
View Answer

Answer: c
Explanation: AI refers to auto increment flag.

150. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ
line
a) goes low
b) goes high
c) remains unchanged
d) none
View Answer

Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by
the CPU.

161. Which of the following is not a mode of data transmission?

a) simplex
b) duplex
c) semi duplex
d) half duplex
View Answer

Answer: c
Explanation: Basically, there are three modes of data transmission. simplex, duplex and half
duplex.

162. If the data is transmitted only in one direction over a single communication channel, then it
is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
View Answer

Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For example, a CPU may
transmit data for a CRT display unit in this mode.

163. If the data transmission takes place in either direction, but at a time data may be transmitted
only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
View Answer

Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a time. For
example, Walkie-Talkie.

164. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
View Answer

Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the rate at which
the character is to be transmitted.

165. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data bits along
with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
View Answer

Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the transmitted data bits
along with other information like start bits, stop bits and parity bits etc.

166. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
View Answer

Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the CPU or polled
by the CPU.

167. The disadvantage of RS-232C is

a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
View Answer

Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like limited speed of
communication, high-voltage level signaling and big-size communication adapters.

168. The USB supports the signaling rate of

a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
View Answer

Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.

169. The bit packet that commands the device either to receive data or transmit data in
transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
View Answer

Answer: b
Explanation: The token packet is the second type of packet which commands the device either to
receive data or transmit data.

170. High speed USB devices neglect

a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
View Answer

Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.

171. The 8257 is able to accomplish the operation of

a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned
View Answer

Answer: d
Explanation: The 8257 can accomplish three types of operations and they are
i) verify DMA operation
ii) write operation
iii) read operation.

172. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned
View Answer

Answer: b
Explanation: If the HLDA signal is received by the DMA controller, it indicates that the bus is
available.

173. To indicate the I/O device that its request for the DMA transfer has been honored by the
CPU, the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK (active low)
d) DACK (active high)
View Answer

Answer: c
Explanation: The DACK (active low) line of the used channel is pulled down by the DMA
controller to indicate the I/O device that its request for the DMA transfer has been honored by
the CPU.

174. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned
View Answer

Answer: c
Explanation: If more than one channel requests service simultaneously, then the transfer occurs
as a burst or continuous transfer.

175. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK (active low)
c) DACK (active high)
d) HLDA
View Answer

176. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned
View Answer

Answer: b
Explanation: The 8257 uses four clock cycles to complete a transfer.

177. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to
be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer
Answer: b
Explanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1.
The DRQ0 has the highest priority.

178. The priority of the channels varies frequently in

a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer

Answer: a
Explanation: In this scheme, the priorities assigned to the channels are not fixed.

179. The register of 8257 that can only be written in is

a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register
View Answer

Answer: c
Explanation: The selected register may be read or written depending on the instruction executed
by the CPU. But only write operation can be performed on the mode set register.

180. The operation that can be performed on the status register is

a) write operation
b) read operation
c) read and write operations
d) none of the mentioned
View Answer

Answer: b
Explanation: The status register can only be read.

181. The register that may be used as an operand register is

a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
View Answer

Answer: d
Explanation: In some instructions, the Accumulator and B register are used to store the operands.
182. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
View Answer

Answer: b
Explanation: B register is used to store one of the operands for multiply and divide instructions.
In other instructions, it may just be used as a scratch pad.

183. The registers that contain the status information is

a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
View Answer

Answer: c
Explanation: The set of flags of program status word contains the status information and is
considered as one of the special function registers.

184. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
View Answer

Answer: c
Explanation: The 8051 stack is not a top-down data structure, like other Intel processors.

185. The architecture of 8051 consists of

a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
View Answer

Answer: d
Explanation: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each of
the four on-chip I/O ports. It contains two 16-bit timer registers.

186. The transmit buffer of serial data buffer is a

a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
View Answer

Answer: b
Explanation: The transmit buffer of serial data buffer is a parallel-in serial-out register.

187. The receive buffer of serial data buffer is a

a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
View Answer

Answer: a
Explanation: The serial data register has two buffers. The transmit buffer is a parallel-in serial-
out register and receive buffer is a parallel-in serial-out register.

188. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
View Answer

Answer: b
Explanation: The registers, TMOD and TCON contain control and status information about
timers/counters.

189. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON
View Answer

Answer: d
Explanation: The registers, PCON and SCON contain control and status information about serial
port.

190. The device that generates the basic timing clock signal for the operation of the circuit using
crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
View Answer

Answer: c
Explanation: The oscillator circuit generates the basic timing clock signal for the operation of the
circuit using crystal oscillator.

191. Which of the following is an 8-bit register?

a) PSW(Program Status Word)
b) TCON(Timer Control Register)
c) Accumulator
d) All of the mentioned
View Answer

Answer: d
Explanation: The registers, PSW, TCON and Accumulator are 8-bit registers.

192. Which of the following register can be addressed as a byte?

a) P1
b) SCON
c) TMOD
d) TCON
View Answer

Answer: c
Explanation: The registers, TMOD, SP, TH0, TH1, TL0, TL1 are to be addressed as bytes.

193. Which of the following is bit-addressable register?

a) SBUF
b) PCON
c) TMOD
d) SCON
View Answer

Answer: d
Explanation: The registers, accumulator, PSW, B, P0, P1, P2, P3, IP, IE, TCON and SCON are
all bit-addressable registers.

194. The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP
View Answer
Answer: c
Explanation: The registers, DPH and DPL are the higher and lower bytes of a 16-bit register
DPTR.

195. The register that is used for accessing external data memory is
a) DPH
b) DPL
c) DPTR
d) NONE
View Answer

Answer: c
Explanation: The Data Pointer(DPTR) is used for accessing external data memory which means
that it includes both DPH and DPL.

196. Among the four groups of register banks, the number of groups that can be accessed at a
time is
a) 1
b) 2
c) 3
d) all the four
View Answer

Answer: a
Explanation: At a time, only one of the four register banks can be accessed.

197. The number of 8-bit registers that a register bank contain is

a) 2
b) 4
c) 6
d) 8
View Answer

Answer: d
Explanation: The 32, 8-bit registers are divided into four groups of 8 registers each, called
register banks.

198. If RS1=1, RS0=0, then the register bank selected is

a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
View Answer

Answer: c
Explanation: If RS1=1, RS0=0, then the register bank selected is register bank 2.
199. If RS1=1, RS0=1, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
View Answer

Answer: d
Explanation: If RS1=1, RS0=1, then the register bank selected is register bank 3. If RS1=0,
RS0=0, then selected bank is register bank 0.

200. The PCON register consists of

a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit
View Answer

Answer: d
Explanation: The power control register, PCON consists of power down bit and idle bit which
activate the power down mode and idle mode in 80C51BH.

201. The on-chip oscillator is stopped in

a) power mode
b) power down mode
c) idle mode
d) ideal mode
View Answer

Answer: b
Explanation: In power down mode, the on-chip oscillator is stopped.

202. In idle mode, the device that is disabled is

a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned
View Answer

Answer: c
Explanation: In idle mode, the oscillator continues to run and the interrupt, serial port and timer
blocks are active but the clock to the CPU is disabled.
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203. The only way to terminate the power down mode is to

a) CLEAR
b) RESET
c) HOLD
d) HLT
View Answer

Answer: b
Explanation: The only way to terminate the power down mode is hardware reset. The reset
redefines all the SFRs but the RAM contents are left unchanged.

204. The idle mode can be terminated by

a) PRESET
b) CLEAR
c) Interrupt
d) Interrupt or reset
View Answer

Answer: d
Explanation: The idle mode can be terminated with a hardware interrupt or hardware reset signal.

205. Which of the following is not an addressing mode of 8051?

a) register instructions
b) register specific instructions
c) indexed addressing
d) none
View Answer

Answer: d
Explanation: The six addressing modes of 8051 are
1. Direct addressing
2. Indirect addressing
3. Register instructions
4. Register specific(Register Implicit) instructions
5. Immediate mode
6. Indexed addressing.

206. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to
specify the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump
View Answer

Answer: c
Explanation: The symbol, ‘addr 16’ represents the 16-bit destination address which is used by
the LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes
program memory.

207. The storage of addresses that can be directly accessed is

a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS
View Answer

Answer: c
Explanation: Only internal data RAM and SFRS can be directly addressed in direct addressing
mode.

208. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
View Answer

Answer: b
Explanation: The address register for storing the 16-bit addresses can only be data pointer.

209. The address register for storing the 8-bit addresses can be
a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
View Answer

Answer: d
Explanation: The registers R0 and R1 of the selected bank of registers or stack pointer can be
used as address registers for storing the 8-bit addresses.

210. The instruction, ADD A, R7 is an example of

a) register instructions
b) register specific instructions
c) indexed addressing
d) none
View Answer

Answer: a
Explanation: In register instructions addressing mode, operands are stored in the registers R0-R7
of the selected register bank. One of these registers is specified in the instruction.
211. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
View Answer

Answer: b
Explanation: In register specific instructions addressing mode, the instructions don’t have source
and destination operands. Some of the instructions always operate only on a specific register.

212. The instruction, RLA performs

a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
View Answer

Answer: b
Explanation: The instruction, RLA rotates accumulator left.

213. The instruction, ADD A, #100 performs

a) 100(decimal) is added to contents of address register
b) 100(decimal) is subtracted from the accumulator
c) 100(decimal) is added to contents of an accumulator
d) none
View Answer

Answer: c
Explanation: Immediate data 100(decimal) is added to the contents of the accumulator.

214. In which of these addressing modes, a constant is specified in the instruction, after the
opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
View Answer

Answer: d
Explanation: In immediate mode, an immediate data, i.e. a constant is specified in the
instruction, after the opcode byte.
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215. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
View Answer

Answer: d
Explanation: Only program memory can be accessed using the indexed addressing mode.

216. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
View Answer

Answer: b
Explanation: The look-up table data address is found out by adding the contents of register
accumulator with that of the program counter or data pointer.

217. Which of the following is not an instruction of 8051 instructions?

a) arithmetic instructions
b) boolean instructions
c) logical instructions
d) none
View Answer

Answer: d
Explanation: The 8051 instructions are categorized as
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Boolean instructions
5. Control transfer instructions.

218. The operations performed by data transfer instructions are on

a) bit data
b) byte data
c) 16-bit data
d) all of the mentioned
View Answer

Answer: d
Explanation: The data transfer instructions implement a bit, byte, 16-bit data transfer operations
between the SRC(source) and DST(destination) operands.
219. Which of the following is true while executing data transfer instructions?
a) program counter is not accessible
b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned
View Answer

Answer: c
Explanation: In data transfer instructions,
1. Program counter is not accessible.
2. Restricted bit-transfer operations are allowed.
3. Both operands can be direct/indirect register operands.
4. BOth operands can be internal direct data memory operands.

220. The logical instruction that affects the carry flag during its execution is
a) XRL A;
b) ANL A;
c) ORL A;
d) RLC A;
View Answer

Answer: d
Explanation: The logical instructions that doesn’t affect the carry flag are, ANL, ORL and XRL.
The logical instructions that affect the carry flag during its execution are RL, RLC, RRC and RR.

221. The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit
View Answer

Answer: c
Explanation: The instruction, CPL Bit is used to complement or invert the bit of a bit addressable
SFR or RAM.

222. The instructions that change the sequence of execution are

a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions
View Answer

Answer: c
Explanation: The control transfer instructions transfer the control of execution or change the
sequence of execution conditionally or unconditionally.
223. The control transfer instructions are divided into
a) explicit and implicit control transfer instructions
b) conditional and unconditional control transfer instructions
c) auto control and self control transfer instructions
d) all of the mentioned
View Answer

Answer: b
Explanation: The control transfer instructions are divided into conditional and unconditional
control transfer instructions.

224. The conditional control transfer instructions check a bit condition which includes any bit of
a) bit addressable RAM
b) bit addressable SFRs
c) content of accumulator
d) all of the mentioned
View Answer

Answer: d
Explanation: The conditional control transfer instructions check a bit condition which includes
any bit of bit addressable RAM or bit addressable SFRs or content of accumulator for
transferring the control to the specified jump location.

225. All conditional jumps are

a) absolute jumps
b) long jumps
c) short jumps
d) none
View Answer

Answer: c
Explanation: All conditional jumps are short jumps.

226. The first byte of a short jump instruction represents

a) opcode byte
b) relative address
c) opcode field
d) none
View Answer

Answer: a
Explanation: The short jump instruction has two byte instruction. The first byte represents
opcode byte and second byte represents an 8-bit relative address.
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227. In logical instructions, the immediate data can be an operand for

a) increment operation
b) decrement operation
c) single operand instruction
d) none
View Answer

Answer: d
Explanation: In logical instructions, the immediate data can’t be an operand for
increment/decrement or any other single operand instruction.

228. The serial communication is

a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned
View Answer

Answer: d
Explanation: The serial communication requires less number of conductors and thus it is cheaper.
It is slow as the bits are transmitted one by one along with start, stop and parity bits.

229. The serial communication is used for

a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
View Answer

Answer: b
Explanation: Serial communication is more popular for communication over longer distances as
it requires less number of conductors.

230. The mcs 51 architecture supports

a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
View Answer

Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and reception of
binary data byte by byte i.e. full duplex mode of communication. It supports serial transmission
and reception of data using standard serial communication interface and baud rates.

231. The number of bits transmitted or received per second is defined as

a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
View Answer

Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted or received per
second.

232. The task of converting the byte into serial form and transmitting it bit by bit along with
start, stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned
View Answer

Answer: c
Explanation: the serial communication unit consists of transmission unit and reception unit. The
task of converting the byte into serial form and transmitting it bit by bit along with start, stop and
parity bits is carried out by transmission unit.

233. The transmission unit does not require assistance from processor if once a byte for
transmission is written to
a) SCON register
b) SBUF register
c) SFR address
d) Any of the mentioned
View Answer

Answer: b
Explanation: once a byte for transmission is written to the serial buffer(SBUF) register, the
transmission unit does not require assistance from a processor.

234. The common unit shared by the receiver unit and transmission unit of serial communication
unit is
a) SCON(Serial Port Control) Register
b) SBUF(Serial Buffer) register
c) 8-bit serial data interface
d) All of the mentioned
View Answer

Answer: d
Explanation: The transmission unit and receiver unit both are controlled by using a common
SCON(Serial Port Control) Register. Also both units share a common serial buffer(SBUF)
register which is a common 8-bit serial data interface.
235. During serial reception, the buffer that receives serial bits and converts to a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none
View Answer

Answer: b
Explanation: During serial reception, the receive buffer 1 receives serial bits and converts to a
byte, it then transfers the received parallel byte in receive buffer 2.

236. If SM0=1, SM1=0, then the transceiver selected is

a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous
View Answer

Answer: d
Explanation: If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is selected.

237. If the microcontroller is expected to communicate in a multiprocessor system, then the

required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
View Answer

Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to communicate in a
multiprocessor system.
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238. In mode 2, the baud rate depends only on

a) SMOD bit
b) SCON bit
c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency
View Answer

Answer: d
Explanation: In mode 2, the baud rate depends only on SMOD bit and oscillator clock frequency.

239. The mode that offers the most secured parity enabled data communication at lower baud
rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
View Answer

Answer: a
Explanation: The mode 3 offers the most secured parity enabled data communication at lower
baud rates of mode 1.

240. The power control register is

a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned
View Answer

Answer: d
Explanation: The power control register is used for power saving during idle state of the
microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is
used to double the baud rate.

241. The state of signals in idle mode is

a) ALE is high
b) PSEN is high
c) PSEN(active low) is high
d) ALE and PSEN(active low) are high
View Answer

Answer: d
Explanation: ALE and PSEN(active low) remain high in Idle mode.

242. To come out of idle mode, the external interrupt that is enabled is
a) SI(serial)
b) INT0
c) INT1
d) All of the mentioned
View Answer

Answer: d
Explanation: To come out of idle mode, any external interrupt that is enabled like SI(Serial),
INT0 and INT1.

243. The microcontroller enters into power down mode when

a) SMOD bit of PCON is set
b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set
View Answer

Answer: c
Explanation: If the PD bit of PCON register is set, it enters power down mode.

244. The clock signal is disabled to all parts of 8051 in

a) normal mode
b) idle mode
c) power down mode
d) addressing mode
View Answer

Answer: c
Explanation: In power down mode, the clock signal to all parts of 8051 chip is disabled.

245. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt
View Answer

Answer: b
Explanation: The supply voltage can be reduced to a value of around 2 volts, during power down
to save battery.

246. The signal that only pulls the microcontroller(8051) out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT
View Answer

Answer: c
Explanation: Only Reset signal can pull 8051 out of the power down mode.

247. The state of signals in power down mode is

a) ALE is high
b) PSEN is low
c) ALE and PSEN(active low) are high
d) ALE and PSEN(active low) are low
View Answer
Answer: d
Explanation: ALE and PSEN(active low) remain low in power down mode of 8051.

248. In power down mode,

a) Port pins maintain their logic levels
b) SFRs maintain their logic levels
c) Clock signal is disabled
d) All of the mentioned
View Answer

Answer: d
Explanation: In power down mode, the clock signal is disabled and all the port pins and
respective SFRs maintain their logic levels.

249. The SMOD bit is used to

a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate
View Answer

Answer: c
Explanation: The SMOD bit is used to double the baud rate.

250. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
View Answer

Answer: d
Explanation: The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H
respectively.