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Lab - 10 - Sequence Detector Using FSM

This document provides instructions for an experiment to design and implement a Mealy finite state machine to detect a 1011 bit sequence using an FPGA. The experiment aims to understand Mealy FSM design. It explains Moore and Mealy machines, with Mealy machines having outputs dependent on present state and inputs. The task is to design a Mealy FSM state transition graph and top level module to detect the 1011 sequence from most to least significant bit on the FPGA pins specified.

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Talha Khalid
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195 views

Lab - 10 - Sequence Detector Using FSM

This document provides instructions for an experiment to design and implement a Mealy finite state machine to detect a 1011 bit sequence using an FPGA. The experiment aims to understand Mealy FSM design. It explains Moore and Mealy machines, with Mealy machines having outputs dependent on present state and inputs. The task is to design a Mealy FSM state transition graph and top level module to detect the 1011 sequence from most to least significant bit on the FPGA pins specified.

Uploaded by

Talha Khalid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 10: Sequence Detector Using FSM

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L)


Sequence Detector Using FSM
1. Objective
This lab exercise is designed to understand the design and then implement the Mealy Finite State
Machine (FSM) to detector 1011 sequence on FPGA.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 2 or Spartan 3E board

3. Introduction
The finite state machines are critical for realizing the control and decision making logic in the
digital systems. The sequential logic that implements FSM can be in only a fixed number of states.
In the finite state machines, the outputs and the next state is a function of the input and the present
state. This means that the choice of the next state can depend on the value of an input and might
lead to more complex behavior of the system. Since in sequential logic we need the past history of
inputs to determine the output hence finite state machine prove very helpful in realizing sequential
logic functions.
There are basically two ways in which we can organize a sequential design. These are the Moore
machine and Mealy machine design implementation which is discussed below.

3.1 Moore Machine:


In the Moore machines, the outputs depend only on the present state. This basically means that the
inputs and the present state are mapped into flip-flop inputs to store the appropriate next state. The
inputs to the logic block that computes the outputs for these machines is then the output states of
the flip-flop. Hence with such a design, whenever there is a state change in response to a clock
edge there is a corresponding change in the output. This means that the outputs are synchronous
with the state change and the clock edge.

3.2 Mealy Machine:


Unlike the Moore machine, in a Mealy machine the outputs depend on the present state as well as
the current value of the inputs. Hence the inputs to the logic block that computes the outputs for a
Mealy machine, would be state outputs from flip-flop and also the present value of the inputs. This
means that any change in the value of the input independent of the clock edge would be reflected
in the outputs. Thus a Mealy machine is said to have asynchronous outputs.

Digital System Design Lab (EE-319L)


4 Lab Task:
Implement a Mealy FSM which can detect 1011 sequence (Starting from MSB to LSB).

State Transition Graph to detect 1011 sequence by using Mealy Machine

Top level module implementation

Spartan 3E Pinouts:

In L13
Clk C9
Clr L14
ClkOut E12
Out F12

Digital System Design Lab (EE-319L)

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