NXP Semiconductors Document Number: MMDS36254H

Technical Data Rev. 0, 01/2018

Advanced Doherty Alignment

Module (ADAM) MMDS36254HT1
The MMDS36254H is an integrated module designed for use in base station
transmitters in conjunction with high power Doherty amplifiers. The device is
designed to enable accurate alignment of phase and amplitude on the carrier 3400–3800 MHz
and peaking amplifiers to ensure performance consistency, in particular for ADAM – ADVANCED DOHERTY
asymmetric implementations. The MMDS36254H enables superior linearity-- ALIGNMENT MODULE
efficiency trade--off while improving output power. It contains a 90 coupler,
digitally selectable phase shifters and step attenuators, and operates from a
single voltage supply. The MMDS36254H is suitable for transmit protocols such
as W--CDMA, UMTS and LTE using frequencies from 3400 to 3800 MHz, and is
controlled using a serial peripheral interface (SPI).
Features
 Frequency: 3400–3800 MHz
QFN 6  6
 Maximum RF Input Power: 25 dBm (CW)
 Low Loss Power Splitter
 0.25 dB Step Programmable Attenuators with 7.75 dB Maximum Range
 6.5 per Bit Phase Shifters with 45.5 Maximum Range
 Power up into a Selectable State
 Single 5 Volt Supply
 Supply Current: 10 mA
 50 Ohm Operation (no external matching required)
 TTL/CMOS/SPI Interface (1.8 V, 3.3 V Logic)
 Cost--effective 32--pin, 6 mm QFN Surface Mount Plastic Package

0
 RFout2

0 to –45.5 0 to 7.75 dB
RFin
0 to –45.5 0 to 7.75 dB

 RFout1
–90

SERIAL DIGITAL INTERFACE

SDI SCLK LCLK SDO PUP LEN VDD BYP GND

Figure 1. Functional Block Diagram

 2018 NXP B.V. MMDS36254HT1

RF Device Data
NXP Semiconductors 1
Table 1. Maximum Ratings
Rating Symbol Value Unit
Supply Voltage VDD 6 V
Logic Inputs (SCLK, LCLK, LEN, PUP, SDI) Vin –0.5 to +3.63 V
RF Input Power (CW) Pin 25 dBm
Storage Temperature Range Tstg –65 to +150 C
Junction Temperature TJ 150 C

Table 2. Recommended Operating Conditions

Characteristic Symbol Min Max Unit
Supply Voltage VDD 4.5 5.5 V
DC Input Voltage (SCLK, LCLK, LEN, SDI) Vin 0 3.3 V

Table 3. Electrical Characteristics (VDD = 5 Vdc, 3600 MHz, TA = 25C, 50 ohm system, in NXP Application Circuit)
Characteristic Symbol Min Typ Max Unit
Insertion Loss (Includes 3 dB power division and 2.5 dB loss) IL — 6.5 — dB
Max Transition Time (Rising Edge of LCLK to RFout) ttransition — 350 — ns
Power Input @ 1dB Compression P1dB — 39 — dBm
Supply Current IDD 9.1 9.7 10.5 mA
Isolation (S32) |S32| — 35 — dB
Input Return Loss (S11) IRL — 15 — dB
Output Return Loss (S22, S33) ORL — 15 — dB
Phase Step  — 6.5 — /bit
Phase Control Range  — 45.5 — 
Attenuation Step R — 0.25 — dB/bit
Attenuation Control Range R — 7.75 — dB
Max Input Voltage Logic Low VIL — — 0.4 V
Min Input Voltage Logic High VIH 1.6 — — V
SDO Output Voltage High VOH 1.8(1) — 0.6  VDD V
SDO Output Voltage Low VOL 0 — 0.4 V
Clock Frequency (50% Duty Cycle) fSCLK — — 26 MHz
1. Load = 20 pF @ maximum clock frequency.
Table 4. Thermal Characteristics
Characteristics Symbol Value (2) Unit
Thermal Resistance, Junction to Case RJC 10 C/W
Case Temperature 78.5C, Pout = 0.01 W, Maximum Phase and
Attenuation State, Pin = 25 dBm CW, 3600 MHz, VDD = 5 Vdc,
IDD = 11 mA

Table 5. ESD Protection Characteristics

Test Methodology Class
Human Body Model (per JESD22--A114) 1C
Charge Device Model (per JESD22--C101) C2

Table 6. Moisture Sensitivity Level

Test Methodology Rating Package Peak Temperature Unit
Per JESD22--A113, IPC/JEDEC J--STD--020 3 260 C

Table 7. Ordering Information

Device Tape and Reel Information Package
MMDS36254HT1 T1 Suffix = 1,000 Units, 16 mm Tape Width, 7--inch Reel QFN 6  6
2. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.

MMDS36254HT1
RF Device Data
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 SDI LCLK VDD N.C. N.C. N.C. N.C. N.C.
32 31 30 29 28 27 26 25

SCLK 1 24 RFout2
SDO 2 23 RFout2
N.C. 3 22 BYP
RFin 4 21 PUP
GND
RFin 5 20 LEN
N.C. 6 19 GND

SDO 7 18 RFout1
SCLK 8 17 RFout1

9 10 11 12 13 14 15 16
SDI LCLK VDD N.C. N.C. N.C. N.C. N.C.
(Top View)
Note: Exposed backside of the package is DC and RF ground.
Figure 2. Pin Connections

Table 8. Package Pin Description

Pin Number Pin Function Pin Description
1, 8 (1) SCLK Serial Data Clock
2(2), 7 (1) SDO Serial Data Output
3, 6, 12, 13, 14, 15, 16, N.C. No Connection
25, 26, 27, 28, 29
4, 5(3) RFin RF Input
9, 32 (1) SDI Serial Data Input
10, 31 (1) LCLK Latch Clock
11, 30 (1) VDD Supply Voltage (attenuators, phase shifters, SPI)
17, 18 (3) RFout1 RF Output 1 (peaking amplifier path)
19 GND Ground
20 (4) LEN Logic Enable (active low)
21 (5) PUP Power--up Programming:
S Minimum attenuation/minimum phase (0 dB/0)
S Maximum attenuation/maximum phase (7.75 dB/–45.5)
22 (6) BYP Internal Core Bypass Voltage (external 100 nF bypass capacitor)
23, 24 (3) RFout2 RF Output 2 (carrier amplifier path)

1. Redundant pins are internally connected. User can connect to either of the internally connected paired pins:
1 and 8, 2 and 7, 9 and 32, 10 and 31, and 11 and 30.
2. The ADAM SPI interface can be connected to a common SPI bus, provided the SDO pin is not connected,
and treated as a write--only device.
3. Each RF pin pair should be tied together.
4. Logic low enables normal SPI operation. Logic high disables SPI and places device at 0 dB attenuation and
0 phase shift.
5. Logic low places device at 0 dB attenuation and 0 phase shift at power up. Logic high places device at 7.75 dB
attenuation and –45.5 phase shift. Because PUP pin has internal pull up, logic high can be set by no
connection to pin. Alternatively, it can be connected to BYP or a user--controlled Vin.
6. Requires external capacitive decoupling to ground.

MMDS36254HT1
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Table 9. Serial Interface Timing Parameters
Symbol Parameter Min Typ Max Units
tSCLK Serial Clock Period 38.5 — — ns
tSCLKH Serial Clock Pulse Width High 10 — — ns
tSCLKL Serial Clock Pulse Width Low 10 — — ns
tSU Serial Data Input Setup Time to SCLK Rising Edge — — 5 ns
tH Serial Data Input Hold Time from SCLK Rising Edge — — 2 ns
tOH Serial Data Output Hold Time from SCLK Rising Edge 1.6 — — ns
tOV (10 pF) Serial Data Output Propagation Delay from SCLK Rising Edge — 5 9 ns
tOV (50 pF) Serial Data Output Propagation Delay from SCLK Rising Edge — 15 26 ns
tOV (150 pF) Serial Data Output Propagation Delay from SCLK Rising Edge — 35 65 ns
tSETTLE Serial Clock Rising Edge Setup Time to Latch Clock Rising Edge — — 27 ns
tLCLKH Latch Clock Pulse Width High 10 — — ns

tSCLK tSCLKH

SCLK

tSU tH
tSCLKL

SDI

tOH tOV

SDO

tSETTLE tLCLKH

LCLK

Figure 3. Serial Interface Timing Diagram

RFout2 RFout1

Attenuator Phase Attenuator Phase

SCLK

SDI b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0

LCLK

Figure 4. Serial Interface Bits Diagram

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Table 10. Logic Truth Table — RFin to RFout1 Table 11. Logic Truth Table — RFin to RFout2
Att. Phase Shift Att. Phase Shift
a7 a6 a5 a4 a3 (dB) a2 a1 a0 () b7 b6 b5 b4 b3 (dB) b2 b1 b0 ()

L L L L L 0 L L L 0 L L L L L 0 L L L 0
L L L L H 0.25 L L H –6.5 L L L L H 0.25 L L H –6.5
L L L H L 0.5 L H L –13 L L L H L 0.5 L H L –13
L L L H H 0.75 L H H –19.5 L L L H H 0.75 L H H –19.5
L L H L L 1.0 H L L –26 L L H L L 1.0 H L L –26
L L H L H 1.25 H L H –32.5 L L H L H 1.25 H L H –32.5
L L H H L 1.5 H H L –39 L L H H L 1.5 H H L –39
L L H H H 1.75 H H H –45.5 L L H H H 1.75 H H H –45.5
L H L L L 2.0 L H L L L 2.0
L H L L H 2.25 L H L L H 2.25
L H L H L 2.5 L H L H L 2.5
L H L H H 2.75 L H L H H 2.75
L H H L L 3.0 L H H L L 3.0
L H H L H 3.25 L H H L H 3.25
L H H H L 3.5 L H H H L 3.5
L H H H H 3.75 L H H H H 3.75
H L L L L 4.0 H L L L L 4.0
H L L L H 4.25 H L L L H 4.25
H L L H L 4.5 H L L H L 4.5
H L L H H 4.75 H L L H H 4.75
H L H L L 5.0 H L H L L 5.0
H L H L H 5.25 H L H L H 5.25
H L H H L 5.5 H L H H L 5.5
H L H H H 5.75 H L H H H 5.75
H H L L L 6.0 H H L L L 6.0
H H L L H 6.25 H H L L H 6.25
H H L H L 6.5 H H L H L 6.5
H H L H H 6.75 H H L H H 6.75
H H H L L 7.0 H H H L L 7.0
H H H L H 7.25 H H H L H 7.25
H H H H L 7.5 H H H H L 7.5
H H H H H 7.75 H H H H H 7.75

Note: ADAM contains a 32--bit shift register, with the last bit connected to the SDO signal. The SDO pin is intended for daisy--chaining
multiple ADAM devices rather than being used as an SPI bus connection; the SDO output is always actively driven, so it should not
be directly connected to the SPI bus.

MMDS36254HT1
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Table 12. Power--up Programming (PUP) State
LCLK PUP Function
X 0 Minimum Attenuation/Minimum Phase (0 dB/0)
X 1 Maximum Attenuation/Maximum Phase (7.75 dB/–45.5)
On 1st rising edge X Normal Operation on 1st Rising Edge LCLK and Subsequent Rising Edges

DRIVER OUTPUT

0 Carrier
MMG30271B 
0 to –45.5 0 to 7.75 dB
Zo
0 to –45.5 0 to 7.75 dB
Peaking
–90

TO ISOLATOR

SERIAL DIGITAL INTERFACE

SDI SCLK LCLK SDO PUP LEN VDD BYP GND

Figure 5. Typical Doherty Base Station Alignment Block Diagram

MMDS36254HT1
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 ALTERNATE SDI ALTERNATE LCLK

32 31 30 29 28 27 26 25

ALTERNATE SCLK 1 24

RF OUTPUT
ALTERNATE SDO 2 23

3 22
C5
4 21
RF INPUT
5 20

6 19

SDO 7 18
RF OUTPUT
SCLK 8 17

9 10 11 12 13 14 15 16

SDI LCLK C1 C2

5V
Figure 6. MMDS36254H Test Circuit Schematic

Table 13. MMDS36254H Test Circuit Component Designations and Values

Part Description Part Number Manufacturer
C1 22 pF Chip Capacitor GRM1885C1H220JA01J Murata
C2 100 pF Chip Capacitor GRM1885C1H101JA01J Murata
C3, C4 Components Not Placed
C5 0.1 F Chip Capacitor GRM155R61A104KA01D Murata
PCB 0.02, r = 3.48 RO4350 Rogers

MMDS36254HT1
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NXP Semiconductors 7
 RFout2

ADAM_36
Phase Shifter/Attenuator C4*
Rogers RO4350 20 mil +
Rogers Theta 5 mil
FSL0124 JUN 2015

C5

SCLK

LCLK
RFin

SDO

SDI1
C1 C2

C3*
+5 V
GND

RFout1

Note: Component numbers C3* and C4* are labeled on board but not placed.

Figure 7. MMDS36254H Test Circuit Component Layout

Table 13. MMDS36254H Test Circuit Component Designations and Values

Part Description Part Number Manufacturer
C1 22 pF Chip Capacitor GRM1885C1H220JA01J Murata
C2 100 pF Chip Capacitor GRM1885C1H101JA01J Murata
C3, C4 Components Not Placed
C5 0.1 F Chip Capacitor GRM155R61A104KA01D Murata
PCB 0.02, r = 3.48 RO4350 Rogers
(Test Circuit Component Designations and Values repeated for reference.)

MMDS36254HT1
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8 NXP Semiconductors
 --6 --6
--7 --7
--8 --8

--9 --9
S21, CARRIER (dB)

S31, PEAKING (dB)

--10 --10

--11 --11
--12 --12

--13 --13

--14 --14
--15 --15
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.3 3.4 3.5 3.6 3.7 3.8 3.9
f, FREQUENCY (GHz) f, FREQUENCY (GHz)
Note: S21 is a combination of static insertion loss and selected Note: S31 is a combination of static insertion loss and selected
path attenuation. path attenuation.
Figure 8. S21 versus Attenuation State Figure 9. S31 versus Attenuation State
versus Frequency versus Frequency

150
PHASE ANGLE DIFFERENCE OF S21 AND S31 ()

140 7

(all b states at 0)
130 6

a state
5
120 4
110 3
2

PHASE INDEX
100 1
90 0
80 1
2
70

(all a states at 0)
3
60 4

b state
5
50 6
40 7
30
3.3 3.4 3.5 3.6 3.7 3.8 3.9

f, FREQUENCY (GHz)
Note: The phase angle difference is a combination of insertion phase
and selected phase adjustment.
Figure 10. Phase Angle Difference of S21 and
S31 versus Phase State versus Frequency

MMDS36254HT1
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NXP Semiconductors 9
 0 0

--5 --5

--10 --10

S22 (dB)
S11 (dB)

--15 --15

--20 --20

--25 --25
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.3 3.4 3.5 3.6 3.7 3.8 3.9
f, FREQUENCY (GHz) f, FREQUENCY (GHz)
Figure 11. S11 versus Frequency Figure 12. S22 versus Frequency

0 0

--5
--5
--10
--10
--15
S33 (dB)
S23 (dB)

--20 --15

--25
--20
--30

--35 --25
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.3 3.4 3.5 3.6 3.7 3.8 3.9
f, FREQUENCY (GHz) f, FREQUENCY (GHz)
Figure 13. S23 versus Frequency Figure 14. S33 versus Frequency

Note: A total of 512 states are plotted in Figures 11 to 14. Graph measurements include 256 states for the carrier side
(combinations of all phase and amplitude states), with the peaking side set to 0 dB attenuation and 0 phase.
Measurements also include 256 states for the peaking side (combinations of all phase and amplitude states) with the
carrier side set to 0 dB attenuation and 0 phase.

MMDS36254HT1
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10 NXP Semiconductors
 --6

--7
--40C
--8 25C
125C
--9
S21 (dB)

--10

--11
--12
--13

--14
--15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ATTENUATION INDEX
Figure 15. S21 versus Attenuation State
versus Temperature

--6

--7
--40C
--8 25C
125C
--9
S21 (dB)

--10

--11
--12
--13

--14
--15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ATTENUATION INDEX
Figure 16. S31 versus Attenuation State
versus Temperature

140
PHASE ANGLE DIFFERENCE OF S21 AND S31 ()

130
--40C
120 25C
110 125C

100
90
80
70
60
Minimal Temperature Variation
50
40
7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

a state b state
PHASE INDEX
(all b states at 0) (all a states at 0)
Figure 17. Phase Angle Difference of S21 and S31
versus Phase State versus Temperature

MMDS36254HT1
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NXP Semiconductors 11
 6.00

0.30
5.00 6.60

0.50

4.4  4.4 Solder

Pad with Thermal
Via Structure

Figure 18. PCB Pad Layout for QFN 6  6

MDS36254H

AWLYWWZ

Figure 19. Product Marking

MMDS36254HT1
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12 NXP Semiconductors
 PACKAGE DIMENSIONS

MMDS36254HT1
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NXP Semiconductors 13
MMDS36254HT1
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14 NXP Semiconductors
 MMDS36254HT1
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 PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS

Refer to the following resources to aid your design process.

Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Development Tools
 Printed Circuit Boards
 Evaluation/Development Boards and Systems (file includes ADAM User’s Guide)
To Download Resources Specific to a Given Part Number:
1. Go to http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu

FAILURE ANALYSIS

At this time, because of the physical characteristics of the part, failure analysis is limited to electrical signature analysis. In
cases where NXP is contractually obligated to perform failure analysis (FA) services, full FA may be performed by third party
vendors with moderate success. For updates contact your local NXP Sales Office.

REVISION HISTORY

The following table summarizes revisions to this document.

Revision Date Description

0 Jan. 2018  Initial release of data sheet

MMDS36254HT1
RF Device Data
16 NXP Semiconductors
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MMDS36254HT1
RF Device
Document Data MMDS36254H
Number:
Rev. 0,Semiconductors
NXP 01/2018 17