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Experiment 8 - Sequential Logic Circuits - Part 1

The document describes an experiment on sequential logic circuits. It defines sequential circuits as having memory, unlike combinational circuits which only depend on current inputs. The experiment involves simulating a J-K flip-flop, 3-bit synchronous up counter, and ring counter using VHDL. Students are instructed to create projects to run the VHDL files and observe the RTL simulations for each circuit.

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Mustafa Maher
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170 views6 pages

Experiment 8 - Sequential Logic Circuits - Part 1

The document describes an experiment on sequential logic circuits. It defines sequential circuits as having memory, unlike combinational circuits which only depend on current inputs. The experiment involves simulating a J-K flip-flop, 3-bit synchronous up counter, and ring counter using VHDL. Students are instructed to create projects to run the VHDL files and observe the RTL simulations for each circuit.

Uploaded by

Mustafa Maher
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect.

Eman Karim

Experiment 8 - Sequential Logic Circuits – Part 1

Objective:

To get familiar with sequential logic circuits.

Theory:

Unlike Combinational Logic Circuits that change state depending upon the actual

signals being applied to their inputs at that time, Sequential Logic Circuits are a form

of the binary circuit that has a Memory built-in.

Flip-Flops

A flip-flop is an electronic circuit that can be used to store binary data. The stored

data can be changed by applying varying inputs. Flip-flops are fundamental building

blocks of digital electronics systems used in computers, communications, and many

other types of systems. Flip-flops are used as data storage elements in sequential logic

circuits. One flip-flop can store one bit of information.

 J-K Flip-Flop

The J-K flip-flop is an improvement on the S-R flip-flop where S=R=1 is not a problem.

If J and K data input are different (i.e. high and low) then the output takes the value of

J at the next clock edge. If J and K are both low then no change occurs. If J and K are

both high at the clock edge then the output will toggle from one state to the other.

1
Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

Synchronous Counters
Synchronous Counters are so called because the clock input of all the individual flip-

flops within the counter are all clocked together at the same time by the same clock

signal.

4-bit Synchronous Counter Waveform Timing Diagram

2
Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

Procedure:

Lab8a: Create (Lab8a) project to run the VHDL file using Quartus Prime Lite of
J-K Flip-Flop. Show the RTL Simulation.

The VHDL Code is:

3
Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

The RTL Simulation is:

Lab8b: Create (Lab8b) project to run the VHDL file using Quartus Prime Lite of
3-bit synchronous up counter. Show the RTL Simulation.

4
Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

The VHDL Code is:

The RTL Simulation is:

5
Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

Lab8c: Create (Lab8c) project to run the VHDL file using Quartus Prime Lite of
Ring Counter. Show the RTL Simulation.

The VHDL Code is:

The RTL Simulation is:

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