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DSD Lab 13 Handout

This document provides instructions for using Chipscope Pro to analyze a digital design implemented on an FPGA. It describes connecting an Integrated Logic Analyzer (ILA) core to monitor specific signals in the design. The steps include: 1. Configuring the design and adding an ILA core in the Chipscope Pro software 2. Setting up the ILA core to monitor an 8-bit counter signal 3. Capturing data samples and observing the signal values in the waveform window The overall goal is to understand how to use Chipscope Pro and the ILA core to debug and monitor an FPGA design.

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83 views9 pages

DSD Lab 13 Handout

This document provides instructions for using Chipscope Pro to analyze a digital design implemented on an FPGA. It describes connecting an Integrated Logic Analyzer (ILA) core to monitor specific signals in the design. The steps include: 1. Configuring the design and adding an ILA core in the Chipscope Pro software 2. Setting up the ILA core to monitor an 8-bit counter signal 3. Capturing data samples and observing the signal values in the waveform window The overall goal is to understand how to use Chipscope Pro and the ILA core to debug and monitor an FPGA design.

Uploaded by

Muhammad Anas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 13: Chipscope Pro

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L) Page 73


Chipscope Pro
1. Objective
This lab exercise is designed to understand the Chipscope Pro and then implement it to
FPGA on Spartan 3E or Spartan 2 kit.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 2 or Spartan 3E board

3. Introduction
Analysis Using Chip Scope Pro
1. Select Start → Programs → Xilinx ISE 12.1→ Project Navigator to open the Project Navigator in the
ISE software.

2. Make a new project and add verilog code from the file given on LMS.

3. Assign pin constraints from the file “Pins” on LMS.

4. Generate Programming file and analyze design using chipscope pro.

5. Now close the chipscope window and follow the steps given below to add Integrated Logic Analyzer
(ILA).

General Flow for this Lab:


Step 1: Step 2: Step 3: Step 4:
Configuring Adding an Setting Up Capturing
the Design ILA Core the Interface Data

Step 5: Step 6:
Debugging Observing
the Design Consumed
Resources
6. Select Project → New Source

7. In the New Source dialog box, select ChipScope Definition and Connection and enter Clock_ILA in the
file name field

8. Click Next, click Next, and click Finish

9. Double-click Clock_ILA.cdc in the Sources window to launch the ChipScope Pro software Core Inserter.

Digital System Design Lab (EE-319L) Page 74


10. Click Next

11. In the set up for the ICON core, leave the Disable JTAG Clock BUFG Insertion option unchecked. Click
New ILA Unit at the bottom of the dialog box. Confirm that an ILA core has been added to the device tree
in the left-hand window (U0: ILA). Click Next

Digital System Design Lab (EE-319L) Page 75


12. Select trigger width “8” and click NEXT. Trigger width defines the width of the register you want to
monitor.

13. Click on clock port and then “modify connections”.

Digital System Design Lab (EE-319L) Page 76


14. Write “clk” in the pattern field and click filter.

Digital System Design Lab (EE-319L) Page 77


15. Select clk_BIFGP and click Make Connections in the lower-right hand corner. This will associate the
clock signal with CH) of ILA. Now click “”trigger/Data Signals” tab under Net Selections. Type
“del_counter*” in the pattern field and make connection of “del_counter <25:18>” fields with Ch0 to Ch7.
Click OK.

Digital System Design Lab (EE-319L) Page 78


16. Click “Return to Project Navigator” and save the selection.

Digital System Design Lab (EE-319L) Page 79


17. Analyze design using Chipscope Pro as explained in the previous lab. Configure the design in the
Chipscope analyzer window. Once configured, Double click Trigger Setup and apply the changes as shown
in the figure.

Digital System Design Lab (EE-319L) Page 80


18. After trigger setup, click RUN with icon ►. This will start getting data samples from “0” upto selected
depth which is 1024 in our case. When you see sample buffer full, click T!. Now you can observe the
register “del_counter<25:18>” in the waveform window. Show this task to Instructor so you will be asked
to modify the core inserter properties and analyze the design in different setup.

Digital System Design Lab (EE-319L) Page 81

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