International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 08: Binary Multiplier

Name of Student: …………………………………..

Roll No.: ……………………………………………

Date of Experiment: ………………………………..

Report submitted on: ………………………………..

Marks obtained: ……………………………………

Remarks: ……………………………………………

Instructor’s Signature: ……………………………...

Digital System Design Lab (EE-319L) Page 1

 Binary Multiplier
1. Objective
This lab exercise is designed to understand the design and then implement Binary
Multiplier (combinational) on Spartan 3E or Spartan 2 kit.

2. Resources Required
• A Computer
• Xilinx ISE
• ModelSim

3. Introduction
Multipliers are important functional elements of arithmetic units, digital signal processors, and
other circuits that execute arithmetic operations. Multiplication can be implemented with a
combinational circuit or by a sequential circuit.
A combinational circuit that multiplies two numbers will require more silicon area, but will operate
faster than a sequential multiplier. Sequential multipliers are attractive because they require less
area, but a complete multiplication takes several clock cycles to form the product.

3.1 4-bit Multiplier

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The structure of a combinational circuit that multiplies two unsigned binary numbers (words) can
be derived from the manual operations for multiplying the numbers in a radix 2 system. For
simplicity, we consider two 4-bit words, A and B (the multiplicand and multiplier, respectively),
and we form their product, A x B, as shown in above figure. Beginning with the LSB of the
multiplier, each bit is multiplied by the bits of the multiplicand to form a so-called partial product.
In a radix 2 system, the operation of multiplication that forms a partial product is equivalent to
AND-ing the multiplier bit with each bit of the multiplicand. Each partial product is shifted toward
the MSB to the position of the corresponding multiplier bit. Then the partial products are added.
As we noted earlier, a manual method would add the terms in the aligned columns of the partial
products, which, in general, requires addition of several terms, but hardware adders are designed
to add only two words. Consequently, the result of adding the rows of the partial products is
accumulated, with attention to any carries that are generated by the addition of the terms in a given
column. The structure will require full adders when carries are involved and half adders otherwise.
In general, the resulting final product may contain as many as 2*L_word significant bits, where
L_word is the length of the multiplier and multiplicand words.

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The combinational logic structure consisting of AND-gates, full adders, and half adders, shown in
above figure, implements a parallel multiplier for a 4-bit wide datapath. This method of
multiplication is called partial product accumulation, because rows of linked adders generate the
accumulated partial products that would evolve from a manual multiplication of the data words.
Most of the array is formed of linked copies of the basic cell shown above. An alternative structure,
composed entirely of basic cells, is shown in the following figure, implementing half adders as
full adders with their carry-in line hard wired to 0. The resulting regular array of identical objects
is called a systolic array (i.e., copies of a basic cell) and is ideally suited for fabrication as an
integrated circuit. In practice, the boundary cells can be replaced by their counterparts from above
figure. A 4-bit combinational multiplier has 16 AND gates, 8 full adders, and 4 half adders. An 8-
bit multiplier would extend the array structure to accommodate 8-bit input datapaths, producing a
16-bit output data- path for the product. The systolic array in following figure is attractive because
it has a regular structure of identical cells and easily accommodates expansion to longer word
length by direct abutment of cells, which leads to an area-efficient physical layout of the cell on a
die, with short interconnect paths between cells. Because the structure is isomorphic to a dataflow
graph, it can be used to identify cutsets for pipelining the structure to obtain greater throughput.

Digital System Design Lab (EE-319L) Page 4

4. Verilog Codes (to be utilized in this lab)

Stimulus #10 A=4'd1; B=4'd11;

#10 A=4'd1; B=4'd12;
module Stimulus; #10 A=4'd1; B=4'd13;
#10 A=4'd1; B=4'd14;
reg [3:0] A,B; #10 A=4'd1; B=4'd15;
wire [7:0] Product;
reg Clk, Clr, Count; //Multiples of 2

//Module Instantiation #10 A=4'd2; B=4'd0;

multiplier m0(Product, A, B); #10 A=4'd2; B=4'd1;
#10 A=4'd2; B=4'd2;
//Values checking part #10 A=4'd2; B=4'd3;
initial #10 A=4'd2; B=4'd4;
begin #10 A=4'd2; B=4'd5;
A=4'd0; B=4'd0; #10 A=4'd2; B=4'd6;
#10 A=4'd0; B=4'd1; #10 A=4'd2; B=4'd7;
#10 A=4'd0; B=4'd2; #10 A=4'd2; B=4'd8;
#10 A=4'd0; B=4'd3; #10 A=4'd2; B=4'd9;
#10 A=4'd0; B=4'd4; #10 A=4'd2; B=4'd10;
#10 A=4'd0; B=4'd5; #10 A=4'd2; B=4'd11;
#10 A=4'd0; B=4'd6; #10 A=4'd2; B=4'd12;
#10 A=4'd0; B=4'd7; #10 A=4'd2; B=4'd13;
#10 A=4'd0; B=4'd8; #10 A=4'd2; B=4'd14;
#10 A=4'd0; B=4'd9; #10 A=4'd2; B=4'd15;
#10 A=4'd0; B=4'd10;
#10 A=4'd0; B=4'd11; //Multiples of 3
#10 A=4'd0; B=4'd12;
#10 A=4'd0; B=4'd13; #10 A=4'd3; B=4'd0;
#10 A=4'd0; B=4'd14; #10 A=4'd3; B=4'd1;
#10 A=4'd0; B=4'd15; #10 A=4'd3; B=4'd2;
#10 A=4'd3; B=4'd3;
//Multiples of 1 #10 A=4'd3; B=4'd4;
#10 A=4'd3; B=4'd5;
#10 A=4'd1; B=4'd0; #10 A=4'd3; B=4'd6;
#10 A=4'd1; B=4'd1; #10 A=4'd3; B=4'd7;
#10 A=4'd1; B=4'd2; #10 A=4'd3; B=4'd8;
#10 A=4'd1; B=4'd3; #10 A=4'd3; B=4'd9;
#10 A=4'd1; B=4'd4; #10 A=4'd3; B=4'd10;
#10 A=4'd1; B=4'd5; #10 A=4'd3; B=4'd11;
#10 A=4'd1; B=4'd6; #10 A=4'd3; B=4'd12;
#10 A=4'd1; B=4'd7; #10 A=4'd3; B=4'd13;
#10 A=4'd1; B=4'd8; #10 A=4'd3; B=4'd14;
#10 A=4'd1; B=4'd9; #10 A=4'd3; B=4'd15;
#10 A=4'd1; B=4'd10;

Digital System Design Lab (EE-319L) Page 5

#10 A=4'd4; B=4'd0; #10 A=4'd6; B=4'd8;
#10 A=4'd4; B=4'd1; #10 A=4'd6; B=4'd9;
#10 A=4'd4; B=4'd2; #10 A=4'd6; B=4'd10;
#10 A=4'd4; B=4'd3; #10 A=4'd6; B=4'd11;
#10 A=4'd4; B=4'd4; #10 A=4'd6; B=4'd12;
#10 A=4'd4; B=4'd5; #10 A=4'd6; B=4'd13;
#10 A=4'd4; B=4'd6; #10 A=4'd6; B=4'd14;
#10 A=4'd4; B=4'd7; #10 A=4'd6; B=4'd15;
#10 A=4'd4; B=4'd8;
#10 A=4'd4; B=4'd9; //Multiples of 6
#10 A=4'd4; B=4'd10;
#10 A=4'd4; B=4'd11; #10 A=4'd7; B=4'd0;
#10 A=4'd4; B=4'd12; #10 A=4'd7; B=4'd1;
#10 A=4'd4; B=4'd13; #10 A=4'd7; B=4'd2;
#10 A=4'd4; B=4'd14; #10 A=4'd7; B=4'd3;
#10 A=4'd4; B=4'd15; #10 A=4'd7; B=4'd4;
#10 A=4'd7; B=4'd5;
//Multiples of 4 #10 A=4'd7; B=4'd6;
#10 A=4'd7; B=4'd7;
#10 A=4'd5; B=4'd0; #10 A=4'd7; B=4'd8;
#10 A=4'd5; B=4'd1; #10 A=4'd7; B=4'd9;
#10 A=4'd5; B=4'd2; #10 A=4'd7; B=4'd10;
#10 A=4'd5; B=4'd3; #10 A=4'd7; B=4'd11;
#10 A=4'd5; B=4'd4; #10 A=4'd7; B=4'd12;
#10 A=4'd5; B=4'd5; #10 A=4'd7; B=4'd13;
#10 A=4'd5; B=4'd6; #10 A=4'd7; B=4'd14;
#10 A=4'd5; B=4'd7; #10 A=4'd7; B=4'd15;
#10 A=4'd5; B=4'd8;
#10 A=4'd5; B=4'd9; //Multiples of 8
#10 A=4'd5; B=4'd10;
#10 A=4'd5; B=4'd11; #10 A=4'd8; B=4'd0;
#10 A=4'd5; B=4'd12; #10 A=4'd8; B=4'd1;
#10 A=4'd5; B=4'd13; #10 A=4'd8; B=4'd2;
#10 A=4'd5; B=4'd14; #10 A=4'd8; B=4'd3;
#10 A=4'd5; B=4'd15; #10 A=4'd8; B=4'd4;
#10 A=4'd8; B=4'd5;
//Multiples of 5 #10 A=4'd8; B=4'd6;
#10 A=4'd8; B=4'd7;
#10 A=4'd6; B=4'd0; #10 A=4'd8; B=4'd8;
#10 A=4'd6; B=4'd1; #10 A=4'd8; B=4'd9;
#10 A=4'd6; B=4'd2; #10 A=4'd8; B=4'd10;
#10 A=4'd6; B=4'd3; #10 A=4'd8; B=4'd11;
#10 A=4'd6; B=4'd4; #10 A=4'd8; B=4'd12;
#10 A=4'd6; B=4'd5; #10 A=4'd8; B=4'd13;
#10 A=4'd6; B=4'd6; #10 A=4'd8; B=4'd14;
#10 A=4'd6; B=4'd7; #10 A=4'd8; B=4'd15;
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 #10 A=4'd11; B=4'd5;
//Multiples of 9 #10 A=4'd11; B=4'd6;
#10 A=4'd11; B=4'd7;
#10 A=4'd9; B=4'd0; #10 A=4'd11; B=4'd8;
#10 A=4'd9; B=4'd1; #10 A=4'd11; B=4'd9;
#10 A=4'd9; B=4'd2; #10 A=4'd11; B=4'd10;
#10 A=4'd9; B=4'd3; #10 A=4'd11; B=4'd11;
#10 A=4'd9; B=4'd4; #10 A=4'd11; B=4'd12;
#10 A=4'd9; B=4'd5; #10 A=4'd11; B=4'd13;
#10 A=4'd9; B=4'd6; #10 A=4'd11; B=4'd14;
#10 A=4'd9; B=4'd7; #10 A=4'd11; B=4'd15;
#10 A=4'd9; B=4'd8;
#10 A=4'd9; B=4'd9; //Multiples of 12
#10 A=4'd9; B=4'd10;
#10 A=4'd9; B=4'd11; #10 A=4'd12; B=4'd0;
#10 A=4'd9; B=4'd12; #10 A=4'd12; B=4'd1;
#10 A=4'd9; B=4'd13; #10 A=4'd12; B=4'd2;
#10 A=4'd9; B=4'd14; #10 A=4'd12; B=4'd3;
#10 A=4'd9; B=4'd15; #10 A=4'd12; B=4'd4;
#10 A=4'd12; B=4'd5;
//Multiples of 10 #10 A=4'd12; B=4'd6;
#10 A=4'd12; B=4'd7;
#10 A=4'd10; B=4'd0; #10 A=4'd12; B=4'd8;
#10 A=4'd10; B=4'd1; #10 A=4'd12; B=4'd9;
#10 A=4'd10; B=4'd2; #10 A=4'd12; B=4'd10;
#10 A=4'd10; B=4'd3; #10 A=4'd12; B=4'd11;
#10 A=4'd10; B=4'd4; #10 A=4'd12; B=4'd12;
#10 A=4'd10; B=4'd5; #10 A=4'd12; B=4'd13;
#10 A=4'd10; B=4'd6; #10 A=4'd12; B=4'd14;
#10 A=4'd10; B=4'd7; #10 A=4'd12; B=4'd15;
#10 A=4'd10; B=4'd8;
#10 A=4'd10; B=4'd9; //Multiples of 13
#10 A=4'd10; B=4'd10;
#10 A=4'd10; B=4'd11; #10 A=4'd13; B=4'd0;
#10 A=4'd10; B=4'd12; #10 A=4'd13; B=4'd1;
#10 A=4'd10; B=4'd13; #10 A=4'd13; B=4'd2;
#10 A=4'd10; B=4'd14; #10 A=4'd13; B=4'd3;
#10 A=4'd10; B=4'd15; #10 A=4'd13; B=4'd4;
#10 A=4'd13; B=4'd5;
//Multiples of 11 #10 A=4'd13; B=4'd6;
#10 A=4'd13; B=4'd7;
#10 A=4'd11; B=4'd0; #10 A=4'd13; B=4'd8;
#10 A=4'd11; B=4'd1; #10 A=4'd13; B=4'd9;
#10 A=4'd11; B=4'd2; #10 A=4'd13; B=4'd10;
#10 A=4'd11; B=4'd3; #10 A=4'd13; B=4'd11;
#10 A=4'd11; B=4'd4; #10 A=4'd13; B=4'd12;
Digital System Design Lab (EE-319L) Page 7
#10 A=4'd13; B=4'd13; //Multiples of 15
#10 A=4'd13; B=4'd14;
#10 A=4'd13; B=4'd15; #10 A=4'd15; B=4'd0;
#10 A=4'd15; B=4'd1;
//Multiples of 14 #10 A=4'd15; B=4'd2;
#10 A=4'd15; B=4'd3;
#10 A=4'd14; B=4'd0; #10 A=4'd15; B=4'd4;
#10 A=4'd14; B=4'd1; #10 A=4'd15; B=4'd5;
#10 A=4'd14; B=4'd2; #10 A=4'd15; B=4'd6;
#10 A=4'd14; B=4'd3; #10 A=4'd15; B=4'd7;
#10 A=4'd14; B=4'd4; #10 A=4'd15; B=4'd8;
#10 A=4'd14; B=4'd5; #10 A=4'd15; B=4'd9;
#10 A=4'd14; B=4'd6; #10 A=4'd15; B=4'd10;
#10 A=4'd14; B=4'd7; #10 A=4'd15; B=4'd11;
#10 A=4'd14; B=4'd8; #10 A=4'd15; B=4'd12;
#10 A=4'd14; B=4'd9; #10 A=4'd15; B=4'd13;
#10 A=4'd14; B=4'd10; #10 A=4'd15; B=4'd14;
#10 A=4'd14; B=4'd11; #10 A=4'd15; B=4'd15;
#10 A=4'd14; B=4'd12; #10 $stop;
#10 A=4'd14; B=4'd13; #10 $finish;
#10 A=4'd14; B=4'd14; end
#10 A=4'd14; B=4'd15;
endmodule

5. Lab Task
Implement a 4-bit combinational Multiplier using 1-bit Full Adders. Also simulate your
design for verification. Utilize the Stimulus given in code section.

Hint: First form partial products. Make use of replication operator “{{ }}” like as follows:
PP1 = {4{A[0]}}&B
Then use full adders for addition (Use the 1st figure for better idea).

6. Home Work
Implement 2-bit combinational Multiplier. Submit the code and wave files in the next lab.
You can utilize a similar Stimulus.

Note:
a) This assignment must be submitted before the next lab.
b) The assignment submitted must be in proper format as instructed by the teacher to get
maximum marks.
c) Marks will be deducted on late submissions.
d) Cheating or using any unfair means will award ZERO marks.

Digital System Design Lab (EE-319L) Page 8

 International Islamic University, Islamabad
Digital System Design Lab

LAB WORKSHEET (Lab # 8)

Q.1 What is the importance of Multiplier?

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Q.2 What are the advantages of combinational Multiplier over sequential one?
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Q.3 What is partial product accumulation?

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Q.4 Draw the basic cell of a Multiplier.

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Digital System Design Lab (EE-319L) Page 9