Tiger Lake-LP Intel® Converged

Security and Management Engine

Firmware 15.0

Consumer Firmware Bring Up Guide

September 2020

Revision 1.37

Intel Confidential
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2 Intel Confidential
Contents
1 Introduction .............................................................................................................. 6
1.1 Related Documentation ........................................................................................ 6
1.2 Prerequisites....................................................................................................... 6
1.3 Acronyms and Definitions ..................................................................................... 7
1.3.1 General................................................................................................... 7
1.3.2 Intel® Converged Security and Management Engine...................................... 8
1.3.3 System States and Power Management ....................................................... 9
1.4 Reference Documents ........................................................................................ 10
1.5 Format and Notation.......................................................................................... 10
1.6 Kit Contents ..................................................................................................... 11
1.7 External Hardware Requirements for Bring Up ....................................................... 20
2 Image Creation: Intel® Flash Image Tool ............................................................... 21
2.1 Start Intel®FIT ................................................................................................. 21
2.2 Step-by-Step Guide to Build SPI Flash Image with Intel® FIT Interface..................... 21
3 Programming SPI Flash Devices and Checking Firmware Status ............................ 143
3.1 Flash Burner/Programmer ................................................................................ 143
3.1.1 In-Circuit SPI Flash Programming for CRB................................................ 143
3.2 Flash Programming Tool (Intel® FPT) ................................................................. 143
3.2.1 Intel® FPT Windows* Version................................................................. 144
3.3 Checking Intel® ME Firmware Status.................................................................. 144
3.4 Common Bring Up Issues and Troubleshooting Table............................................ 146
A Appendix — Flash Configurations........................................................................... 147
B Appendix — Intel® ICCS SKU Support Matrix ......................................................... 148
C Appendix — Boot Guard Configuration ................................................................... 149
D Appendix — Intel® Platform Trust Technology ....................................................... 151
E Appendix — Integrated Sensor Hub (ISH) Public Key Settings............................... 152
F Appendix — RVP Platform Specific Settings ........................................................... 154

Intel Confidential 3
Figures

Tables
1-1 Number Format Notation........................................................................................... 10
1-2 Data Format Notation ............................................................................................... 10
1-3 Kit Contents ............................................................................................................ 11
2-1 - Initial Screen Layout .............................................................................................. 22
2-2 - Build Settings........................................................................................................ 31
2-3 - Flash Layout ......................................................................................................... 33
2-4 - Flash Settings ....................................................................................................... 39
2-5 - Intel® ME Kernel ................................................................................................... 49
2-6 - Intel® AMT ........................................................................................................... 54
2-7 - Platform Protection ................................................................................................ 62
2-8 - Integrated Clock Controller ..................................................................................... 71
2-9 - Networking & Connectivity ...................................................................................... 78
2-10- Internal PCH Buses ................................................................................................ 82
2-11- Power .................................................................................................................. 87
2-12- Integrated Sensor Hub ........................................................................................... 89
2-13- Camera ................................................................................................................ 91
2-14- Debug .................................................................................................................. 92
2-15- CPU Straps ........................................................................................................... 97
2-16- Flex I/O Straps...................................................................................................... 99
2-17- GPIO.................................................................................................................. 115
2-18- Download and Execute ......................................................................................... 134
2-19- Intel® Unique Platform ID ..................................................................................... 136
2-20- FW Update Image Build ........................................................................................ 137
2-21- Intel® FIT - Build Image ....................................................................................... 142
3-1 Common Bring Up Issues and Troubleshooting Table .................................................. 146

Intel Confidential 4
Revision History

Document Revision
Description Revision Date
Number Number

0.5 Initial Release March 2018

0.51 Updated Tiger Lake and Intel®CSME references February 2019
0.7 Synced to the latest FIT UI layout February 2019
0.71 Updated to latest RVP defaults June 2019
0.8 Updated for Alpha release August 2019
0.81 Added GBST settings September 2019
0.82 Added Version to IUNIT, PCHC and GBST entries in Flash Layout October 2019
eSPI / EC Bus Frequency listed 40MHz should have been 48MHz
Updated USB2 Port Configuration screen capture
Updated OPI Link volt recommended default
0.83 Added missing 1.05v value to OPI Link Voltage November 2019
1.0 Updated to revision 1.0 December 2019
1.1 Updated screen capture and settings information to latest UI layout February 2020
Added Platform Appendix section
1.2 Added note to USB3 Port Speed Capability settings. February 2020
1.3 Updated with latest UI changes March 2020
1.31 Updated to add Intel® ME Measured Boot Configuration setting April 2020
VCC ST PG Present and VCC STG PG Present values changed
1.32 Updated CPU settings section to align with latest UI changes May 2020
1.33 Updated with latest UI changes June 2020
1.34 Updated with latest UI changes July 2020
1.35 Added CPU Boot Hang Recovery Enabled setting under CPU Straps July 2020
1.36 Updated OPI Link Voltage value for UP4 September 2020
1.37 Corrected Appendix reference for Hash Key Configuration for Bootguard / September 2020
ISH
Updated UP3 GPP_C2 Individual Voltage Select value to 1.8v

§§

Intel Confidential 5
Introduction

1 Introduction

This document covers the Intel® Converged Security and Management Engine
Firmware (Intel® ME) 15.0 - Consumer / Consumer Firmware bring up procedure.
Intel® ME is tied to essential platform functionality — this dependency cannot be
avoided for engineering reasons.

The bring up procedure primarily involves building a Serial Peripheral Interface (SPI)
Flash image that will contain:
• [required] Descriptor region — Contains sizing information for all other SPI Flash
image regions, SPI settings (including Vendor Specific Configuration - or VSCC -
tables, SPI device parameters), and region access permissions.
• [required] BIOS region — Contains firmware for the processor (or host) and/or
Embedded Controller (EC).
• [required] Intel® CSME FW region — Contains firmware for the Intel® Converged
Security and Management Engine.
• [optional] GbE region — Contains firmware for Intel LAN solution.

For more details on SPI Flash layout, see the document Tiger Lake-H / LP SPI
Programming Guide SPI Programming Guide and Appendix A. Once the SPI Flash
image is built, it will be programmed to the target based platform and the platform will
be booted. This document also covers any tests and checks required to ensure that this
boot process is successful and that Intel® ME Consumer FW is operating as expected.

1.1 Related Documentation

VIP: Kit# WIP - Intel® Ethernet Network Connections (xx.x OEM Gen) - LAN Software

CDI # WIP Intel® Ethernet Connection i2xx

Intel® CSME FW Features

This firmware release includes the following applications:

• Platform Clocks – Tune clock silicon to the parameters of a specific board, configure
clocks at run time, and power management clocks. Benefit: Allows extensive
customization and soft control of “Third generation” clock solution and makes
clocks available before CPU powers up.
• Silicon Workaround Capability – Intel® CSME FW will have limited capabilities to
perform targeted workarounds for silicon issues. Benefit: Allows Intel® CSME FW
to address some issues that otherwise would require a new silicon stepping.

1.2 Prerequisites
Before this document is read and utilized, it is essential that the reader first review the
Consumer FW Release Notes (included with this Intel® ME Consumer FW kit).

Intel Confidential 6
Introduction

This document is constructed so that the reader can complete the bring up steps as
given for the Intel Customer Reference Board (CRB). However, in the case that bring up
is being performed on a different Intel® x based platform, this document will highlight
any changes that must be imposed onto the bring up steps accordingly.

This document makes only the following limited assumptions regarding hardware:
• The platform is Tiger Lake LP/H based
• The platform is equipped with one or more SPI Flash devices with a total capacity
sufficient for storing all relevant firmware images.

1.3 Acronyms and Definitions

1.3.1 General

Acronym or Term Definition

BIOS Basic Input Output System

DIMM Dual In-line Memory Module

DMI Direct Media Interface

EC Embedded Controller

FPF Field Programmable Fuses

FW Firmware

GbE Gigabit Ethernet

HECI Host Embedded Controller Interface (aka Intel® MEI)

Intel® ICCS Intel® Integrated Clock Controller Service

Intel® CSME Intel® Converged Security and Management Engine (Intel®ME)

®
Intel MEI Intel® Converged Security and Management Engine Interface (Intel®
MEI) (renamed from HECI)

Intel® PTT Intel® Platform Trusted Technology (Intel® PPT)

®
Intel MSS Intel® Management and Security Status Application

KVM Keyboard, Video, Mouse

LAN Local Area Network

MCP Multi-Chip Package (Central Processing Unit / Platform Controller Hub)

NVM Non-Volatile Memory

OOB Out-of-Band

OS Operating System

PAVP Protected Audio and Video Path

PCI Peripheral Component Interconnect

PCIe* Peripheral Component Interconnect Express

PHY Physical Layer (Networking)

RTC Real Time Clock

SBT Intel® Small Business Technology

SMBus System Management Bus

Intel Confidential 7
Introduction

Acronym or Term Definition

SPI Flash Serial Peripheral Interface Flash

TPM Trusted Platform Module

VSCC Vendor Specific Configuration

1.3.2 Intel® Converged Security and Management Engine

Acronym or Term Definition

3PDS 3rd Party Data Storage

Agent Software that runs on a client PC with OS running

End User The person who uses the computer (either Desktop or Mobile). In
corporate, the user usually does not have administrator privileges.

Host or Host CPU The processor that is running the operating system. This is different
than the management processor running the Intel® Converged Security
and Management Engine Firmware.

Host ServTiger/Application An application that is running on the host CPU

INF An information file (.inf) used by Microsoft* operating systems that

supports the Plug & Play feature. When installing a driver, this file
provides the OS the necessary information about driver filenames,
driver components, and supported hardware.

Intel® Converged Security and Interface between the Converged Security and Management Engine and
Management Engine the Host system
Interface (Intel® MEI)

Intel® MEI driver Intel® ME host driver that runs on the host and interfaces between ISV
Agents and the Intel® ME HW.

IT User Information Technology User. Typically very technical and uses a

management console to ensure functionality of multiple PCs on a
network.

LMS Local Management ServTiger: A SW application which runs on the host

machine and provide a secured communication between the ISV agent
and the Intel® Converged Security and Management Engine Firmware.

Intel® ME Intel® Converged Security and Management Engine: The embedded

processor residing in the chipset MCP

MECI ME-VE Communication Interface

NVM Non-Volatile Memory: A type of memory that will retain its contents
even if power is removed. In the Intel® AMT current implementation,
this is achieved using a FLASH memory device.

OOB Interface Out Of Band interface: This is WSMAN interface over secure or non-
secure TCP protocol.

OS not Functional The Host OS is considered non-functional in Sx power state and any one
of the following cases when system is in S0 power state:
• OS is hung
• After PCI reset
• OS watch dog expires
• OS is not present

System States Operating System power states such as S0. See detailed definitions in
System States and Power Management section.

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Introduction

1.3.3 System States and Power Management

Acronym or Term Definition

G3 A system state of Mechanical Off where all power is disconnected from

the system. G3 power state does not necessarily indicate that RTC
power is removed.

CM0 Intel® Converged Security and Management Engine firmware power

state where all hardware power planes are activated. The host power
state is S0.

CM3 Intel® Converged Security and Management Engine power state where
the host is in Sx. The processor DRAM Controller is turned off and DRAM
power stays in off/self refresh mode. There is no UMA usage in CM3
state. Less than 1MB of SRAM used for code and data. Code is executed
off of flash takes ~1mS.

CM0-PG Core Well Powered; Intel® ME Well Powered; (Intel® ME core not
consuming power) DRAM available.

CM3-PG An Intel® ME Firmware power state where no power is applied to the

Converged Security and Management Engine subsystem. (Intel® ME
firmware is shut down).

OS Hibernate System state where the OS state is saved on the hard drive.

S0 A system state where power is applied to all HW devices and the system
is running normally.

S1, S2, S3 A system state where the host CPU is halted but power remains
available to the memory system (memory is in self-refresh mode).

S4 A system state where the host CPU and memory are not active.

S5 A system state where all power to the host system is off, however the
power cord (and/or battery in mobile designs) is still connected.

Shut Down Equivalent to the S5 state.

Snooze Mode Intel® Converged Security and Management Engine activities are
mostly suspended to save power. The Intel® Converged Security and
Management Engine monitors HW activities and can restore its activities
depending on the HW event.

Standby System state where the OS state is saved in memory and resumed from
the memory when mouse/keyboard is clicked.

Sx All S states which are different than S0.

1.4 Reference Documents

Doc Number/
Document
Location*

Tiger Lake Intel® Converged Security and Management Engine (Intel® CSME) and 549024 / CDI
Embedded Controller Interaction Product Specification Revision 0.5

Intel® Converged Security and Management Engine BIOS Writers Guide TBD / *
®
Intel Converged Security and Management Engine (Intel® CSME) 15 SKU Firmware TBD / CDI
Consumer Compliance Guide for Tiger Lake PCH-H/LP Chipset Family - Tiger Lake Platform
Compliancy and Testing Guide - Revision x.x

Note: * Unless specified otherwise, a document can be ordered by providing its reference number to your
Intel Field Applications Engineer.

Intel Confidential 9
Introduction

1.5 Format and Notation

The formats and notations used within this document model are those typically used by
BIOS vendors. This section describes the formatting and the notations that will be
followed in this document.

Table 1-1. Number Format Notation

Number Format Notation Example

Decimal (default) d 14d. Note that any number without an explicit suffix can be
assumed to be decimal.

Binary b 1110b

Hex h 0Eh

Hex 0x 0x0E

Table 1-2. Data Format Notation

Data Type Notation Size

Bit b Smallest unit, 0 or 1

Byte B 8 bits

Word W 16 bits or 2 bytes

Double-word DW 32 bits or 4 bytes

Quad-word QW 8 bytes or 4 words

Kilobyte KB 1024 bytes

Megabit Mb 1,048,576 bits or 128 KB

Megabyte MB 1,048,576 bytes or 1024 KB

Gigabit Gb 1,073,741,824 bits

Gigabyte GB 1024 MB

Intel Confidential 10
 Introduction

1.6 Kit Contents

The Intel® CSME Consumer FW kit can be downloaded from VIP
(https://platformsw.intel.com/). The contents of this kit are detailed below (Note that only key files
are listed).

Table 1-3. Kit Contents (Sheet 1 of 8)

File or [Directory] Content Description

[root] Root directory

[Installers]

[3rd party Licenses in Security SW]

ACE-TAO-CIAO.pdf Copyright and Licensing Information for ACE(TM),

TAO(TM), and CIAO(TM)

Apache-Xerces-C++-XML-Parser.txt Apache license for C++ XML parser

Inno Setup License.txt Inno Setup License

LICENSE.libmei libmei BSD License

Microsoft Windows Classic Samples.txt Microsoft Windows Classic Samples License

Microsoft winfile MIT.txt Microsoft winfile MIT License

openwsman.pdf Intel openwsman License

Windows driver samples.txt Microsoft driver samples License

WixLicenseNote.txt Microsoft Wix License

[ME_SW_DCH]

IntelMEFWVer.dll DLL file containing software version information

mup.xml XML file containing software version and driver

information

SetupME.exe DCH software installer executable

[ME_SW_MSI]

IntelMEFWVer.dll DLL file containing software version information

mup.xml XML file containing software version and driver

information

SetupME.exe MSI software installer executable

[MEI-Only Installer MSI]

IntelMEFWVer.dll DLL file containing MEI version information

mup.xml XML file containing MEI software version and driver

information

SetupME.exe Intel® MEI software installer executable

[WindowsDriverPackages]

[ICLS] Intel® Capability Licensing Service folder

iclsClient.cat iCLS CAT file

iclsClient.inf UWD iCLS Client INF

[JHI]

[IotCorePackages]

Intel.Drivers.DAL.cab Intel® Dynamic Application Loader CAB file

[Win10]

DAL.cat Intel® Dynamic Application Loader CAT file

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Table 1-3. Kit Contents (Sheet 2 of 8)

File or [Directory] Content Description

DAL.inf Intel® Dynamic Application Loader INF file

JHI.dll Intel® Dynamic Application Loader 32bit DLL file

jhi_service.exe Intel® Dynamic Application Loader Windows

Services executable file

JHI64.dll Intel® Dynamic Application Loader 64bit DLL file

SpoolerApplet.dalp Intel® Dynamic Application Loader Spooler Applet

TEEManagement.dll Intel® Dynamic Application Loader TEE

Management 32bit DLL

TEEManagement64.dll Intel® Dynamic Application Loader TEE

Management 64bit DLL

[LMS]

[Certificates]

B2C067A6568D27791074C3F5C5A58966D6F12E36.cer LMS Certificates files

BBAF7E023DFAA6F13C848EADEE3898ECD93232D4.cer

BF4E419CC0A20D33947C2A04867B27DE63A2174F.cer

SFIP Production SHA256.cer

[Templates]

5710ABF3E156BFE90FD5C8E21606788DA4D69ADD.data LMS Template file

Intel Confidential 12
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Table 1-3. Kit Contents (Sheet 3 of 8)

File or [Directory] Content Description

1200_PD_PFU.BIN Intel® CSME 12.x Firmware Update binaries

1200_PP_PFU.BIN

1300_PD_PFU.BIN Intel® CSME 13.x Firmware Update binaries

1300_PP_PFU.BIN

1400_PD_PFU.BIN Intel® CSME 14.x Firmware Update binaries

1400_PP_PFU.BIN

1500_PD_PFU.BIN Intel® CSME 15.x Firmware Update binaries

1500_PP_PFU.BIN

ACE.dll ADAPTIVE Communication Environment(TM) DLL

ComEventHandler.dll COM Event Handler DLL

Common.dll Common DLL

Configurator.dll Configurator DLL

EventManager.dll Windows Event Manager DLL

FWUpdateLib_10.dll Firmware Update Library DLL for Intel® ME 10.x

FWUpdateLib_11.dll Firmware Update Library DLL for Intel® ME 11.x

FWUpdateLib_12.dll Firmware Update Library DLL for Intel® ME 12.x -

15.x

GmsCommon.dll GMS Common DLL

HistoryEventHandler.dll History Event Handler DLL

HostChangesNotificationService.dll Host Changes Notification Service DLL

IPRefreshService.dll IP Refresh Service DLL

LMS.cat LMS CAT file

LMS.exe LMS Service executable

LMS.inf LMS INF file

Log.txt LMS Log file

PartialFWUpdateService.dll Partial Firmware Update Service DLL

PortForwardingService.dll Port Forwarding Service DLL

PowerOperationsService.dll Power Operation Service DLL

SharedStaticIPService.dll Shared Static IP Service DLL

SoapServerService.dll Soap Server Service DLL

StatusEventHandler.dll Status Event Handler DLL

TimeSyncService.dll Time Sync Service DLL

WiFiProfileSyncService.dll WiFi Profile Sync Server DLL

WinLogEventHandler.dll Windows Log Event Handler DLL

WMIEventHandler.dll WMI Event Handler DLL

WsmanClient.dll WSMAN Client DLL

[MEI]

[Win7]

[x64]

TeeDriverx64.sys Windows 7 64bit MEI TeeDriver file

[x86]

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Table 1-3. Kit Contents (Sheet 4 of 8)

File or [Directory] Content Description

TeeDriver.sys Windows 7 32bit MEI TeeDriver file

heci.cat Windows 7 MEI TeeDriver CAT file

heci.inf Windows 7 MEI TeeDriver INF file

[Win8]

[x64]

TeeDriverW8x64.sys Windows 8 64bit MEI TeeDriver file

[x86]

TeeDriverW8.sys Windows 8 32bit MEI TeeDriver file

heci.cat Windows 8 MEI TeeDriver CAT file

heci.inf Windows 8 MEI TeeDriver INF file

[Win10]

[x64]

TeeDriverW10x64.sys Windows 10 64bit MEI TeeDriver file

[x86]

TeeDriverW10.sys Windows 10 32bit MEI TeeDriver file

heci.cat Windows 10 MEI TeeDriver CAT file

heci.inf Windows 10 MEI TeeDriver INF file

[MEI_iCLS]

ReleaseNotes.txt iCLS Client release notes

[SOL]

mesrl.cat Serial Over LAN CAT file

mesrl.inf Serial Over LAN INF file

[TGP-LP]

[3rd party Licenses in Security FW]

Apache Harmony Apache Version 2.0, January 2004 w header.txt Apache Harmony Apache Version 2.0 License

Apache-Xerces-Java-XML-Parser.txt Apache Xerces Java XML Parser License

ConvertUTF unicode license.txt Convert UTF Unicode License

CxImage license complete.txt CxImage License

HTTP Client C MIT license.txt HTTP Client MIT License

llvm.org University of Illinois_NCSA.txt Compiler_RT MIT License

Microsoft TPM 2.0 BSD Two Clause License.txt TPM 2.0 BSD Two Clause Microsoft License

Minix 3.pdf Minix 3 operating system License

MIT Kerberos for Windows.pdf Kerberos for Windows MIT License

newlib_licenses.txt Newlib License

Synopsys UFS Host Controller OS.pdf Synopsys UFS Host Controller OS License

wpa supplicant license.txt WPA Supplicant License

zlib license.txt Zlib compression library License

[FWU_Prestitched]

Cons_Prestitched_FWUpdate.bin Consumer Firmware Updated Pre-stitched binary

Corp_Prestitched_FWUpdate.bin Corporate Firmware Updated Pre-stitched binary

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Table 1-3. Kit Contents (Sheet 5 of 8)

File or [Directory] Content Description

[Image Components]

[CSME]

[Silicon]

[LP]

[A0]

[PreProduction]

CSME_FW_Consumer_TGP-LP_A0.bin Intel® CSME firmware image (Non-Production

FW) - supports un-fused Tiger Lake PCH-LP
Platform I/O MCP stepping:
• Un-fused (Super SKU)

Note: For PAVP Testing, you must match

Production FW with Production Part and
Non-Production FW with Non-Production
Parts.

[PCHC]

pchc_TGL_PCHC_15.0.0.xxxx.bin Un-signed PCH Configuration binary

pchc_TGL_PCHC_15.0.0.xxxx_signed.bin Signed PCH Configuration binary

[PMC]

TGPLP_Z0_PMC_FW_150.01.00.xxxx.bin PMC firmware binary

[TCSS]

[IOM]

iomfw_v10.000c.0.0_signed.bin IOM firmware binary

[PHY]

TcssPartition_v2.1017.bin PHY firmware binary

[Retimer]

BBR_CDR_A1_TGL_PORTS_0_1_rev2_2_sign.bin Retimer firmware binary for TCSS Ports 0 and 1

BBR_CDR_A1_TGL_PORTS_2_3_rev2_2_sign.bin Retimer firmware binary for TCSS Ports 2 and 3

[TBT]

TBT_TGL_A0_REV1_PRE16_signed.bin ThunderboltTM firmware binary

TGL-LP Consumer Bring Up Guide.pdf This document

TGL-LP Corporate Bring Up Guide.pdf

Tigerlake-LP Client SPI Programming Guide.pdf

[Tools]

[ICC Tools]

[ICC SDK]

[Windows64]

icc_sdk_api.h Integrated Clock Controller SDK API .H file

sdkLib.lib Integrated Clock Controller SDK Library file

[WDT Driver]

[ICCWDT_11.7.0.1000_19H1_Cert]

[Win7]

[ICCWDT.Dev.Install]

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Table 1-3. Kit Contents (Sheet 6 of 8)

File or [Directory] Content Description

[ICCWDT_Driver]

[x64]

iccwdt.sys

WdfCoInstaller01009.dll

iccwdt.cat

iccwdt.inf

iccwdt.sys

WdfCoInstaller01009.dll

[x64]

DIFxAPI.dll ICC Watch Dog Timer 64bit driver install

frameworks API DLL

Drv64.exe

DIFxAPI.dll ICC Watch Dog Timer 32bit driver install

frameworks API DLL

license.txt ICC Watch Dog Timer SDK License

Readme.txt ICC Watch Dog Timer Readme file

Setup.cfg ICC Watch Dog Timer Setup configuration file

setup.exe ICC Watch Dog Timer Setup executable

Setup.if2 ICC Watch Dog Timer IF2 file

[ICCWDT.Install]

[Win10]

[ICCWDT.Dev.Install]

[ICCWDT.Install]

Intel(R) ME Firmware ICC Tools User Guide.pdf Integrated Clock Controller Tools User guide

[System Tools]

[Documentation]

Signing and Manifesting User Guide.pdf Signing and Manifest Users Guide

SLA_TOOLS.PDF MEInfo and FWUpdLcl Redistribution License

TGL_System_Tools_UG.pdf System Tools User guide

VSCCommn_bin Content.pdf List of supported SPI Flash devices with specific

Flash parameters.

[FIT]

Windows32]

fit.exe Intel® Flash Image Tool

vsccommn.bin Binary containing the supported SPI parts.

[FPT]

[Efi64]

Fpt.efi 64bit uEFI Intel® Flash Programming Tool

executable.

[Windows64]

FPTW64.exe Windows 64bit Intel® Flash Programming Tool

executable.

Intel Confidential 16
 Introduction

Table 1-3. Kit Contents (Sheet 7 of 8)

File or [Directory] Content Description

Idrvdll32e.dll Windows DLL files for Intel® Flash Programming

Tool.
Pmxdll32e.dll

[FWUpdate]

[Efi64]

errorlist.c 64bit uEFI C Source and Library files for Firmware

Update.
errorlist.h

fwudef.h

FwUpdateEfiLib.lib

fwupdatelib.h

fwupdatelibdeprecated.h

FWUpdLcl.efi 64bit uEFI Firmware Update executable.

[Windows64]

errorlist.c Windows 64bit C Source and Library and Sample

code files for Firmware Update.
errorlist.h

fwudef.h

FwUpdateEfiLib.lib

fwupdatelib.h

fwupdatelibdeprecated.h

FWUpdateSample.c

FWUpdLcl64.exe Windows 64bit Firmware Update executable.

[FWUpdate_RS]

[Efi64]

errorlist.c Reduced size 64bit uEFI C Source and Library files

for Firmware Update.
errorlist.h

fwudef.h

FwUpdateEfiLib.lib

fwupdatelib.h

fwupdatelibdeprecated.h

FWUpdLcl.efi Reduced size 64bit uEFI Firmware Update

executable.

FWUpdLclApp.c Reduced size 64bit uEFI Firmware Update

Application sample.
FWUpdLclAppDeprecated.c

[MEInfo]

[Efi64]

MEInfo.efi 64bit uEFI Intel® ME Information executable.

[Windows64]

MEInfoWin64.exe Window 64bit Intel® ME Information executable.

Idrvdll32e.dll Windows DLL files for Intel® ME Information Tool.

Pmxdll32e.dll

[MEManuf]

[Efi64]

Intel Confidential 17
 Introduction

Table 1-3. Kit Contents (Sheet 8 of 8)

File or [Directory] Content Description

MEManuf.efi 64bit uEFI Intel® ME Manufacturing test tool

executable.

[Windows64]

MEManufWin64.exe Windows 64bit Intel® ME Manufacturing test tool

executable.

Idrvdll32e.dll Windows DLL files for Intel® ME Information Tool.

Pmxdll32e.dll

[MEU]

[Windows32]

meu.exe Windows 32bit Intel® Manifest Extension Utility

executable.

Intel Confidential 18
 Introduction

1.7 External Hardware Requirements for Bring Up

Acquire the following hardware tools before moving on to the next step.

Windows* OS System Flash Burner DOS Bootable USB Key

Equipment: Equipment: Equipment:

• Laptop or desktop that • (Optional) For platforms that • A DOS Bootable USB Key
supports win32 applications don’t boot, a Flash Chip (Size > 512 MB)
Programmer will be required
Purpose: • For platforms that can boot to Purpose:
• Will run firmware image DOS or Windows*, a Intel® • Acting as a bootable device
assembly and build process FPT is provided in this kit and will be used to run Intel®
software. FPT (fpt.exe) directly on the
Purpose: system that is undergoing
• Will burn firmware images Bring Up process.
onto the target system Flash • Or will be used to transfer a
device(s). firmware image onto a Flash
burner.

§§

Intel Confidential 19
Image Creation: Intel® Flash Image Tool

2 Image Creation: Intel® Flash

Image Tool

Intel® Flash Image Tool (Intel® FIT) can be used to generate either a full SPI Flash
binary image with Descriptor, GbE, BIOS, and Intel® ME Regions. Additionally, it can be
used to create a simple image containing only the Intel® ME Region only for use with
custom SPI Flash binary image assembly solutions. Use the steps shown in following
sections.

After this image has been created, it will need to be burned onto the target platform’s
SPI Flash device(s). Section 3, “Programming SPI Flash Devices and Checking
Firmware Status”later in this document provides steps to do this.

Note: The Flash Image Tool may be updated throughout the release cycles. As a general rule,
please ensure you use the tools, images and other content from the same kit and
refrain from using different version tools.

2.1 Start Intel®FIT

1. Invoke Intel® Flash Image Tool. Using Explorer*, navigate to
[root]\Tools\System Tools\Flash Image Tool. Verify that the directory
contents are correct (see Section 1.6). Double-click FIT.exe.
2. NOTE: In the tables below, where default settings are listed for TGL LP/H, if the
value is the same one value will be listed. If there is a different default value when
the program loads with either platform, both values will be listed to show the
difference.

2.2 Step-by-Step Guide to Build SPI Flash Image with

Intel® FIT Interface

Intel Confidential 20
Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 1 of 9)

# Label Contents

This button labeled ‘New’ on rollover allows opening of a new session with default
1 New
values

2 Open This button labeled ‘Open’ on rollover allows opening of an xml or bin file

3 Save This button labeled ‘Save’ on rollover allows saving of xml file

4 Clear Console This button labeled ‘Clear Console’ clears the console area (see page 23)

This button labeled ‘Build Settings’ brings up the build settings popup Window
5 Build Settings
see (Table 2-2)

6 Build Image This button labeled ‘Build Image’ on rollover allows build of the image

This button labeled ‘Build Image For FWUpdate’ allows the user to build separate
7 Build Image For FWUpdate
firmware update binaries.

Intel Confidential 21
Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 2 of 9)

# Label Contents

8 9 10

8 Drop Down Selector This drop down allows selection of platform

9 Drop Down Selector This drop down allows selection of SKU within platform selected

10 Indicator This displays the type of Boot Media Target based on FW being used

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Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 3 of 9)

# Label Contents

Intel Confidential 23
Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 4 of 9)

# Label Contents
Flash Layout which contains (see Table 2-3):
• Descriptor Region
11 • BIOS Region
• IFWI: Intel® ME and PMC Region
Flash Layout Tab • EC Region
• GBE Region
• SubPartitions
• PDR Region
Flash Settings which contains (see Table 2-4):
• Flash Components
12 • Host CPU/ BIOS Master Access
• Intel® ME Master Access

Flash Settings Tab

• GBE Master Access
• EC Master Access
• Flash Configuration
• Legacy VSCC Table - VSCC Entries
• BIOS Configuration
• FPF Configuration
Intel® ME Kernel which contains (see Table 2-5):
• Processor
13 • Intel® ME Firmware Update
• Image Identification
Intel® ME Kernel Tab • Firmware Diagnostics
• End of Manufacturing Configuration
• MCTP Configuration
• Intel® ME Boot Configuration
• Intel® ME Assisted Boot Configuration
• Reserved

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Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 5 of 9)

# Label Contents

Intel® AMT which contains (see Table 2-6):

• Intel® AMT Configuration
14 • KVM Configuration

Intel® AMT Tab

• Provisioning Configuration
• OEM Customizable Certificates (1, 2, 3)
• OEM Default Certificates (1, 2, 3, 4, 5)
• Redirection Configuration
• TLS Configuration
Platform Protection which contains (see Table 2-7):
• Content Protection
15 • Graphics uController
• Hash Key Configuration for Bootguard / ISH
• Boot Guard Configuration
• Type-C Firmware Anti-Rollback Configuration
Platform Protection Tab • Intel® PTT Configuration
• TPM Over SPI Bus Configuration
• BIOS Guard Configuration
• TXT Configuration
• Crypto Hardware Support
• Platform Trusted Device Setup Support
• Intel FPF Anti-Rollback Configuration
Integrated Clock Controller which contains (see Table 2-8):
• Integrated Clock Controller Policies
16 Integrated Clock Controller Tab
• Profiles

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Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 6 of 9)

# Label Contents
Networking & Connectivity which contains (see Table 2-9):
• Platform vPro NIC
17 Networking & Connectivity Tab
• Docking Station
• Wired LAN Configuration
• Wireless LAN Configuration
• Time Sensitive Networking Configuration

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Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 7 of 9)

# Label Contents

Internal PCH Buses which contains (see Table 2-10):

• PCH Timer Configuration
18 Internal PCH Buses Tab
• SMBus / SMLink Configuration
• DMI Configuration
• OPI /DMI Configuration
• eSPI Configuration
Power which contains (see Table 2-11):
• Platform Power
19 Power Tab
• Deep Sx
• PCH Thermal Reporting
Integrated Sensor Hub which contains (see Table 2-12):
• Integrated Sensor Hub
20 Integrated Sensor Hub Tab
• ISH Image
• ISH Data
• IPU Security (see Table 2-13):

21 Camera

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Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 8 of 9)

# Label Contents

Debug which contains (see Table 2-14):

• IDLM
22 • Delayed Authentication Mode Configuration
• Intel® Trace Hub Technology
Debug Tab • Intel® ME Firmware Debugging Overrides
• Direct Connection Interface Configuration
• eSPI Freature Overrides
• Early USB DBC over Type-A Configuration
• TRC Emulation
CPU Straps which contain a detailed list of parameters (see Table 2-15)
• CPU Straps
23 CPU Straps Tab

Flex I/O which contains (see Table 2-16):

• PCIe Lane Reversal Configuration
24 • PCIe Port Configuration

Flex I/O Tab

• SATA / PCIe Combo Port Configuration
• USB3 Port Configuration
• USB2 Port Configuration
• Type-C Subsystem Configuration
• Thunderbolt Configuration
GPIO which contains (see Table 2-17):
• ME Feature Pins
25 GPIO Tab • Touch Controller Pins
• GPIO VCCIO Voltage Control
• Thunderbolt LSx/BSSB-LS Configuration

Intel Confidential 28
Image Creation: Intel® Flash Image Tool

Table 2-1. - Initial Screen Layout (Sheet 9 of 9)

# Label Contents
Download and Execute which contains (see Table 2-18):
• DnX Configuration
26 Download and Execute
• USB Descriptor

FW Update Image Build which contains (see Table 2-19):

• Intel® Unique Platform ID Configuration
27 Intel® Unique Platform ID

FW Update Image Build which contains (see Table 2-20):

• ME Image
28 • PMC Image
• OEM KM Image

FW Update Image Build

• IOM Image
• NPHY Image
• TBT Image
• ISH Image
• INUIT Image
• PCHC Image
Console Window Area Displays opening messages, log file entries, and build activity messages

Intel Confidential 29
Image Creation: Intel® Flash Image Tool

Table 2-2. - Build Settings (Sheet 1 of 2)

Click on Build Button in the top menu bar> Build Settings window pop up is displayed:

10
11
12
13
14

15

# Parameter CRB Values

Output Path Double click to the right of outimage.bin and click to get browse button to
specify path and name of file to create for the build - default is

1 outimage.bin in the same folder as Intel® FIT tool

FWUpdate Output Path Double click to the right of FWUpdate.bin and click to get browse button to
specify path and name of file to create for the build - default is
2 FWUpdate.bin in the same folder as Intel® FIT tool

Build FWUpdate With No Yes/No - No is default

Full Image
3

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Image Creation: Intel® Flash Image Tool

Table 2-2. - Build Settings (Sheet 2 of 2)

Click on Build Button in the top menu bar> Build Settings window pop up is displayed:
Generate Intermediate Yes Yes/No - Yes is default
Files
4
Enable Boot Guard Yes Yes/No - Yes is default
warning message at
5 build time

Enable Intel (R) Yes Yes/No - Yes is default

Platform Trust
6 Technology warning
message at build time

Region Order Yes 53241 - is default

7
Yes 32-bit value to use as the IFWI build version number.

8 IFWI Build Version

Yes This setting enabled Redundancy support for critical layout components.

9 Redundancy Enabled

Disabled Enable data restore support to manufacturing defaults.

Factory Defaults
10 Restoration Status

Yes Enable Intel® CSE Default Data partition

Default Data Partition
11 Enabled

Yes
Intel® Manifest
12 Extension Utility Path

Yes

13 Signing Tool Path

Yes

14 Signing Tool

$WorkingDir and $DestDir can be left at the default ‘.’

Click on $SourceDir Value field and type in path where the Image

15 Components are located for the Manageability Engine kit

Click on Build Button in the top menu bar> Build Settings window pop up is displayed:

Intel Confidential 31
Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 1 of 6)

Click on Flash Layout in the left tabs menu> Descriptor Region is expanded by default:

# Parameter Platform Settings

OEM Section Binary UP4 OEM Binary
This loads the OEM Section binary that will be merged into the output image UP3 (optional)

1 generated by the Intel® FIT tool.

Click on Flash Layout in the left tabs menu> BIOS Region is expanded by default:

# Parameter Platform Settings

BIOS Region

2
BIOS Region - Length -This displays the length of the BIOS binary.
Note: This value will be automatically populated by Intel® FIT during image
build.
BIOS Binary File UP4 biosimage.bin
Navigate to path to load bios.rom file. This loads the BIOS binary that will be UP3 biosimage.bin
merged into the output image generated by the Intel® FIT tool.
Click on Flash Layout in the left tabs menu> Ifiw: Intel® ME and PMC Region is expanded by default:

Intel Confidential 32
Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 2 of 6)

# Parameter Platform Settings

Ifwi: Intel® ME and PMC Region

3
Intel® CSME Binary File UP4 meimage.bin
Navigate to your Source Directory (as specified in Table 2-2) and switch to the UP3 meimage.bin
Intel® CSME subdirectory. Choose the appropriate Intel® CSME Firmware binary
image. This loads the Intel® CSME binary that will be merged into the into the
output image generated by the Intel® FIT tool.
Note: You may choose to build the Intel® CSME Region only. To do so, the Number
of Flash Components in Flash Settings> Flash Components must be set to 0.
Note: If loading meimage.bin file, check that the ME region is enabled in tool
before building image.
Major Version - This displays Major revision number of the currently loaded Intel®
CSME binary.
Minor Version - This displays Minor revision number of the currently loaded Intel®
CSME binary.
Hotfix Version - This displays Hot-Fix revision number of the currently loaded
Intel® CSME binary.
Build Version - This displays Build version number of the currently loaded Intel®
CSME binary.
Chipset Initialization Version - This displays the current Chipset Initialization
version contained in the currently loaded Intel® CSME binary.

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Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 3 of 6)

Chipset Initialization Binary - This loads the Chipset Initialization binary that will UP4 Chipset.bin
be merged into the output image generated by the Intel® FIT. If specified, this will UP3 (Optional)
override the version contained in the Intel® CSME binary to align with the values Chipset.bin
programmed by BIOS. (Optional)

Note: When BIOS passes new Chipset Initialization settings to ME, a Global Reset
is initiated (only required on the first boot, subsequent boots will not incur
a global reset). This allows for the new settings to be stored in the ME
Region and programmed into the PCH. This global reset can be avoided by
loading the proper chipset initialization binary in to the ME Region when
building the image that aligns with the values in BIOS. The Chipset
Initialization Binary will be included in BIOS RC package. If BIOS contains
an older version of Chipset Initialization settings ME will be updated at boot
with the older settings regardless of any newer settings being present in
firmware. In order to avoid this problem and the additional Global Reset
customers should ensure that both BIOS and ME are updated with same
Chipset Initialization binary.
ChipsetInit Override Version - This displays the version of the Chipset
Initialization Binary override if specified.
PMC Binary File - This loads the PMC binary that will be merged into the output UP4 PMC.bin
image generated by the Intel® FIT tool. UP3 PMC.bin

PMC Length - This displays the length of the PMC binary.

Note: This value will be automatically populated by Intel® FIT during image
build.
Version - This displays the version of PMC
Enables NFTP resize for FTPR loading - Used to enable resize for FTPR loading UP4 Enabled
to perform firmware update process. UP3 Enabled

Note: Disable for SKUs and platforms with limited image size, without planned
firmware update support only.
Click on Flash Layout in the left tabs menu> EC Region is expanded by default:

# Parameter Platform Settings

EC Region UP4 0
UP3 0
4
EC Region - Length
Note: This value will be automatically populated by Intel® FIT during image
build.
EC Binary File UP4 EC Binary
Navigate to path to load EC bin file. This loads the Embedded Controller binary used UP3 EC Binary
for eSPI that will be merged into the output image generated by the Intel® FIT tool.
EC Region Enable UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This option allows the user to enable or disable the Embedded Controller data
region.

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Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 4 of 6)

EC Region Pointer File UP4 EC Pointer

This loads a binary file containing the 16 byte Embedded Controller pointer value at UP3 Binary
the start of the flash descriptor EC Pointer
Binary
Click on Flash Layout in the left tabs menu> GbE Region is expanded by default:

# Parameter Platform Settings

GbE Region
This loads the Intel® Integrated LAN binary that will be merged into the output
5 image generated by the Intel® FIT tool.

GbE Region - Length

Note: This value will be automatically populated by Intel® FIT during image
build.
GbE Binary File UP4 gbeimage.bin
Navigate to your Source Directory (as specified in Table 2-2) and switch to the UP3 gbeimage.bin
GbE subdirectory. Choose the appropriate Intel GbE LAN Firmware binary image. If
not using Intel LAN then load the GbE image before disabling the region
along with changing additional settings below. This loads the Intel®
integrated LAN binary that will be merged into the output image generated by the
Intel® FIT tool.
Note: If loading gbeimage.bin file, check that the GbE region is enabled in tool
before building image.
GbE Region Enable UP4 Enabled
Values: Enabled/Disabled - This option allows the user to enable or disable the UP3 Enabled
Gigabit Ethernet Region.
NOTE: If choosing a configuration that does not include the GbE LAN the
following settings need to be adjusted:

LAN Power Well: Core Well

Intel® Integrated Wired LAN Enabled: No
GbE MAC SMBus Address: No
Intel® PHY over PCIe Enabled: No
LAN PHY Power Control GDP11 Signal Configuration: Enable as GDP11
Image Id - This displays the Image ID of the currently loaded Intel® Integrated
LAN binary.
Major Version - This displays the Major revision number of the currently loaded
Intel® Integrated LAN binary.
Minor Version - This displays the Minor revision number of the currently loaded
Intel® Integrated LAN binary.
Click on Flash Layout in the left tabs menu> IUnit Sub-Partion is expanded by default:

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Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 5 of 6)

# Parameter Platform Settings

IUNIT Sub-Partition Binary UP4 Iunit.bin
This loads the IUnit Sub Partition binary that will be merged into the output image UP3 (Optional)

6 generated by the Intel® FIT tool. Iunit.bin

(Optional)
Length - This displays the length of the IUNIT Sub-Partition.
Note: This value will be automatically populated by Intel® FIT during image
build.
Version - This displays the version number of the IUNIT Sub-Partition
Click on Flash Layout in the left tabs menu> PCH Configuration Sub-Partion is expanded by default:

# Parameter Platform Settings

PCH Configuration Sub-Partition

7
This loads the PCH Configuration binary that will be merged in the output image
generated by the Intel® FIT tool.

PCH Configuration File UP4 PCHC.bin

Navigate to path to load PCHC.bin file. This loads the PCH Configuration binary. UP3 PCHC.bin
Version - This displays the version number of the PCHC Configuration Sub-
Partition
Length - This displays the length of the PCH Configuration Sub-Partition.
Note: This value will be automatically populated by Intel® FIT during image
build.
Click on Flash Layout in the left tabs menu> GBST Configuration Sub-Partion is expanded by default:

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Image Creation: Intel® Flash Image Tool

Table 2-3. - Flash Layout (Sheet 6 of 6)

# Parameter Platform Settings

GBST Configuration Sub-Partition
This loads the GBST Configuration binary that will be merged in the output image
8 generated by the Intel® FIT tool.

Note: The GBST sub-partition is used for FuSa safety standards and are
not applicable for client platforms.
GBST Configuration File UP4 GBST.bin
Navigate to path to load GBST.bin file. This loads the GBST Configuration binary. UP3 (Optional)
Version - This displays the version number of the GBST Configuration Sub-
Partition
Length - This displays the length of the GBST Configuration Sub-Partition.
Note: This value will be automatically populated by Intel® FIT during image
build.
Click on Flash Layout in the left tabs menu> PDR Region is expanded by default:

# Parameter Platform Settings

PDR Region - This loads the Platform Data region binary that will be merged into
the output image generated by the Intel® FIT tool.
9
PDR Region - Length
Region is disabled by default. Displays Region size information when Binary input
file is specified.
PDR Binary File UP4 PDR.bin
Navigate to path to load pdrimage.bin file if required and available. UP3 (Optional)
PDR.bin
(Optional)
PDR Region Enable UP4 Disabled
Values: Enabled/Disabled - This option allows the user to enable or disable the UP3 Disabled
Platform Data Region.
Note: If loading PDR.bin file, check that the PDR region is enabled in tool before
building image.

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Image Creation: Intel® Flash Image Tool

Table 2-4. - Flash Settings (Sheet 1 of 10)

Click on Flash Settings in the left tabs menu> Flash Components is expanded by default:

# Parameter Platform Settings

Flash Components

1
Number of Components UP4 1
Values: 0, 1, 2 - This setting configures the total number of flash components for UP3 1
the platform. Note: Choosing a selection of '0' part will cause the Intel® FIT tool to
build an output image containing only the Intel® ME region.
Flash component 1 Size UP4 32MB
Values: 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB - This setting UP3 32MB
determines the size of Flash component 1 for the platform image.
Flash component 2 Size UP4 Greyed Out
Values: 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB - This setting UP3 Greyed Out
determines the size of Flash component 2 for the platform image. Note: This
setting is only applicable when the Number of Flash Components option is set to '2'.
SPI Global Protected Range - This sets the default value of the Global Protected UP4 0x0
Range register in the SPI Flash Controller. UP3 0x0
SPI Idle to Deep Power Down Timeout - This sets SPI Idle to Deep Power Down UP4 0x5
Timeout Default Specifies the time in microseconds that the Flash Controller waits UP3 0x5
after all activity is idle before commanding the flash devices to Deep Power down,
time = 2^N microseconds.
SPI Out of Order operation Enabled - When this setting is enabled priority UP4 Yes
operations may be issued while waiting for write / erase operations to complete on UP3 Yes
the flash device. When this setting is disabled all write / erase type operations in
order.
SPI Resume Hold-off Delay - This specifies the time after the completion of a UP4 4us
pri_op before the flash controller sends the resume instruction. If a new pri_op is UP3 4us
eligible to be issued prior to the end of this delay time then the pri_op is issued
and the timer is reinitialized to tRHD. 3-bit field encodes count with range 0-7.
tRHD = count * 2us.

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Image Creation: Intel® Flash Image Tool

Table 2-4. - Flash Settings (Sheet 2 of 10)

SPI Max write / erase Resume to Suspend intervals - This setting specifies UP4 No Ceiling
the maximum value for the write and erase Resume to Suspend intervals. UP3 No Ceiling
SPI Suspend / Resume Enabled - When this setting is enabled writes and erases UP4 Yes
may be suspended to allow a read to be issued on the flash device. When this UP3 Yes
setting is disabled no transaction will be allowed to the busy flash device.
Software Re-Binding Enabled UP4 No
Values: Yes / No UP3 No
When enabled this settings will allow for SPI re-binding to a new PCH during
manufacturing and re-manufacturing flows prior to platform EOM.

Note: Re-binding to a replacement PCH can only be done a maximum of 5 times

before the SPI part needs to be re-flashed.
Click on Flash Layout in the left tabs menu> BIOS Region is expanded by default:

# Parameter Platform Settings

Host CPU / BIOS Master Access

2
Host CPU / BIOS Write Access Intel Recommended UP4 0xFFFF
Values: 0xFfFF, 0x000A, 0x001A, 0x010A, 0x011A - This setting determines UP3 0xFFFF
write access control for the BIOS region.
0xFfFF = Debug/Manufacturing
0x000A = Production
0x001A = Production with access to PDR (should ONLY be used if PDR region is
implemented).
0x010A = Production with access to EC
0x011A = Production with access to EC and PDR
Custom = User custom Host / BIOS Write Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
Host CPU / BIOS Write Access Custom - This setting allows free form user UP4 Hex Input
customized Host CPU / BIOS Write Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the Host CPU /
BIOS Write Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security

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Image Creation: Intel® Flash Image Tool

Table 2-4. - Flash Settings (Sheet 3 of 10)

Host CPU / BIOS Read Access UP4 0xFFFF

Values: 0xFFF, 0x00F, 0x01F, 0x10F, 0x11F - This setting determines read UP3 0xFFFF
access control for the BIOS region.
0xFFF = Debug/Manufacturing
0x00F = Production
0x01F = Production with access to PDR (should ONLY be used if PDR region is
implemented).
0x10F = Production with access to EC
0x11F = Production with access to EC and PDR
Custom = User custom Host / BIOS Read Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide.
Host CPU / BIOS Read Access Custom - This setting allows free form user UP4 Hex Input
customized Host CPU / BIOS Read Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the Host CPU /
BIOS Read Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security
Click on Flash Settings in the left tabs menu> Intel® ME Master Access is expanded by default:

# Parameter Platform Settings

Intel® ME Master Access

3
Intel® ME Write Access Intel Recommended UP4 0xFFFF
Values: 0xFFFF, 0x0004- This setting determines write access control for the ME UP3 0xFFFF
region.
0xFFFF = Debug/Manufacturing
0x0004 = Production
Custom = User custom Intel® ME Write Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
Intel® ME Write Access Custom - This setting allows free form user customized UP4 Hex Input
Intel® ME Write Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the Intel® ME
Write Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security

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Image Creation: Intel® Flash Image Tool

Table 2-4. - Flash Settings (Sheet 4 of 10)

Intel® ME Read Access Intel Recommended UP4 0xFFFF

Values: 0xFFFF, 0x000D - This setting determines read access control for the ME UP3 0xFFFF
region.
0xFFFF = Debug/Manufacturing
0x000D = Production
Custom = User custom Intel® ME Read Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
Intel® ME Read Access Custom - This setting allows free form user customized UP4 Hex Input
Intel® ME Read Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the Intel® ME
Read Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security
Click on Flash Settings in the left tabs menu> GbE Master Access is expanded by default:

# Parameter Platform Settings

GbE Master Access

4
GbE Write Access Intel Recommended UP4 0xFFFF
Values: 0xFFFF, 0x0008 - This setting determines write access control for the UP3 0xFFFF
Gigabit Ethernet Region.
0xFFFF = Debug/Manufacturing
0x0008 = Production
Custom = User custom GbE Write Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
GbE Write Access Custom - This setting allows free form user customized GbE UP4 Hex Input
Write Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the GbE Write
Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security

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Table 2-4. - Flash Settings (Sheet 5 of 10)

GbE Read Access Intel Recommended UP4 0xFFFF

Values: 0xFFFF, 0x0009 - This setting determines read access control for the UP3 0xFFFF
Gigabit Ethernet Region.
0xFFFF = Debug/Manufacturing
0x0009 = Production
Custom = User custom GbE Read Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
GbE Read Access Custom - This setting allows free form user customized GbE UP4 Hex Input
Read Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the GbE Read
Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security
Click on Flash Settings in the left tabs menu> EC Master Access is expanded by default:

# Parameter Platform Settings

EC Master Access

5
EC Write Access Intel Recommended UP4 0xFFFF
Values: 0xFFFF, 0x0100 - This setting determines write access control for the UP3 0xFFFF
Embedded Controller Region.
0xFFFF = Debug/Manufacturing
0x0100 = Production
Custom = User custom EC Write Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
EC Write Access Custom - This setting allows free form user customized EC Write UP4 Hex Input
Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the EC Write
Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security

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Table 2-4. - Flash Settings (Sheet 6 of 10)

EC Read Access Intel Recommended UP4 0xFFFF

Values: 0xFFFF, 0x0101, 0x0103 - This setting determines read access control UP3 0xFFFF
for the Embedded Controller Region.
0xFFFF = Debug/Manufacturing
0x0101 = Production
0x0103 = Production with EC BIOS Read Access
Custom = User custom EC Read Access values

For further details on Region Access Control see Tiger Lake LP SPI Programming
guide further details.
EC Read Access Custom - This setting allows free form user customized EC Read UP4 Hex Input
Access regions permissions UP3

Note: This setting is grayed out unless Custom is selected under the EC Read
Access Intel Recommended drop down menu.

Warning: Setting region access permission values outside of Intel

recommendation could result in compromised platform
security
Click on Flash Layout in the left tabs menu> IUnit Sub-Partion is expanded by default:

# Parameter Platform Settings

Flash Configuration

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Table 2-4. - Flash Settings (Sheet 7 of 10)

Dual I/O Read Enabled UP4 Yes

Values: Yes/No - This setting allows the customer to enable support for Dual I/O UP3 Yes
Read capabilities for flash components. See Tiger Lake LP SPI Programming guide
for further details.
Dual Output Read Enabled UP4 Yes
Values: Yes/No - This setting allows the customer to enable support for Dual UP3 Yes
Output Read capabilities for flash components. See Tiger Lake LP SPI Programming
guide for further details.
Fast Read Clock Frequency UP4 50MHz
Values: 14MHz, 25MHz, 33MHz, 50MHz, 100MHz- This setting allows the UP3 50MHz
customer to configure the flash component clock frequency setting for Fast Read.
See Rocket Lake LP SPI Programming guide for further details.
Note: The 100MHz frequency setting not valid on client platforms
Fast Read Supported UP4 Yes
Values: Yes/No - This setting allows the customer to enable support for Fast Read UP3 Yes
capabilities for flash components. See Tiger Lake LP SPI Programming guide for
further details.
Note: If fast read supported is set to “No” any changes made to Dual I/O, Quad I/
O, Dual Output, or Quad Output will not be affected if set to yes. Fast read
supported should also be set to enable frequencies greater than 20MHz.
Invalid Instruction 0 - This setting allows the customer to configure invalid UP4 0x00000021
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x00000021
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 1 - This setting allows the customer to configure invalid UP4 0x00000042
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x00000042
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 2 - This setting allows the customer to configure invalid UP4 0x00000060
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x00000060
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 3 - This setting allows the customer to configure invalid UP4 0x000000AD
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x000000AD
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 4 - This setting allows the customer to configure invalid UP4 0x000000B7
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x000000B7
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 5 - This setting allows the customer to configure invalid UP4 0x000000B9
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x000000B9
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 6 - This setting allows the customer to configure invalid UP4 0x000000C4
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x000000C4
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Invalid Instruction 7 - This setting allows the customer to configure invalid UP4 0x000000C7
instruction to protect against Chip Erase. See Tiger Lake LP SPI Programming guide UP3 0x000000C7
for further details. Note: This setting should be set to '0' if there are not Invalid
instructions.
Quad I/O Read Enabled UP4 Yes
Values: Yes/No - This setting allows the customer to enable support for Quad I/O UP3 Yes
Read capabilities for flash components. See Tiger Lake LP SPI Programming guide
for further details.
Quad Output Read Enabled UP4 Yes
Values: Yes/No - This setting allows the customer to enable support for Quad UP3 Yes
Output Read capabilities for flash components. See Tiger Lake LP SPI Programming
guide for further details.

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Table 2-4. - Flash Settings (Sheet 8 of 10)

Read ID and Read Status clock frequency UP4 50MHz

Values: 14MHz, 25MHz, 33MHz, 50MHz, 100MHz- This setting allows the UP3 50MHz
customer to configure the flash component clock frequency setting for Read ID and
Read Status clock. See Rocket Lake LP SPI Programming guide for further details.
Note: The 100MHz frequency setting not valid on client platforms
Write and Erase clock frequency UP4 50MHz
Values: 14MHz, 25MHz, 33MHz, 50MHz, 100MHz- This setting allows the UP3 50MHz
customer to configure the flash component clock frequency setting for Write and
Erase. See Rocket Lake LP SPI Programming guide for further details.
Note: The 100MHz frequency setting not valid on client platforms
Click on Flash Settings in the left tabs menu> Legacy VSCC Table is expanded by default:

# Parameter Platform Settings

Legacy VSCC Table

7
VSCC Entries

W25Q128BV
VSCC Entries UP4
UP3

8
Name - This setting allow the OEM input a name designation for each flash UP4 Winbond
component being used. Note: This is a free form entry field it does not affect actual UP3 Winbond
flash component operation.
Vendor ID - This configures the JEDEC vendor specific byte ID of the SPI flash UP4 0xEF
component. See Tiger Lake LP SPI Programming guide for further details. UP3 0xEF
device ID 0 - This configures the JEDEC device specific byte ID 0 of the SPI flash UP4 0x40
component. See Tiger Lake LP SPI Programming guide for further details. UP3 0x40
device ID 1 - This configures the JEDEC device specific byte ID 1 of the SPI flash UP4 0x19
component. See Tiger Lake LP SPI Programming guide for further details. UP3 0x19
+ Add VSCC Entry

9
Click on Flash Settings in the left tabs menu> BIOS Configuration is expanded by default:

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Table 2-4. - Flash Settings (Sheet 9 of 10)

10

# Parameter Platform
BIOS Configuration

10
BIOS Redundancy Assistance UP4 Disabled
Values: Enabled, Disabled UP3 Disabled
In cases of BIOS boot failure, Intel®CSME will configure the platform to boot with
backup BIOS using Top Swap when this setting is enabled.

Note: This option is only applicable when Boot Guard is enabled.

Top Swap Block Size UP4 128KB
Values: 64KB, 128KB, 256KB, 512KB, 1MB - This configures the Top Swap UP3 128KB
Block size for the platform. For further details see Tiger Lake LP Platform Controller
Hub EDS.
BIOS Boot Select UP4 Boot from SPI
Values: Boot from SPI / Boot from LPC UP3 Boot from SPI
This setting determines if BIOS will be booted from LPC or SPI.
Click on Flash Settings in the left tabs menu> BIOS Configuration is expanded by default:

11

FPF Configuration

11
Hardware Binding Enabled UP4 Disabled
Values: Enabled / Disabled UP3 Disabled

This setting configures the FPF Hardware binding behavior for the platform image.
If this setting is enabled FPF Hardware binding will occur when platform close
manufacturing flow is executed with Intel® FPT. If this setting is disabled FPF
Hardware binding will not take place when close manufacturing flow is executed.

For Revenue parts this setting will be ignored and FPF Hardware binding will take
place when close manufacturing flow is executed.
Click on Flash Settings in the left tabs menu> RPMC Configuration is expanded by default:

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Table 2-4. - Flash Settings (Sheet 10 of 10)

12

RPMC Configuration

12
RPMC Supported UP4 No
Values: Yes / No UP3 No

This setting determines if RPMC is enabled.

Note: The SPI parts being used need to support RPMC In order to use this
feature.
RPMC Rebinding Enabled UP4 No
Values: Yes / No UP3 No

This setting determines if Rebinding of RPMC enabled SPI parts is enabled.

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Table 2-5. - Intel® ME Kernel (Sheet 1 of 5)

Click on Intel® ME Kernel in the left tabs menu> Processor is expanded by default:

# Parameter Platform Settings

Processor

1
Processor Emulation UP4 EMULATE Intel®
Values: No Emulation UP3 Core (TM)
branded
EMULATE Intel® vPro (TM) capable Processor
Processor
EMULATE Intel® Core (TM) branded Processor
EMULATE Intel®
EMULATE Intel® Celeron (R) branded Processor Core (TM)
EMULATE Intel® Pentium (R) branded Processor branded
EMULATE Intel® Xeon (R) branded Processor Processor
EMULATE Intel® Xeon (R) Manageability capable Processor
This setting determines processor type to be emulated on pre-production silicon.
Set this parameter to the type of processor that the target system will use during
production. This field will emulate that processor class for pre-production silicon. It
is necessary to set this to Emulate Intel® vPro™ Processor in order to enable Intel®
AMT.
Click on Intel® ME Kernel in the left tabs menu> Intel® ME Firmware Update is expanded by default:

# Parameter Platform Settings

Intel® ME Firmware Update

2
Firmware Update OEM ID - This setting allows configuration of an OEM unique ID UP4 0 string
to ensure that customers can only update their platform with images from the OEM UP3 0 string
of the platform.
Hide Intel® MEBx Firmware Update Control UP4 No
Values: Yes/No - This setting allows the customer to hide the Firmware Update UP3 No
option in the Intel® MEBx interface.
Intel® ME Region Flash Protection Override UP4 Yes
Values: Yes/No - This setting enables descriptor unlock of the Intel® CSME UP3 Yes
Region when the HMRFPO message is sent to firmware prior to BIOS End of POST.
Click on Intel® ME Kernel in the left tabs menu> Image Identification is expanded by default:

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Table 2-5. - Intel® ME Kernel (Sheet 2 of 5)

# Parameter Platform Settings

Image Identification

3
OEM Tag - This is a free form 32bit field that allows the OEM to configure their own UP4 0x00000000
unique identifier in the firmware image. UP3 0x00000000
Click on Intel® ME Kernel in the left tabs menu> Firmware Diagnostics is expanded by default:

# Parameter Platform Settings

Firmware Diagnostics

4
Automatic Built in Self Test UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
This setting enables the firmware Automatic Built in Self Test which is executed
during first platform boot after initial image flashing.
Click on Intel® ME Kernel in the left tabs menu> End of Manufacturing Configuration is expanded by default:

# Parameter Platform Settings

End of Manufacturing Configuration

5
EOM of First Boot Enabled UP4 No
Value: Yes/No UP3 No
This setting determines if End of Manufacturing will be triggered on first boot of the
platform after flashing. Note: When this setting is enabled Intel® CSME will enter
End of Manufacturing regardless of the descriptor settings.

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Table 2-5. - Intel® ME Kernel (Sheet 3 of 5)

Flexible EOM setting options UP4 Lock Descriptor

Value: Lock Descriptor and OEM Configs/Lock OEM Configs Only/Lock UP3 and OEM
Descriptor Only/Do not lock Descriptor and OEM Configs Configs
This setting determines which settings will be automatically committed during End
of Manufacturing flows. Note: The FPFs, RPMB / RPMC and set manufacturing mode
settings are mandatory and cannot be overridden revenue parts. Simulation can be
done on non-revenue part with the Hardware binding set to disabled.
Click on Intel® ME Kernel in the left tabs menu> MCTP Configuration is expanded by default:

# Parameter Platform Settings

MCTP Configuration

6
MCTP Stack Configuration UP4 0x920030
Defines the Intel® ME’s 8-bits MCTP Endpoint ID’s for each SMBus physical UP3 0x920030
interface (SMBus, SMLink0, and SMLink1). These values are needed for FW to
communicate with MCTP end points. For each of these 3 bytes, a value of 0x00
means not used, and values 0xFF or 0x01 - 0x07 or 0x20 - 0x2F are not allowed.
MctpdevicePortEc UP4 0x02
UP3 0x02
MctpdevicePortSio UP4 0x00
UP3 0x00
MctpdevicePortIsh UP4 0x00
UP3 0x00
MctpdevicePortBmc UP4 0x00
UP3 0x00
Click on Intel® ME Kernel in the left tabs menu> Intel® ME Boot Configuration is expanded by default:

# Parameter Platform Settings

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Table 2-5. - Intel® ME Kernel (Sheet 4 of 5)

Intel® ME Boot Configuration

7
Persistent PRTC Backup Power UP4 Exists
Values: None / Exists UP3 Exists
FPF that indicates if the device is designed such that it may lose PRTC power more
than 10 times throughout the normal life-cycle of the product and hence has no
persistent time or AR protection. At EOM this value is burned to the FPF, and can
never be changed
Click on Intel® ME Kernel in the left tabs menu> Intel® ME Measured Boot Configuration is expanded by default:

Intel® ME Measured Boot Configuration

8
Intel® ME Measured Boot State UP4 Disabled
Values: Disabled / EnabledIntel® UP3 Disabled
When measured boot is enabled firmware will use additional extended registers for
all IUPs and Key Manifests that firmware loads and verifies from flash. When
measured boot is enabled any IUPs or firmware updates will require a global reset.

Note: Leave this setting configured to “Disabled”

Click on Intel® ME Kernel in the left tabs menu> Intel® ME Assisted Boot Configuration is expanded by default:

Intel® ME Assisted Boot Configuration

9
Intel® ME Assisted BIOS Boot UP4 Normal
Values: Normal / Intel® ME Assisted UP3 Normal
This setting configures Intel® ME Assisted BIOS Boot capabilities.

Note: Leave this setting configured to “Normal”

Click on Intel® ME Kernel in the left tabs menu> Reserved is expanded by default:

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Table 2-5. - Intel® ME Kernel (Sheet 5 of 5)

10

Reserved

10
Reserved UP4 No
Values: Yes/No UP3 No

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Table 2-6. - Intel® AMT (Sheet 1 of 8)

Click on Intel® AMT in the left tabs menu> Intel® AMT is expanded by default:

# Parameter Platform Settings

Intel® AMT Configuration

1
Intel® AMT Supported UP4 No
Values: Yes/No - This setting allows customers to disable Intel® AMT on the UP3 No
platform and force the platform into Standard Manageability mode.

Note: If this setting has been set to disabled Intel® AMT cannot be re-enabled
once the descriptor has been locked. This setting applies to Desktop and
Workstation only.
Manageability Application Hardware Status UP4 Enabled
Values: Enabled / Disabled - This setting will permanently disable Manageability UP3 Enabled
hardware through platform FPFs. At End-of-Manufacturing (EOM), enable/disable
policy value is committed to FPF and can never be changed. Permanently disabling
Manageability hardware with this setting requires “Manageability Application
Supported” and “Disabled” and “Intel® ME Network Services Supported” are set to
“No”.
Note: When “Manageability Application Hardware Status” is Enabled but
“Manageability Application Supported” and “Intel® ME Network Services
Supported” are set to “No”, Manageability Hardware will be disabled by the
Intel®CSME through CVAR.
Intel® ME Network Services Supported UP4 No
Values: Yes/No - This setting allows customers to enable / disable Intel® ME UP3 No
Network Services on the platform.

Note: This setting and TLS needs to be enabled for proper operation of Intel®
Authenticate (Corporate Only). In addition if this setting is disabled Intel®
AMT will also be disabled.
Intel® Manageability Application Supported UP4 No
Values: Yes/No - This setting allows customers to force Intel® AMT enabled UP3 No
platforms to operate in Standard Manageability mode.

Note: This setting only applies to Desktop and Workstation platforms.

Manageability Application initial power-up state UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
This setting allows customers to determine the power up state for Intel® AMT or
Standard Manageability.

Note: If this setting is disabled Intel® AMT or Standard Manageability can still be
re-enabled through the Intel® MEBx interface.

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Table 2-6. - Intel® AMT (Sheet 2 of 8)

# Parameter Platform Settings

Intel® AMT Idle Timeout UP4 0xFFFF
Values: 0xFFFF - This setting configures the idle timeout value before Intel® AMT UP3 0xFFFF
enters into an off state.
Intel® AMT Watchdog Automatic Reset Enabled UP4 No
Values: Yes/No - This setting allows customers to enable the Intel® ME firmware UP3 No
to trigger an automatic platform reset if either the MEI or Agent Presence are in a
hung state.

Note: This feature only allows one reset at a time when the watchdog expires.
After this feature has triggered a reset, it must be re-armed for reuse via
management console.
Click on Intel® AMT in the left tabs menu> KVM Configuration is expanded by default:

# Parameter Platform Settings

KVM Configuration

2
Firmware KVM Screen Blanking UP4 No
Values: Yes/No - This setting enables KVM Screen blanking capabilities in the UP3 No
firmware image.

Note: This feature is dependent on processor level support.

KVM Redirection Supported UP4 No
Values: Yes/No - This setting allows OEMs to enable / disable the KVM UP3 No
Redirection capabilities of the firmware.

Note: If this setting has been set to disabled it cannot be re-enabled once the
descriptor has been locked.
Click on Intel® AMT in the left tabs menu> Provisioning Configuration is expanded by default:

# Parameter Platform
Provisioning Configuration

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Table 2-6. - Intel® AMT (Sheet 3 of 8)

Embedded Host Based Configuration UP4 No

Values: Yes/No - This setting allows customers to enable / disable Embedded UP3 No
Host Based Configuration. Important - EHBC is primarily intended for use in
embedded systems as it offers less user privacy/security protection than may be
appropriate for business client systems.

Note: The Intel® FIT tool will not adjust the Redirection Privacy/Security value
based on selection here. Please set security level as needed.
PKI Domain Name Suffix - This setting allow OEMs to pre-configure the Domain UP4 -
Name Suffix used for PKI provisioning in their firmware image. UP3 -

Note: For normal out-of-box provisioning functionality this setting should be left
empty.
Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 1 is expanded by default:

# Parameter Platform Settings

OEM Customizable Certificate 1

4
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Custom UP3 No
Certificate 1.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Custom Certificate 1. Maximum of 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning Custom Certificate 1. If enabled the certificate will be used in addition UP3 -
to those already pre-loaded in base firmware during provisioning.

Note: If the platform is un-configured the Custom Certificate Hash will be

deleted.
Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 2 is expanded by default:

# Parameter Platform Settings

OEM Customizable Certificate 2

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Table 2-6. - Intel® AMT (Sheet 4 of 8)

Certificate Enabled UP4 No

Values: Yes/No - This setting allows customers to enable PKI provisioning Custom UP3 No
Certificate 2.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Custom Certificate 2. Maximum of 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning Custom Certificate 2. If enabled the certificate will be used in addition UP3 -
to those already pre-loaded in base firmware during provisioning.

Note: If the platform is un-configured the Custom Certificate Hash will be

deleted.
Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 3 is expanded by default:

# Parameter Platform Settings

OEM Customizable Certificate 3

6
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Custom UP3 No
Certificate 3.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Custom Certificate 3. Maximum 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning Custom Certificate 3. If enabled the certificate will be used in addition UP3 -
to those already pre-loaded in base firmware during provisioning.

Note: If the platform is un-configured the Custom Certificate Hash will be

deleted.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 1 is expanded by default:

# Parameter Platform Settings

OEM Default Certificate 1

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Table 2-6. - Intel® AMT (Sheet 5 of 8)

Certificate Enabled UP4 No

Values: Yes/No - This setting allows customers to enable PKI provisioning Default UP3 No
certificate 1.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Default Certificate 1. Maximum 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning custom certificate 1. UP3 -

Note: Default Certificates if enabled will be used in addition to those already pre-
loaded in firmware during provisioning. Unlike Customizable Certificates
the Default Certificates are not deleted when the platform is un-
provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 2 is expanded by default:

# Parameter Platform Settings

OEM Default Certificate 2

8
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Default UP3 No
certificate 2.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Default Certificate 2. Maximum 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning custom certificate 2. UP3 -

Note: Default Certificates if enabled will be used in addition to those already pre-
loaded in firmware during provisioning. Unlike Customizable Certificates
the Default Certificates are not deleted when the platform is un-
provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 3 is expanded by default:

# Parameter Platform Settings

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Table 2-6. - Intel® AMT (Sheet 6 of 8)

OEM Default Certificate 3

9
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Default UP3 No
certificate 3.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Default Certificate 3. Maximum 32 characters. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning custom certificate 3. UP3 -

Note: Default Certificates if enabled will be used in addition to those already pre-
loaded in firmware during provisioning. Unlike Customizable Certificates
the Default Certificates are not deleted when the platform is un-
provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 4 is expanded by default:

10

# Parameter Platform Settings

OEM Default Certificate 4

10
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Default UP3 No
certificate 4.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Default Certificate 4. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning custom certificate 4. UP3 -

Note: Default Certificates if enabled will be used in addition to those already pre-
loaded in firmware during provisioning. Unlike Customizable Certificates
the Default Certificates are not deleted when the platform is un-
provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 5 is expanded by default:

11

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Table 2-6. - Intel® AMT (Sheet 7 of 8)

# Parameter Platform Settings

OEM Default Certificate 5

11
Certificate Enabled UP4 No
Values: Yes/No - This setting allows customers to enable PKI provisioning Default UP3 No
certificate 5.
Certificate Friendly Name - This setting allows customers to assign a user UP4 -
friendly name for PKI provisioning Default Certificate 5. UP3 -
Certificate Stream - This setting allows customers to input hash stream for PKI UP4 -
provisioning custom certificate 5. UP3 -

Note: Default Certificates if enabled will be used in addition to those already pre-
loaded in firmware during provisioning. Unlike Customizable Certificates
the Default Certificates are not deleted when the platform is un-
provisioned.
Click on Intel® AMT in the left tabs menu> Redirection Configuration is expanded by default:

12

# Parameter Platform Settings

Redirection Configuration

12
Redirection Localized Language - This setting allows customers to configure UP4 English
which localized language will be used initially by firmware for user consent output UP3 English
information (Examples: May be displayed before SOL / KVM session starts).
Redirection Privacy / Security Level - This setting allows customers to UP4 Default
configure the Privacy and Security level for redirection operations. UP3 Default
Default enables all redirection ports (User consent is configurable).
Enhanced - Enables all redirection ports. (User consent is required and cannot be
disabled).
Extreme - Disables Redirection and Remote Configuration / Client Control Mode.

Note: The Intel® FIT tool will not adjust the Embedded Host Based Configuration
value based on selection here. Please set EHBC to yes or no as needed.
Click on Intel® AMT in the left tabs menu> TLS Configuration is expanded by default:

13

# Parameter Platform Settings

TLS Configuration

13

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Table 2-6. - Intel® AMT (Sheet 8 of 8)

Transport Layer Security Supported UP4 No

Values: Yes/No - This setting allows customers to enable / disable firmware UP3 No
Transport Layer Security support.

Note: If this is disabled TLS will be permanently disabled in the firmware image.
This setting needs to be enabled along with along with the Intel® ME
Network Services Supported for proper operation of the Intel®
Authenticate (Corporate Only) feature.

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Table 2-7. - Platform Protection (Sheet 1 of 9)

Click on Platform Protection in the left tabs menu> Content Protection is expanded by default:

# Parameter Platform Settings

Content Protection

1
PAVP Supported UP4 Yes
Values: Yes/No UP3 Yes
This setting determines if the Protected Audio Video Path (PAVP) feature will be
permanently disabled in the FW image.
HDCP Internal Display Port 1 - 5K UP4 PortA
Values: None, Port A, Port B, Port C, Port D UP3 PortA
This setting determines which port is connected for 5K output on the Internal
Display 1.

Note: Both Display Port 1 & 2 need to be configured for proper operation.
HDCP Internal Display Port 2 - 5K UP4 None
Values: None, Port A, Port B, Port C, Port D UP3 None
This setting determines which port is connected for 5K output on the Internal
Display 2.

Note: Both Display Port 1 & 2 need to be configured for proper operation.
Click on Platform Protection in the left tabs menu> Graphics uController is expanded by default:

# Parameter Platform Settings

Graphics UController

2
GuC Encryption Key UP4 0x00000000
Values: This option is for entering the raw hash 256 bit string or certificate file for UP3 0x00000000
the Graphics uController.
Click on Platform Protection in the left tabs menu> Hash Key Configuration for Bootguard / ISH is expanded by
default:

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Table 2-7. - Platform Protection (Sheet 2 of 9)

# Parameter Platform
Hash Key Configuration for Bootguard / ISH

3
OEM Public Key Hash UP4 0x00000000
Values: This option is for entering the raw hash string or certificate file for Boot UP3 0x00000000
Guard and ISH. This 384-bit field represents the SHA-384 hash of the OEM public
key corresponding to the private key used to sign the BIOS-SM or ISH image.
Please see Appendix E for further details.
OEM Key Manifest Binary UP4
Signed manifest file containing hashes of keys used for signing components of UP3
image. This setting is only configurable when OEM signing is enabled (See
PlatformIntegrity / OemPublicKeyHash).
Second OEM Key hash UP4 0x00000000
This option is for entering a secondary raw hash string or certificate file for Boot UP3 0x00000000
Guard and ISH used in instances of OEM Key Revocation. This 384-bit field
represents the SHA-384 hash of the OEM public key corresponding to the private
key used to sign the BIOS-SM or ISH image. Please see Appendix E for further
details.

Note: This setting is greyed out and not configurable until the Second OEM Key
Revocation Enable is set to Yes.
OEM Key Revocation Enabled UP4 No
Values: Yes/No UP3 No
This setting enables firmware OEM Key Revocation capabilities.

Note: This setting requires that both OEM Public Key Hash and Second OEM Key
Hash are configured.
Skip OEM Key Check UP3 No
Values: Yes/No UP4 No
This is meant for debugging purposes only. Enabling this parameter impacts image
creation procedure in FIT tool only.
Click on Platform Protection in the left tabs menu> Descriptor Configuration is expanded by default:

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Table 2-7. - Platform Protection (Sheet 3 of 9)

# Parameter Platform
Descriptor Configuration

4 These settings are used for FuSa safety standards and are not applicable
for client platforms.
Flash Descriptor Verification Enabled UP4 No
Values: Yes/No UP3 No
This setting enables / disables Flash Descriptor Verification.
Descriptor Signing Key UP4 -
Values: Hex UP3 -
This is the path to the private key used to sign the Descriptor, while public key hash
of it is included in the OEM hash manifest. This setting is only configurable when
Flash Descriptor Verification is enabled (See PlatformIntegrity/FdvEnabled).
exclude master access in the signature UP4 No
Values: Yes/No UP3 No
Include/exclude master access in the signature.
Click on Platform Protection in the left tabs menu> Exclusion Ranges is expanded by default:

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Table 2-7. - Platform Protection (Sheet 4 of 9)

# Parameter Platform
Exclusion Ranges

5 These settings are used for FuSa safety standards and are not applicable
for client platforms.
Range 1 offset UP4 0x800
Range 1 offset covers manifest, cannot be changed UP3 0x800
Range 1 size UP4 0x400
Range 1 size covers manifest, cannot be changed. UP3 0x400
Range 2 offset UP4 0x80
Range 2 offset covers manifest, cannot be changed UP3 0x80
Range 2 size UP4 0x20
Range 2 size covers manifest, cannot be changed. UP3 0x20
Range 3 offset UP4 0x0
Values: Hex UP3 0x0
Range 3 offset covers OEM defined unprotected range start.
Range 3 size UP4 0x0
Values: Hex UP3 0x0
Range 3 size covers OEM defined unprotected range length

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Table 2-7. - Platform Protection (Sheet 5 of 9)

Range 4 offset UP4 0x0

Values: Hex UP3 0x0
Range 4 offset covers OEM defined unprotected range start.
Range 4 size UP4 0x0
Values: Hex UP3 0x0
Range 4 size covers OEM defined unprotected range length
Range 5 offset UP4 0x0
Values: Hex UP3 0x0
Range 5 offset covers OEM defined unprotected range start.
Range 5 size UP4 0x0
Values: Hex UP3 0x0
Range 5 size covers OEM defined unprotected range length
Range 6 offset UP4 0x0
Values: Hex UP3 0x0
Range 6 offset covers OEM defined unprotected range start.
Range 6 size UP4 0x0
Values: Hex UP3 0x0
Range 6 size covers OEM defined unprotected range length
Range 7 offset UP4 0x0
Values: Hex UP3 0x0
Range 7 offset covers OEM defined unprotected range start.
Range 7 size UP4 0x0
Values: Hex UP3 0x0
Range 7 size covers OEM defined unprotected range length
Range 8 offset UP4 0x0
Values: Hex UP3 0x0
Range 8 offset covers OEM defined unprotected range start.
Range 8 size UP4 0x0
Values: Hex UP3 0x0
Range 8 size covers OEM defined unprotected range length
Click on Platform Protection in the left tabs menu> Boot Guard Configuration is expanded by default:

# Parameter Platform Settings

Boot Guard Configuration

6
Key Manifest ID UP4 0x0
Values: This option is for entering the hash of another public key, used by the ACM UP3 0x0
to verify the Boot Policy Manifest.

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Table 2-7. - Platform Protection (Sheet 6 of 9)

Boot Guard Profile Configuration UP4 Boot Guard

Values: Boot Guard Profile 0 - No_FVME UP3 Profile 0 -
No_FVME
Boot Guard Profile 3 - VM
Boot Guard
Boot Guard Profile 4 - FVE
Profile 0 -
Boot Guard Profile 5 - FVME No_FVME
This option configures which Boot Guard Policy Profile will be used.
CPU Debugging UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting determines if CPU debug modes will be displayed. When set to
'Enabled' CPU debugging is enabled.
BSP Initialization UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting determines BSP behavior when it receives an INIT signal. When set to
'Enabled' BSP will behave normally if it receives an INIT (Disabled BSP Initialization
(DBI) bit=0). When set to ‘Disabled’ BSP will shutdown if it receives an INIT (“DBI”
bit=1).
Click on Platform Protection in the left tabs menu> Type-C Firmware Anti-Rollback Configuration is expanded by
default:

# Parameter Platform Settings

Type-C Firmware Anti-Rollback Configuration

7
IO Manageability Engine Manifest Anti-Rollback Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enables Anti-Rollback for the Type-C Subsystem I/O Manageability
Engine binary.
NPHY Manifest Anti-Rollback Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enabled Anti-Rollback for the Type-C Subsystem NPHY binary.
ThunderboltTM Manifest Anti-Rollback Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enabled Anti-Rollback for the Type-C Subsystem ThunderboltTM binary.
Click on Platform Protection in the left tabs menu> Intel® PTT Configuration is expanded by default:

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Table 2-7. - Platform Protection (Sheet 7 of 9)

# Parameter Platform Settings

Intel® PTT Configuration

8
Intel® PTT Supported UP4 Yes
Values: Yes/No - This setting permanently disables Intel® PTT in the firmware UP3 Yes
image.
Intel® PTT initial power-up state UP4 Enabled
Values: Enabled/Disabled - This setting determines if Intel® PTT is enabled on UP3 Enabled
platform power-up.
Intel® PTT Supported [FPF] UP4 Yes
Values: Yes/No - This setting will permanently disable Intel® PTT through UP3 Yes
platform FPFs.

Caution: Setting this option to Yes will permanently disable Intel® PTT on
the platform hardware.
SMx Support state UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting enables/disables SMx support.
Click on Platform Protection in the left tabs menu> TPM Over SPI Bus Configuration is expanded by default:

# Parameter Platform Settings

TPM Over SPI Bus Configuration

9
TPM Clock Frequency UP4 14MHz
Values: 14MHz, 25MHz, 48MHz - This setting determines the clock frequency UP3 14MHz
setting to be used for the TPM over SPI bus.
TPM Over SPI Bus Enabled UP4 No
Values: Yes/No - This setting determines if TPM over SPI bus is enabled on the UP3 No
platform.
Click on Platform Protection in the left tabs menu> BIOS Guard Configuration is expanded by default:

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Table 2-7. - Platform Protection (Sheet 8 of 9)

10

# Parameter Platform Settings

BIOS Guard Configuration

10
BIOS Guard Protection Override Enabled UP4 No
This setting allows BIOS Guard to bypass SPI flash controller protections (i.e. UP3 No
Protected Range Registers and Top Swap).
Click on Platform Protection in the left tabs menu> TXT Configuration is expanded by default:

11

# Parameter Platform Settings

TXT Configuration

11
TXT Supported UP4 No
This setting determines if enabled for the platform. UP3 No
Click on Platform Protection in the left tabs menu> Crypto Hardware Support is expanded by default:

12

# Parameter Platform Settings

Crypto HW Support

12
Crypto HW Support UP4 Yes
Values: Yes/No - This setting can be used to disable Intel® CSME cryptographic UP3 Yes
functionality.

Caution: Configuring this setting to “No” will disables all Intel® CSME
cryptographic related features.
Click on Platform Protection in the left tabs menu> Platform Trusted Device Setup Support is expanded by default:

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Table 2-7. - Platform Protection (Sheet 9 of 9)

13

# Parameter Platform Settings

Platform Trusted Device Setup Support

13
Enable TDS Capabilities UP4 No
Values: Yes/No - This setting enables Intel® Trusted Device Setup on the UP3 No
platform.
Click on Platform Protection in the left tabs menu> FuSa Configuration is expanded by default:

14

# Parameter Platform Settings

FuSa Configuration

14 These settings are used for FuSa safety standards and are not applicable
for client platforms.

FuSa Proof Tests Reporting I2C Interface UP4 SMLink0

Values: SMBus/SMLink0/SMLink1 UP3 SMLink0
FuSa Proof Tests Reporting I2C Interface" help_text="This setting determines
which SMBus interface will be used for FuSa Proof Tests Reporting I2C interface.
FuSa Proof Tests MCU I2C Address UP4 0x50
Values: Hex UP3 0x50
This setting configures the FuSa Proof Tests I2C MCU address for the platform.
FuSa Proof Tests Components UP4 0x1780
Values: Hex UP3 0x1780
This setting determines which FuSa tests will be run based on the mask value
input.

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Table 2-8. - Integrated Clock Controller (Sheet 1 of 7)

Click on Integrated Clock Controller in the left tabs menu> Integrated Clock Controller Policies are expanded by
default:

# Parameter Platform Settings

Integrated Clock Controller Policies

1
Boot Profile UP4 Profile 0
UP3 Profile 0
This parameter allows user to select default profile to be used by the final
generated SPI Flash binary image for the target platform at boot time.

Selection is limited to the profiles defined under “Integrated Clock Controller |

Profiles “up to maximum 16 profiles. Profiles can be added by clicking on “Add
profile” button under “Integrated Clock Controller | Profiles”.

The ‘Record #’ refers to profile created under the “Integrated Clock Controller |
Profiles”.
Default boot profile for system is Profile 0.

Double click on value column of this parameter to choose from available options.
Failsafe Profile UP4 Profile 0
UP3 Profile 0
This parameter specifies the profile index of the fail-safe profile. On boot failure
detection or CMOS clear the Intel® ME Firmware will revert to this profile if
“Integrated Clock Controller |Integrated Clock Controller Policies - Profile
Changeable “ is set to True. If profile Changeable parameter is set to False, User
can not select Failsafe Boot Profile and profile 0 will be selected as a fail safe boot
profile by default.

The ‘Record #’ refers to profile created under the “Integrated Clock Controller |
Profiles”.
Default Failsafe boot profile for system is Profile 0.

Double click on value column of this parameter to choose from available options.
Profile Changeable UP4 True
UP3 True
Possible configuration: True/False.

This parameter controls if BIOS or 3rd party application can select boot profile or
not. When set to true, it allows user to change boot profile via BIOS or 3rd party
application. When set to false, Runtime change to boot profile is not allowed and
boot profile selected by “Integrated Clock Controller |Integrated Clock
Controller Policies - Boot Profile “ parameter will be used to boot platform.

Double click on value column of this parameter to choose from available options.
Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Bclk Clock Configuration is
expanded by default:

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Table 2-8. - Integrated Clock Controller (Sheet 2 of 7)

# Parameter Platform Settings

BCLK Clock Configuration

2
BCLK Clock Configuration Enabled UP4 Disabled
Values: Enabled / Disabled UP3 Disabled

This setting enables / disables BCLK Clock configuration values for Adaptive /
Overclocking profiles

BCLK Clock Frequency UP4 N/A

UP3 N/A
This parameter allows user to select the nominal frequency for the selected clock.
Range is limited based on the Clock Range Definition record and HW SKU.

Standard Setting Profile Type - Option is grayed out.

Adaptive Setting Profile Type - Option is able to be edited.

BCLK Spread Setting UP4 N/A

UP3 N/A
This parameter allows user to select the percentage of Spread setting for the
selected clock. Range is limited based on the Clock Range Definition record and HW
SKU.

BCLK Clock Frequency

Standard Setting Profile Type - Option is grayed out.
Adaptive Setting Profile Type - Option is able to be edited.

Click on Integrated Clock Controller in the left tabs menu> Profiles are expanded by default:

4
3

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Table 2-8. - Integrated Clock Controller (Sheet 3 of 7)

# Parameter Platform Settings

Profiles - Profile 0 UP4 Standard
UP3 Standard
3 Note: Intel® ME image has to be loaded to enable other ICC profile settings.

For UP3/UP4, Intel® FIT provides 2 pre-defined ICC profiles to choose from.
•Standard: This profile provides default settings for standard configuration, no
adaptive clocking is allowed. Platform clocks output internal and external are driven
from USB3PCIE clock. Default clock frequency is 100 MHz with 0.47%DownSpread.
BCLK clock source should be turned off in this case to save power.
•Adaptive: This profile provides Wimax/3G friendly configuration. This profile will
configure the platform based on the Adaptive profile allowing adaptive clocking
adjustment for BCLK clock source to reduce EMI interference. It supports default
clock frequency of 98.875 MHz with 0.48% Downspread.

For TGL UP3/UP4, Intel® FIT provides 5 pre-defined ICC profiles to choose from.

•Standard
•Adaptive

Note: User can select pre-defined profiles via “Integrated Clock Controller |
Profiles - Profile Type “ parameter

User can add up to maximum 16 profiles.To add new profile, please use
“Integrated Clock Controller | Profiles - + Add Profile Button”
Profile Name UP4 Profile 0
UP3 Profile 0
This parameter allows user to customize profile name for easy identification. By
default it uses pre-defined profile name like Profile 0.
Profile Type UP4 Standard
UP3 Standard
Available ICC profiles for TGL UP3/UP4 are Standard, Adaptive.

This parameter indicates which pre- defined profile selected for each profile#.

Double click on value column of this parameter to choose from available options.
+ Add Profile Button UP4
UP3
4 This button is used to add new ICC profile. User can add up to maximum 16
profiles. New profile will be added under “Integrated Clock Controller |
Profiles” tab.

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Clock Range Definition Record is
expanded by default:

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Table 2-8. - Integrated Clock Controller (Sheet 4 of 7)

# Parameter Platform Settings

Clock Range Definition Record

5
BCLK PLL Clock Source Maximum Frequency - This parameter allows user to UP4
specify the maximum frequency that can be applied to BCLK clock source when UP3
overclocking the platform. Value is limited by divider/frequency limits determined
by HW SKU, and cannot be less than 100 MHz.

Standard Setting Profile Type - Option is grayed out.

Adaptive Setting Profile Type - Option is able to be edited.
BCLK PLL Clock Source Minimum Frequency - This parameter allows user to UP4
specify the minimum frequency that can be applied to BCLK clock source when UP3
underclocking the platform. Value is limited by divider/frequency limits determined
by HW SKU, and cannot be greater than 100 MHz.

Standard Setting Profile Type - Option is grayed out.

Adaptive Setting Profile Type - Option is able to be edited.
BCLK SSC Halt Allowed - This parameter allows user to select if the spread UP4
generator can be disabled at runtime or not.if set to “True”, the spread generator UP3
can be enabled and disabled at runtime.

Standard Setting Profile Type - Option is grayed out.

Adaptive Setting Profile Type - Option is able to be edited.
BCLK SSC Percentage - This parameter Specifies the maximum percentage of UP4
spread adjustment that can be applied to the clock. Value is specified in 1/100th of UP3
percent(50=0.5%)

Standard Setting Profile Type - Option is grayed out.

Adaptive Setting Profile Type - Option is able to be edited.
Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Clock Output Configuration is
expanded by default:

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Table 2-8. - Integrated Clock Controller (Sheet 5 of 7)

# Parameter Platform Settings

Clock Output Configuration

6
SRC0[6:15] UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
These parameters come under the Power Management section and they control
Enabling /Disabling of specific Output Clocks at boot time.
These settings should match with platform
hardware design.

For CRB, recommend keeping defaults for

bring up with Intel® CSME FW.

These parameters are specifically used to Enable/Disable the respective

CLKOUT_XXX differential output buffers
SRC1 UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
Enables or Disables the CLKOUT_SRC1 differential output buffer.
SRC2 UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
Enables or Disables the CLKOUT_SRC2 differential output buffer.
SRC3 UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
Enables or Disables the CLKOUT_SRC3 differential output buffer.
SRC4 UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
Enables or Disables the CLKOUT_SRC4 differential output buffer.
SRC5 UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
Enables or Disables the CLKOUT_SRC5 differential output buffer.
SRC6 UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
Enables or Disables the CLKOUT_SRC6 differential output buffer.

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Table 2-8. - Integrated Clock Controller (Sheet 6 of 7)

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Power Management Configuration is
expanded by default:

# Parameter Platform Settings

Profile Power Management Configuration

7 Configuring CLKREQ# and assigning GPIO depends on how CLKOUT_SRCx

configuration via FIT is done (Enabled or Disabled) and if CLKREQ is required or
not.

Please refer to Appendix B.3 (How to configure CLKREQ# parameters) for

the detail of CLKREQ configuration for SRC Output clocks. Please configure CLKREQ
parameters accordingly.
SRC0[5:0] CLKREQ# Mapping UP4 GPP_D5
Possible configuration: Select one of the GPIOs from the list to map it as a UP3 GPP_D5
CLKREQ# for specific SRC# Output clock.
This parameter controls association of dynamic CLKREQ control with SRC (PCIe)
clocks.

SRC[15:6] CLKREQ# Mapping - TGL/CFL H/S Only

Possible configuration: Select one of the GPIOs from the list to map it as a
CLKREQ# for specific SRC# Output put clock.
This parameter controls association of dynamic CLKREQ control with SRC (PCIe)
clocks.
SRC1 CLKREQ# Mapping UP4 GPP_D6
Assign the CLKREQ# signal associated with CLKOUT_SRC1. UP3 GPP_D6

SRC2 CLKREQ# Mapping UP4 GPP_D7

Assign the CLKREQ# signal associated with CLKOUT_SRC2. UP3 GPP_D7

SRC3 CLKREQ# Mapping UP4 GPP_D8

Assign the CLKREQ# signal associated with CLKOUT_SRC3. UP3 GPP_D8

SRC4 CLKREQ# Mapping UP4 GPP_H10

Assign the CLKREQ# signal associated with CLKOUT_SRC4. UP3 GPP_H10

SRC5 CLKREQ# Mapping UP4 GPP_H11

Assign the CLKREQ# signal associated with CLKOUT_SRC5. UP3 GPP_H11

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Table 2-8. - Integrated Clock Controller (Sheet 7 of 7)

SRC6 CLKREQ# Mapping UP4 GPP_F19

Assign the CLKREQ# signal associated with CLKOUT_SRC6. UP3 GPP_F19

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> PCIe RefClock Configuration is
expanded by default:

# Parameter Platform Settings

PCIe RefClock Configuration

8
SSCEN UP4 Enabled
Values: Enabled / Disabled UP3 Enabled

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Table 2-9. - Networking & Connectivity (Sheet 1 of 4)

Click on Networking & Connectivity in the left tabs menu> Discrete vPro NIC is expanded by default:

# Parameter Platform Settings

Platform vPro 2.5G Wired LAN

1
Platform vPro 2.5G Wired LAN Enabled UP4 No
Values: Yes / No UP3 No
This setting enables / disables Discrete Intel® vPro Network adapter support on the
platform.
Platform vPro 2.5G Wired LAN slave SMBus Address UP4 0x0
Values: Hex UP3 0x0
This setting configures the SMBus address for the Discrete Intel®vPro Network
adapter.
Click on Networking & Connectivity in the left tabs menu> Docking Station is expanded by default:

# Parameter Platform Settings

Intel vPro(TM) for Thinderbolt 3(TM) / USB-C Dock Station

2
vPro Dock Enabled UP4 No
This setting enables Intel® vPro communication over supported NIC in a UP3 No
ThunderboltTM Dock.
vPro 2.5G Wired LAN on dock slave SMBus Address UP4 0x0
This setting configures the NIC SMBus slave address. UP3 0x0
Type-C Port1 Re-Timer SMBus Address UP4 0x20
This setting configures Intel® SMBus Address. UP3 0x20
Type-C Port2 Re-Timer SMBus Address UP4 0x21
This setting configures Intel® SMBus Address. UP3 0x21

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Table 2-9. - Networking & Connectivity (Sheet 2 of 4)

Type-C Port3 Re-Timer SMBus Address UP4 0x22

This setting configures Intel® SMBus Address. UP3 0x22
Type-C Port4 Re-Timer SMBus Address UP4 0x23
This setting configures Intel® SMBus Address. UP3 0x23
Click on Networking & Connectivity in the left tabs menu> Wired LAN Configuration is expanded by default:

# Parameter Platform Settings

Wired LAN Configuration

3
LAN Power Well UP4 SLP_LAN#
Values: Core Well, Sus Well, ME Well, SLP_LAN - This setting allows customers UP3 SLP_LAN#
to configure the power well that will be used by Intel® Integrated LAN.
Note: Recommended setting is SLP_LAN#.
LAN PHY Power Up Time UP4 100ms
Values: 50ms, 100ms UP3 100ms
Intel® Integrated Wired LAN Enable UP4 Enabled
Values: Enabled/Disabled - This setting enables or disables the Intel® UP3 Enabled
Integrated LAN.
GbE PCIe Port Select UP4 Port 7
Values: None, PORT7, PORT8, PORT9 - This setting allows customers to UP3 Port 7
configure the PCIe Port that will Intel® Integrated LAN will operate on.
GbE PHY SMBus Address UP4 0x64
This setting configures Intel® Integrated Wired LAN PHY SMBus address to accept UP3 0x64
SMBus cycles from the MAC. Note: Recommended setting is 64h.
GbE SMBus Address Enabled UP4 Yes
Values: Yes/No - This enables the Intel® Integrated Wired LAN MAC SMBus UP3 Yes
address. Note: This setting must be enabled if using Intel® Integrated LAN.
GbE MAC SMBus Address UP4 0x70
This setting configures Intel® Integrated Wired LAN MAC SMBus address to accept UP3 0x70
SMBus cycles from the PHY. Note: Recommended setting is 70h.
PHY Connection UP4 PHY on SMLink0
Values: No PHY connected, PHY on SMLink0 UP3 PHY on SMLink0

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Table 2-9. - Networking & Connectivity (Sheet 3 of 4)

LAN PHY Power Control GPD11 Signal Configuration UP4 LANPHYPC

Values: GPD11, LANPHYPC - This setting allows the customer to assign the LAN UP3 LANPHYPC
PHY Power Control signal to GbE or as GDP11.
Note: If using Intel® Integrated LAN this setting should be set to "Enable as
LANPHYPC".
Click on Networking & Connectivity in the left tabs menu> Wireless LAN Configuration is expanded by default:

# Parameter Platform Settings

Wireless LAN Configuration

4
CLINK Enabled UP4 No
Values: Yes/No UP3 No
This setting allows customers to enable / disable the Wireless LAN CLINK signal
through Intel® CSME firmware.

Note: For using Intel® vPro Wireless solutions this should be set to “Yes”.
WLAN Microcode UP4 0xA0F0
This setting allow OEMs to configure which Intel® Wireless LAN card microcode to UP3 0xA0F0
load into the firmware image.
WLAN Power Well UP4 SLP_WLAN#
Values: Disabled, Sus Well, ME Well, SLP_M#||SPDA, SLP_WLAN# UP3 SLP_WLAN#
This setting allows OEMs to configure the power well that will be used by Intel®
Wireless LAN.

WLAN Sleep via SLP_WLAN# (default)

Note: Recommended setting is SLP_WLAN#.

CNVi / On Die CLINK Enabled UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting determines if the internal CNVi / On-die CLINK port is enabled.

Note: This setting should be enabled if the WLAN adapter on the platform is
CNVi.
SLP_WLAN# / GPD9 Signal Configuration UP4 Enable as
Values: SLP_WLAN#, GPD9 UP3 SLP_WLAN#
This setting allows the customer to assign the WLAN Power Control signal to WLAN Enabled as
or as GDP9. SLP_WLAN #

Note: If using Intel® Wireless LAN this setting should be set to “Enable as
SLP_WLAN#”.
Click on Networking & Connectivity in the left tabs menu> Time Sensitive Networking Configuration is expanded
by default:

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Table 2-9. - Networking & Connectivity (Sheet 4 of 4)

# Parameter Platform Settings

Time Sensitive Networking Configuration

5 These settings are not applicable for client platforms.

Time Sensitive Networking UP4 Disabled

Values: TSN Enable / TSN Disabled UP3 Disabled

Note: Time Sensitive Networking and Wired LAN are mutually exclusive only one
of these features can enabled on the platform.
TSN GbE PCIe Port Select UP4 None
Values: None, TSN PORT6, TSN PORT 7 - This setting allows customers to UP3 None
configure the PCIe port that TSN will operate on.

Note: The Intel® Integrated LAN and TSN GbE are mutually exclusive.

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Table 2-10. - Internal PCH Buses (Sheet 1 of 5)

Click on Internal PCH Buses in the left tabs menu> PCH Timer Configuration is expanded by default:

# Parameter Platform Settings

PCH Timer Configuration

1
PCH clock output stable to PROCPWRGD high (tPCH45) UP4 1ms
Values: 100ms, 50ms, 5ms, 1ms - This setting configures the minimum timing UP3 1ms
from XCK_PLL locked to CPUPWRGD high. For further details see Tiger Lake LP
Platform Controller Hub EDS.
PCIe Power Stable Timer (tPCH33) UP4 Disabled
Values: Enabled/Disabled - This setting configures the enables / disables the t36 UP3 Disabled
timer. When enabled PCH will count 99ms from PWROK assertion before PLTRST# is
de-asserted.

Note: The recommended setting is "Disabled".

PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion (tPCH46) UP4 1ms
Values: 1ms, 2ms, 5ms - This setting configures the minimum timing from UP3 1ms
CPUPWRGD assertion to SUS_STAT#. For further details see Tiger Lake LP Platform
Controller Hub EDS.
APWROK Timing UP4 2ms
Values: 2ms, 4ms, 8ms, 15ms - This soft strap determines the time between the UP3 2ms
SLP_A# pin de-asserting and the APWROK timer expiration. For further details see
Tiger Lake LP Platform Controller Hub EDS.
Over Clocking Watchdog Self Start Enable UP4 OC WDT
Values: OC WDT Disabled, OC WDT 3 Second Timeout, OC WDT 5 Second UP3 Disabled
Timeout, OC WDR 10 Second Timeout, OC WDT 15 Second Timeout, OC OC WDT
WDT 30 Second Timeout, OC WDT 45 Second Timeout, OC WDT 60 Second Disabled
Timeout - This setting affect whether the Over Clocking Watchdog Timer is
enabled to automatically start on Host power cycle
Click on Internal PCH Buses in the left tabs menu> SMBus / SMLink Configuration is expanded by default:

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Table 2-10. - Internal PCH Buses (Sheet 2 of 5)

# Parameter Platform Settings

SMBus / SMLink Configuration

2
Intel® SMLink0 MCTP Address UP4 0x0
This setting configures the Intel® SMLink0 MCTP Address. UP3 0x0
Note: This setting is only used for testing.
Intel® SMLink0 MCTP Address Enabled UP4 No
Value: Yes/No UP3 No
This setting configures the Intel® SMLink0b MCTP Address.
Note: This setting is only used for testing.
Intel® SMBus ASD Address - This setting configures the Intel® SMBus Alert UP4 0x0
Sending device Address. For details see Tiger Lake LP SPI Programming guide for UP3 0x0
further details.

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Table 2-10. - Internal PCH Buses (Sheet 3 of 5)

# Parameter Platform Settings

Intel® SMBus ASD Address Enabled UP4 No
Values: Yes/No - This setting enables / disables the Intel® SMBus Alert Sending UP3 No
device. For details see Tiger Lake LP SPI Programming guide for further details.
Intel® SMBus Subsystem Vendor & device ID for ASF - This setting configures UP4 0x0
the Intel® SMBus Subsystem Vendor & device ID for ASF. For details see Tiger Lake UP3 0x0
LP SPI Programming guide further details.
Intel® SMBus I2C Address - This setting configures the Intel® SMBus I2C UP4 0x0
Address. Note: This setting is only used for testing purposes. The recommended UP3 0x0
setting is "0000000".
Intel® SMBus I2C Address Enabled UP4 No
Values: Yes/No - This setting enables / disables the Intel® SMBus I2C Address. UP3 No
Note: This setting is only used for testing purposes. The recommended setting is
"No".
Intel® SMBus MTCP Address - This setting configures the Intel® SMBus MCTP UP4 0x0
Address. Note: This setting is only used for testing purposes. The default setting is UP3 0x0
"0000000".
Intel® SMBus MCTP Address Enabled UP4 No
Values: Yes/No - This setting enables / disables the Intel® SMBus MCTP Address. UP3 No
Note: This setting is only used for testing purposes. The recommended setting is
"No".
SMBus / SMLink TCO Slave Connection UP4 Intel® SMBus
Values: Intel® SMBus, SMLink0 - This setting configures the TCO Slave UP3 Intel® SMBus
connection to ether the Intel® SMBus or SMLink0. For further details see Tiger Lake
LP Platform Controller Hub EDS.
SMLink0 Enabled UP4 Yes
Values: Yes/No - This setting enables / disables SMLink0 interface. For further UP3 Yes
details see Tiger Lake LP Platform Controller Hub EDS.
SMLink0 Frequency UP4 1 MHz
Values: 100KHz, 400KHz, 1 MHz - This setting determines the frequency at UP3 1 MHz
which the SMLink0 will operate. Note: The recommended setting is "1MHz".
SMLink1 I2C Target Address - This setting configures SMLink1 I2C Target UP4 0x0
Address. For further details see Tiger Lake LP Platform Controller Hub EDS. UP3 0x0
SMLink1 I2C Target Address Enabled UP4 No
Values: Yes/No - This setting configures SMLink1 I2C Target Address. For further UP3 No
details see Tiger Lake LP Platform Controller Hub EDS.
SMLink1 GP Target Address - This setting configures SMLink1 GP Target UP4 0x0
Address. For further details see Tiger Lake LP Platform Controller Hub EDS. UP3 0x0
SMLink1 GP Target Address Enabled UP4 Yes
Values: Yes/No - This setting enables / disables SMLink1 GP Target Address UP3 Yes
interface. For further details see Tiger Lake LP Platform Controller Hub EDS. Note:
This setting must be set to "Yes" if using PCH / MCP Thermal reporting.
SMLink1 Enabled UP4 Yes
Values: Yes/No - This setting enables / disables SMLink1 interface. For further UP3 Yes
details see Tiger Lake LP Platform Controller Hub EDS. Note: This setting must be
set to "Yes" if using PCH / MCP Thermal reporting.
SMLine1 MTCP Address - This setting configures the SMLink1 MCTP Address. UP4 0x0
Note: This setting is only used for testing purposes. The default setting is UP3 0x0
"0000000".
SMLink1 MCTP Address Enabled UP4 No
Values: Yes/No - This setting enables / disables the SMLink1 MCTP Address. UP3 No
Note: This setting is only used for testing purposes. The recommended setting is
"No".
SMLink1 Frequency UP4 100 KHz
Values: 100KHz, 400KHz, 1 MHz - This setting determines the frequency at UP3 100 KHz
which the SMLink1 will operate. Note: The recommended setting is "100KHz".
Intel® SMBus ASD Mode Configuration UP4 Enable as
This setting determines the native mode of operation for the Intel® SMBus ASD UP3 GPP_C2
signal. Enable as
GPP_C2

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Table 2-10. - Internal PCH Buses (Sheet 4 of 5)

# Parameter Platform Settings

SMLink0 I2C Target Address - This setting configures SMLink0 I2C Target UP4 0x0
Address. For further details see Rocket Lake LP Platform Controller Hub EDS. UP3 0x0
SMLink0 I2C Target Address Enabled UP4 No
Values: Yes/No - This setting configures SMLink0 I2C Target Address. For further UP3 No
details see Rocket Lake LP Platform Controller Hub EDS.
Click on Internal PCH Buses in the left tabs menu> DMI Configuration is expanded by default:

# Parameter Platform Settings

DMI Configuration

3
DMI Lane Reversal UP4 No
Values: Yes/No - This setting allows the DMI Lane signals to be reversed. For UP3 No
further details see Tiger Lake LP Platform Controller Hub EDS.
DMI Port Staggering UP4 Yes
Values: Yes/No - This setting configures DMI for Port Staggering. For further UP3 Yes
details see Tiger Lake LP Platform Controller Hub EDS.
Click on Internal PCH Buses in the left tabs menu> OPI Configuration is expanded by default:

# Parameter Platform Settings

OPI / DMI Configuration

4
OPI Link Speed UP4 2 GT/s
Values: GT2/GT4 - This setting configures the OPI / DMI Link Speed. For further UP3 4 GT/s
details see Tiger Lake PCH EDS.
OPI Link Voltage UP4 0.85 Volts
Values: 0.85 Volts, 0.95 Volts, 1.05 Volts - This setting configures the OPI / UP3 0.95 Volts
DMI Link Voltage. For further details see Tiger Lake PCH EDS.
OPI Link Width UP4 8 Lanes
Values: 1 Lanes, 2 Lanes, 4 Lanes, 8 Lanes - This setting configures the OPI / UP3 8 Lanes
DMI Link Width. For further details see Tiger Lake PCH EDS.
Click on Internal PCH Buses in the left tabs menu> eSPI Configuration is expanded by default:

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Table 2-10. - Internal PCH Buses (Sheet 5 of 5)

# Parameter Platform Settings

eSPI Configuration

5
eSPI / EC Bus Frequency UP4 20MHz
Value: 20MHz, 25MHz, 33MHz, 50MHz UP3 20MHz
Indicates the maximum frequency of the eSPI bus that is supported by the eSPI
Master and platform configuration (trace length, number of Slaves, etc.). The
actual frequency of the eSPI bus will be the minimum of this field and the Slave's
maximum frequency advertised in its General Capabilities register.
eSPI / EC Maximum I/O Mode UP4 Single
Values: Single, Single and Dual, Single and Quad, Single Dual and Quad UP3 Single
Indicates the maximum IO Mode (Single/Dual/Quad) of the eSPI bus that is
supported by the eSPI Master and specific platform configuration. The actual IO
Mode of the eSPI bus will be the minimum of this field and the Slave's maximum
IO Mode advertised in its General Capabilities register.
eSPI / EC CRC Check Enabled UP4 No
Values: Yes/No UP3 No
This setting enables CRC checking on eSPI Slave 0 channel.
eSPI / EC Max Outstanding Request for Master Attached Flash Channel UP4 2
Values: 1/2 UP3 2
This setting determines the Maximum outstanding requests on the eSPI / EC
Master Attached Flash Channel.
eSPI / EC Slave Attached Flash Multiple Outstanding Requests Enable UP4 Single
Values: Single Outstanding Request/Multiple Outstanding Requests UP3 Outstanding
Request
This setting enabled multiple outstanding requests for the eSPI / EC Slave Attached
Flash device. Single
Outstanding
Request
eSPI / EC Slave Attached Flash Channel OOO Enable UP4 In-Order SAF
Values: In-Order SAF Requests/Out-of-Order SAF Requests UP3 Requests
This setting enables Out or Order requests on the eSPI / EC Slave Attached Flash In-Order SAF
device. Requests

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Table 2-11. - Power (Sheet 1 of 2)

Click on Power in the left tabs menu> Platform Power is expanded by default:

# Parameter Platform Settings

Platform Power

1
SLP_S3# / GPD4 Signal Configuration UP4 SLP_S3#
Values: SLP_S3#, GPD4 - This setting allows the customer to assign the UP3 SLP_S3#
SLP_S3# Power Control signal as SLP_S3# or as GDP4. For further details see Tiger
Lake LP Platform Controller Hub EDS.
SLP_S4# / GPD5 Signal Configuration UP4 SLP_S4#
Values: SLP_S4#, GPD5 - This setting allows the customer to assign the UP3 SLP_S4#
SLP_S4# Power Control signal as SLP_S4# or as GDP5. For further details see Tiger
Lake LP Platform Controller Hub EDS.
SLP_S5# / GPD10 Signal Configuration UP4 SLP_S5#
Values: SLP_S5#, GPD10 - This setting allows the customer to assign the UP3 SLP_S5#
SLP_S5# Power Control signal as SLP_S5# or as GDP10. For further details see
Tiger Lake LP Platform Controller Hub EDS.
SLP_A# / GPD6 Signal Configuration UP4 SLP_A#
Values: SLP_A#, GPD6 - This setting allows the customer to assign the SLP_A# UP3 SLP_A#
Power Control signal as SLP_A# or as GDP6. For further details see Tiger Lake LP
Platform Controller Hub EDS.
SLP_S0# Tunnel UP4 Disabled
This setting Enables / Disables the tunneling of the SLP_S0# pin over ESPI to the UP3 Disabled
EC when in ESPI mode.
Click on Power in the left tabs menu> Deep Sx is expanded by default:

# Parameter Platform Settings

Deep Sx

2
Deep Sx Enabled UP4 Yes
Values: Yes/ No - This setting enables / disables support for Deep Sx operation. UP3 Yes
For further details see Tiger Lake LP Platform Controller Hub EDS. Note: Support
for Deep Sx is board design dependent.
Click on Power in the left tabs menu> PCH Thermal Reporting is expanded by default:

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Table 2-11. - Power (Sheet 2 of 2)

# Parameter Platform Settings

PCH Thermal Reporting

3
Thermal Power Reporting Enabled UP4 Yes
This setting enabled a once-per-second timer interrupt is enabled which triggers UP3 Yes
firmware to report power and temperature information as enabled by configuration
registers. Note: When this setting is disabled ensure that the once-per-second
timer interrupt associated with this feature is also disabled.

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Table 2-12. - Integrated Sensor Hub (Sheet 1 of 2)

Click on Integrated Sensor Hub in the left tabs menu> Integrated Sensor Hub is expanded by default:

# Parameter Platform Settings

Integrated Sensor Hub

1
Integrated Sensor Hub Supported UP4 No
Values: Yes/No UP3 No
This setting allows customers to disable ISH on the platform.
Integrated Sensor Hub Power Up State UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
Field is enabled for editing if “Integrated Sensor Hub Supported” field above is set
to “Yes”. This setting allows customers to determine the power up state for ISH.
Click on Integrated Sensor Hub in the left tabs menu> ISH Image is expanded by default:

# Parameter Platform Settings

ISH Image

2
Length - Total size (in bytes) of the ISH code partition including reserved space. It
is recommended to be at least 256kb.
Input File UP4 ISH Binary
UP3 (Optional)
Version - This displays the version of ISH
Click on Integrated Sensor Hub in the left tabs menu> ISH Data is expanded by default:

# Parameter Platform Settings

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Table 2-12. - Integrated Sensor Hub (Sheet 2 of 2)

Integrated Sensor Hub - ISH Data

3
PDT Binary File UP4 Path for PDT
UP3 Binary file
Path for PDT
Binary file

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Table 2-13. - Camera

Click on Camera in the left tabs menu> IPU Security is expanded by default:

# Parameter Platform Settings

IPU Security

1
Secure Touch UP4 Disabled
Values: Enabled / Disabled UP3 Disabled
When set, CAMERA_MASK register bits per CSI port are used to mask the data of
cameras. When cleared, camera data is not masked.
FW Secure Mode UP4 Enabled
Values: Enabled / Disabled UP3 Enabled
If enabled, access blockers in IS and PS are enabled, and FW is read from IMR.
Must be enabled for FW authentication flow and execution of authenticated FW.
Secure Touch Camera Mask UP4 0xFF
Values: Hex Input UP3 0xFF
Camera mask bits per CSI port. When SECURE_TOUCH is set each set bit masks a
CSI port for secure touch. When SECURE_TOUCH is cleared this register has no
impact on the CSI ports.

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Table 2-14. - Debug (Sheet 1 of 5)

Click on Debug in the left tabs menu> Intel® ME Firmware Debugging Overrides is expanded by default:

# Parameter Platform Settings

IDLM

1
IDLM Binary UP4 IDLM Binary
This allows an IDLM binary to be merged into output image built by Intel® FIT. UP3 (Optional)
Click on Debug in the left tabs menu> Delayed Authentication Mode Configuration is expanded by default:

# Parameter Platform Settings

Delayed Authentication Mode Configuration

2
Delayed Authentication Mode Enabled UP4 No
Values: Yes/No - This setting enable / disables Delayed Authentication Mode on UP3 No
the platform.
Click on Debug in the left tabs menu> Intel® Trace Hub Technology is expanded by default:

# Parameter Platform Settings

Intel® Trace Hub Technology

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Table 2-14. - Debug (Sheet 2 of 5)

Intel® Trace Hub Binary - This loads the Intel® Trace Hub binary that will be UP4 Trace Hub
merged into the output image generated by the Intel® FIT tool. UP3 Binary
Trace Hub
Binary
Intel® Trace Hub Emergency Mode Enabled UP4 No
Values: Yes/No - This setting enable / disables Intel® Trace Hub in the firmware UP3 No
base image.
Intel® Trace Hub Filtering UP4 Trace Hub Filter
This setting allows a user input binary for filtering of output messages for Intel® UP3 Binary
Trace Hub (Optional)
Trace Hub Filter
Binary
(Optional)
PMC Debug Messages Enabled UP4 Yes
Values: Yes/No - This setting enables/disables the PMC debug messages. UP3 Yes
Unlock Token UP4 Unlock Token
This allows the OEM to input an Unlock Token binary file for closed chassis debug. UP3 Binary
(Optional)
Unlock Token
Binary
(Optional)
Click on Debug in the left tabs menu> Intel® ME Debugging Overrides is expanded by default:

# Parameter Platform Settings

Intel® ME Firmware Debugging Overrides

4
Debug Override Pre-Production Silicon - Allows the OEM to control FW features UP4 0x00000000
to assist with pre-production platform debugging. This control has no effect if used UP3 0x00000000
on production silicon.
Bit 0: Disable DRAM_INIT_DONE (default timeout 60 seconds)
Bit 1: Disable Host Reset Timer
Bit 2: Disable CPU_RESET_DONE timeout
Bit 3: Reserved
Bit 4: Disable Intel® ME Power Gating
Bit 5: Reserved
Bit 6: Secure Boot debug hook. Used to shorten wait time before ENF shutdown.
Bit 7: Force real FPFs on preproduction (default is to use flash)
Bit 8: Secure Boot debug hook. Used to reduce S3 or FFS optimization tries.
Bit 9: Reserved
Bit 10: Override power package to always enter M3.
Note: Certain options do not work when the descriptor is locked.

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Table 2-14. - Debug (Sheet 3 of 5)

Debug Override Production Silicon - Allows the OEM to control FW features to UP4 0x00000000
assist with production platform debugging. UP3 0x00000000
Bit 0: Extend DRAM_INIT_DONE timeout to 30 minutes (default timeout 15
seconds)
Bit 1: Disable Host Reset Timer
Bit 2: Disable CPU_RESET_DONE timeout
Note: Certain options do not work when the descriptor is locked.
Intel® ME Reset Behavior UP4 Intel® Alternate
Values: Intel® ME will Halt / Intel® Alternate image boot UP3 image boot
This setting determines Intel® ME behavior when boot image errors are Intel® Alternate
encountered. Warning: This setting should be used for debug purposes only. image boot
Note: This may block normal Firmware functional flows.
Enable Intel® ME Reset Capture on CLR_RST# UP4 No
This setting configures Intel® ME behavior when it resets during CL_RST#1. Note: UP3 No
The recommended default for this setting is 'No'
Firmware ROM Bypass UP4 No
Values: Yes/No - This setting enables / disables firmware ROM bypass. Note: UP3 No
This setting only has affect when the firmware being used has ROM Bypass code
present.
ASF Idle Flash Reclaim Enabled UP4 Yes
Values: Yes / No UP3 Yes
This controls enabling / disable the Intel® AFS Idle flash reclaim capabilities.

Note: This setting should be used for debug purposes only.

Click on Debug in the left tabs menu> Direct Connection Interface Configuration is expanded by default:

# Parameter Platform Settings

Direct Connection Interface Configuration

5 Note: When any of the DCI BSSB USB3 Port interfaces are enabled the
associated USB3 port selection control will be greyed out under the USB3
Port Configuration settings section under the Flex I/O tab
Intel® DCI DbC Interface Enabled UP4 Yes
Values: Yes/No - This setting enables / disables the Intel® DCI DbC interface. UP3 Yes
DCI OOB over USB3 Port1 Enabled UP4 Yes
Values: Yes / No UP3 Yes
This setting determines if the USB port being enabled for DCI OOB. If disabled it
will block DCI OOB connection.

Note: When this setting is enabled the corresponding USB3 Combo Port in the
Flex I/O Tab will be Grayed out.

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Table 2-14. - Debug (Sheet 4 of 5)

DCI OOB over USB3 Port 2 Enabled UP4 Yes

Values: Yes / No UP3 Yes
This setting determines if the USB port being enabled for DCI OOB. If disabled it
will block DCI OOB connection.

Note: When this setting is enabled the corresponding USB3 Combo Port in the
Flex I/O Tab will be Grayed out.
DCI OOB over USB3 Port 3 Enabled UP4 No
Values: Yes / No UP3 No
This setting determines if the USB port being enabled for DCI OOB. If disabled it
will block DCI OOB connection.

Note: When this setting is enabled the corresponding USB3 Combo Port in the
Flex I/O Tab will be Grayed out.
DCI OOB over USB3 Port 4 Enabled UP4 No
Values: Yes / No UP3 No
This setting determines if the USB port being enabled for DCI OOB. If disabled it
will block DCI OOB connection.

Note: When this setting is enabled the corresponding USB3 Combo Port in the
Flex I/O Tab will be Grayed out.
Click on Debug in the left tabs menu> eSPI Feature Overrides is expanded by default:

# Parameter Platform Settings

eSPI Feature Overrides

6
eSPI / EC Low Frequency Debug Override UP4 No
When enabled this setting will divide eSPI clock frequency by 8. UP3 No

Note: This setting should only be used for debugging purposes. Leaving this set
to “Yes” will impact eSPI performance on the platform.
Click on Debug in the left tabs menu> Early USB DBC Type-A Configuration is expanded by default:

# Parameter Platform Settings

Early USB DBC Type-A Configuration

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Table 2-14. - Debug (Sheet 5 of 5)

Enabled early USB2 DbC connection UP4 No

Values: Yes / No UP3 No
This setting enabled a delay during Intel® ME firmware bring-up to allow USB2 DbC
connection to be established
USB2 DbC port enable UP4 No USB2 Ports
This setting determines which USB2 ports are enabled for Early DbC debugging. UP3 No USB2 Ports
USB Connectors associated USB3 Port enable UP4 No USB3 Ports
This setting determines which USB3 ports goes to the target USB2 ports connector UP3 No USB3 Ports
for Early DbC debugging.
Click on Debug in the left tabs menu> Early TRC Emulation is expanded by default:

# Parameter Platform Settings

TRC Emulation

8
TRC Enabled UP4 No
Values: Yes / No UP3 No
This setting enables TRC HIP and TRC Countermeasures used by Intel® CSME for
the detection of hardware glitches as a part of security hardening. The purpose of
this setting is to allow OEMs to enable TRC for testing prior to close of
manufacturing and FPF commit.
TRC Enabled (FPF) UP4 No
Values: Yes / No UP3 No
When enabled the TRC HIP and TRC Countermeasures are enabled. When
manufacture is completed, this value is burned into an FPF.

Note: This setting should be set to “Yes” for production platforms.

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Table 2-15. - CPU Straps (Sheet 1 of 2)

Click on CPU Straps in the left tabs menu> CPU Straps are expanded by default:

# Parameter Platform Settings

CPU Straps - CPU Straps

1
Number of Active Cores UP4 All Cores Active
Values: All, 1, 2, 3, 4, 5, 6, 7, 8 UP3 All Cores Active
This setting controls the number of active processor cores.
Note: This strap is intended for debugging purposes only. See BIOS Spec for
more details on enabling or disabling processor cores.
Disable Hyperthreading UP4 No
Values: Yes/No UP3 No
This setting controls enabling or disabling of Hyper threading.
Note: This strap is intended for debugging purposes only. See BIOS Spec for
more details on enabling / disabling Hyperthreading.
BIST Initialization UP4 No
Values: Yes/No UP3 No
This setting determines if BIST will be run at platform reset after BIOS requested
actions.
Note: This strap is intended for debugging purposes only.
Flex Ratio UP4 0x0
This setting controls the maximum processor non-turbo ratio. UP3 0x0
Note: This strap is intended for debugging purposes only. See BIOS Spec for
more details on maximum processor non-turbo ratio configuration.

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Table 2-15. - CPU Straps (Sheet 2 of 2)

Processor Boot at P1 Frequency UP4 Yes

Values: Yes/No UP3 Yes
This setting determines if the processor will operate at maximum frequency at
power-on and boot.
Note: This strap is intended for debugging purposes only.
JTAG Power Disable UP4 No JTAG Power
Values: Yes - JTAG Power on C10 and Lower/No - No Power on C10 and UP3 on C10 and
Lower Lower
This setting determines if JTAG power will be maintained on C10 or lower power No JTAG Power
states. on C10 and
Note: This strap is intended for debugging purposes only. Lower
SVID Presence UP4 SVID Present
Value: SVID Present/SVID Not Present UP3 SVID Present
This setting determines if SVID rails are present on the platform. See Processor
EDS for details.
Platform IMON UP4 Enabled
Value: Enabled/Disabled UP3 Enabled
Note: This strap should be left at the recommended default setting.
VCC Aux Present UP4 Yes
Value: Yes/No UP3 Yes
This setting determines if VCC Aux exists as a separate VR.
VCCIN SVID Address UP4 0x0
This setting determines the VCCIN SVID Address. See Processor EDS for details. UP3 0x0
Note: This strap should be left at the recommended default setting.
VCC SVID VR Type UP4 SVID
Values: SVID/Fixed VR UP3 SVID
This setting determines the VCC IN SVID VR Type. See Processor EDS for details.
VCC ST PG Present UP4 Yes
Values: Yes/No UP3 Yes
This setting determines if VCC ST PG is present on the platform.
VCC STG PG Present UP4 Yes
Values: Yes/No UP3 Yes
This setting determines if VCC STG PG is present on the platform.
CPU Boot Hang Recovery Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting is enabled by default and will allow PMC to recover from CPU boot
hangs through either Global reset or SLP_SUS# assertion (based on 'VCC ST PG
Present' CPU strap setting).

Note: This setting should be set to “No”; if the platform configurations employs
EC or other mechanism to recover from CPU hangs.
VCCIN Aux Level LP UP4 1.65v or 1.8v
Values: 1.8v/1.65v UP3 1.8v
This setting determines the VCCIN Aux Level LP Voltage.
Note: On UP4 based MCP this setting can be configured to 1.65v. On the UP3
MCP types set to 1.8v

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Table 2-16. - Flex I/O Straps (Sheet 1 of 16)

Click on Flex I/O in the left tabs menu> PCIe Lane Reversal Configuration is expanded by default:

# Parameter Platform Settings

PCIe Lane Reversal Configuration

1
PCIe Controller 1 Lane Reversal Enabled UP4 No
Values: Yes/ No - This setting allows the PCIe lanes on Controller 1 to be UP3 No
reversed. Note: Refer to EDS for PCIe supported port
configurations.
PCIe Controller 2 Lane Reversal Enabled UP4 No
Values: Yes/ No - This setting allows the PCIe lanes on Controller 2 to be UP3 No
reversed. Note: Refer to EDS for PCIe supported port
configurations.
PCIe Controller 3 Lane Reversal Enabled UP4 Yes
Values: Yes/ No - This setting allows the PCIe lanes on Controller 3 to be UP3 Yes
reversed. Note: Refer to EDS for PCIe supported port
configurations.
Click on Flex I/O in the left tabs menu> PCIe Port Configuration is expanded by default:

# Parameter Platform Settings

PCIe Port Configuration

2
PCIe Controller 1 (Port 1-4) UP4 4x1
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port UP3 4x1
configurations for PCIe Controller 1. For further details see Tiger Lake LP
Platform Controller Hub EDS.

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Table 2-16. - Flex I/O Straps (Sheet 2 of 16)

PCIe Controller 2 (Port 5-8) UP4 4x1

Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port UP3 1x2, 2x1
configurations for PCIe Controller 2. For further details see Tiger Lake LP
Platform Controller Hub EDS.

Note: On UP4 only lanes 7 and 8 are available for use.

PCIe Controller 3 (Port 9-12) UP4 1x4
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port UP3 1x4
configurations for PCIe Controller 3. For further details see Tiger Lake LP
Platform Controller Hub EDS.
Click on Flex I/O in the left tabs menu> SATA / PCIe Combo Port Configuration is expanded by default:

# Parameter Platform Settings

SATA / PCIe Combo Port Configuration

3
SATA / PCIe Combo Port 0 UP4 PCIe
Values: SATA, PCIe, GPIO Polarity PCIe, GPIO Polarity SATA - This setting UP3 PCIe
configures the PCIe port to operate as either:
PCIe Port 11 or SATA Port 0
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.
SATA / PCIe Combo Port 1 UP4 GPIO Polarity PCIe
Values: SATA, PCIe, GPIO Polarity PCIe, GPIO Polarity SATA - This setting UP3 GPIO Polarity PCIe
configures the PCIe port to operate as either:
PCIe Port 12 or SATA Port 1
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.
Click on Flex I/O in the left tabs menu> USB3 Port Configuration is expanded by default:

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Table 2-16. - Flex I/O Straps (Sheet 3 of 16)

# Parameter Platform Settings

USB3 Port Configuration

4
USB3 / PCIe Combo Port 0 UP4 USB3
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to operate UP3 USB3
as either:
PCIe Port 1 or USB3 Port 1
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.

Note: If DCI BSSB for this USB3 Combo port it will be Grayed out.

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Table 2-16. - Flex I/O Straps (Sheet 4 of 16)

USB3 / PCIe Combo Port 1 UP4 USB3

Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to operate UP3 USB3
as either:
PCIe Port 2 or USB3 Port 2
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.

Note: If DCI BSSB for this USB3 Combo port it will be Grayed out.
USB3 / PCIe Combo Port 2 UP4 PCIe
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to operate UP3 PCIe
as either:
PCIe Port 3 or USB3 Port 3
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.

Note: If DCI BSSB for this USB3 Combo port it will be Grayed out.
USB3 / PCIe Combo Port 3 UP4 PCIe
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to operate UP3 PCIe
as either:
PCIe 4 or USB3 Port 4
For further details on Flex I/O see Tiger Lake LP Platform Controller Hub EDS.

Note: If DCI BSSB for this USB3 Combo port it will be Grayed out.
USB3 Port 1 Connector Type Select UP4 Type-A
This setting configures the physical connector type to be used for USB 3.0 / 3.1 UP3 Type-A
Port 1.
USB3 Port 2 Connector Type Select UP4 Type-A
This setting configures the physical connector type to be used for USB 3.0 / 3.1 UP3 Type-A
Port 2.
USB3 Port 3 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for USB 3.0 / 3.1 UP3 Type-C
Port 3.
USB3 Port 4 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for USB 3.0 / 3.1 UP3 Type-C
Port 4.
USB3 Port 1 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
This setting determines USB3 Port 1 speed during platform power-up. UP3 USB3.1 Gen1 LBPM
USB3 Port 2 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
This setting determines USB3 Port 2 speed during platform power-up. UP3 USB3.1 Gen1 LBPM
USB3 Port 3 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
This setting determines USB3 Port 3 speed during platform power-up. UP3 USB3.1 Gen1 LBPM
USB3 Port 4 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
This setting determines USB3 Port 4 speed during platform power-up. UP3 USB3.1 Gen1 LBPM
USB3 Port 1 Speed Capability UP4 USB 3.1 Gen2
This setting determines the USB3 Port 1 speed capabilities. UP3 USB 3.1 Gen2

Note: When a USB 3.2 Gen 2x1 (10 Gb/s) capable port is configured to USB
3.2 Gen 1x1 (5 Gb/s) speed using the soft strap, the port may still send
10 Gb/s compliance patterns if the USB compliance test (TD1.4, and
TD1.7) is run on the port.
USB3 Port 2 Speed Capability UP4 USB 3.1 Gen2
This setting determines the USB3 Port 2 speed capabilities. UP3 USB 3.1 Gen2

Note: When a USB 3.2 Gen 2x1 (10 Gb/s) capable port is configured to USB
3.2 Gen 1x1 (5 Gb/s) speed using the soft strap, the port may still send
10 Gb/s compliance patterns if the USB compliance test (TD1.4, and
TD1.7) is run on the port.

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USB3 Port 3 Speed Capability UP4 USB 3.1 Gen2

This setting determines the USB3 Port 3 speed capabilities. UP3 USB 3.1 Gen2

Note: When a USB 3.2 Gen 2x1 (10 Gb/s) capable port is configured to USB
3.2 Gen 1x1 (5 Gb/s) speed using the soft strap, the port may still send
10 Gb/s compliance patterns if the USB compliance test (TD1.4, and
TD1.7) is run on the port.
USB3 Port 4 Speed Capability UP4 USB 3.1 Gen2
This setting determines the USB3 Port 4 speed capabilities. UP3 USB 3.1 Gen2

Note: When a USB 3.2 Gen 2x1 (10 Gb/s) capable port is configured to USB
3.2 Gen 1x1 (5 Gb/s) speed using the soft strap, the port may still send
10 Gb/s compliance patterns if the USB compliance test (TD1.4, and
TD1.7) is run on the port.
USB Type AB Mode Select UP4 USB Type AB SW
This setting determines how the USB Type AB connector switching is handled. UP3 Select
USB Type AB SW
Select
Click on Flex I/O in the left tabs menu> USB2 Port Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - USB2 Port Configuration

5
USB2 Port 1 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for USB2 Port 1. UP3 Type-C
USB2 Port 2 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 2. UP3 Express Card / M.2
S2
USB2 Port 3 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 3. UP3 Type A / Type C
USB2 Port 4 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 4. UP3 Type A / Type C

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USB2 Port 5 Connector Type Select UP4 Type-C

This setting configures the physical connector type to be used for USB2 Port 5. UP3 Type-C
USB2 Port 6 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for USB2 Port 6. UP3 Type-C
USB2 Port 7 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 7. UP3 Type-C
USB2 Port 8 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 8. UP3 Type A / Type C
USB2 Port 9 Connector Type Select UP4 Type A / Type C
This setting configures the physical connector type to be used for USB2 Port 9. UP3 Type A / Type C
USB2 Port 10 Connector Type Select UP4 Express Card / M.2
This setting configures the physical connector type to be used for USB2 Port 10. UP3 S2
Express Card / M.2
S2
Click on Flex I/O in the left tabs menu> Type-C Subsystem Configuration is expanded by default:

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# Parameter Platform Settings

Type-C Subsystem Configuration

6
IO Manageability Engine Binary File - This loads the IO Manageability binary UP4 IOM Binary
that will be merged into the output image generated by the Intel® FIT. UP3 IOM Binary
IO Manageability Engine Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enables / disables the Type-C Subsystem IO Manageability Engine on
the platform.
IO Manageability Engine Length - This displays the length of the IO
Manageability binary.
Note: This value will be automatically populated by Intel® FIT during image
build.
IO Manageability Engine Version - This displays the version of IO
Manageability binary.
PHY Binary File - This loads the MG PHY binary that will be merged into the UP4 PHY Binary
output image generated by the Intel® FIT. UP3 PHY Binary
PHY Manifest Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enables / disables the NPHY on the platform.
PHY Length - This displays the length of the PHY binary.
Note: This value will be automatically populated by Intel® FIT during image
build.
PHY Version - This displays the version of PHY binary.
Thunderbolt(TM)/USB4(TM) Binary File UP4 TBT Binary
Values: Yes/No UP3 TBT Binary
This setting enables Anti-Roll back for the Type-C Subsystem Thunderbolt(TM)/
USB4(TM) binary.
Thunderbolt(TM)/USB4(TM) Length - This displays the length of the
Thunderbolt(TM)/USB4(TM) binary.
Note: This value will be automatically populated by Intel® FIT during image
build.
Thunderbolt(TM)/USB4(TM) Version - This displays the version of
Thunderbolt(TM)/USB4(TM) binary.
Tcss - Partial Update Enabled UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
This setting enabled partial firmware update of the TCSS partitions.
Type-C Subsystem Port Enable Mask UP4 0xF
This setting determines the Type-C Subsystem Port Enable Mask UP3 0xF
Type-C Subsystem Authentication Enabled UP4 Yes
Values: Yes/No UP3 Yes
This setting enables / disables firmware authentication for the Type-C Subsystem
on power-up.
Type-C Port 1 Configuration UP4 No Restrictions
Value: No Restrictions/DP Fixed Connection/No Thunderbolt UP3 No Restrictions
This setting determines the configuration for Type-C Port 1
Type-C Port 2 Configuration UP4 No Restrictions
Value: No Restrictions/DP Fixed Connection/No Thunderbolt UP3 No Restrictions
This setting determines the configuration for Type-C Port 2
Type-C Port 3 Configuration UP4 No Restrictions
Value: No Restrictions/DP Fixed Connection/No Thunderbolt UP3 No Restrictions
This setting determines the configuration for Type-C Port 3
Type-C Port 4 Configuration UP4 No Restrictions
Value: No Restrictions/DP Fixed Connection/No Thunderbolt UP3 No Restrictions
This setting determines the configuration for Type-C Port 4

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Type-C Port 1 Speed Capability UP4 USB 3.1 Gen2

Values: USB 3.1 Gen2/USB 3.1 Gen1 UP3 USB 3.1 Gen2
This setting determines the Type-C Port 1 speed capability
Type-C Port 2 Speed Capability UP4 USB 3.1 Gen2
Values: USB 3.1 Gen2/USB 3.1 Gen1 UP3 USB 3.1 Gen2
This setting determines the Type-C Port 2 speed capability
Type-C Port 3 Speed Capability UP4 USB 3.1 Gen2
Values: USB 3.1 Gen2/USB 3.1 Gen1 UP3 USB 3.1 Gen2
This setting determines the Type-C Port 3 speed capability
Type-C Port 4 Speed Capability UP4 USB 3.1 Gen2
Values: USB 3.1 Gen2/USB 3.1 Gen1 UP3 USB 3.1 Gen2
This setting determines the Type-C Port 4 speed capability
Type-C Port 1 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
Values: USB3.1 Gen1 LBPM/USB3.1 Gen2 skip LBPM UP3 USB3.1 Gen1 LBPM
This setting determines Type-C Port 1 speed during platform power-up.
Type-C Port 2 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
Values: USB3.1 Gen1 LBPM/USB3.1 Gen2 skip LBPM UP3 USB3.1 Gen1 LBPM
This setting determines Type-C Port 2 speed during platform power-up.
Type-C Port 3 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
Values: USB3.1 Gen1 LBPM/USB3.1 Gen2 skip LBPM UP3 USB3.1 Gen1 LBPM
This setting determines Type-C Port 3 speed during platform power-up.
Type-C Port 4 Initialization Speed Select UP4 USB3.1 Gen1 LBPM
Values: USB3.1 Gen1 LBPM/USB3.1 Gen2 skip LBPM UP3 USB3.1 Gen1 LBPM
This setting determines Type-C Port 4 speed during platform power-up.
Type-C Port 1 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for Type-C Port 1. UP3 Type-C
Type-C Port 2 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for Type-C Port 2. UP3 Type-C
Type-C Port 3 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for Type-C Port 3. UP3 Type-C
Type-C Port 4 Connector Type Select UP4 Type-C
This setting configures the physical connector type to be used for Type-C Port 4. UP3 Type-C
xDCI Split Die Configuration UP4 xDCI Split Die
Values: xDCI Split Die Enabled, xDCI Split Die Disabled UP3 Enabled
This determines USB3 behavior between the PCH USB3 ports and the CPU Type- xDCI Split Die
C ports. Enabled

Note: This setting needs to be set to xDCI Split Die Enabled when using the
CPU side Type-C Subsystem.
Thunderbolt(TM)/USB4(TM) Port 2 Speed Capability UP4 Gen3
Values: Gen2 Only, Gen3 UP3 Gen3
This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 1 if it
will only be supporting Gen2 speeds.

Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps

Thunderbolt(TM) 3 - Compatibility Mode.
Thunderbolt(TM)/USB4(TM) Port 1 Speed Capability UP4 Gen3
Values: Gen2 Only, Gen3 UP3 Gen3
This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 1 if it
will only be supporting Gen2 speeds.

Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps

Thunderbolt(TM) 3 - Compatibility Mode.
Thunderbolt(TM)/USB4(TM) Port 4 Speed Capability UP4 Gen3
Values: Gen2 Only, Gen3 UP3 Gen3
This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 1 if it
will only be supporting Gen2 speeds.

Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps

Thunderbolt(TM) 3 - Compatibility Mode.

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Thunderbolt(TM)/USB4(TM) Port 3 Speed Capability UP4 Gen3

Values: Gen2 Only, Gen3 UP3 Gen3
This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 1 if it
will only be supporting Gen2 speeds.

Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps

Thunderbolt(TM) 3 - Compatibility Mode.
Click on Flex I/O in the left tabs menu> Thunderbolt Configuration is expanded by default:

# Parameter Platform Settings

Thunderbolt Configuration

7
Thunderbolt(TM)/USB4(TM) Enable UP4 Yes
Values: Yes/No UP3 Yes
This setting determines if the Thunderbolt(tm)/USB4(TM) interface is enabled on
the platform.
Click on Flex I/O in the left tabs menu> Power Delivery PD Controller Configuration is expanded by default:

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Power Delivery PD Controller Configuration

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PMC-PD controller USB-C Mode Enabled UP4 PMC / SMBus

Values: UP3 PMC / SMBus
0: PMC interfaces with an eSPI connected agent via eSPI OOB
1: PMC interfaces with PD chips/Re-timer via ALERT# pin which triggers
SMBus transactions.

This bit defines how the PMC interfaces with the Type-C components on the
board.

Notes:
1. This setting is greyed and not configurable for LP based SKUs. for UP3/UP4
SKUs, PMC interfaces with PD chips/Re-timer via ALERT# pin.
2. if user selection is 0 where PMC interfaces with an eSPI connected agent, all
of the below parameters are N/A and will be grayed out.
Re-timer Power Gating Enabled UP4 No
Values: Yes / No UP3 No
This setting indicates whether platform Re-timer power gating is enabled.
Type-C port 1 Enabled UP4 Yes
Values: Yes / No UP3 Yes
This setting indicates whether the associated Type-C port1 is enabled.

Note: This setting is only available for configuration when PMC-PD controller
USB-C Mode Enabled parameter is set to 1.

USB2 Port Number associated for Type-C Port 1 UP4 USB2 Port 1
Values: USB2 Port 1,USB2 Port 2,USB2 Port 3,USB2 Port 4,USB2 Port UP3 USB2 Port 1
5,USB2 Port 6,USB2 Port 7,USB2 Port 8,USB2 Port 9,USB2 Port 10
This indicates the USB2 port number for the associated Type-C port1.

Notes:
1. This parameter is applicable only when Type-C port 1 Enabled is set to yes.
2. Once user selects USB2 port number associated with Type-C port1,the
respective USB2 port connector selection will be greyed out and auto set to
Type-C under the USB2 Port Configuration section. example: if USB2 Port
number associated for Type-C Port 1 is set to “USB2 Port 2” ,Parameter
under Flex I/O->USB2 Port Configuration->USB2 Port 2 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
USB3 Port number associated for Type-C Port 1 UP4 USB3 Port 1
Values: USB3 Port 1,USB3 Port 2,USB3 Port 3,USB3 Port 4 UP3 USB3 Port 1
This indicates the USB3 port number for the associated Type-C port1.

Notes:
1. This parameter is applicable only when Type-C port 1 Enabled is set to yes.
2. Once user selects USB3 port number associated with Type-C port1,the
respective USB3 port connector selection will be greyed out and auto set to
Type-C under the USB3 Port Configuration section. example: if USB Port
number associated for Type-C Port 1 is set to “USB3 Port 6” ,Parameter
under Flex I/O->USB3 Port Configuration->USB3 Port 6 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
Type-C Port 1 Re-timer Present UP4 Yes
Values: Yes / No UP3 Yes
This indicates whether a re-timer is present for the associated Type-C port.

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Type-C Port 1 Re-timer Configuration Enabled UP4 No

Values: Yes / No UP3 No
Indicates whether the associated re-timer requires configuration. Yes =
configuration done via PMC; No = configuration done via PD Controller.
Type-C Port 1 Re-timer SMBus Address UP4 0x40
Value: Hex UP3 0x40
This indicates the SMBus address for the associated re-timer.
Type-C Port 1 SMBus Address UP4 0x20
Value: Hex UP3 0x50
This indicates the SMBus address for the associated Type-C port.

Note: OEMs are recommended to set unique SMBus address allocation for
Type-C port and Re-timer associated.
Type-C port 2 Enabled UP4 Yes
Values: Yes / No UP3 Yes
This setting indicates whether the associated Type-C port is enabled.

Note: This setting is only available for configuration when PMC-PD controller
USB-C Mode Enabled parameter is set to 1.
USB2 Port Number associated for Type-C Port 2 UP4 USB2 Port 5
Values: USB2 Port 1,USB2 Port 2,USB2 Port 3,USB2 Port 4,USB2 Port UP3 USB2 Port 5
5,USB2 Port 6,USB2 Port 7,USB2 Port 8,USB2 Port 9,USB2 Port 10
This indicates the USB2 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 2 Enabled is set to yes.
2. Once user selects USB2 port number associated with Type-C port2,the
respective USB2 port connector selection will be greyed out and auto set to
Type-C under the USB2 Port Configuration section. example: if USB2 Port
number associated for Type-C Port 2 is set to “USB2 Port 2” ,Parameter
under Flex I/O->USB2 Port Configuration->USB2 Port 2 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
USB3 Port number associated for Type-C Port 2 UP4 USB3 Port 2
Values: USB3 Port 1,USB3 Port 2,USB3 Port 3,USB3 Port 4 UP3 USB3 Port 2
This indicates the USB3 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 2Enabled is set to yes.
2. Once user selects USB3 port number associated with Type-C port2,the
respective USB3 port connector selection will be greyed out and auto set to
Type-C under the USB3 Port Configuration section. example: if USB Port
number associated for Type-C Port 2is set to “USB3 Port 6” ,Parameter
under Flex I/O->USB3 Port Configuration->USB3 Port 6 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
Type-C Port 2 Re-timer Present UP4 Yes
Values: Yes / No UP3 Yes
This indicates whether a re-timer is present for the associated Type-C port.
Type-C Port 2 Re-timer Configuration Enabled UP4 No
Values: Yes / No UP3 No
Indicates whether the associated re-timer requires configuration. Yes =
configuration done via PMC; No = configuration done via PD Controller.

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Type-C Port 2 Re-timer SMBus Address UP4 0x41

Value: Hex UP3 0x41
This indicates the SMBus address for the associated re-timer.
Type-C Port 2 SMBus Address UP4 0x24
Value: Hex UP3 0x51
This indicates the SMBus address for the associated Type-C port.

Note: OEMs are recommended to set unique SMBus address allocation for
Type-C port and Re-timer associated.
Type-C port 3 Enabled UP4 Yes
Values: Yes / No UP3 Yes
This setting indicates whether the associated Type-C port is enabled.

Note: This setting is only available for configuration when PMC-PD controller
USB-C Mode Enabled parameter is set to 1.
USB2 Port Number associated for Type-C Port 3 UP4 USB2 Port 6
Values: USB2 Port 1,USB2 Port 2,USB2 Port 3,USB2 Port 4,USB2 Port UP3 USB2 Port 6
5,USB2 Port 6,USB2 Port 7,USB2 Port 8,USB2 Port 9,USB2 Port 10
This indicates the USB2 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 3 Enabled is set to yes.
2. Once user selects USB2 port number associated with Type-C por3 ,the
respective USB2 port connector selection will be greyed out and auto set to
Type-C under the USB2 Port Configuration section. example: if USB2 Port
number associated for Type-C Port 3 is set to “USB2 Port 2” ,Parameter
under Flex I/O->USB2 Port Configuration->USB2 Port 2 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
USB3 Port number associated for Type-C Port 3 UP4 USB3 Port 3
Values: USB3 Port 1,USB3 Port 2,USB3 Port 3,USB3 Port 4 UP3 USB3 Port 3
This indicates the USB3 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 3 Enabled is set to yes.
2. Once user selects USB3 port number associated with Type-C port3,the
respective USB3 port connector selection will be greyed out and auto set to
Type-C under the USB3 Port Configuration section. example: if USB Port
number associated for Type-C Port 3 is set to “USB3 Port 6” ,Parameter
under Flex I/O->USB3 Port Configuration->USB3 Port 6 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
Type-C Port 3 Re-timer Present UP4 Yes
Values: Yes / No UP3 Yes
This indicates whether a re-timer is present for the associated Type-C port.
Type-C Port 3 Re-timer Configuration Enabled UP4 No
Values: Yes / No UP3 No
Indicates whether the associated re-timer requires configuration. Yes =
configuration done via PMC; No = configuration done via PD Controller.
Type-C Port 3 Re-timer SMBus Address UP4 0x42
Value: Hex UP3 0x42
This indicates the SMBus address for the associated re-timer.

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Type-C Port 3 SMBus Address UP4 0x23

Value: Hex UP3 0x52
This indicates the SMBus address for the associated Type-C port.

Note: OEMs are recommended to set unique SMBus address allocation for
Type-C port and Re-timer associated.
Type-C port 4 Enabled UP4 No
Values: Yes / No UP3 Yes
This setting indicates whether the associated Type-C port is enabled.

Note: This setting is only available for configuration when PMC-PD controller
USB-C Mode Enabled parameter is set to 1.
USB2 Port Number associated for Type-C Port 4 UP4 USB2 Port 7
Values: USB2 Port 1,USB2 Port 2,USB2 Port 3,USB2 Port 4,USB2 Port UP3 USB2 Port 7
5,USB2 Port 6,USB2 Port 7,USB2 Port 8,USB2 Port 9,USB2 Port 10
This indicates the USB2 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 4 Enabled is set to yes.
2. Once user selects USB2 port number associated with Type-C port4,the
respective USB2 port connector selection will be greyed out and auto set to
Type-C under the USB2 Port Configuration section. example: if USB2 Port
number associated for Type-C Port 4 is set to “USB2 Port 2” ,Parameter
under Flex I/O->USB2 Port Configuration->USB2 Port 2 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
USB3 Port number associated for Type-C Port 4 UP4 USB3 Port 4
Values: USB3 Port 1,USB3 Port 2,USB3 Port 3,USB3 Port 4 UP3 USB3 Port 4
This indicates the USB3 port number for the associated Type-C port.

Notes:
1. This parameter is applicable only when Type-C port 4 Enabled is set to yes.
2. Once user selects USB3 port number associated with Type-C port4,the
respective USB3 port connector selection will be greyed out and auto set to
Type-C under the USB3 Port Configuration section. example: if USB Port
number associated for Type-C Port 4 is set to “USB3 Port 6” ,Parameter
under Flex I/O->USB3 Port Configuration->USB3 Port 6 Connector Type
Select will be grayed out and auto set to “Type C”.
3. OEMs are recommended to configure different USB-C connectors with
increasing port numbers (TCP0_*, TCP1_*, TCP2_*, TCP3_*), should be
paired with increasing number of USB2 ports from PCH. (this is needed to
make split xDCI controller work functionally)E.g. (TCP0_* , USB2*_1),
(TCP1_* , USB2*_3), (TCP2_* , USB2*_4), (TCP3_* , USB2*_5)
Type-C Port 4 Re-timer Present UP4 No
Values: Yes / No UP3 Yes
This indicates whether a re-timer is present for the associated Type-C port.
Type-C Port 4 Re-timer Configuration Enabled UP4 No
Values: Yes / No UP3 No
Indicates whether the associated re-timer requires configuration. Yes =
configuration done via PMC; No = configuration done via PD Controller.
Type-C Port 4 Re-timer SMBus Address UP4 0x0
Value: Hex UP3 0x43
This indicates the SMBus address for the associated re-timer.
Type-C Port 4 SMBus Address UP4 0x0
Value: Hex UP3 0x53
This indicates the SMBus address for the associated Type-C port.

Note: OEMs are recommended to set unique SMBus address allocation for
Type-C port and Re-timer associated.

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Type-C Port 1 Re-Timer Configuration Type Select UP4 1 Re-Timer

Values: 1 Re-Timer, 2 Re-Timers UP3 1 Re-Timer
This setting determines the number of Re-Timers being used for TYpe-C Port 1
Type-C Port 2 Re-Timer Configuration Type Select UP4 1 Re-Timer
Values: 1 Re-Timer, 2 Re-Timers UP3 1 Re-Timer
This setting determines the number of Re-Timers being used for TYpe-C Port 2
Type-C Port 3 Re-Timer Configuration Type Select UP4 1 Re-Timer
Values: 1 Re-Timer, 2 Re-Timers UP3 1 Re-Timer
This setting determines the number of Re-Timers being used for TYpe-C Port 3
Type-C Port 4 Re-Timer Configuration Type Select UP4 1 Re-Timer
Values: 1 Re-Timer, 2 Re-Timers UP3 1 Re-Timer
This setting determines the number of Re-Timers being used for TYpe-C Port 4

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Table 2-17. - GPIO (Sheet 1 of 19)

Click on GPIO in the left tabs menu> GPIO VCCIO Voltage Control is expanded by default:

# Parameter Platform Settings

GPIO VCCIO Voltage Control

1 Warning: Incorrectly configuring GPIO voltages may result in MCP

damage. The voltage settings below are for the specific RVPs
noted under the Platform column. Customers should check
their schematics to verify that the appropriate voltages are
configured.

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Table 2-17. - GPIO (Sheet 2 of 19)

GPP_A0 Individual Voltage Select UP4 1.8 Volts

Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A0 GPIO pin.
# Parameter Platform Settings
GPP_A1 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A1 GPIO pin.
GPP_A2 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A2 GPIO pin.
GPP_A3 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A3 GPIO pin.
GPP_A4 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A4 GPIO pin.
GPP_A5 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A5 GPIO pin.
GPP_A6 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A6 GPIO pin.
GPP_A7 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A7 GPIO pin.
GPP_A8 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A8 GPIO pin.
GPP_A9 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A9 GPIO pin.
GPP_A10 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_A10 GPIO pin.
GPP_A11 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A11 GPIO pin.
GPP_A12 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A12 GPIO pin.
GPP_A13 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A13 GPIO pin.
GPP_A14 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A14 GPIO pin.
GPP_A15 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A15 GPIO pin.
GPP_A16 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A16 GPIO pin.
GPP_A17 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A17 GPIO pin.

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Table 2-17. - GPIO (Sheet 3 of 19)

GPP_A18 Individual Voltage Select UP4 3.3 Volts

Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A18 GPIO pin.
GPP_A19 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A19 GPIO pin.
GPP_A20 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A20 GPIO pin.
GPP_A21 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A21 GPIO pin.
GPP_A22 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A22 GPIO pin.
GPP_A23 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_A23 GPIO pin.

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Table 2-17. - GPIO (Sheet 4 of 19)

# Parameter Platform Settings

GPP_B0 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B0 GPIO pin.
GPP_B1 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B1 GPIO pin.
GPP_B2 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B2 GPIO pin.

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Table 2-17. - GPIO (Sheet 5 of 19)

# Parameter Platform Settings

GPP_B3 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B3 GPIO pin.
GPP_B4 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B4 GPIO pin.
GPP_B5 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B5 GPIO pin.
GPP_B6 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B6 GPIO pin.
GPP_B7 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B7 GPIO pin.
GPP_B8 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B8 GPIO pin.
GPP_B9 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B9 GPIO pin.
GPP_B10 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B10 GPIO pin.
GPP_B11 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B11 GPIO pin.
GPP_B12 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B12 GPIO pin.
GPP_B13 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B13 GPIO pin.
GPP_B14 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B14 GPIO pin.
GPP_B15 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B15 GPIO pin.
GPP_B16 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B16 GPIO pin.
GPP_B17 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B17 GPIO pin.
GPP_B18 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B18 GPIO pin.
GPP_B19 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B19 GPIO pin.
GPP_B20 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B20 GPIO pin.

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Table 2-17. - GPIO (Sheet 6 of 19)

# Parameter Platform Settings

GPP_B21 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B21 GPIO pin.
GPP_B22 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_B22 GPIO pin.
GPP_B23 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_B23 GPIO pin.

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Table 2-17. - GPIO (Sheet 7 of 19)

# Parameter Platform Settings

GPP_C0 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C0 GPIO pin.
GPP_C1 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C1 GPIO pin.
GPP_C2 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C2 GPIO pin.
GPP_C3 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C3 GPIO pin.
GPP_C4 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C4 GPIO pin.
GPP_C5 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C5 GPIO pin.
GPP_C6 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C6 GPIO pin.
GPP_C7 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C7 GPIO pin.
GPP_C8 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C8 GPIO pin.
GPP_C9 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C9 GPIO pin.
GPP_C10 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C10 GPIO pin.
GPP_C11 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C11 GPIO pin.
GPP_C12 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C12 GPIO pin.
GPP_C13 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C13 GPIO pin.
GPP_C14 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C14 GPIO pin.
GPP_C15 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C15 GPIO pin.
GPP_C16 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C16 GPIO pin.
GPP_C17 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C17 GPIO pin.

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Table 2-17. - GPIO (Sheet 8 of 19)

# Parameter Platform Settings

GPP_C18 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C18 GPIO pin.
GPP_C19 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_C19 GPIO pin.
GPP_C20 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C20 GPIO pin.
GPP_C21 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C21 GPIO pin.
GPP_C22 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C22 GPIO pin.
GPP_C23 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_C23 GPIO pin.

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Table 2-17. - GPIO (Sheet 9 of 19)

# Parameter Platform Settings

GPP_D0 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D0 GPIO pin.
GPP_D1 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D1 GPIO pin.
GPP_D2 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D2 GPIO pin.
GPP_D3 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D3 GPIO pin.
GPP_D4 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D4 GPIO pin.

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Table 2-17. - GPIO (Sheet 10 of 19)

# Parameter Platform Settings

GPP_D5 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D5 GPIO pin.
GPP_D6 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D6 GPIO pin.
GPP_D7 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D7 GPIO pin.
GPP_D8 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D8 GPIO pin.
GPP_D9 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D9 GPIO pin.
GPP_D10 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D10 GPIO pin.
GPP_D11 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D11 GPIO pin.
GPP_D12 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D12 GPIO pin.
GPP_D13 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D13 GPIO pin.
GPP_D14 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D14 GPIO pin.
GPP_D15 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D15 GPIO pin.
GPP_D16 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_D16 GPIO pin.
GPP_D17 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D17 GPIO pin.
GPP_D18 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D18 GPIO pin.
GPP_D19 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_D19 GPIO pin.

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Table 2-17. - GPIO (Sheet 11 of 19)

# Parameter Platform Settings

GPP_E0 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E0 GPIO pin.
GPP_E1 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E1 GPIO pin.
GPP_E2 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E2 GPIO pin.

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Table 2-17. - GPIO (Sheet 12 of 19)

# Parameter Platform Settings

GPP_E3 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E3 GPIO pin.
GPP_E4 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E4 GPIO pin.
GPP_E5 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E5 GPIO pin.
GPP_E6 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E6 GPIO pin.
GPP_E7 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E7 GPIO pin.
GPP_E8 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E8 GPIO pin.
GPP_E9 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E9 GPIO pin.
GPP_E10 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E10 GPIO pin.
GPP_E11 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E11 GPIO pin.
GPP_E12 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E12 GPIO pin.
GPP_E13 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E13 GPIO pin.
GPP_E14 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E14 GPIO pin.
GPP_E15 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E15 GPIO pin.
GPP_E16 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E16 GPIO pin.
GPP_E17 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_E17 GPIO pin.
GPP_E18 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E18 GPIO pin.
GPP_E19 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E19 GPIO pin.
GPP_E20 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E20 GPIO pin.

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Table 2-17. - GPIO (Sheet 13 of 19)

# Parameter Platform Settings

GPP_E21 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E21 GPIO pin.
GPP_E22 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E22 GPIO pin.
GPP_E23 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_E23 GPIO pin.

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Table 2-17. - GPIO (Sheet 14 of 19)

# Parameter Platform Settings

GPP_F0 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F0 GPIO pin.
GPP_F1 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F1 GPIO pin.
GPP_F2 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F2 GPIO pin.
GPP_F3 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F3 GPIO pin.
GPP_F4 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F4 GPIO pin.
GPP_F5 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F5 GPIO pin.
GPP_F6 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F6 GPIO pin.
GPP_F7 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F7 GPIO pin.
GPP_F8 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F8 GPIO pin.
GPP_F9 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F9 GPIO pin.
GPP_F10 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F10 GPIO pin.
GPP_F11 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F11 GPIO pin.
GPP_F12 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F12 GPIO pin.
GPP_F13 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F13 GPIO pin.
GPP_F14 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F14 GPIO pin.
GPP_F15 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F15 GPIO pin.
GPP_F16 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F16 GPIO pin.
GPP_F17 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F17 GPIO pin.

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Table 2-17. - GPIO (Sheet 15 of 19)

# Parameter Platform Settings

GPP_F18 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_F18 GPIO pin.
GPP_F19 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F19 GPIO pin.
GPP_F20 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F20 GPIO pin.
GPP_F21 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F21 GPIO pin.
GPP_F22 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F22 GPIO pin.
GPP_F23 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_F23 GPIO pin.

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Table 2-17. - GPIO (Sheet 16 of 19)

# Parameter Platform Settings

GPP_H0 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H1 GPIO pin.
GPP_H1 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H2 GPIO pin.
GPP_H2 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H3 GPIO pin.

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Table 2-17. - GPIO (Sheet 17 of 19)

# Parameter Platform Settings

GPP_H3 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H4 GPIO pin.
GPP_H4 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H5 GPIO pin.
GPP_H5 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H5 GPIO pin.
GPP_H6 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H6 GPIO pin.
GPP_H7 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H7 GPIO pin.
GPP_H8 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H8 GPIO pin.
GPP_H9 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H9 GPIO pin.
GPP_H10 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H10 GPIO pin.
GPP_H11 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H11 GPIO pin.
GPP_H12 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H12 GPIO pin.
GPP_H13 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H13 GPIO pin.
GPP_H14 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H14 GPIO pin.
GPP_H15 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H15 GPIO pin.
GPP_H16 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H16 GPIO pin.
GPP_H17 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H17 GPIO pin.
GPP_H18 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H18 GPIO pin.
GPP_H19 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H19 GPIO pin.
GPP_H20 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H20 GPIO pin.

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Table 2-17. - GPIO (Sheet 18 of 19)

# Parameter Platform Settings

GPP_H21 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H21 GPIO pin.
GPP_H22 Individual Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for the GPP_H22 GPIO pin.
GPP_H23 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_H23 GPIO pin.

# Parameter Platform Settings

GPP_T2 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_T2 GPIO pin.
GPP_T3 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_T3 GPIO pin.

# Parameter Platform Settings

GPP_U4 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_U4 GPIO pin.
GPP_U5 Individual Voltage Select UP4 3.3 Volts
Values: 3.3Volts / 1.8Volts UP3 3.3 Volts
This setting configures the VCCIO voltage for the GPP_U5 GPIO pin.
Intel® HD Audio Voltage Select UP4 1.8 Volts
Values: 3.3Volts / 1.8Volts UP3 1.8 Volts
This setting configures the VCCIO voltage for all of the Intel® HD Audio GPIO
pins.

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Table 2-17. - GPIO (Sheet 19 of 19)

# Parameter Platform Settings

Thunderbolt LSx/BSSB-LS Configuration

4
Thunderbolt LSx/BSSB-LS 0 VCCIO UP4 TX VCCIO
Values: TX VCCIO / Legacy VCCIO UP3 TX VCCIO
This setting configured Thunderbolt LSx/BSSB-LS 0 VCCIO.
Thunderbolt LSx/BSSB-LS 1 VCCIO UP4 TX VCCIO
Values: TX VCCIO / Legacy VCCIO UP3 TX VCCIO
This setting configured Thunderbolt LSx/BSSB-LS 0 VCCIO.
Thunderbolt LSx/BSSB-LS 2 VCCIO UP4 TX VCCIO
Values: TX VCCIO / Legacy VCCIO UP3 TX VCCIO
This setting configured Thunderbolt LSx/BSSB-LS 0 VCCIO.
Thunderbolt LSx/BSSB-LS 3 VCCIO UP4 TX VCCIO
Values: TX VCCIO / Legacy VCCIO UP3 TX VCCIO
This setting configured Thunderbolt LSx/BSSB-LS 0 VCCIO.

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Table 2-18. - Download and Execute

Click on Download and Execute in the left tabs menu> DnX Image is expanded by default:

# Parameter Platform Settings

Dnx Image

1
Platform ID UP4 0
Value: Hex UP3 0
This configures the Platform ID that DnX uses to verify the image is correct for the
platform. Before FPFs are fused, this field is ignored and DnX will accept any image.
After FPS lock, only images with this Platform ID will be accepted by DnX.

Caution: Ensure that the Platform ID value is correctly populated prior to

close of manufacturing on the platform.
OEM ID UP4 0
Value: Hex UP3 0
This configures the OEM ID that DnX uses to verify the image is correct for the
platform. Before FPFs fused, this field is ignored and DnX will accept any image.
After FPF lock, only images with this OEM ID will be accepted by DnX.

Caution: Ensure that the OEM ID value is correctly populated prior to

close of manufacturing on the platform.
BuildEnabled UP4 No
Value:Binary Yes / No UP3 No
This setting determines if the Intel® FIT tool should build a DnX image
OutputFileName UP4 dnx.bin
Value:Binary File UP3 dnx.bin
This setting allow the OEM to designate the DnX binary name for the output file.
DnX image private sign key path UP4 -
This designates the path to the private key to use to sign the DnX image. This UP3 -
setting is only configurable when OEM signing is enabled (See Platform Integrity /
OemPublicKeyHash).
Click on Download and Execute in the left tabs menu> DnX Fuses is expanded by default:

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Table 2-18. - Download and Execute

# Parameter Platform Settings

DnX Fuses

2
DnX Enabled UP4 Yes
Value: Yes / No UP3 Yes
This setting enables / disables DnX.

Caution: Setting this option to No will permanently DnX on the platform

hardware.
Platform ID UP4 0
Value: Hex UP3 0
This configures the Platform ID that DnX uses to verify the image is correct for the
platform. Before FPFs are fused, this field is ignored and DnX will accept any image.
After FPS lock, only images with this Platform ID will be accepted by DnX.

Caution: Ensure that the Platform ID value is correctly populated prior to

close of manufacturing on the platform.
OEM ID UP4 0
Value: Hex UP3 0
This configures the OEM ID that DnX uses to verify the image is correct for the
platform. Before FPFs fused, this field is ignored and DnX will accept any image.
After FPF lock, only images with this OEM ID will be accepted by DnX.

Caution: Ensure that the OEM ID value is correctly populated prior to

close of manufacturing on the platform.

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Table 2-19. - Intel® Unique Platform ID

Click on Intel® Unique Platform ID in the left tabs menu> Intel® Unique Platform ID Configuration is expanded by
default:

# Parameter Platform Settings

Intel® Unique Platform ID Configuration

1
UPID Supported Feature RKL-S No
Values: Yes/No
Unique Platform ID RKL-S 0x0
Values: Hex
This setting allows OEMs to configure their Unique ID into the platform FPFs.

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Table 2-20. - FW Update Image Build

Click on FW Update Image Build in the left tabs menu> ME Image is expanded by default:

# Parameter Platform Settings

The FW Update Image Build tab allows users to build firmware update
image binaries based on one or several of the following elements
combined together:

Intel® ME, PMC, OEM KM, IOM, MG, TBT, ISH, iUnit, PCHC and GBST
ME Image

1
ME Binary Image UP4 ME Binary
Values: Binary File UP3 ME Binary
This loads the Embedded Controller binary that will be merged into the FWUpdate
image generated by the Intel® FIT tool.
Click on FW Update Image Build in the left tabs menu> PMC Image is expanded by default:

# Parameter Platform Settings

PMC Image

2
PMC Max Length
PMC Binary Image UP4 PMC Binary
Values: Binary File UP3 PMC Binary
This loads the PMC binary that will be merged into the FWUpdate image generated
by the Intel® FIT tool.
Click on FW Update Image Build in the left tabs menu> OEM KM Image is expanded by default:

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Table 2-20. - FW Update Image Build

# Parameter Platform Settings

OEM KM Image

3
OEM KM UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables OEM KM in the FWUpdate image.
OEM KM Max Length
OEM Key Manifest Binary File UP4 OEM KM Binary
Values: Binary File UP3 OEM KM Binary
This loads the OEM Key manifest binary merged into the output image generated
by the Intel® FIT tool.
Click on FW Update Image Build in the left tabs menu> IOM Image is expanded by default:

# Parameter Platform Settings

IOM Image

4
IOM UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables IOM in the FWUpdate image.
IO Manageability Engine Max Length
IO Manageability Engine Binary File UP4 IOM Binary
Values: Binary File UP3 IOM Binary
This loads the IO Manageability binary merged into the output image generated by
the Intel® FIT tool.
Click on FW Update Image Build in the left tabs menu> MG Image is expanded by default:

# Parameter Platform Settings

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Table 2-20. - FW Update Image Build

PHY Image

5
PHY UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables NPHY in the FWUpdate image.
PHY Max Length
PHY Binary File UP4 NPHY Binary
Values: Binary File UP3 NPHY Binary
This loads the NPHY binary merged into the output image generated by the Intel®
FIT tool.
Click on FW Update Image Build in the left tabs menu> Thunderbolt(TM)/USB4(TM) Image is expanded by default:

# Parameter Platform Settings

Thunderbolt(TM)/USB4(TM) Image

6
Thunderbolt(TM)/USB4(TM) UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables Thunderbolt(TM)/USB4(TM) in the FWUpdate image.
Thunderbolt(TM)/USB4(TM) Max Length
Thunderbolt(TM)/USB4(TM) Binary File UP4 TBT Binary
Values: Binary File UP3 TBT Binary
This loads the Thunderbolt(TM)/USB4(TM) binary merged into the output image
generated by the Intel® FIT tool.
Click on FW Update Image Build in the left tabs menu> ISH Image is expanded by default:

# Parameter Platform Settings

ISH Image

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Table 2-20. - FW Update Image Build

ISH UP4 Enabled

Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables ISH in the FWUpdate image.
ISH Max Length
ISH Binary File UP4 ISH Binary
Values: Binary File UP3 ISH Binary
This loads the ISH binary merged into the output image generated by the Intel®
FIT tool.
Click on FW Update Image Build in the left tabs menu> IUNIT Image is expanded by default:

# Parameter Platform Settings

IUNIT Image

8
IUnit UP4 Enabled
Values: Enabled/Disabled UP3 Enabled
This setting Enables / Disables IUNIT in the FWUpdate image.
IUnit Max Length
IUnit Binary File UP4 IUnit Binary
Values: Binary File UP3 IUnit Binary
This loads the IUnit binary merged into the output image generated by the Intel®
FIT tool.
Click on FW Update Image Build in the left tabs menu> PCHC Image is expanded by default:

# Parameter Platform Settings

PCHC Image

9
PCH Configuration Max Length
Values: Binary File UP4 PCHC Binary
This loads the PCHC binary merged into the output image generated by the Intel® UP3 PCHC Binary
FIT tool.
Click on FW Update Image Build in the left tabs menu> GBST Image is expanded by default:

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Table 2-20. - FW Update Image Build

# Parameter Platform Settings

GBST Image

10
GBST Configuration Enable UP4 Disabled
Values: Enabled/Disabled UP3 Disabled
This setting Enables / Disables GBST in the FWUpdate image.
GBST Configuration Max Length
Values: Binary File UP4 GBST Binary
This loads the GBST binary merged into the output image generated by the Intel® UP3 (Optional)
FIT tool. GBST Binary
(Optional)
Note: The GBST sub-partition is used for FuSa safety standards and is not
applicable for client platforms.

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Table 2-21. - Intel® FIT - Build Image

Green Build button

Can also select CTRL+B, or Build> Build Image from the menu bar along the top of the screen
1
Console shows status of build and path where saved

2
Console shows status of build and path where saved

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Programming SPI Flash Devices and Checking Firmware Status

3 Programming SPI Flash Devices

and Checking Firmware Status

Now that the Flash image file has been created, it can be programmed into the SPI
Flash device(s) of the target machine. For platforms that don’t boot, a Flash Chip
Programmer will be required. For platforms that can boot to DOS or Windows*, the
Intel® FPT can be used.

3.1 Flash Burner/Programmer

The specific use of a Flash burner/programmer is beyond the scope of this document.
Here are some general steps that may be followed:
1. Navigate to your Output Directory (as specified in Table 2-2) where your
generated SPI Flash image(s) are saved. It is assumed that this image file is named
outimage.bin.

If two total SPI Flash devices were specified during the build process, then
additional image files will be saved, one for each SPI Flash devices. These files are
assumed to be named outimage(1).bin and outimage(2).bin.
2. Utilize a Flash burner/programmer to program the image(s). For multiple SPI Flash
devices, the images are numbered sequentially to correspond to the first and
second SPI Flash devices accordingly.

3.1.1 In-Circuit SPI Flash Programming for CRB

Mobile CRBs have the SPI Flash devices soldered down. As a result, to program the SPI
Flash for mobile CRBs, follow these steps:
1. Leave CRB powered on.
2. Connect Flash Programmer (such as DediProg SF600) header to connector J3F3
which is labelled “SPI TPM”. Make sure to line up pin 1 on the header.
3. Program the first image [outimage(1).bin] to the CRB.
4. In Dediprog software, select application memory chip 2 button and load second
image if created.
5. Program the second image [outimage(2).bin] to the CRB if created.
6. Once programming is complete, disconnect the Flash Programmer header. Power
off and unplug CRB. Remove cell coin battery, wait approximately 10 seconds.
Replace cell coin battery, plug CRB back in and power on.

3.2 Flash Programming Tool (Intel® FPT)

Intel® FPT can be used to substitute for a Flash burner/programmer, provided the
system is capable of booting to a DOS or Windows* OS.

Note: Intel® FPT will automatically disable the Intel® ME or EFI prior to flashing the
image to the platform.

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3.2.1 Intel® FPT Windows* Version

The Windows* OS versions supported by Intel® FPT are: Windows* PE 64, Windows*
7, Windows* 8/8.1. There are two versions of Intel® FPT for Windows*: a 32-bit
version and a 64-bit version. Most Windows* OS, Windows* 7 (32-bit or 64-bit),
Windows* 8/8.1 (32-bit or 64-bit) can use Windows* version of Intel® FPT. However,
Windows* OS which do not support 32 bit compatible mode (Win PE 64-bit) must use
Intel® FPT Windows* 64-bit version due to compatibility issues.

Use the following steps to program the SPI Flash devices,

1. Navigate to your Output Directory (as specified in Table 2-2) where your
generated SPI Flash image(s) are saved. It is assumed that this image file is named
outimage.bin. Copy this image file to Intel® FPT directory located at “(root)
\Tools\System Tools\Flash Programming Tool\Windows”.
2. Boot the target system to Windows* and open a Command Prompt window. In this
window, change to the Intel® FPT directory and at the prompt type:

fptw.exe -i

The system should respond with the number of SPI Flash device available. For
example:

--- Flash devices Found ---

W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)
W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)

Note: If the SPI Flash device does not currently contain a descriptor it may
report only a single device.
3. Program the SPI Flash image to the Flash device(s) by issuing the following
command at the prompt:

fptw.exe -f outimage.bin

If the programming was successful, then the following message will be shown.

FPT Operation Passed

If the programming was NOT successful, then repeat this step to try again. If
programming problems persist, then check the SPI Flash devices and platform
hardware.
4. Use fptw.exe -greset to perform a G3 power cycle. Next go to Section 3.3 to check
the Intel® ME Firmware status.

3.3 Checking Intel® ME Firmware Status

Use the following steps to check the platform health and Intel® CSME FW status,
1. Copy the file MEInfo.exe in the “(root)\Tools\System Tools\MEInfo\DOS” directory
to the root directory of a bootable USB key.

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2. Boot the target system and use F2 or Del to enter the BIOS setup menu. Load
default values for BIOS (on Intel® CRBs press F3 to load default values). Save and
reboot (on Intel® CRBs press F4 and select Yes).
3. Boot the target system to DOS and change to the root directory of the bootable
USB key. At the DOS prompt type:

MEInfo.exe -fwsts

The system should respond with a message similar to below.

Intel® MEInfo Version: 15.0.0.xxxx

Copyright(C) 2005 - 2017, Intel Corporation. All rights reserved.

FW Status Register1: 0x1E000255

FW Status Register2: 0x60002306
FW Status Register3: 0x00000300
FW Status Register4: 0x00004001
FW Status Register5: 0x00000101
FW Status Register6: 0x03C00FC9

Current State: Normal

ManufacturingMode: Enabled
FlashPartition: Valid
OperationalState: M0 with UMA
InitComplete: Complete
BUPLoadState: Success
ErrorCode: No Error
ModeOfOperation: Normal
Phase: HOSTCOMM Module
ICC: Valid OEM data, ICC programmed
SPI Flash Log: Not Present
ME File System Corrupted: No
FPF and ME Config Status: Not committed

As in the above example if there are NO errors shown, then

• your platform’s health is good
• Intel® CSME FW has successfully initialized
• Intel® CSME FW is operating normally

Note: This section is only intended to show how to use the MEInfo.exe tool for checking
firmware status. For full usage and capabilities of the MEInfo.exe tool, please see the
System Tools User Guide.

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3.4 Common Bring Up Issues and Troubleshooting

Table
Table 3-1. Common Bring Up Issues and Troubleshooting Table

Problem / Issue Solution / Workaround

System does not boot to By default, the system will boot to EFI Shell. To boot to DOS,
DOS 1. Enter BIOS menu, then go to the ‘Boot’ screen
2. Change ‘Boot Option #1’ to be your USB key (ensure USB key is
formatted to be DOS bootable)
3. Press ‘F4’ to save settings and reboot
Hear 3 beeps when Possible device is disconnected or device not found, check
platform powers on • platform power and MCP fan power connectors
• DIMM memory modules (if applicable for memory down modules
• USB devices (keyboard, mouse, USB key) may be plugged into
inactive USB port
• missing/incorrect jumpers
• missing or poorly socketed MCP
No display on monitor Ensure Corporate FW SKU supports integrated graphics. Try external
graphics card.
USB device not detected USB device may be plugged into inactive USB port
or does not work
System does not boot Incorrect Flash image – possible reasons:
(Post Code 00) • wrong FW selected during Flash image build process
• wrong Flash size selected
Re-build image with correct settings and re-flash using Flash burner.

§§

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Appendix — Flash Configurations

A Appendix — Flash
Configurations

This chapter covers only the basic information needed for clock control parameter
programming. For a more detailed treatment of Mainstream - Mobile Family clocks, see
Intel®Tiger Lake PCH-H / LP Clocks and Intel® Converged Security and Management
Engine — Platform Compliancy Guide for ME Hardware.

Figure A-1. Configuration “A” — Desktop/Server/Workstation or Mobile

§§

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Appendix — Intel® ICCS SKU Support Matrix

B Appendix — Intel® ICCS SKU

Support Matrix

The following table describes ICC features supported for specific PCH SKU, clock range
(maximum and minimum), spread mode supported by Tiger Lake-LP SKUs.

Note: Please refer to Tiger Lake-H/LP Platform Controller Hub (PCH) External Design
Specification (EDS) for details about Tiger Lake-H/LP Chipset Clock architecture

In below tables,

Min = Clock Div Max (minimum allowed frequency)

Max = Clock Div Min (maximum allowed frequency)

B.1 Intel® ICCS SKU Matrix - TGP-LP

Note: ICC SKU is divided into 2 categories: Basic and Enhanced. Mark "x" indicates
category supported by PCH SKU.

Table B-1. Intel® ICCS SKU Matrix - TGP-LP

PCH SKU Basic Enhanced

Premium Y x

Premium U x

Base U x

Features Standard Clock Configuration Standard Clock Configuration

Supported Adaptive Clock Configuration

Pre-Defined Standard Standard

ICC profile Adaptive
supported

Clock Range
[Min-Max]=100 MHz. BCLK [Min-Max] = 98 - 100 MHz.
Supported

SSC
Down SSC: 0 - 0.5% Down SSC: 0 - 0.5%
Supported

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Appendix — Boot Guard Configuration

C Appendix — Boot Guard

Configuration

C.1 Boot Guard Profiles

The following table describes the profiles available for Boot Guard Configuration.

Table C-1. Profile Description

Index Profile Name F V M ENF PBE Description

Boot Guard Profile - 0 0 0 00 0 This configuration will invoke Boot Guard during boot with
No_FVME neither Verification nor Measurement. For platforms with all
0
the required Boot Guard components but do not wish to enable
Boot Guard boot block verification protection.

3 Boot Guard VM 0 1 1 00 1 When Verification and Measured are desired and the asset
protection is provided by TPM protection.

4 Boot Guard FVE 1 1 0 11 1 Strict Verification enforcement.

5 Boot Guard FVME 1 1 1 11 1 Strict Verification and Measured enforcement. Prevents

unverified IBB from running.

C.2 Enforcement Policies

Table C-2. Enforcement Policy Description

Error Enforcement
Enforcement Mode Name Description
Policy (ENF)

Infinite time before shutdown – don’t shutdown the

0 Unrestricted Mode platform, let everything run normally.

30 minutes before shutdown – enough time to

1 Remediation Mode remediate the system, e.g. update BIOS or other data
on flash via host tools.

2 Reserved
3 Restricted Mode 0 minutes before shutdown – instant shutdown policy.

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Appendix — Boot Guard Configuration

C.3 OEM Profile Parameters

Table C-3. Profile Parameters Description

Parameter Description Settings

Force Boot Guard ACM Enabled Force Boot Guard Boot determines if the false - Allow the CPU to jump to the
(F) platform starts the Force Boot Guard Boot legacy reset vector if the Boot Guard
timer. If it successfully starts it indicates Module cannot be successfully loaded.
success. When the Force Boot Guard timer (default)
stops, it starts the Protect Bios Environment
timer, if indicated by the boot policy
true - Force the Boot Guard ACM to
restrictions. Anchor ACM then jumps to the
execute.
Initial Boot Block(IBB) with the Force Boot
Guard Boot time stopped and the Protect BIOS
enable timer running.

Verified Boot Enabled (V) Boot Guard cryptographically verifies the false - Platform does not perform
platform Initial Boot Block (IBB) using the verified boot (default)
boot policy key. On successful verification,
Boot Guard executes Initial Boot Block (IBB)
true - Platform performs verified boot
using the boot policy key. If the verification
fails, Anchor signals or enters Remediation.

Measured Boot Enabled (M) Boot Guard measures the Initial Boot Block false - Platform does not perform
(IBB) into the TPM. Boot Guard perform no measured boot (default)
verification that the IBB is correct or from the
platform manufacturer. The Slylake
true - Platform performs measured
implementation of Boot Guard will support
boot
measurements into TPM or Intel’s Platform
Trust Technology.

Protect Bios Environment Platform manufacturer may want Initial boot false - Take no actions to control the
Enabled (PBE) block to be protected between verification/ environment during execution of the
measurement and execution from attacks on BIOS components (default)
buses and non-CPU components. Boot Guard
accomplishes this by allowing the initial boot
true - Takes actions to control the
block to be verified and executed in LLC in
environment during the execution of
NEM if PBE is enabled.
the BIOS components.

Error Enforcement Policy (ENF) Boot Guard invokes the Enforcement Policy See Section C-2 for details.
when a fatal error is encountered. The action
taken by ENF is determined by the OEM set
persistent policies. Like,
• Allowing platform to continue to boot
• Immediate Shutdown
• Shutdown with Timeout intervals
When the ENF logic is invoked, PTT or TPM
also disconnects.

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Appendix — Intel® Platform Trust Technology

D Appendix — Intel® Platform

Trust Technology

D.1 Intel® Platform Trust Technology

The following table describes the platform configurations supported by Intel® Platform
Trust Technology.

Table D-1. Intel® Platform Trust Technology Configuration table

Platform Protection> Intel® PTT Configuration

Platform Protection> Intel® PTT Configuration

Platform Protection> Intel® PTT Configuration

Intel® PTT initial power up state

Intel® PTT Supported [FPF]

Configuration Description
Intel® PTT Supported

Intel® PTT Permanently Disabled No No After the End of Manufacturing command, this setting will
Disabled in HW via FPF permanently set into the FPFs contained in the MCP. If disabled,
the specific MCP can never be enabled for Intel® PTT.

Intel® PTT Permanently Disabled No Yes This setting allows Intel® PTT to be set to disabled without
Disabled in base firmware disabling the MCP FPFs. This is the recommended option to
image permanently disable Intel® PTT on a platform.

Intel® PTT Ship State Disabled Yes Yes Intel® PTT initially shipped in disabled mode, can be enabled by
Disabled in base firmware BIOS command.
image

Intel® PTT Enabled Enabled Yes Yes This is the recommended option to enable Intel® PTT on a
platform.

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 Appendix — Integrated Sensor Hub (ISH) Public Key Settings

E Appendix — Integrated Sensor Hub

(ISH) Public Key Settings
The following table describes the configuration matrix required for ISH configuration for the Intel®
FIT tool. Please see System Tools User Guide within ME kit, Manufacturing Test with Intel® Converged
Security and Management Engine (Intel® ME) Firmware 12 and Intel® Integrated Sensor Solution on
Tiger Lake Mobile, Tiger Lake Desktop, (CDI # WIP) for additional details.

CLSMNF = Close Manufacturing switch used with Intel® Flash Programming Tool (FPT)

PV = Production Version

For additional information on FPT see System Tools User Guide included with ME kit under system
tools folder.

Table E-1. ISH Public Key Settings

FPF Automatic FPF MEI command after FPF MEI command before
Firmware MCP
Commit CLSMNF (Yes/No) CLSMNF (Yes/No)

Pre-production Production No No - Not a valid combination No - Not a valid combination

Production (PV not set) Pre-production No Yes No

Production (PV not set) Production No Yes No

Pre-production Pre-production No Yes No

Production (PV not set) Production Yes No No

Note: The Intel® FIT allows integration of binary files within Integrated Sensor Hub section under ISH
Image and ISH Data. The Intel® FIT does not generate or create the required files. The table above
lists configuration combinations that can be used.

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 Appendix — Integrated Sensor Hub (ISH) Public Key Settings

152 Intel Confidential

 Appendix — RVP Platform Specific Settings

F Appendix — RVP Platform Specific

Settings
The following table describes the configuration matrix of RVP specific settings in the Intel® FIT XML.

Table F-1. RVP Settings

RVP Type Intel® FIT XML setting in StrapsDifferences section Value

UP4

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 Appendix — RVP Platform Specific Settings

154 Intel Confidential