AN-1536

APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

ADuM4135 Gate Driver Performance Driving APTMC120AM20CT1AG

SiC Power Switches
by Martin Murnane

INTRODUCTION to ringing at the gate of the device. These disadvantages can

In solar photovoltaics (PV) and energy storage applications, cause problems when driving higher voltage SiC devices, where
there is a trend towards increased power density, along with the significant power density improvement can be achieved by their
ever present need of improved efficiency. A solution to this implementation. One combination of gate driver and SiC that
problem comes in the form of silicon carbide (SiC) power can solve these problems is the ADuM4135 and the Microsemi
devices. SiC devices are wide band-gap devices that can operate APTMC120AM20CT1AG module. The ADuM4135 gate driver
at an increased voltage of >1000 V dc and tend to have a low is a single-channel device with a typical drive capability of 7 A
drain source impedance (RDSON). SiC devices also fill the need source and sink at a 25 V operating voltage (VDD to VSS). It has a
for reduced conduction and, therefore, increased efficiency. SiC minimum CMTI of 100 kV/μs. The APTMC120AM20CT1AG
devices can also exhibit fast switching speeds of >100 kHz with power module is a half bridge SiC device with a 1200 V
low parasitic capacitance and associated charge during collector emitter voltage rating, RDSON of 17 mΩΩ, and a
switching. However, disadvantages include a requirement for continuous current capability of 108 A. Its gate source voltage
higher common-mode transient immunity (CMTI) greater than (VGS) rating is −10 V to +25 V.
100 kV/μs required for gate drivers. Another disadvantage is
that higher switching across the drain source of the SiC can lead

16468-001

Figure 1. ADuM4135 Gate Drive Module

Rev. 0 | Page 1 of 11
AN-1536 Application Note

TABLE OF CONTENTS
Introduction ...................................................................................... 1  Load Testing ...................................................................................6 
Revision History ............................................................................... 2  High Current Testing ....................................................................8 
Test Setup ........................................................................................... 3  PWM Delay ....................................................................................9 
Electrical Setup ............................................................................. 3  Schematic ......................................................................................... 10 
Test Results ........................................................................................ 4  Conclusion....................................................................................... 11 
No Load Testing ............................................................................ 4 

REVISION HISTORY
4/2018—Revision 0: Initial Version

Rev. 0 | Page 2 of 11
Application Note AN-1536

TEST SETUP
ELECTRICAL SETUP
The system test circuit setup is shown in Figure 2. A dc voltage
is applied to the inputs across the full half bridge, where a
decoupling capacitor of 900 μF is added to the input stage. The
output stage is an inductor capacitor (LC) filter stage of 83 μH
and 128 μF, filtering the output into the load, R1, of 2 Ω to 30 Ω.
Table 1 shows a list of the test setup power components. A
physical setup is shown in Figure 3, and Table 2 details the
setup equipment used for testing.

16468-002
Figure 2. System Test Circuit Setup

Table 1. Test Setup Power Components

Equipment Value
U1 200 V to 900 V
C1 900 μF
L1 83 μH
C2 128 μF
R1 2 Ω to 30 Ω

Table 2. Setup Equipment Used for Testing

Equipment Manufacturer Type
Oscilloscope Keysight DSO-X 3024T
DC Supply Delta Elektronika SM 660-AR-11 (two in serial)
Gate Driver Board Watt&Well ADUM4135-WW-MS-01 SN001
Waveform Generator Agilent 33522A
Current Probe Hioki 3275
Passive Voltage Probe Keysight N2873A 500 MHz
Passive High Voltage Probe Elditest GE3421 100 MHz

HV+
L1

C2 R1
16468-003

HV+

Figure 3. Physical Setup

Rev. 0 | Page 3 of 11
AN-1536 Application Note

TEST RESULTS
NO LOAD TESTING
Table 3. No Load Testing—Figure Assignments
Test VHV (V)1 Switching Frequency, fSW (kHz) Duty Cycle (%) IIN (A)2 Figures
1 600 50 50 0.26 Figure 5 and Figure 4
2 600 100 50 0.22 Figure 7 and Figure 6
3 900 50 50 0.37 Figure 8 and Figure 9
1
VHV is the differential voltage between HV+ and HV−.
2
IIN is the input current through U1.
Table 4. No Load Testing—Temperature Summary
DC-to-DC DC-to-DC
Ambient Heatsink Power Supply Power Supply Gate Driver Gate Driver
fSW Temperature Temperature Temperature, Temperature, Temperature, Temperature,
Test VHV (V) (kHz) (°C) (°C) High-Side (°C) Low-Side (°C) High-Side (°C) Low-Side (°C)
4 600 50 20 21.3 25.4 25.4 34 33.5
5 600 100 20 23.5 31.5 31.5 42 42
6 900 50 20 23 29 29 37 37

In the latest revision of ADuM4135, some changes include: a

capacitor of 2.2 nF was added on the gates of the power metal-
oxide semiconductor field effect transistors (MOSFETs), Q1, LOW-SIDE VGS
and Q2. C0G decoupling capacitors of 15 nF have been added
to VHV. Table 3 and Table 4 summarize of the results observed, LOW-SIDE VDS

and Figure 4 through Figure 9 show the proof of results. Test 1

and Test 2 were carried out at 600 V, respectively, at 50 kHz and
100 kHz switching frequencies, whereas Test 3 was carried out
at 900 V at a switching frequency of 50 kHz. 2
Y1
Y2
3

16468-005
CH2 5.00V CH2 7.19V
CH3 200V

Figure 4. VHV = 600 V, fSW = 50 kHz, No Load, Turn On

LOW-SIDE VGS

LOW-SIDE VDS

Y1
2
Y2
3
16468-004

CH2 5.00V CH2 7.19V

CH3 200V

Figure 5. VHV = 600 V, fSW = 50 kHz, No Load, Turn Off

Rev. 0 | Page 4 of 11
Application Note AN-1536

LOW-SIDE VDS

LOW-SIDE VDS

Y1 Y1
2 2
Y2 Y2
LOW-SIDE VGS 3 LOW-SIDE VGS
3

16468-007

16468-008
CH2 5.00V CH2 7.19V CH2 5.00V CH2 7.19V
CH3 200V CH3 200V

Figure 6. VHV = 600 V, fSW = 100 kHz, No Load, Turn On Figure 8. VHV = 900 V, fSW = 50 kHz, No Load, Turn On

LOW-SIDE VDS
LOW-SIDE VGS LOW-SIDE VGS

LOW-SIDE VDS

Y1 Y1
2 2
Y2 Y2
3 3
16468-006

16468-009
CH2 5.00V CH2 7.19V CH2 5.00V CH2 7.19V
CH3 200V CH3 200V

Figure 7. VHV = 600 V, fSW = 100 kHz, No Load, Turn Off Figure 9. VHV = 900 V, fSW = 50 kHz, No Load, Turn Off

Rev. 0 | Page 5 of 11
AN-1536 Application Note
LOAD TESTING
Table 5. Load Testing
Test VHV (V) fSW (kHz) Duty Cycle (%) IOUT1 (A) VOUT2 (V) POUT3 (W) IIN4 (A) Figures
4 200 50 25 1.7 48 83 0.55 Figure 10 and Figure 11
5 600 50 25 6.9 145 1000 1.66 Figure 12 and Figure 13
6 900 50 25 8.7 215 1870.5 2.47 Figure 14 and Figure 15
7 900 100 25 8.2 200 1640 2.13 Figure 16 and Figure 17
1
IOUT is the output current in Load Resistor R1.
2
VOUT is the output voltage across R1.
3
POUT is the output power (IOUT × VOUT).
4
IIN is the input current through U1.

Board configuration is similar to the test setup of the No Load

Testing section.
Table 5 is a summary of the results observed for load testing,
and Figure 10 through Figure 17 show the proof of results.
LOW-SIDE VDS
Output voltage (VOUT) was measured as the voltage across R1.
The test results show some Miller feedback on VGS, but VGS
remains at the −5 V level at the gate of the SiC. At 900 V, some
ringing is seen on VDS, but it is <100 V of the input dc voltage.
This design shows how the ADuM4135 can drive SiC MOSFETs 2
LOW-SIDE VGS
with clean performance. 3

16468-012
CH2 5.00V A CH2 11.3V
CH3 200V

LOW-SIDE VDS Figure 12. VHV = 600 V, fSW = 50 kHz, POUT = 1000 W, Turn On

LOW-SIDE VGS

LOW-SIDE VDS
2
LOW-SIDE VGS
3
16468-010

CH2 5.00V A CH2 11.3V

CH3 50.0V 2

Figure 10. VHV = 200 V, fSW = 50 kHz, POUT = 83 W, Turn On 3 16468-013

CH2 5.00V A CH2 11.3V

CH3 200V
LOW-SIDE VGS
Figure 13. VHV = 600 V, fSW = 50 kHz, POUT = 1000 W, Turn Off

2
LOW-SIDE VDS
3
16468-011

CH2 5.00V A CH2 11.3V

CH3 50.0V

Figure 11. VHV = 200 V, fSW = 50 kHz, POUT = 83 W, Turn Off

Rev. 0 | Page 6 of 11
Application Note AN-1536

LOW-SIDE VDS
LOW-SIDE VDS

2 LOW-SIDE VGS
LOW-SIDE VGS 3
3

16468-014

16468-016
CH2 5.00V A CH2 11.3V CH2 5.00V A CH2 338mV
CH3 200V CH3 200V

Figure 14. VHV = 900 V, fSW = 50 kHz, POUT = 1870.5 W, Turn On Figure 16. VHV = 900 V, fSW = 100 kHz, POUT = 1640 W, Turn On

2
2
LOW-SIDE VGS
LOW-SIDE VDS
LOW-SIDE VDS LOW-SIDE VGS
3
3
16468-015

16468-017
CH2 5.00V A CH2 11.3V CH2 5.00V CH2 338mV
CH3 200V CH3 200V
Figure 15. VHV = 900 V, fSW = 50 kHz, POUT = 1870.5 W, Turn Off Figure 17. VHV = 900 V, fSW = 100 kHz, POUT = 1640 W, Turn Off

Rev. 0 | Page 7 of 11
AN-1536 Application Note
HIGH CURRENT TESTING
Table 6. High Current Testing
Test VHV (V) fSW (kHz) Duty Cycle (%)1 IOUT2 (A) VOUT3 (V) PIN4 (W) IIN5 (A) Figures
4 300 50 25 21.8 70.14 1526 5 Figure 18 and Figure 19
5 400 50 25 27.1 93.8 2640 6.6 Figure 21 and Figure 20
6 600 50 25 40.5 141 6000 10 Figure 23 and Figure 22
1
Duty cycle high side.
2
IOUT is the output current in Load Resistor R1.
3
VOUT is the output voltage across R1.
4
PIN is the input power (IIN × VHV)
5
IIN is the input current through U1.

Board configuration is similar to the test setup of the No Load

Testing section. A Regatron power supply was used in this test.
Table 6 is a summary of the results observed for high current
1
testing, and Figure 18 through Figure 23 show the proof of
results.
VOUT was measured as the voltage across R1.

2
LOW-SIDE VGS LOW-SIDE VDS
3

1
LOW-SIDE VDS

16468-021
CH1 20.0A CH2 5.00V A CH2 10.7V
CH3 100V

Figure 20. VHV = 400 V, fSW = 50 kHz, Output Current (IOUT) = 27.1 A, Turn On

2
3
LOW-SIDE VGS

1
16468-018

CH1 20.0A CH2 5.00V CH2 10.7V

CH3 100V

Figure 18. VHV = 300 V, fSW = 50 kHz, Output Current (IOUT) = 21.8 A, Turn On

3 LOW-SIDE VDS LOW-SIDE VGS

1
LOW-SIDE VDS
16468-020

CH1 20.0A CH2 5.00V A CH2 10.7V

CH3 100V

Figure 21. VHV = 400 V, fSW = 50 kHz, Output Current (IOUT) = 27.1 A, Turn Off

2
3
LOW-SIDE VGS
16468-019

CH1 20.0A CH2 5.00V A CH2 10.7V

CH3 100V

Figure 19. VHV = 300 V, fSW = 50 kHz, Output Current (IOUT) = 21.8 A, Turn Off

Rev. 0 | Page 8 of 11
Application Note AN-1536
PWM DELAY
The ADuM4135 input and output PWM measures the delay
between the two signals. The measures have been made directly
LOW-SIDE VDS
on the input and output pins of the ADuM4135. The delay is to
1 59.4 ns.

LOW-SIDE VGS

2
LOW-SIDE VDS
LOW-SIDE VGS
1

16468-023
CH1 20.0A CH2 5.00V A CH2 10.7V
CH3 200V

Figure 22. VHV = 600 V, fSW = 50 kHz, Output Current (IOUT) = 40.5 A Pulse-
Width Modulation (PWM) Delay, Turn On
3

X1 X2

16468-025
CH1 20.0A CH2 1.00V A CH3 12.1V
CH3 5.00V
LOW-SIDE VDS
Figure 24. Delay Between Input and Output PWM, Turn On
1

LOW-SIDE VGS 1
16468-022

CH1 20.0A CH2 5.00V A CH2 10.7V

CH3 200V LOW-SIDE VDS

Figure 23. VHV = 600 V, fSW = 50 kHz, Output Current (IOUT) = 40.5 A, Turn Off 3 Y1
2 LOW-SIDE VGS

X1 X2 Y2

16468-024
CH1 20.0A CH2 5.00V A CH2 10.7V
CH3 200V

Figure 25. Delay Between Input and Output PWM, Turn Off

Rev. 0 | Page 9 of 11
 AN-1536

PRIMARY Phase
i i
SCHEMATIC
LV D2 U2 LT8609EMSE#PBF + 25V-ISO-H-REC
9 1 C5
VIN BST X7R
10 C1
EN/UV 50 TP4 TP5
1N5819HW-7-F + 5V U1 X7R
100n L2 R4 50 R2
5 2 1 7 R3
J1 SYNC SW +5V Vin+ Vout+ 1u SOURCE-H
3 4u7 5000 1210 10k
1 INTVcc 100m 5000 +20V 0
6
1206 C2 DC/DC Com + 5V-ISO-H
2 R12 X7R -5V C4
7 8 R5 50 2 5 X7R
C8 C9 TR/SS PG C10 C40 C11 1k Vin- Vout- C6
470k 10u 50 X7R
X7R X7R C12 C0G (NP0) X7R CTC3B
PM5.08/2/90 BLK 4 6 1210 1u 50
50 50 X7R RT FB 50 22u 22u R05P22005D
1210

GND
10u 16 16 10u
1u 50 10p LED1 1210
1210 1210 R7 R8
10n SML-010LTT86

11
18k 100k 1210
GND-ISO-H
GND
LV = 12V ± 2V U3
GND
+5V LT3999HMSE
P1/P2 : 5 turns AWG 26
S1 : 25 turns AWG 26 + 25V-ISO-H-REC + 25V-ISO-H

3
L4 L1 R1
R6
10k 100u
D1 D3 1 R9
4 2 D16

V in
UVLO VS-30BQ100TRPBF VS-30BQ100TRPBF 1206 SOURCE-H
8 1 3 BZX84C27LT1G U4
SYNC SWA C7 C13 C14 0
R10 5 8 1
OVLO/DC P1 X7R IN OUT + 5V-ISO-H
10k S1 1210
NC X7R
1 4 50 50 5
HTSW-106-14-G-D + 5V 100n SCHDN +5V C16
6 1k
J3A RDC 10u
PWM_L READY_HS 7 S2 1210 1206
1 7 RT P2 GND X7R
J3G 9 10 5 50
J3B R50 ILIM/SS SWB D17 D18
FAULT_HS 2 6

3
GND 2 8 UVLO = 2.5V RBIAS VS-30BQ100TRPBF VS-30BQ100TRPBF 10u
J3H + 5V 1210

GN D
J3C C410 OVLO = disable C18 0
PWM_H RESET_HS R43 R44 R48 R49 R52
3 9 0603 fsw = 159kHz C17 LT1121CS8-5#PBF
X7R
J3I NC 10 NC 100k NC 47k B65808N1006D001 GND-ISO-H
J3D READY_LS tss = 8us X7R 50

11
50 10u 1:5 transformer
+ 5V 4 10 Ilim = disable
100n 1210 add kapton tape under the core
R64 J3J GND R51
NTC1 J3E FAULT_LS
5 11
C62 J3K GND GND GND GND GND GND GND GND
0 C42 0
0603 0603
R65 NC J3F RESET_LS + 25V-ISO-L-REC
NTC2 NC
6 12
0 J3L
GND C50
+ 5V U5 X7R
1 R53
7 50 R54
Vin+ Vout+ 1u SOURCE-L
10k
C51 +20V 1210 0
X7R 6
V2 V4 V5 V7 DC/DC Com + 5V-ISO-L
50 C53
2 -5V C52
10u 5 X7R
M3_SS M3_SS M3_SS M3_SS Vin- Vout- X7R
1210 50
50
M3_SS M3_SS M3_SS M3_SS R05P22005D 1u 10u
1210 1210

U14
GND-ISO-L
TP10 LT3999HMSE GND
GND
5001 + 5V
P1/P2 : 5 turns AWG 26
TP13 + 25V-ISO-L-REC + 25V-ISO-L

3
S1 : 25 turns AWG 26 L3 R55
GND R56 L5
5001
10k 100u
D19 D20 1 R57
4 2 D21

V in
UVLO VS-30BQ100TRPBF VS-30BQ100TRPBF C55 C56 SOURCE-L
8 1 3 C54 BZX84C27LT1G U15
SYNC SWA X7R X7R 0
R58 5 1210 8 1
OVLO/DC P1 50 50 IN OUT + 5V-ISO-L
10k S1 NC 10u 100n
1 C57
4 1210 1206 5 1k
+5V SCHDN +5V X7R
6 1206
RDC 50
7 S2 GND 10u
RT P2
9 10 5 1210
ILIM/SS SWB D22 D23
2 6
UVLO = 2.5V RBIAS VS-30BQ100TRPBF VS-30BQ100TRPBF 3
C58

GND
OVLO = disable 0
R59 R60 R61 X7R R62 R63 + 5V HV_RTN
fsw = 159kHz LT1121CS8-5#PBF
10 NC 100k 50 NC 47k C59 B65808N1006D001 i GND-ISO-L
tss = 8us

11
100n X7R 1:5 transformer
Ilim = disable 10u add kapton tape under the core
50
1210 Phase
GND GND GND GND GND GND GND
GND i
Stud M6

Rev. 0 | Page 10 of 11
+ 25V-ISO-H J4
HV
+ 25V-ISO-H
C20
X7R +25V-ISO-H
C19
C43 X7R 50
R40 R11
50 100n D9
+ 5V GND 4k7 D8
10u D4 D14
NC VS-10BQ100TRPBF 1206 R42
+ 5V + 5V + 5V X7R 1210
50 D10 100
+ 5V 100n R17 STTH112U
VS-10BQ100TRPBF C21 2010
+ 5V R13 U6 + 5V R14 R15 10k BZX84C6V2LT1G STTH112U
GND-ISO-H C0G (NP0)

5
U8 NC Vcc M74VHC1G132DFT1G U9 10k 10k U7

5
5
TP14 100
P1 Vcc MC74VHC1G14DFT1G 2 Vcc MC74VHC1G14DFT1G 1 16
R18 VSS1 VSS2 GND-ISO-H 220p
PWM_H 2 4 4 2 4 2 15
Vi+ GATE_SENSE
5000 100 1 3 14 GND-ISO-H
Vi- VOUT_ON
Gnd Gnd READY_HS 4 13 R16

3
3
READY VDD2 + 25V-ISO-H

3
R124426123 R20 C22 D5 R21 Gnd FAULT_HS 5 12 10
R22 FAULT VOUT_OFF
FDLL333 Q1

Figure 26. ADuM4135 Gate Drive Board Schematic

10k C0G (NP0) 5k6 RESET_HS 6 11 R19
RESET GND2 + 5V-ISO-H 1206
GND 50 GND GND 7 10 10 D1 NTC1 NTC1
0 + 5V VDD1 DESAT
CLASS NAME: HV/2
CLASS NAME: HV/2
CLASS NAME: HV/2

100p GND R23 C23 8 9 R24

VSS1 VSS2 GND-ISO-H 1206 TP15 C3 C15 C48
C24 C25 NC C0G (NP0) 4R7 Q1 NTC2
C26 C44 4R7 C0G (NP0) C0G (NP0) C0G (NP0)
GND 50 R25 G1 NTC2
50 + 5V GND + 5V GND ADUM4135BRWZ 1206 CR1 10n 10n 10n
C27 1n +5V-ISO-H GND-ISO-H 4R7
C0G (NP0) 4R7 5000 TP1 C60 C29 1812 1812 1812
C28
X7R X7R X7R R26
+ 5V GND 47p X7R 5000 MP J5 MKP MKP 630 630 630
50 50 GND GND GND 2n2 10k E1 D2S1
50 220n 220n HV/2 i HV/2 i HV/2 i
100n 100n 100
X7R 100n 1500
SOURCE-H 1500
50 GND Q2 Stud M6
G2 C30 C47 C49
100n + 25V-ISO-L R32
CR2 C0G (NP0) C0G (NP0) C0G (NP0)
C45 10 C61
R45 TP2 10n 10n 10n
C32 R31 5000 X7R R27
+ 5V GND C31 1206 TP16 1812 1812 1812
X7R 10 2n2 10k E2
NC X7R 5000 630 630 630
+ 5V + 5V + 5V X7R 50 50 100
100n R38 SOURCE-L
50 10u 1206
+5V 4R7 S2
100n 1210 4R7
+ 5V U12 R28 U10 + 5V R29 R30 R34
U11 1206 APTMC120AM20CT1AG

5
MC74VHC1G14DFT1G NC Vcc M74VHC1G132DFT1G U13 10k 10k 4R7

5
5
TP17 4R7
P2 Vcc 2 Vcc MC74VHC1G14DFT1G 1 16 +25V-ISO-L
R33 4 VSS1 VSS2 GND-ISO-L
PWM_L 2 4 2 4 2 15
Vi+ GATE_SENSE +25V-ISO-L
1 3 14
5000 100 Vi- VOUT_ON R35
GND GND READY_LS 4 13 R46

3
3
C33 READY VDD2 + 25V-ISO-L 4k7

3
R124426123 R36 R37 GND FAULT_LS 5 12 100 D7
C0G (NP0) D6 FAULT VOUT_OFF D12 1206 D11
10k 5k6 RESET_LS 6 11 STTH112U
50 FDLL333 RESET GND2 + 5V-ISO-L 2010
GND GND GND 7 10 VS-10BQ100TRPBF
100p R39 + 5V VDD1 DESAT
GND R41 C34 8 9
0 C39
C0G (NP0) VSS1 VSS2 GND-ISO-L D13
C35 C38 C36 C37 NC R47 C0G (NP0)
50 VS-10BQ100TRPBF D15
GND 10k 100 BZX84C6V2LT1G
+ 5V GND C0G (NP0) + 5V GND + 5V GND 1n ADUM4135BRWZ STTH112U
C46
47p 220p
X7R X7R X7R + 5V-ISO-L GND-ISO-L GND-ISO-L
190.5ns deadtime 50
50 50 50 GND GND GND
X7R
100n 100n 100n
50 GND-ISO-L HV_RTN
GND HV_RTN
100n J6
F2 F4 i Stud M6
M1 M2 M3 M4

6278230121 6278230121
16468-026

F1 F3

6278230121 6278230121
Application Note
Application Note AN-1536

CONCLUSION
The ADuM4135 gate driver has the current drive capability, the The test results provide data showing a solution is available for
correct power supply range, and a strong CMTI capability of isolated power supply, high voltage gate drivers driving SiC.
>100 kV/μs to deliver clean performance when driving SiC
MOSFETs.

©2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
AN16468-0-4/18(0)

Rev. 0 | Page 11 of 11