U1 L6 Application of Compiler Technology Notes Part 1
U1 L6 Application of Compiler Technology Notes Part 1
Parallelism –
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1. All modern microprocessors support instruction level parallelism and it is hidden from
the programmer. The programmers has written the program and assumes the
execution of the program sequentially but the dynamically hardware checks the
different types of dependencies in sequential instructions and when possible execute it
in parallel.
2. In some cases, machine includes a hardware scheduler to change the instruction
ordering to increase the parallelism in the program and in such cases, if hardware does
not re-order the instructions; the compiler can rearrange the instructions to make
instruction level parallelism more effective.
3. Instruction level parallelism can also appear explicitly in the instruction set. Very Long
Instruction Word ( VLLW ) machines can operate multiple instruction at a time.
Example – IA64.
All high performance, general purpose microprocessors include instructions that can
operate on a vector at the same time.
So compiler techniques have been developed to generate code automatically for such
machines from the sequential program.
Memory Hierarchies
1. Memory Hierarchies consist of several levels of storage with different speeds and sizes
and memory which is closest to the processor (cache memory) being fastest which is in
very size (and costly). The average memory – access time of a program is reduced if
most of the date suppose accessed by the faster levels of hierarchies. Both parallelism
and Memory Hierarchies improve the performance of the machine but it should be
harnessed effectively by the compiler to deliver the real performance.
2. To improve the performance of the machine it is necessary to make effective
utilization of the registers , need to manage the softwares explicitly.
3. Cache and physical memories hidden from the instruction set and managed by the
hardware and it has been found that cache-management policies implemented by the
hardware and are not effective in some of the cases which involves scientific code that
has large data structures (typically arrays).
However, it is possible to improve the effectiveness of the memory hierarchy either by
changing the layout of the data or changing the order of accessing the data by the
instructions.
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