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U1 L6 Application of Compiler Technology Notes Part 1

This document discusses the applications of compiler technology. It begins by explaining how compilers implement high-level programming languages by optimizing code to improve performance. Techniques used include aggregate data types, control flows, data flow optimization, and object-oriented features. The document also discusses how compilers optimize code for computer architectures using parallelism at the instruction and processor level, as well as optimizing for memory hierarchies through cache management and data layout/access ordering.

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0% found this document useful (0 votes)
144 views4 pages

U1 L6 Application of Compiler Technology Notes Part 1

This document discusses the applications of compiler technology. It begins by explaining how compilers implement high-level programming languages by optimizing code to improve performance. Techniques used include aggregate data types, control flows, data flow optimization, and object-oriented features. The document also discusses how compilers optimize code for computer architectures using parallelism at the instruction and processor level, as well as optimizing for memory hierarchies through cache management and data layout/access ordering.

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preetam
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Department of Computer Science and Engineering


School of Technology

Class - T. Y. B. Course - Compiler Design (CST305R1)


Tech
Unit No – 1 Introduction To Compiler
[ U1 – L5 ] 1.The compiler construction tools and its uses

2.Revision on Language Design Tools


3. Applications of Compiler Technology
1. Introduction is given to the learners about
Contents to be different compiler construction tools are used in
covered
industry for implementing the work of the
different phases of the compiler.
2. Revision on language design tools with respective
of working of the compiler
3. Importance of compiler technology and
applications of it.
Author : Ms. Sujata A Pardeshi
Applications of Compiler Technology
1. Implementation of High – Level Programming Languages
A HLL programming languages defines programme abstraction while writing the
programs which are less efficient as it takes more time to convert the code into low level
language. Writing the programme in low level language is highly efficient but its very
difficult to write down code. So once code is written in HLL, it is required for optimizing
compilers to include the techniques to improve the performance of the generated target
code. Following are the techniques used by the different HLL:
1) Use of User defined aggregate data types such as arrays and structure in C, C++ and
COBOL programming languages.
2) High level control flow such as loops and invocations of procedures.
3) Use of Data flow optimization compiler optimization techniques to analyze the flow
of data through the program and remove the redundancies across these constructs.
4) Use of Data Abstraction techniques, Inheritance of properties in different
languages such as C++, C#, and Java to make program more modular and easier to
maintain.
5) Use of Type - Safe, Checking of bounds of arrays in Java.
6) Java uses the Built in Garbage collection which automatically frees memory of
variables which are not in use. So efficient algorithms have been written to
minimize the overhead of the garbage collection.
7) OOP program contain many more but small procedures called as methods for
which compiler optimization must perform procedure inlining.
So, compiler optimization techniques have been developed to reduce such overheads by
eliminating unnecessary range checks, by allocating objects which are not accessible
beyond a procedure on the stack instead of heap.

2. Optimization for Computer Architectures


Rapid evolution of computer architectures demand for new compiler technologies and
almost all high-performance systems takes advantage of the two basic techniques: 1)
Parallelism that found at the instructional level where multiple instructions can be
executed simultaneously and at the processor level, where different threads if the same
application are run on the different processors.
2) Memory Hierarchies through which it may possible to build very large storage.

Parallelism –

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1. All modern microprocessors support instruction level parallelism and it is hidden from
the programmer. The programmers has written the program and assumes the
execution of the program sequentially but the dynamically hardware checks the
different types of dependencies in sequential instructions and when possible execute it
in parallel.
2. In some cases, machine includes a hardware scheduler to change the instruction
ordering to increase the parallelism in the program and in such cases, if hardware does
not re-order the instructions; the compiler can rearrange the instructions to make
instruction level parallelism more effective.
3. Instruction level parallelism can also appear explicitly in the instruction set. Very Long
Instruction Word ( VLLW ) machines can operate multiple instruction at a time.
Example – IA64.
All high performance, general purpose microprocessors include instructions that can
operate on a vector at the same time.
So compiler techniques have been developed to generate code automatically for such
machines from the sequential program.

Memory Hierarchies
1. Memory Hierarchies consist of several levels of storage with different speeds and sizes
and memory which is closest to the processor (cache memory) being fastest which is in
very size (and costly). The average memory – access time of a program is reduced if
most of the date suppose accessed by the faster levels of hierarchies. Both parallelism
and Memory Hierarchies improve the performance of the machine but it should be
harnessed effectively by the compiler to deliver the real performance.
2. To improve the performance of the machine it is necessary to make effective
utilization of the registers , need to manage the softwares explicitly.
3. Cache and physical memories hidden from the instruction set and managed by the
hardware and it has been found that cache-management policies implemented by the
hardware and are not effective in some of the cases which involves scientific code that
has large data structures (typically arrays).
However, it is possible to improve the effectiveness of the memory hierarchy either by
changing the layout of the data or changing the order of accessing the data by the
instructions.

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