OPA2180

OPA4180
www.ti.com SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011

0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift

OPERATIONAL AMPLIFIERS
Check for Samples: OPA2180, OPA4180

1FEATURES APPLICATIONS
•
2 Low Offset Voltage: 75 μV (max) • Bridge Amplifiers
• Zero-Drift: 0.1 μV/°C • Strain Gauges
• Low Noise: 10 nV/√Hz • Test Equipment
• Very Low 1/f Noise • Transducer Applications
• Excellent DC Precision: • Temperature Measurement
– PSRR: 126 dB • Electronic Scales
– CMRR: 114 dB • Medical Instrumentation
– Open-Loop Gain (AOL): 120 dB • Resister Thermal Detectors
• Quiescent Current: 525 μA (max) • Precision Active Filters
• Wide Supply Range: ±2 V to ±18 V
• Rail-to-Rail Output: DESCRIPTION
Input Includes Negative Rail The OPA2180 and OPA4180 operational amplifiers
use zero-drift techniques to simultaneously provide
• Low Bias Current: 250 pA (typ) low offset voltage (75 μV), and near zero-drift over
• RFI Filtered Inputs time and temperature. These miniature,
• MicroSIZE Packages high-precision, low quiescent current amplifiers offer
high input impedance and rail-to-rail output swing
within 18 mV of the rails. The input common-mode
range includes the negative rail. Either single or dual
supplies can be used in the range of +4.0 V to +36 V
(±2 V to ±18 V).
50 nV/div

The dual version is offered in MSOP-8 and SO-8

packages. The quad is offered in SO-14 and
TSSOP-14 packages. All versions are specified for
operation from –40°C to +105°C.
Peak-to-Peak Noise = 250 nV

Time (1 s/div)

Zero-Drift Amplifier Portfolio

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT BANDWIDTH
VERSION PRODUCT (µV) (µV/°C) (MHz)
Single (1) OPA188 (4 V to 36 V) 25 0.085 2
OPA333 (5 V) 10 0.05 0.35
Single OPA378 (5 V) 50 0.25 0.9
OPA735 (12 V) 5 0.05 1.6
OPA2188 (4 V to 36 V) 25 0.085 2
OPA2180 (4 V to 36 V) 75 0.35 2
Dual OPA2333 (5 V) 10 0.05 0.35
OPA2378 (5 V) 50 0.25 0.9
OPA2735 (12 V) 5 0.05 1.6
OPA4188 (4 V to 36 V) 25 0.085 2
Quad (1)
OPA4180 (4 V to 36 V) 75 0.35 2
Quad OPA4330 (5 V) 50 0.25 0.35

(1) Shaded rows denote future product releases.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains Copyright © 2011, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA2180
OPA4180
SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE INFORMATION (1)

SPECIFIED
PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY
DUAL
OPA2180ID Rails, 100
OPA2180 SO-8 D –40°C to +105°C 2180
OPA2180IDR Tape and Reel, 2500
OPA2180IDGKT Tape and Reel, 250
OPA2180 (2) MSOP-8 DGK –40°C to +105°C TBD
OPA2180IDGKR Tape and Reel, 2500
QUAD
OPA4180ID Rails, 90
SO-14 D –40°C to +105°C OPA4180
OPA4180IDR Tape and Reel, 2000
OPA4180 (2)
OPA4180IPW Rails, 90
TSSOP-14 PW –40°C to +105°C OPA4180
OPA4180IPWR Tape and Reel, 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Shaded rows denote future product releases.

ABSOLUTE MAXIMUM RATINGS (1)

OPA2180, OPA4180 UNIT
Supply voltage ±20, 40 (single supply) V
Voltage (V–) – 0.5 to (V+) + 0.5 V
Signal input terminals
Current ±10 mA
Output short-circuit (2) Continuous
Operating temperature –55 to +125 °C
Storage temperature –65 to +150 °C
Junction temperature +150 °C
Human body model (HBM) 1.5 kV
ESD ratings
Charged device model (CDM) 1 kV

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.

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ELECTRICAL CHARACTERISTICS: VS = ±2 V to ±18 V (VS = +4 V to +36 V)

At TA = +25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
OPA2180, OPA4180
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 15 75 μV
dVOS/dT Input offset voltage drift TA = –40°C to +105°C 0.1 0.35 μV/°C
VS = 4 V to 36 V, VCM = VS/2 0.1 0.5 μV/V
PSRR Power-supply rejection ratio TA = –40°C to +105°C,
0.5 μV/V
VS = 4 V to 36 V, VCM = VS/2
See
Long-term stability μV
note (1)
Channel separation, dc 1 μV/V
INPUT BIAS CURRENT
VCM = VS/2 ±0.25 ±1 nA
IB Input bias current
TA = –40°C to +105°C ±5 nA
±0.5 ±2 nA
IOS Input offset current
TA = –40°C to +105°C ±2.5 nA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 0.25 μVPP
en Input voltage noise density f = 1 kHz 10 nV/Hz
in Input current noise density f = 1 kHz 10 fA/Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range V– (V+) – 1.5 V
(V–) < VCM < (V+) – 1.5 V 104 114 dB
CMRR Common-mode rejection ratio TA = –40°C to +105°C,
100 104 dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V
INPUT IMPEDANCE
Differential 100/6 MΩ/pF
Common-mode 6/9.5 1012 Ω/pF
OPEN-LOOP GAIN
(V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ 110 120 dB
AOL Open-loop voltage gain TA = –40°C to +105°C,
104 114 dB
(V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ
FREQUENCY RESPONSE
GBW Gain-bandwidth product 2 MHz
SR Slew rate G = +1 0.8 V/μs
0.1% VS = ±18 V, G = 1, 10-V step 22 μs
Settling time
0.01% VS = ±18 V, G = 1, 10-V step 30 μs
Overload recovery time VIN × G = VS 1 μs
THD+N Total harmonic distortion + noise f = 1 kHz, G = 1, VOUT = 1 VRMS 0.0001 %

(1) 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV.

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ELECTRICAL CHARACTERISTICS: VS = ±2 V to ±18 V (VS = +4 V to +36 V) (continued)

At TA = +25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
OPA2180, OPA4180
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT
No load 8 18 mV
Voltage output swing from rail RL = 10 kΩ 250 300 mV
TA = –40°C to +105°C, RL = 10 kΩ 325 360 mV
ISC Short-circuit current ±18 mA
RO Open-loop output resistance f = 2 MHz, IO = 0 mA 120 Ω
CLOAD Capacitive load drive 1 nF
POWER SUPPLY
VS Operating voltage range ±2 (or 4) ±18 (or 36) V
450 525 μA
IQ Quiescent current (per amplifier)
TA = –40°C to +105°C, IO = 0 mA 600 μA
TEMPERATURE
Specified range –40 +105 °C
Operating range –40 +125 °C
Storage range –65 +150 °C

THERMAL INFORMATION: OPA2180

OPA2180
(1)
THERMAL METRIC D (SO) DGK (MSOP) UNITS
8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 111.0 159.3
θJCtop Junction-to-case (top) thermal resistance 54.9 37.4
θJB Junction-to-board thermal resistance 51.7 48.5
°C/W
ψJT Junction-to-top characterization parameter 9.3 1.2
ψJB Junction-to-board characterization parameter 51.1 77.1
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

THERMAL INFORMATION: OPA4180

OPA4180
THERMAL METRIC (1) D (SO) PW (TSSOP) UNITS
14 PINS 14 PINS
θJA Junction-to-ambient thermal resistance TBD TBD
θJCtop Junction-to-case (top) thermal resistance TBD TBD
θJB Junction-to-board thermal resistance TBD TBD
°C/W
ψJT Junction-to-top characterization parameter TBD TBD
ψJB Junction-to-board characterization parameter TBD TBD
θJCbot Junction-to-case (bottom) thermal resistance TBD TBD

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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PIN CONFIGURATIONS

OPA2180
D, DGK PACKAGES (SO-8, MSOP-8) OPA4180
(TOP VIEW) D, PW PACKAGES (SO-14, TSSOP-14)
(TOP VIEW)

OUT A 1 8 V+
OUT A 1 14 OUT D
A
-IN A 2 7 OUT B
-IN A 2 A D 13 -IN D
+IN A 3 B 6 -IN B
+IN A 3 12 +IN D
V- 4 5 +IN B
V+ 4 11 V-

+IN B 5 10 +IN C
B C
-IN B 6 9 -IN C

OUT B 7 8 OUT C

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OPA4180
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TYPICAL CHARACTERISTICS

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE
IB and IOS vs Common-Mode Voltage Figure 1
Input Bias Current vs Temperature Figure 2
Output Voltage Swing vs Output Current (Maximum Supply) Figure 3
CMRR vs Temperature Figure 4
0.1-Hz to 10-Hz Noise Figure 5
Input Voltage Noise Spectral Density vs Frequency Figure 6
Open-Loop Gain and Phase vs Frequency Figure 7
Open-Loop Gain vs Temperature Figure 8
Open-Loop Output Impedance vs Frequency Figure 9
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 10, Figure 11
No Phase Reversal Figure 12
Positive Overload Recovery Figure 13
Negative Overload Recovery Figure 14
Small-Signal Step Response (100 mV) Figure 15, Figure 16
Large-Signal Step Response Figure 17, Figure 18
Large-Signal Settling Time (10-V Positive Step) Figure 19
Large-Signal Settling Time (10-V Negative Step) Figure 20
Short-Circuit Current vs Temperature Figure 21
Maximum Output Voltage vs Frequency Figure 22
Channel Separation vs Frequency Figure 23
EMIRR IN+ vs Frequency Figure 24

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TYPICAL CHARACTERISTICS
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
IB AND IOS vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE
500 4000
+IB IB+
400 -IB IB-
3000
IOS

Input Bias Current (pA)

300 IOS
2000
IB and IOS (pA)

200

100 1000

0
0
-100
-1000
-200

-300 -2000
-20 -15 -10 -5 0 5 10 15 20 -55 -35 -15 5 25 45 65 85 105 125
VCM (V) Temperature (°C)
Figure 1. Figure 2.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

(Maximum Supply) CMRR vs TEMPERATURE
20 40
-40°C Common-Mode Rejection Ratio (mV/V) (V-) < VCM < (V+) - 1.5 V
19
18 +85°C 35 (V-) + 0.5 V < VCM < (V+) - 1.5 V
17 +125°C
30
Output Voltage (V)

16 VSUPPLY = ±2 V
15 25
14
20
-14
-15 15
-16
-17 10
-18
5
-19
-20 0
0 2 4 6 8 10 12 14 16 18 20 22 24 -55 -35 -15 5 25 45 65 85 105 125
Output Current (mA) Temperature (°C)
Figure 3. Figure 4.

INPUT VOLTAGE NOISE SPECTRAL DENSITY vs

0.1-Hz TO 10-Hz NOISE FREQUENCY
100
Voltage Noise Density (nV/ÖHz)
50 nV/div

10

Peak-to-Peak Noise = 250 nV

1
Time (1 s/div) 0.1 1 10 100 1k 10k 100k
Frequency (Hz)
Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPEN-LOOP GAIN vs TEMPERATURE
140 180 3
Gain VSUPPLY = 4 V, RL = 10 kW
120 Phase
2.5 VSUPPLY = 36 V, RL = 10 kW
100 135

80 2
Gain (dB)

Phase (°)

AOL (mV/V)
60 90
1.5
40
1
20 45

0 0.5
−20 0
10 100 1k 10k 100k 1M 10M 100M 0
Frequency (Hz) G007 -55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
Figure 7. Figure 8.

SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD

OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY (100-mV Output Step)
10k 40
RL = 10 kW
35
1k ROUT = 0 W
30
ROUT = 25 W
Overshoot (%)

100 25 ROUT = 50 W
ZO (W)

20
10 15
+18 V
G = +1
ROUT
10 Device

1 -18 V
RL CL

1m 0
1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz) Capacitive Load (pF)
Figure 9. Figure 10.

SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD

(100-mV Output Step) NO PHASE REVERSAL
40
ROUT = 0 W +18 V

35
ROUT = 25 W Device

30 ROUT = 50 W
-18 V
Overshoot (%)

37 VPP
25 Sine Wave
5 V/div

(±18.5 V)

20

15
RI = 10 kW RF = 10 kW G = -1
10 +18 V
ROUT VIN
Device
5 CL
VOUT
RL = 10 kW -18 V

0
0 100 200 300 400 500 600 700 800 900 1000 Time (100 ms/div)
Capacitive Load (pF)
Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY

VOUT VIN

20 kW
20 kW
2 kW +18 V

2 kW +18 V
5 V/div

5 V/div
Device VOUT
VIN Device VOUT
-18 V VIN
-18 V
G = -10 G = -10

VOUT
VIN

Time (5 ms/div) Time (5 ms/div)

Figure 13. Figure 14.

SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE

(100 mV) (100 mV)
RL = 10 kW RL = 10 kW
CL = 10 pF CL = 10 pF
20 mV/div

20 mV/div

RI = 2 kW RF = 2 kW
+18 V
G = +1
+18 V

Device
Device

-18 V RL CL CL
-18 V
G = -1

Time (1 ms/div) Time (20 ms/div)

Figure 15. Figure 16.

LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE

G = +1 G = -1
RL = 10 kW
RL = 10 kW
CL = 10 pF
CL = 10 pF
5 V/div

5 V/div

Time (50 ms/div) Time (50 ms/div)

Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
LARGE-SIGNAL SETTLING TIME LARGE-SIGNAL SETTLING TIME
(10-V Positive Step) (10-V Negative Step)
10 10
G = -1 G = -1
8 8
6 6
D From Final Value (mV)

D From Final Value (mV)

4 4
12-Bit Settling 12-Bit Settling
2 2
0 0
-2 -2
(±1/2 LSB = ±0.024%) (±1/2 LSB = ±0.024%)
-4 -4
-6 -6
-8 -8
-10 -10
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Time (ms) Time (ms)
Figure 19. Figure 20.

SHORT-CIRCUIT CURRENT vs TEMPERATURE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

30 15
VS = ±15 V
20 12.5
Output Voltage (VPP)

10 10 Maximum output voltage without

slew-rate induced distortion.
ISC (mA)

ISC, Source
0 ISC, Sink 7.5
VS = ±5 V
-10 5

-20 2.5 VS = ±2.25 V

-30 0
-55 -35 -15 5 25 45 65 85 105 125 1k 10k 100k 1M 10M
Temperature (°C) Frequency (Hz)
Figure 21. Figure 22.

CHANNEL SEPARATION vs FREQUENCY EMIRR IN+ vs FREQUENCY

-60 160
Channel A to B
-70 Channel B to A 140
Channel Separation (dB)

-80 120
EMIRR IN+ (dB)

-90
100
-100
80
-110
60
-120
40
-130

-140 20

-150 0
1 10 100 1k 10k 100k 1M 10M 100M 10M 100M 1G 10G
Frequency (Hz) Frequency (Hz)
Figure 23. Figure 24.

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APPLICATION INFORMATION

The OPAx180 family of operational amplifiers combine precision offset and drift with excellent overall
performance, making them ideal for many precision applications. The precision offset drift of only 0.085 µV/°C
provides stability over the entire temperature range. In addition, the device offers excellent overall performance
with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.

OPERATING CHARACTERISTICS
The OPAx180 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the
specifications apply from –40°C to +105°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.

EMI REJECTION
The OPAx180 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx180
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 25 shows the results of this testing on the OPAx180. Detailed information can also be found in the
Application Report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from the TI
website.
160

140

120
EMIRR IN+ (dB)

100

80

60

40

20

0
10M 100M 1G 10G
Frequency (Hz)

Figure 25. OPAx180 EMIRR Testing

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GENERAL LAYOUT GUIDELINES

For best operational performance of the device, good printed circuit board (PCB) layout practices are
recommended. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to
single-supply applications.

PHASE-REVERSAL PROTECTION
The OPAx180 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPAx180 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26.

+18 V

Device

-18 V
37 VPP
Sine Wave
5 V/div

(±18.5 V)

VIN
VOUT

Time (100 ms/div)

Figure 26. No Phase Reversal

CAPACITIVE LOAD AND STABILITY

The dynamic characteristics of the OPAx180 have been optimized for a range of common operating conditions.
The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier
and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the
output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in
series with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load
for several values of ROUT. Also, refer to the Applications Report, Feedback Plots Define Op Amp AC
Performance (SBOA015), available for download from the TI website, for details of analysis techniques and
application circuits.
40 40
RL = 10 kW ROUT = 0 W
35 35
ROUT = 25 W
ROUT = 0 W
30 30 ROUT = 50 W
ROUT = 25 W
Overshoot (%)

Overshoot (%)

25 ROUT = 50 W 25

20 20

15 G = +1 15
+18 V
ROUT
RI = 10 kW RF = 10 kW G = -1
10 Device 10 +18 V
ROUT
RL CL
-18 V Device
5 5 CL

RL = 10 kW -18 V

0 0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF) Capacitive Load (pF)

Figure 27. Small-Signal Overshoot versus Figure 28. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step) Capacitive Load (100-mV Output Step)

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ELECTRICAL OVERSTRESS
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings. Figure 29 shows how a series input resistor may be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
its value should be kept to a minimum in noise-sensitive applications.

V+

IOVERLOAD
10 mA max
Device VOUT
VIN
5 kW

Figure 29. Input Current Protection

An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration,
high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk
that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal
operation.
However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): OPA2180 OPA4180
OPA2180
OPA4180
SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com

APPLICATION EXAMPLES
The application examples of Figure 30 and Figure 31 highlight only a few of the circuits where the OPAx180
family of devices can be used.
15 V

U2
½
OPA2180 VOUTP

3.3 V
VDIFF/2 R5
-15 V 1 kW
Ref 1
Ref 2
RG R7 U1 VOUT
+ 500 W 1 kW INA159
VCM
10 Sense

-VDIFF/2 -15 V

U5
½
OPA2180 VOUTN

15 V

Figure 30. Discrete INA + Attenuation for ADC with 3.3-V Supply

+15 V

(5 V) Out In
REF5050
1 mF 1 mF
R2
49.1 kW R3
60.4 kW

R1
4.99 kW
VOUT 0°C = 0 V
OPA2180
200°C = 5 V

R5
(1)
RTD 105.8 kW
Pt100

R4
1 kW

(1) R5 provides positive-varying excitation to linearize output.

Figure 31. RTD Amplifier with Linearization

14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

Product Folder Link(s): OPA2180 OPA4180

 OPA2180
OPA4180
www.ti.com SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2011) to Revision B Page

• Changed footnote 1 of Electrical Characteristics table ......................................................................................................... 3

• Updated Figure 7 .................................................................................................................................................................. 8

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): OPA2180 OPA4180
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2012

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
OPA2180ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR
& no Sb/Br)
OPA2180IDGK PREVIEW VSSOP DGK 8 80 TBD Call TI Call TI
OPA2180IDGKR PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI
OPA2180IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR
& no Sb/Br)
OPA4180ID PREVIEW SOIC D 14 50 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR
& no Sb/Br)
OPA4180IDR PREVIEW SOIC D 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR
& no Sb/Br)
OPA4180IPW PREVIEW TSSOP PW 14 90 Green (RoHS Call TI Level-2-260C-1 YEAR
& no Sb/Br)
OPA4180IPWR PREVIEW TSSOP PW 14 2000 Green (RoHS Call TI Level-2-260C-1 YEAR
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2012

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2180IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2180IDR SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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