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Magic MasalaQuestion Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmabl Programmable
Intelligent Interface e Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC
to ____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller Watchdog
are ______ Timers ADC All of these D
5 Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access
data RAM in PIC 18 microcontroller. 4 8 12 16 C
9
___ address lines are used to access
program ROM in PIC 18 microcontroller. 18 19 20 21 D
10
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller
is ___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller
is ___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is 128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle deep power A
20 sleep sleep
WDT stands for _______ Watch Watch Dog Width Delay d Delay
Watch
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
Synchronou Synchronou Synchronous C
25 Serial Port
S i l l P S i lP
Flag 'N' in Status register of PIC18F452 d Negative
Zero Flag Overflow Flag Carry Flag B
26 Flag
How many banks are available in PIC 18F
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result Results saved Ressult
ADDWF F D a Undefined D
saved in F in F and W Saaved in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
Reset Reset B
29 Reset Debug Detection
D t ti D t ti
Circuit used for initialization of all values t Power-On Brown Out Power ON/
Reset Detection WDT circuit A
30 OFF circuit
In Immediate (Literal) addressing mode Ci it Ci it
The operand is _____ that follows the a register a number a pointer an address B
31
d
PIC18F452 has power down modes as __ deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated
in____ oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in
OSCCONFI
PIC18F4550 is controlled through two CONFIG2 CONFIG1L
G1 and None of the
Configuration registers as _______ and and C
OSCCONFI above
CONFIG2 CONFIG1H
G2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
Synchrnous Synchrnous Synchrnous Asynchronous C
36
CONFIG2L is used for A h A ti A h R i
Frequency Background Watch dog
Reset voltage D
Selection debugger timer
37
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontrol Resets all the Set all registers B
for ler in registers
38
peripherals standby
Where is the result stored after an Working None of the
execution of increment and decrement File Register Both a & b C
39 Register above
Whichti status bits
thexhibit icarry
l from
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator
on OSC1 and OSC2 pins is divided by 1 2 3 4 D
_____ and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8
Timer 0 Timer 1 Timer 2 Timer 3 A
pre-scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of
TMR0ON T08BIT T0CS T0SE A
Timer0.
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by
Timer0 if FFF6 h is loaded into it. 5.6 μS 5.2 μS 4.6 μS 4 μS D
Assume crystal frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
frequency = 16 MHz and prescaler of 0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller
5 6 7 8 B
is ___ bits.
Size of Port E in PIC 18 microcontroller
3 4 5 6 A
is ___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
is a ON/OFF control bit of TMRxON Tx8BIT TxCS TxSE A
is a clock source selector bit of TMRxON Tx8BIT TxCS TxSE C
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is output input bidirectional None of B
Upon reset content of TRISB register is 0000 0000 000 000 1111 1111 111 111 C
Which of the following instruction is used to BSF BCG BTG BMF A
Which of the following instruction is used to BSF BCG BTG BMF B
Which of the following instruction is used to BSF BCG BTG BMF C
Question Option A Option B Option C Option D Answer
By which of the following method(s)
devices receive service from the Interrupts Polling Both of these None of these C
microcontroller?
Asynchronous request for service by
peripherals to processor is known as Interrupt Polling Both of these None of these A
____
Which of the following can cause Serial data Serial data
Timer overflow All of these D
interrupt generation? reception transmission
In which of the following method(s)
priority can be assigned to the devices Interrupts Polling Both of these None of these A
demanding for service?
In which of the following method(s)
microcontroller can not ignore a device Interrupts Polling Both of these None of these B
request for service?
Which of the following method(s) waste
Interrupts Polling Both of these None of these B
microcontroller’s time
Input Interrupt Interrupt
Input Service
Full form of ISR is_______ Synchronous Synchronous Service D
Routine
Routine Routine Routine
Interrupt
Input Vector Inerrupt Input Vector
Full form of IVT is_______ Vector B
Table Vector Table Testbench
Testbench
Power on Reset Vector in PIC 18 is
0000 0008 0018 0028 A
_____h
High Priority Interrupt Vector in PIC 18 is
0000 0008 0018 0028 B
_____h
Low Priority Interrupt Vector vector in
0000 0008 0018 0028 C
PIC 18 is _____h
Fixed locations in memory that holds
IGT IMT IRT IVT D
addresses of ISRs are called as ____
Correct sequence of steps in executing
an interrupt is ______ Where 1=Execute
1-2-3-4 3-2-1-4 4-3-2-1 3-2-4-1 D
ISR, 2= Consult IVT, 3=Save PC on
stack and 4=Jump to ISR
While servicing an interrupt content of
PC MAR MBR IR A
____ register are saved on the stack
What is the status of interrupts in PIC 18 All are Some are
All are enabled None of these B
after power on or reset? disabled enabled
____ bit is used for enabling/disabling of
FIE GIE HIE JIE B
all interrupts
Global Interrupt Enable (GIE) bit is
INTCON RCON PIR PIE A
present in ______ register
Interrupt Priority Enable (IPEN) bit is
INTCON RCON PIR PIE B
present in ______ register
Peripheral Interrupt Enable (PEIE) bit is
INTCON RCON PIR PIE A
present in ______ register
To enable serial communication
interrupts which of the following bit(s) Only GIE Only PEIE Both of these None of these B
must be set?
To enable timer 0 interrupt which of the
Only GIE Only PEIE Both of these None of these A
following bit(s) must be set?
There are ___ registers to control
11 12 13 14 C
interrupt operation in PIC 18
In PIC18F, any interrupt source is
enabled when corresponding IE bit is 0 1 X None of these D
____.
Which of the following bit(s) control
operation of an interrupt source in PIC18 Flag bit Enable bit Priority bit All of these D
F?
The default ISR address in PIC18F is
0000 0008 0018 0028 B
_____ h
Which of the following bit(s) indicate that
Flag bit Enable bit Priority bit All of these A
an interrupt event has occurred?
Which of the following bit(s) is used to
Flag bit Enable bit Priority bit All of these C
assign priority to an interrupt?
Setting of ___ and ____ bit allows
Enable,
program execution to branch to the Flag, Enable Flag, Priority All of these A
Priority
interrupt vector address.
If the interrupt is one of the peripheral
(timers 1,2 , serial, etc. ) we need to set
TMR0IE INT0IE PEIE RBIE C
____ bit from INTCON register along
with GIE bit.
Which of the following interrupt has no
INT3 INT2 INT1 INT0 D
priority bit?
_____ interrupt has default high priority. INT0 INT1 INT2 All of these D
For any interrupt source, to assign high
priority the corresponding IP bit must be 0 1 X None of these B
____.
For any interrupt source, to assign low
priority the corresponding IP bit must be 0 1 X None of these A
____.
Which of the following is not a core Serial
TMR0 INT0 INT1 D
interrupt source? Transmit
Which of the following is not a peripheral
TMR3 TMR2 TMR1 TMR0 D
interrupt source?
Which of the following is not a peripheral Serial
TMR1 INT0 TMR2 B
interrupt source? Transmit
Upon power-on reset the external
Positive edge Negative edge Positive level Negative level
hardware interrupts INT0-INT2 are of A
triggered triggered triggered triggered
type _____.
Which of the following avoids tying down
Interrupts Polling Both of these None of these A
the microcontroller?
PIC 18 ha ____ external hardware
1 2 3 4 C
interrupts.
External hardware interrupts of PIC18F E D C B D
PORTB-change interrupt is assocaied 4 3 2 1 A
PORTB-change interrupt is assocaied RB0-RB3 RB2-RB5 RB3-RB6 RB4-RB7 D
Register Select pin of LCD selects_____ Status Command Data Program B
Register Select pin of LCD selects_____ Status Command Data Program C
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these B
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these A
1) How many clock pulses are confined by each machine cycle of Peripheral-
Interface Controllers?
a. 4
b. 8
c. 12
d. 16
Answer Explanation Related Ques
ANSWER: 4
Explanation:
No explanation is available for this question!
2) Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
Answer Explanation Related Ques
3) What is the execution speed of instructions in PIC especially while operating at
the maximum value of clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
Answer Explanation Related Ques
ANSWER: 0.2 μs
Explanation:
No explanation is available for this question!
4) Which operational feature of PIC allows it to reset especially when the power
supply drops the voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Brown-out reset
Explanation:
No explanation is available for this question!
5) Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program
memory
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
6) Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs
a. Only C
b. C & D
c. A, B & D
d. A, B & C
Answer Explanation Related Ques
ANSWER: A, B & C
Explanation:
No explanation is available for this question!
7) Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
Answer Explanation Related Ques
ANSWER: Watchdog Timer (WDT)
Explanation:
No explanation is available for this question!
8) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
Answer Explanation Related Ques
ANSWER: Program Counter Latch (PCLATH) Register
Explanation:
No explanation is available for this question!
9) Which register/s is/are mandatory to get loaded at the beginning before loading
or transferring the contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
Answer Explanation Related Ques
ANSWER: W
Explanation:
No explanation is available for this question!
10) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
Answer Explanation Related Ques
ANSWER: 1
Explanation:
No explanation is available for this question!
11) Which among the below mentioned bits specify the reset status of register in
readable format and are usually utilized in sleep mode of PIC?
a. TO
b. PD
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Both a & b
Explanation:
No explanation is available for this question!
12) The RPO status register bit has the potential to determine the effective address
of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
Answer Explanation Related Ques
ANSWER: Direct Addressing Mode
Explanation:
No explanation is available for this question!
13) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Digits Carry bit (DC)
Explanation:
No explanation is available for this question!
14) Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF
instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction
in indirect addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
Answer Explanation Related Ques
ANSWER: Only A
Explanation:
No explanation is available for this question!
15) Which among the below stated registers specify the address reachability within
7 bits of address independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
16) Where do the contents of PCLATH get transferred in the higher location of
program counter while writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
Answer Explanation Related Ques
ANSWER: 13th bit
Explanation:
No explanation is available for this question!
17) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
Answer Explanation Related Ques
ANSWER: Low
Explanation:
No explanation is available for this question!
18) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
Answer Explanation Related Ques
ANSWER: the detection of increment in VDD from 1.5 V to 2.1 V
Explanation:
No explanation is available for this question!
19) What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
Answer Explanation Related Ques
ANSWER: 1024 cycles
Explanation:
No explanation is available for this question!
20) Which kind of mode is favourable for MCLR pin for indulging in reset
operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
Answer Explanation Related Ques
ANSWER: Sleep mode
Explanation:
No explanation is available for this question!
21) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
Answer Explanation Related Ques
ANSWER: For ensuring the inception and stabilization of an oscillator in a proper manner
Explanation:
No explanation is available for this question!
22) Which program location is allocated to the program counter by the reset
function in Power-on-Reset (POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
Answer Explanation Related Ques
ANSWER: Initial address
Explanation:
No explanation is available for this question!
23) When does it become very essential to use the external RC components for the
reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
Answer Explanation Related Ques
ANSWER: Only if VDD power-up slope is insufficient at a requisite level
Explanation:
No explanation is available for this question!
24) Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
Answer Explanation Related Ques
ANSWER: C & D
Explanation:
No explanation is available for this question!
25) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
Answer Explanation Related Ques
ANSWER: It can reset the PIC automatically in running condition
Explanation:
No explanation is available for this question!
26) What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
Answer Explanation Related Ques
ANSWER: CPU resets PIC once again in BOR mode
Explanation:
No explanation is available for this question!
27) What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
Answer Explanation Related Ques
ANSWER: (1/8) x frequency of OSC1
Explanation:
No explanation is available for this question!
28) Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
Answer Explanation Related Ques
ANSWER: LP (Low-Power Clocking)
Explanation:
No explanation is available for this question!
29) Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
30) What is the executable frequency range of High speed (HS) clocking
method by using cystal/ ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
Answer Explanation Related Ques
ANSWER: 4-20 MHz
Explanation:
No explanation is available for this question!
31) How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
Answer Explanation Related Ques
ANSWER: 11 & 12 bits
Explanation:
No explanation is available for this question!
32) What location is attributed to 'goto Mainline' instruction in the program memory
of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
Answer Explanation Related Ques
ANSWER: 000H
Explanation:
No explanation is available for this question!
33) When do the special address 004H get automatically loaded into the program
counter?
a. After the execution of RESET action in program counter
b. After the execution of 'goto Mainline ' instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
Answer Explanation Related Ques
ANSWER: At the occurrence of interrupt into the program counter
Explanation:
No explanation is available for this question!
34) How many bits are utilized by the instruction of direct addressing mode in order
to address the register files in PIC?
a. 2
b. 5
c. 7
d. 8
Answer Explanation Related Ques
ANSWER: 7
Explanation:
No explanation is available for this question!
35) Which registers are adopted by CPU and peripheral modules so as to control
and handle the operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
Answer Explanation Related Ques
ANSWER: Special Function Registers
Explanation:
No explanation is available for this question!
Related Content
https://www.careerride.com/mcq-daily/microcontrollers-applications-test-questions-set-7-565.aspx
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit I MCQs
Q.1 A computer accepts data from the user processes the data according to the
instructions given and produces the desired output result.
A. True B. False Ans: True
Q.2 RAM stands for
A. Rigid Access memory B. Register Accumulator Memory
C. Random Access Memory D. None of the above Ans:C
Q.3 A single IC which consists of ALU, control section and Register section is called
as
A.Microprocessor B. Microcontroller
C.Minicomputer D. None of the above Ans:A
Q.4 What is the name of the system which carries only the control and timing
signals
A. Address Bus B. Data Bus C. Control Bus D. System Bus Ans:C
Q.5 The various ways of specifying the data is called .
A. Instruction B. Assembler Directive C. Addressing Mode Ans:C
Q.6 Interpreter translates language into machine level language and the
translation is done line by line.
A. Low B. High Ans:B
Q.7 Complier translates high-level language into .
A. Machine level language B. Assembly Level Language
C. C Language D. Low Level Language Ans:A
Q.8 enables the programmers to run the program step by step so that the
programmer can find out the exact location of the error.
A. Assembler B. Linker C. Loader D. Debugger Ans:D
Q.9 Memory addressing mode can be divide into groups.
A. 1 B. 2 C. 3 D. 4 Ans:B
Q. 10 CALL instruction transfers the control of execution of the program to the
subroutine or procedure
A. True B. False Ans:A
Q.11 A macro is unlike a in that the machine instructions are repeated each
time the macro is referenced.
A. Procedure B. Call C. Return D. Assembler Ans:A
Q.12 The meaning of ‘interrupts’ is to break the sequence of operation.
A. True B. False Ans:A
Q.13 The process of interrupting the normal program execution to carry out a specific
task/work is referred to as .
A. Interrupt B. ISR C. Macro D. Procedure Ans:A
Q.14 Register that is used to hold the memory address of the next instruction to be
executed is
A. Program Memory B. Program Counter
C. Control Unit D. Instruction Decoder Ans:B
Q.15 Which register is used to store the output generated by ALU?
A. SFR B. GPR C. Accumulator (W) D. SP Ans:C
Q.16 The has built-in ROM,RAM, Parallel I/O, Serial I/O, counters and
clock circuit.
A. Microcontroller B. Microprocessor
C. Mainframe computers D. none of the above Ans: A
Q.17 PIC uses architecture.
A. Von Neumann B. Harvard Ans: B
Q.18 The PIC can control up to independent interrupt sources.
A. 6 B. 8 C. 10 D. 12 Ans: D
Q.19 The instruction set of PIC consists of instructions.
A. 66 B. 77 C. 88 D. 99 Ans:B
Q.20 In PIC memory sizes from 8 to 128 KB.
A. ROM B. Flash Program C. RAM Ans:B
Q.21 The PIC is High performance processor.
A. RISC B. CISC Ans: A
Q.22 The PIC has bit ADC.
A. 8 B. 9 C. 10 D. 12 Ans: C
Q.23 The PIC has CCP Modules
A. 4 B. 5 C. 6 D. 7 Ans: B
Q.24 Out of 40 Pins, 33 pins are dedicated to Ports of PIC.
A.4 B. 5 C. 6 D. 7 Ans: B
Q.25 RESET pin is in the PIC.
A. WR’ B. OSC C. MCLR’ D. ECCP Ans: C
Q.26 used for control and status of the controller and peripheral functions.
A. SFRs B. GPRs C. WREG D. FSRs Ans: A
Q.27 used for data storage and scratchpad operations in the user’s
application.
A. SFRs B. GPRs C. WREG D. FSRs Ans: B
Q.28 acts as an Accumulator.
A. SFRs B. GPRs C. WREG D. FSRs Ans: C
Q.29 register that stores flags- indicates the status of the operation done
by ALU.
A. Status B. SFR C.GPR D. FSR Ans:A
Q.30 is a 4 bit register used in Direct addressing the data memory.
A. Status B. SFR C.GPR D. BSR Ans:D
Q.31 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.32 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.33 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.34 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.35 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.36 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.37 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.38 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C.Over Flow D. Zero Ans:D
Q.39 Flag is set whenever the result of signed number operation is too large,
causing the high order bit to over flow in to sign bit.
A. Carry B. Negative C.Over Flow D. Zero Ans:C
Q. 40 After execution of ALU operations, if bit 7 of the result is 1, the flag is set
indicating result is negative.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:D
Q. 41 In PIC, the data memory is implemented as static RAM. It is also known as _
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q. 42 When using addressing, the BSR is used to select the desired bank.
A. Direct B. Indirect C. Implied D. Immediate Ans: A
Q. 43 Indirect addressing requires use of .
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q.44 Each FSR holds a bit address value that can be used to access any location
in the data memory map without banking.
A. 10 B. 11 C. 12 D. 13 Ans: C
Q.45 Upon reset BSR= H.
A. 001B B. 0000 C. 0FFF D. FFFF Ans:B
Q.46 Immediate data is also called Literal in PIC18.
A. True B. False Ans:A
Q.47 In addressing mode, the letter ‘F’ in the instruction means the address of
the File Register location.
A. Direct B. Indirect C. Immediate D. Register Ans:D
Q.48 The ECIO oscillator mode functions like the EC mode, except that the
OSC2 pin becomes an additional general purpose I/O pin.
A. True B. False Ans:A
Q.49 The PLL can only be enabled when the oscillator configuration bits are
programmed for HS mode.
A. True B. False Ans:A
Q.50 In the Sleep mode, the on-chip clocks and oscillator are turned off.
A. True B. False Ans:A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit II MCQs
Q.1 When does it become possible for a bit to get accessed from bank '0' in the direct
addressing mode of PICs?
A. Only when RPO bit is set 'zero'
B. Only when RPO bit is set '1'
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.2 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to
turn on the weak internal pull-ups of port B?
A. RPO’ B. RPBU’ C. RBIF D. All of the above Ans:B
Q.3 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of 'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.4 Which digital operations are performed over the detected mismatch outputs with
an intention to generate a single output RB port change output?
A. OR B. AND C. EXOR D. NAND Ans: A
Q.5 How many clock pulses are confined by each machine cycle of Peripheral-Interface
Controllers?
A. 4 B. 8 C.12 D. 16 Ans:A
Q.6 Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
A. Carry (C) Flags B. Zero (Z) Flags
C. Digit Carry (DC) Flags D. All of the above Ans:D
Q.7 What is the execution speed of instructions in PIC especially while operating at the
maximum value of clock rate?
A. 0.1 μs B. 0.2 μs C. 0.4 μs D. 0.8 μs Ans: B
Q.8 Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?
A. Built-in Power-on-reset B. Brown-out reset
C. Both a & b D. None of the above Ans:B
Q.9 Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
A. Improvement in bandwidth
B. Instruction fetching becomes possible over a single instruction cycle
C. Independent bus access provision to data memory even while accessing the
program memory
D. All of the above Ans:D
Q.10 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C
B. C&D
C. A, B & D
D. A, B & C Ans:D
Q.11 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT)
B. Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT)
D. All of the above Ans:C
Q. 12 Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
A. Status Register
B. Program Counter Latch (PCLATH) Register
C. Program Counter Low Byte (PCL) Register
D. File Selection Register (FSR) Ans: B
Q.13 Which register/s is/are mandatory to get loaded at the beginning before loading or
transferring the contents to corresponding destination registers?
A. W B. INDF C. PCL D. All of the above Ans: A
Q.14 How many RPO status bits are required for the selection of two register banks?
A. 1 B.2 C. 8 D. 16 Ans: A
Q.15 The RPO status register bit has the potential to determine the effective address
of
A. Direct Addressing Mode
B. Indirect Addressing Mode
C. Immediate Addressing Mode
D. Indc. Watchdog Timer (WDT) exed Addressing Mode Ans:A
Q.16 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B. Digits Carry bit (DC)
C. Both A & B D. None of the above Ans:B
Q.17 Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
A. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
B. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
C. Address byte must be written in FSR at the same time during the execution of
INDF instruction in indirect addressing mode
D. Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode
A. Only A B. Only B C. Only A & B D. A & D Ans:A
Q.18 Which among the below stated registers specify the address reachability within 7
bits of address independent of RP0 status bit register?
A. PCL B. FSR C. INTCON D. All of the above Ans:D
Q.19 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th Bit B. 12th Bit C. 13th Bit D. 14th Bit Ans:C
Q.20 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B. Low C. Moderate D. All of the above Ans:B
Q.21 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor Ans:A
Q.22 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 Cycles B. 1024 Cycles C. 2048 Cycles D.4096 Cycles Ans:B
Q.23 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode
B. Sleep mode
C. Power-down mode
D. Any flexible mode Ans:B
Q.24 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A. For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.25 Which program location is allocated to the program counter by the reset function
in Power-on-Reset (POR) action modes?
A. Initial address
B. Middle address
C. Final address
D. At any address reliable for reset operations Ans:A
Q.26 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans:B
Q. 27 Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
A. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
A. A & B B. C & D C. A & C D. B & D Ans:B
Q.28 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.29 What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
A. (1/2) x frequency of OSC1
B. (1/4) x frequency of OSC1
C. (1/8) x frequency of OSC1
D. (1/16) x frequency of OSC1 Ans:C
Q.30 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC
B. LP (Low-Power Clocking)
C. XT
D. HS (High Speed) Ans:B
Q.31 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy
B. Proficiency in time generation
C. Applicability in real-time operations
D. All of the above Ans:A
Q.32 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ ceramic/ resonator or any other external clock source?
A.0-4 MHz B. 5-200 KHz C.100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.33 How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
A. 4 & 8 bits B. 8 & 16 bits C. 11 & 12 bits D. 12 & 16 bits Ans:C
Q.34 When do the special address 004H get automatically loaded into the program
counter?
A. After the execution of RESET action in program counter
B. After the execution of ‘goto Mainline ‘ instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.35 How many bits are utilized by the instruction of direct addressing mode in order to
address the register files in PIC?
A. 2 B.5 C.7 D.8 Ans:C
Q.36 Which registers are adopted by CPU and peripheral modules so as to control and
handle the operation of device inhibited in RFS?
A. General Purpose Register
B. Special Purpose Register
C. Special Function Register
D. All of the above Ans:C
Q.37 Which among the below specified registors are addressable only from bank1 of
RFS?
A. PORTA (05H)
B. PORTB (06H)
C. FSR (04H)
D. ADCON0 (07H) Ans:A
Q.38 Which register acts as an input-output control as well as data direction register for
PORTA in bank 2 of RFS?
A. INDF (80H) B. TRISB (85H) C. TRISA (85H) D. PCLATH (8A) Ans:C
Q.39 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1
B. Only Bank 2
C. Either Bank 1 or Bank 2
D. Neither Bank 1 nor Bank 2 Ans:C
Q.40 Which bit of OPTION register has a potential to decide the falling or rising edge
sensitivity for the external interrupt INT?
A. RBPU B.INTEDG C.PSA D.RTS Ans:B
Q.41 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC
B. Only Watchdog timer
C. Either RTCC or Watchdog timer
D. Neither RTCC nor Watchdog timer Ans:C
Q.42 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C.ADRES D.PCLATH Ans:B
Q.43 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B.ADIE C.RBIE D.TOIE Ans:A
Q.44 When does it become possible for a bit to get accessed from bank ‘0’ in the direct
addressing mode of PICs?
A. Only when RPO bit is set ‘zero’
B. Only when RPO bit is set ‘1’
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.45 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of ‘interrupt on change’?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.46 What is the purpose of acquiring two different bits from INTCON register for
performing any interrupt operation in PIC 16C61 / 71?
A. One for enabling & one for disabling the interrupt
B. One for enabling the interrupt & one for its occurrence detection
C. One for setting or clearing the RBIE bit
D. None of the above Ans:B
Q.47 What kind of external edge-sensitive interrupt is generated due to transition effect
at pin RBO/INT?
A. INT
B. RBO
C. INTF
D. All of the above Ans:A
Q.48 Consider the following statements. Which of them is /are incorrect?
A. By enabling INTE bit of an external interrupt can wake up the processor before
entering into sleep mode.
B. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
C. During the occurrence of interrupt, GIE bit is set in order to prevent any further
interrupts.
D. goto instruction written in program memory cannot direct the program control to
ISR.
A. A & B
B. C & D
C. Only A
D. Only C Ans:B
Q.49 What is the purpose of setting TOIE bit in INTCON along with GIE bit?
A. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow
interrupt
B. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow
interrupt
C. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
D. None of the above Ans:A
Q.50 Which command enables the PIC to enter into the power down mode during the
operation of watchdog timer (WDT)?
A. SLEEP B. RESET C. STATUS D. CLR Ans:A
Q.51 How much delay is required to sunchronize the externalclock at TOCKI in Timer 0
of Pic16FXXX?
A. 2 cycles B. 4cycles C. 6cycles D. 8cycles Ans:A
Q.52 How much time is required for conversion per channel if PIC possesses four analog
channels, each comprising of 8 bits?
A. 10 µs B.15 µs C.20 µs D. 25µs Ans: C
Q.53 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT) B.Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT) D.All of the above
Ans:C
Q.54 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B.Digits Carry bit (DC)
C. Both a & b D.None of the above Ans:B
Q.55 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th bit B.12th bit C.13th bit D.14th bit Ans:C
Q.56 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B.Low C. Moderate D. All of the above Ans:B
Q.57 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor
Ans:A
Q.58 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode B.Sleep mode C.Power-down mode D.Any flexible mode Ans:B
Q.59 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 cycles B.1024 cycles C.2048 cycles D. 4096 cycles Ans:B
Q.60 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A.For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.61 Which program location is allocated to the program counter by the reset function
in Power-onReset (POR) action modes?
A. Initial address B.Middle address
C.Final address D.At any address reliable for reset operations Ans: A
Q.62 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans: B
Q.63 What output is generated by OSC2 pin in PIC oscillator comprising RC components
for sychronizing the peripherals with PIC microcontroller?
A.(1/2) x frequency of OSC1
B.(1/4) x frequency of OSC1
C.(1/8) x frequency of OSC1
D.(1/16) x frequency of OSC1 Ans: C
Q.64 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans: A
Q.65 What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
A.CPU resets PIC once again in BOR mode
B.BOR reset mode gets disabled
C.PIC does not remain in BOR mode until the voltage increases irrespective of
stability
D.Power-up timer kills 72ms more again
Ans: A
Q.66 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC B.LP (Low-Power Clocking) C. XT D. HS (High Speed) Ans: B
Q.67 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy B.Proficiency in time generation
C. Applicability in real-time operations D.All of the above Ans:D
Q.68 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ceramic/ resonator or any other external clock source?
A. 0-4 MHz B. 5-200 KHz C. 100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.69 Which bits play a crucial role in specifying the details or reasons associated with
the system wake-up in WDT?
A. PD’ & TO’ B. C & Z C. DC & RPO D. All of the above Ans:A
Q.70 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B. ADIE C. RBIE D. TOIE Ans: A
Q.71 Which instruction is applicable to set any bit while performing bitwise operation
settings?
A. bcf B. bsf C. Both A & B D. None of the above Ans:B
Q.72 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
A. Provision of MPLAB specific extensions
B. Floating-point Format Support
C. Data in Program Memory
D. All of the above Ans:D
Q.73 What does the 'program idata' section of data memory contain in C-18 Compiler?
A. statically assigned/allocated initialized user variables
B. statically assigned /allocated uninitialized user variables
C. only executable instructions
D. variables as well as constants Ans:A
Q.74 Where is the result stored after an execution of increment and decrement operations over
the special - purpose registers in PIC?
A. File Register B. Working Register C. Both A & B D. None of the above Ans:C
Q.75 Which flags of status register are most likely to get affected by the single-cycle increment
and decrement instructions?
A. P Flags B. C Flags C. OV Flags D. Z Flags Ans:D
Q.76 Which command-line option of compiler exhibits the banner comprising overall number of
errors, messages, warnings and version number after an accomplishment of the
compilation process?
A. help B. verbose C. overlay D. char Ans:B
Q.77 Which among the below assertions represent the salient features of PIC in C-18 compiler?
A. Transparent read/ write access to an external memory
B. Provision of supporting an inline assembly during the necessity of an overall control
C. Integration with MPLAB IDE for source-level debugging
D. All of the above Ans:D
Q.78 Which bit plays a salient role in defining the master or slave mode in TXSTA register
especially in synchronous mode?
A. RSRC B. CSRC C. SPEN D. SYNC Ans:B
Q.79 What is the status of shift clock supply in an USART synchronous mode?
A. Master-internally, Slave-externally
B. Master-externally, Slave-internally
C. Master & Slave (both) - internally
D. Master & Slave (both) – externally Ans:A
Q.80 When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of
'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.81 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn
on the weak internal pull-ups of port B?
A.RPO B.RPBU’ C. RBIF D.All of the above Ans:B
Q.82 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C. ADRES D.PCLATH Ans:B
Q.83 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC B. Only Watchdog timer
C. Either RTCC or Watchdog timer D. Neither RTCC nor Watchdog timer Ans:C
Q.84 Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity
for the external interrupt INT?
A. RBPU B. INTEDG C. PSA D. RTS Ans:B
Q.85 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1 B. Only Bank 2
C. Either Bank 1 or Bank 2 D. Neither Bank 1 nor Bank 2 Ans:C
Q.86 Which register acts as an input-output control as well as data direction register for PORTA
in bank 2 of RFS?
A. INDF B. TRISB C.TRISA D.PCLATH Ans:C
Q.87 Which registers are adopted by CPU and peripheral modules so as to control and handle
the operation of device inhibited in RFS?
A. General Purpose Register B. Special Purpose Register
C. Special Function Registers D. All of the above Ans:C
Q.88 How many bits are utilized by the instruction of direct addressing mode in order to address
the register files in PIC?
A. 2 B. 5 C. 7 D. 8 Ans:C
Q.89 When do the special address 004H get automatically loaded into the program counter?
A. After the execution of RESET action in program counter
B. After the execution of 'goto Mainline ' instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.90 Which significant feature/s of crystal source contribute/s to its maximum predilection and
utility as compared to other clock sources?
A. High accuracy B. Proficiency in time generation
C. Applicability in real-time operations D. All of the above Ans:D
Q.91 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely
unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.92 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C B. C & D C. A, B & D D. A, B & C Ans:D
Q.93 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.94 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.95 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.96 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.97 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.98 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.99 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.100 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C. Over Flow D. Zero Ans:D
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator
on OSC1 and OSC2 pins is divided by 1 2 3 4 D
_____ and fed to timer.
Which of the following timers have both 8
Timer 0 Timer 1 Timer 2 Timer 3 A
and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8
Timer 0 Timer 1 Timer 2 Timer 3 A
pre-scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of
TMR0ON T08BIT T0CS T0SE A
Timer0.
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by
Timer0 if FFF6 h is loaded into it. 5.6 μS 5.2 μS 4.6 μS 4 μS D
Assume crystal frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
frequency = 16 MHz and prescaler of 0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
1:16
Find timer's clock period with crystal
frequency = 32 MHz and prescaler of 1 μS 2 μS 3 μS 4 μS A
1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair FFFF h 1234 h 0000 h 4321 h C
for generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller
5 6 7 8 B
is ___ bits.
Size of Port E in PIC 18 microcontroller
3 4 5 6 A
is ___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of
TMRxON Tx8BIT TxCS TxSE A
Timerx.
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
MICROPROCESSOR
BCA
IV Sem
MULTIPLE CHOICE QUESTIONS
1) Which is the microprocessor comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
2) What is the store by register?
a. data
b. operands
c. memory
d. None of these
3) Accumulator based microprocessor example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
4) A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
5) There are primarily two types of register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
6) Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
7) BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
8) Which is used to store critical pieces of data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
9) The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
10) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a. 16
b. 32
c. 36
d. 64
12) Which is not the control bus signal:
a. READ
b. WRITE
c. RESET
d. None of these
13) PROM stands for:
a. Programmable read‐only memory
b. Programmable read write memory
c. Programmer read and write memory
d. None of these
14) EPROM stands for:
a. Erasable Programmable read‐only memory
b. Electrically Programmable read write memory
c. Electrically Programmable read‐only memory
d. None of these
15) Each memory location has:
a. Address
b. Contents
c. Both A and B
d. None of these
16) Which is the type of microcomputer memory:
a. Processor memory
b. Primary memory
c. Secondary memory
d. All of these
17) Secondary memory can store____:
a. Program store code
b. Compiler
c. Operating system
d. All of these
18) Secondary memory is also called____:
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
19) Customized ROMS are called:
a. Mask ROM
b. Flash ROM
c. EPROM
d. None of these
20) The RAM which is created using bipolar transistors is called:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. DDR RAM
21) Which type of RAM needs regular referred:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
22) Which RAM is created using MOS transistors:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
23) A microprocessor retries instructions from :
a. Control memory
b. Cache memory
c. Main memory
d. Virtual memory
24) The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
a. Address bus
b. System bus
c. Control bus
d. Data bus
25) The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
a. Read
b. Write
c. Both A and B
d. None of these
26) The CPU removes the ___ signal to complete the memory write operation:
a. Read
b. Write
c. Both A and B
d. None of these
27) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
28) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
29) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
30) Eight of the register are known as:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
31) The four index register can be used for:
a. Arithmetic operation
b. Multipulation operation
c. Subtraction operation
d. All of these
32) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
33) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
34) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
36) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
37) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
38) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
39) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
40) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
41) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
42) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
43) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
44) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
45) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
46) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
47) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
48) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
49) ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a. Data segment
b. Code segment
c. Stack segment
d. Extra segment
50) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
51) Which are the factor of cache memory:
a. Architecture of the microprocessor
b. Properties of the programs being executed
c. Size organization of the cache
d. All of these
52) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
53) Which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
54) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
55) Microprocessor reference that are available in the cache are called______:
a. Cache hits
b. Cache line
c. Cache memory
d. All of these
56) Microprocessor reference that are not available in the cache are called_________:
a. Cache hits
b. Cache line
c. Cache misses
d. Cache memory
57) Which causes the microprocessor to immediately terminate its present activity:
a. RESET signal
b. INTERUPT signal
c. Both
d. None of these
58) Which is responsible for all the outside world communication by the microprocessor:
a. BIU
b. PIU
c. TIU
d. LIU
59) INTR: it implies the__________ signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
60) Which of the following are the two main components of the CPU?
a. Control Unit and Registers
b. Registers and Main Memory
c. Control unit and ALU
d. ALU and bus
61) Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
a. Conductors
b. Buses
c. Connectors
d. Consecutives
62) The language that the computer can understand and execute is called
a. Machine language
b. Application software
c. System program
d. All of the above
63) Which of the following is used as a primary storage device?
a. Magnetic drum
b. PROM
c. Floppy disk
d. All of these
64) Which of the following memories needs refresh?
a. SRAM
b. DRAM
c. ROM
d. All of above
65) The memory which is programmed at the time it is manufactured
a. PROM
b. RAM
c. PROM
d. EPROM
66) Which of the following memory medium is not used as main memory system?
a. Magnetic core
b. Semiconductor
c. Magnetic tape
d. Both a and b
67) Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
68) One of the main feature that distinguish microprocessors from micro‐computers is
a. Words are usually larger in microprocessors
b. Words are shorter in microprocessors
c. Microprocessor does not contain I/O devices
d. Exactly the same as the machine cycle time
69) The first microprocessor built by the Intel Corporation was called
a. 8008
b. 8080
c. 4004
d. 8800
70) An integrated circuit is
a. A complicated circuit
b. An integrating device
c. Much costlier than a single transistor
d. Fabricated on a tiny silicon chip
71) Most important advantage of an IC is its
a. Easy replacement in case of circuit failure
b. Extremely high reliability
c. Reduced cost
d. Low powers consumption
72) Which of the following items are examples of storage devices?
a. Floppy / hard disks
b. CD‐ROMs
c. Tape devices
d. All of the above
73) The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
a. 8 bits
b. 12 bits
c. 16 bits
d. 32 bits
74) Which is the type of memory for information that does not change on your computer?
a. RAM
b. ROM
c. ERAM
d. RW / RAM
75) What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
a. Extended
b. Expanded
c. Base
d. Conventional
76) Before a disk can be used to store data. It must be…….
a. Formatted
b. Reformatted
c. Addressed
d. None of the above
77) Which company is the biggest player in the microprocessor industry?
a. Motorola
b. IBM
c. Intel
d. AMD
78) A typical personal computer used for business purposes would have… of RAM.
a. 4 KB
b. 16 K
c. 64 K
d. 256 K
78) The word length of a computer is measured in
a. Bytes
b. Millimeters
c. Meters
d. Bits
79) What are the three decisions making operations performed by the ALU of a computer?
a. Grater than
b. Less than
c. Equal to
d. All of the above
80) Which part of the computer is used for calculating and comparing?
a. Disk unit
b. Control unit
c. ALU
d. Modem
81) Can you tell what passes into and out from the computer via its ports?
a. Data
b. Bytes
c. Graphics
d. Pictures
82) What is the responsibility of the logical unit in the CPU of a computer?
a. To produce result
b. To compare numbers
c. To control flow of information
d. To do math’s works
83) The secondary storage devices can only store data but they cannot perform
a. Arithmetic Operation
b. Logic operation
c. Fetch operations
d. Either of the above
84) Which of the following memories allows simultaneous read and write operations?
a. ROM
b. RAM
c. EPROM
d. None of above
85) Which of the following memories has the shortest access times?
a. Cache memory
b. Magnetic bubble memory
c. Magnetic core memory
d. RAM
86) A 32 bit microprocessor has the word length equal to
a. 2 byte
b. 32 byte
c. 4 byte
d. 8 byte
87) An error in computer data is called
a. Chip
b. Bug
c. CPU
d. Storage device
88) The silicon chips used for data processing are called
a. RAM chips
b. ROM chips
c. Micro processors
d. PROM chips
89) The metal disks, which are permanently housed in, sealed and contamination free containers
are called
a. Hard disks
b. Floppy disk
c. Winchester disk
d. Flexible disk
90) A computer consists of
a. A central processing unit
b. A memory
c. Input and output unit
d. All of the above
91) The instructions for starting the computer are house on
a. Random access memory
b. CD‐Rom
c. Read only memory chip
d. All of above
92) The ALU of a computer normally contains a number of high speed storage element called
a. Semiconductor memory
b. Registers
c. Hard disks
d. Magnetic disk
93) The first digital computer built with IC chips was known as
a. IBM 7090
b. Apple – 1
c. IBM System / 360
d. VAX‐10
94) Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
95) Which of the following is used for manufacturing chips?
a. Control bus
b. Control unit
c. Parity unit
d. Semiconductor
96) To locate a data item for storage is
a. Field
b. Feed
c. Database
d. Fetch
97) A directly accessible appointment calendar is feature of a … resident package
a. CPU
b. Memory
c. Buffer
d. ALU
98) The term gigabyte refers to
a. 1024 bytes
b. 1024 kilobytes
c. 1024 megabytes
d. 1024 gigabyte
99) A/n …. Device is any device that provides information, which is sent to the CPU
a. Input
b. Output
c. CPU
d. Memory
100) Current SIMMs have either … or … connectors (pins)
a. 9 or 32
b. 30 or 70
c. 28 or 72
d. 30 or 72
101) Which is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
102) Which technology using the microprocessor is fabricated on a single chip:
a. POS
b. MOS
c. ALU
d. ABM
103) MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
104) In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
105) The register section is related to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
106) In Microprocessor one of the operands holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
107) Which register is a temporary storage location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
108) PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
109) IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
110) SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
111) The act of acquiring an instruction is referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
112) How many bit of instruction on our simple computer consist of one____:
a. 2‐bit
b. 6‐bit
c. 12‐bit
d. None of these
113) How many parts of single address computer instruction :
a. 1
b. 2
c. 3
d. 4
114) Single address computer instruction has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
115) LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
116) Which are the flags of status register:
a. Over flow flag
b. Carry flag
c. Half carry flag
d. Zero flag
e. Interrupt flag
f. Negative flag
g. All of these
117) The carry is operand by:
a. C
b. D
c. S
d. O
118) The sign is operand by:
a. S
b. D
c. C
d. O
119) The zero is operand by:
a. Z
b. D
c. S
d. O
120) The overflow is operand by:
a. O
b. D
c. S
d. C
121) _________ Stores the instruction currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
122) In which register instruction is decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
123) The status register is also called the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
124) The area of memory with addresses near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
125) The processor uses the stack to keep track of where the items are stored on it this by using
the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
126) Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
127) Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
128) SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
129) How many bit stored by status register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
130) The 16 bit register is separated into groups of 4 bit where each groups is called:
a. BCD
b. Nibble
c. Half byte
d. None of these
131) A nibble can be represented in the from of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
132) The left side of any binary number is called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
133) MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
134) _____ a subsystem that transfer data between computer components inside a computer
or between computer:
a. Chip
b. Register
c. Processor
d. Bus
135) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
136) Which bus carry addresses:
a. System bus
b. Address bus
c. Control bus
d. Data bus
137) A 16 bit address bus can generate___ addresses:
a. 32767
b. 25652
c. 65536
d. none of these
138) CPU can read & write data by using :
a. Control bus
b. Data bus
c. Address bus
d. None of these
139) Which bus transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a. Control bus
b. Data bus
c. Address bus
d. None of these
140) When memory read or I/O read are active data is to the processor :
a. Input
b. Output
c. Processor
d. None of these
141) When memory write or I/O read are active data is from the processor:
a. Input
b. Output
c. Processor
d. None of these
142) CS stands for:
a. Cable select
b. Chip select
c. Control select
d. Cable system
143) WE stands for:
a. Write enable
b. Wrote enable
c. Write envy
d. None of these
144) MAR stands for:
a. Memory address register
b. Memory address recode
c. Micro address register
d. None of these
145) MDR stands for:
a. Memory data register
b. Memory data recode
c. Micro data register
d. None of these
146) Which are the READ operation can in simple steps:
a. Address
b. Data
c. Control
d. All of these
147) DMA stands for:
a. Direct memory access
b. Direct memory allocation
c. Data memory access
d. Data memory allocation
148) The ____ place the data from a register onto the data bus:
a. CPU
b. ALU
c. Both A and B
d. None of these
149) The microcomputer system by using the ____device interface:
a. Input
b. Output
c. Both A and B
d. None of these
150) The standard I/O is also called:
a. Isolated I/O
b. Parallel I/O
c. both a and b
d. none of these
151) The external device is connected to a pin called the ______ pin on the processor chip.
a. Interrupt
b. Transfer
c. Both
d. None of these
152) Which interrupt has the highest priority?
a) INTR
b) TRAP
c) RST6.5
d) none of these
153) In 8085 name the 16 bit registers?
a) Stack pointer
b) Program counter
c) a & b
d) none of these
154) What are level Triggering interrupts?
a) INTR&TRAP
b) RST6.5&RST5.5
c) RST7.5&RST6.5
d) none of these
155) Which stack is used in 8085?
a) FIFO
b) LIFO
c) FILO
d) none of these
156) What is SIM?
a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask.
d) none of these
157) RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
d) none of these
158) In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR d) none of these
159) In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
160) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
161) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
162) Which are the part of architecture of 8086:
a. The bus interface unit
b. The execution unit
c. Both A and B
d. None of these
163) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
164) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
165) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
166) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
167) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
168) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
169) The upper 8 bit are called______:
a. BH
b. BL
c. AH
d. CH
170) The lower 8 bit are called_______:
a. AL
b. CL
c. BL
d. DL
171) IP stand for:
a. Industry pointer
b. Instruction pointer
c. Index pointer
d. None of these
172) Which has great important in modular programming:
a. Stack segment
b. Queue segment
c. Array segment
d. All of these
173) Which register containing the 8086/8088 flag:
a. Status register
b. Stack register
c. Flag register
d. Stand register
174) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
175) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
176) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
177) The physical address of memory is :
a. 20 bit
b. 16 bit
c. 32 bit
d. 64 bit
178) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
179) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
180) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
181) PA stand for:
a. Project address
b. Physical address
c. Pin address
d. Pointer address
182) SBA stand for:
a. Segment bus address
b. Segment bit address
c. Segment base address
d. Segment byte address
183) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
184) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
185) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
186) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
187) DS stand for:
a. Default segment
b. Defect segment
c. Delete segment
d. Definition segment
188) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
189) AD stand for:
a. Address data
b. Address delete
c. Address date
d. Address deal
190) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
191) PC stand for:
a. program counter
b. project counter
c. protect counter
d. planning counter
192) AH stand for:
a. Accumulator high
b. Address high
c. Appropriate high
d. Application high
193) AL stand for:
a. Accumulator low
b. Address low
c. Appropriate low
d. Application low
194) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
195) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
196) which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
197) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
198) How many type of cache memory:
a. 1
b. 2
c. 3
d. 4
199) Which is the type of cache memory:
a. Fully associative cache
b. Direct‐mapped cache
c. Set‐associative cache
d. All of these
200) ) Which memory is used to holds the address of the data stored in the cache :
a. Associative memory
b. Case memory
c. Ordinary memory
d. None of these
PAI UNIT -2 MCQ
1. 1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
2.
1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
3. 3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor
4. The unit that decodes the instructions concurrently and translate them into micro-
operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
4. 5. In complex instructions, when the instruction needs to be translated into more than 4
micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
5. 6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
6. 8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
7. 9. If complex instructions like interrupt handling, string manipulation appear, then the
control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
8. 10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
9. 11. The mechanism to provide protection, that is accomplished with the help of
read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
10. 12. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
11. 13. The mechanism that is accomplished using descriptor usages limitations, and rules of
privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
12. 14. The mechanism that is executed at certain privilege levels, determined by CPL
(Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
13. 15. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) none of the mentioned
14. 16. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
15. 17. The condition, “CPL not equals to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) all of the mentioned
16. 18. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) all of the mentioned
17. 19. The instruction at which the exception is generated, but the processor extension
registers containthe address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
18. 20. The exception that has no error code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
19. 21. By using privilege mechanism the protection from unauthorised accesses is done to
a) operating system
b) interrupt handlers
c) system softwares
d) all of the mentioned
20. 22. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) none of the mentioned
21. 23. Once the CPL is selected, it can be changed by
a) HOLD
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
22. 24. The data segments defined in GDT (global descriptor table) and the LDT (local
descriptor table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
23. 25. A task with privilege level 0, doesnot refer to all the lower level privilege descriptors
in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) none of the mentioned
24. 26. The selector RPL that uses a less trusted privilege than the current privilege level for
further use is known as
a) Least task privilege level
b) descriptor privilege level
c) effective privilege level
d) none of the mentioned
25. 27. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
26. 28. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
27. 29. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) all of the mentioned
28. 30. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
29. Answers
1-d 2-c 3-d 4-b 5-cc
6-a 7-d 8-b 9-a 10-a
11-a 12-c 13-b 14-c 15-c
16-c 17-d 18-c 19-d 20-b
21-d 22-b 23-c 24-a 25-b
26-c 27-c 28-c 29-b 30-c
TOPICS– Privilege
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Privilege”.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
View Answer
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be protected
from unauthorized accesses in virtual address space of each task using the privilege mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) None of the mentioned
View Answer
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task privilege level
at that instant is called the Current Privilege Level (CPL).
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
View Answer
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a single
code segment. It can only be changed by transferring the control, using gate descriptors, to a new
segment.
4. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor
table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
View Answer
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data segments
defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) None of the mentioned
View Answer
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors which apply
to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
View Answer
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for further use.
This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
View Answer
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of RPL
and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
View Answer
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level(CPL, RPL, DPL).
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned
View Answer
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with DPL equal to
CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
View Answer
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same privilege as
CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than
the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
View Answer
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with DPL equal
to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must
be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
View Answer
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment(TSS) descriptor, then
DPL must be less or equally privileged than CPL.
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13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
View Answer
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data segment
access.
14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
View Answer
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an exception 13
is generated. If the referenced segment is not present in physical memory, an exception 11 is ge
Topic – Protection
1. The mechanism to provide protection, that is accomplished with the help of read/write
privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
View Answer
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are restricted by
classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege
check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is accomplished
using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL (Current
Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
View Answer
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
View Answer
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
View Answer
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this
condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
View Answer
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT,
LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
View Answer
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI
and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
View Answer
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers
contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
View Answer
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
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11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
View Answer
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun, processor
extension segment overrun, are the protected mode exceptions.
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TOPIc– Protected Virtual Address Mode (PVAM) -2
This set of Advanced Microprocessors Questions and Answers focuses on “Protected Virtual
Address Mode (PVAM) -2”.
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
View Answer
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called system
descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate and trap
gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control transfer,
required stack manipulations, privilege level and its type.
4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d) trap gate
View Answer
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
View Answer
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
View Answer
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
View Answer
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number of bytes
to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM (read only memory)
View Answer
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor information,
from the main memory, cache memory is used in which the most frequently required data for execution
is stored.
9. The selector field consists of
a) requested privilege level (RPL)
b) table indicator
c) index
d) all of the mentioned
View Answer
Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as selectors. The
selector field consists of three fields namely, RPL, table indicator (TI) and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
View Answer
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero (0) is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
View Answer
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at privilege level
0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
View Answer
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table, containing
the base address, and limit for LDT.
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13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
View Answer
14. The number of interrupt descriptors that the interrupt descriptor table (IDT) handles is
a) 16
b) 64
c) 128
d) 256
View Answer
Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
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1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.
3. The number of debug registers that are available in 80386, for hardware debugging and control is a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware debugging and
control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging and four
levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is known as a)
segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organise the available
physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
Explanation: The 80386 has on-chip address translation cache, and instruction set is upward compatible
with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode of
operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286 (to be
executed under the control of memory management and protection abilities of 80386).
11. Which of the units is not a part of internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
12. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
Explanation: The central processing unit is further divided into execution unit and instruction unit.
13. The unit that is used for handling data, and calculate offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
14. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
15. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
16. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
17. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
18. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
19. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
Explanation: The paging unit works under the control of segmentation unit; i.e. each segment is further
divided into pages.
20. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
21. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
22. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
23. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
24. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) none of the mentioned
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
25. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
26. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
27. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.
28. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a
prefix of
a) X
b) E
c) 32
d) XX
Answer: b
Explanation: A 32 bit register, known as extended register, is represented by the register name with a
prefix of E.
29. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) none of the mentioned
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
30. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) all of the mentioned
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
31. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
32. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) none of the mentioned
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
33. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
34. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) task switch operation
c) IRET instruction or task switch operation
d) none of the mentioned
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
35. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
36. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
37. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of segments.
38. The 32-bit control register, that is used to hold global machine status, independent of the executed
task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
39. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) TSS (Task state segment descriptor)
e) all of the mentioned
Answer: e
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
40. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
41. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
42. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
Answer: c
Explanation: Two test registers are provided by 80386 for page cacheing, namely test control and test
status registers.
43. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
44. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
45. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
46. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
47. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers, rather, they
are internally used to store the descriptor information.
48. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
49. Contents of an index register are multiplied by a scale factor that may be added further to get the
operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
50. Contents of an index register are multiplied by a scale factor and then added to base register to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
51. In based scaled indexed mode with displacement mode, the contents of an index register are
multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is addedto a
base register and a displacement to get the offset of an operand.
52. The following statement of ALP is an example of MOV EBX, [EDX*4] [ECX]
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
53. The following statement is an example of MOV EBX, LIST [ESI*2] MUL ECX, LIST [EBP*4] a) base
scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
54. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
55. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
56. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
Answer: c
Explanation: The integer word is the signed 16-bit data.
57. A 16-bit displacement that references a memory location using any of the addressing modes is
a) pointer
b) character
c) BCD
d) offset
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing modes.
58. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
59. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
60. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
Answer: c
Explanation: The paging unit is disabled in real address mode.
61. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
62. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
63. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
64. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
65. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
66. If the paging unit is enabled, then it converts linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The paging unit when enabled, it converts linear address into physical address.
67. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The linear address is used as physical address if the paging unit is disabled.
68. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
Answer: c
Explanation: The paging unit is enabled only in protected mode.
69. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
70. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granulary bit
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
71. The TYPE field of descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
72. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
73. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
74. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
75. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
76. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Answer: d
Explanation: The five types of segment descriptors of 80386 are: 1. Code or data segment descriptors 2.
System descriptors 3.Local descriptors 4.TSS(task state segment) descriptors 5. Gate descriptors
77. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
78. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
79. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
80. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
81. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
Answer: b
Explanation: The paging divides the memory into fixed size pages.
82. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by segmentation unit, into physical addresses.
83. The control register that stores the 32-bit linear address, at which the previous page fault is detected
is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
84. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
85. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
86. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
87. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
88. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
89. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
90. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) all of the mentioned
Answer: c
Explanation: The D-bit is undefined for page directory entries.
91. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
92. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
93. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
Answer: c
Explanation: The page table cache is also known as translation look aside buffer
The internal RAM memory of the 8051 is:
A. 32 bytes
B. 64 bytes
C. 128 bytes
D.256 bytes
Answer: Option C
2. This program code will be executed continuously:
STAT: MOV A, #01H
JNZ STAT
A.True
B. False
Answer: Option A
3. The 8051 has ________ 16-bit counter/timers.
A. 1
B. 2
C. 3
D.4
Answer: Option B
4. The address space of the 8051 is divided into four distinct areas: internal data, external data,
internal code, and external code.
A.True
B. False
Answer: Option A
5. Data transfer from I/O to external data memory can only be done with the MOVX command.
A.True
B. False
Answer: Option A
6. The 8051 can handle ________ interrupt sources.
A. 3
B. 4
C. 5
D.6
Answer: Option C
Explanation:
There are five interrupt sources for the 8051, which means that they can recognize 5 different events
that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting
bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of
the same register.
7. The special function registers are maintained in the next 128 locations after the general-
purpose data storage and stack.
A.True
B. False
Answer: Option A
8. This statement will set the address of the bit to 1 (8051 Micro-controller):
SETB 01H
A.True
B. False
Answer: Option B
9. MOV A, @ R1 will:
A. copy R1 to the accumulator
B. copy the accumulator to R1
C. copy the contents of memory whose address is in R1 to the accumulator
D.copy the accumulator to the contents of memory whose address is in R1
Answer: Option C
10. A label is used to name a single line of code.
A.True
B.False
Answer: Option A
11. The following program will receive data from port 1, determine whether bit 2 is high, and
then send the number FFH to port 3:
READ: MOV A,P1
ANL A,#2H
CJNE A,#02H,READ
MOV P3,#FFH
A.True
B.False
Answer: Option A
12. Device pins XTAL1 and XTAL2 for the 8051 are used for connections to an external
oscillator or crystal.
A.True
B.False
Answer: Option A
13. When the 8051 is reset and the line is HIGH, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option A
14. An alternate function of port pin P3.4 in the 8051 is:
A. Timer 0
B. Timer 1
C. interrupt 0
D.interrupt 1
Answer: Option A
15. Both registers TL0 and TL1 are needed to start Timer 0.
A.True
B.False
Answer: Option B
16. The I/O ports that are used as address and data for external memory are:
A. ports 1 and 2
B. ports 1 and 3
C. ports 0 and 2
D.ports 0 and 3
Answer: Option C
17. The last 96 locations in the internal data memory are reserved for general-purpose data
storage and stack.
A.True
B.False
Answer: Option B
18. Microcontrollers often have:
A. CPUs
B. RAM
C. ROM
D.all of the above
Answer: Option D
19. The 8051 has ________ parallel I/O ports.
A. 2
B. 3
C. 4
D.5
Answer: Option C
20. The total external data memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
21. Which of the following instructions will load the value 35H into the high byte of timer 0?
A. MOV TH0, #35H
B. MOV TH0, 35H
C. MOV T0, #35H
D.MOV T0, 35H
Answer: Option A
23. The 8-bit address bus allows access to an address range of:
A. 0000 to FFFFH
B. 000 to FFFH
C. 00 to FFH
D.0 to FH
Answer: Option C
24. The contents of the accumulator after this operation
MOV A,#0BH
ANL A,#2CH
will be
A. 11010111
B. 11011010
C. 00001000
D.00101000
Answer: Option C
25. The start-conversion on the ADC0804 is done by using the:
A.
B. CS line
C. INTR line
D.V ref/2 line
Answer: Option A
26. This program code will be executed once:
STAT: MOV A, #01H
JNZ STAT
A.True
B.False
Answer: Option B
27. Which of the following instructions will move the contents of register 3 to the accumulator?
A. MOV 3R, A
B. MOV R3, A
C. MOV A, R3
D.MOV A, 3R
Answer: Option C
28. Which of the following statements will add the accumulator and register 3?
A. ADD @R3, @A
B. ADD @A, R3
C. ADD R3, A
D.ADD A, R3
Answer: Option D
29. Data transfer from I/O to external data memory can only be done with the MOV command.
A.True
B.False
Answer: Option B
30. Which of the following commands will move the number 27H into the accumulator?
A. MOV A, P27
B. MOV A, #27H
C. MOV A, 27H
D.MOV A, @27
Answer: Option B
31. This program code will read data from port 0 and write it to port 2, and it will stop looping
when bit 3 of port 2 is set:
STAT: MOV A, PO
MOV P2,A
JNB P2.3, STAT
A.True
B.False
Answer: Option A
32. Which of the following commands will move the value at port 3 to register 2?
A. MOV P2, R3
B. MOV R3, P2
C. MOV 3P, R2
D.MOV R2, P3
Answer: Option D
33. The number of data registers is:
A. 8
B. 16
C. 32
D.64
Answer: Option C
34. When the 8051 is reset and the EA line is LOW, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option B
35. The designs of a centigrade thermometer and a PWM speed-control circuit can be
implemented by the 8051.
A.True
B.False
Answer: Option A
36. What is the difference between the 8031 and the 8051?
A. The 8031 has no interrupts.
B. The 8031 is ROM-less.
C. The 8051 is ROM-less.
D.The 8051 has 64 bytes more memory.
Answer: Option B
37. The I/O port that does not have a dual-purpose role is:
A. port 0
B. port 1
C. port 2
D.port 3
Answer: Option B
38. To interface external EPROM memory for applications, it is necessary to demultiplex the
address/data lines of the 8051.
A.True
B.False
Answer: Option A
39. The following command will copy the accumulator to the location whose address is 23H:
MOV 23H,A
A.True
B.False
Answer: Option A
40. The special function registers can be referred to by their hex addresses or by their register
names.
A.True
B.False
Answer: Option A
41. The contents of the accumulator after this operation
MOV A,#2BH
ORL A,00H
will be:
A. 1B H
B. 2B H
C. 3B H
D.4B H
Answer: Option B
42. The following program will cause the 8051 to be stuck in a loop:
LOOP: MOV A, #00H
JNZ LOOP
A.True
B.False
Answer: Option B
43. Which of the following commands will copy the contents of RAM whose address is in
register 0 to port 1?
A. MOV @ P1, R0
B. MOV @ R0, P1
C. MOV P1, @ R0
D.MOV P1, R0
Answer: Option C
44. The statement LCALL READ passes control to the line labelled READ.
A.True
B.False
Answer: Option A
45. Which of the following commands will copy the contents of location 4H to the accumulator?
A. MOV A, 04H
B. MOV A, L4
C. MOV L4, A
D.MOV 04H, A
Answer: Option A
46. The microcontroller is useful in systems that have nonvariable programs for dedicated
applications.
A.True
B.False
Answer: Option A
47. The total amount of external code memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
48. The ADC0804 has ________ resolution.
A. 4-bit
B. 8-bit
C. 16-bit
D.32-bit
Answer: Option B
49. A HIGH on which pin resets the 8051 microcontroller?
A. RESET
B. RST
C. PSEN
D.RSET
50. An alternate function of port pin P3.1 in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option B
51. Which of the following instructions will move the contents of the accumulator to register 6?
A. MOV 6R, A
B. MOV R6, A
C. MOV A, 6R
D.MOV A, R6
Answer: Option B
52. The following command will rotate the 8 bits of the accumulator one position to the left:
RL A
A.True
B.False
Answer: Option A
53. An alternate function of port pin P3.0 (RXD) in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option A
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Arithmetic and Logic Instructions”.
1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
View Answer
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator.
Example- ADD A,R0; ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
View Answer
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
View Answer
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of
the register or some immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
View Answer
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
View Answer
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to
1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
View Answer
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is
important and in signed number operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
View Answer
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the
data copy instructions, so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
View Answer
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to
mask the status of the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
View Answer
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not
equal and it resets CY if the destination address is larger then the source address and sets CY if
the destination address is smaller then the source address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the
source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the
source address
d) any register as the destination address and any immediate data as the source address
View Answer
Answer: a
Explanation: These commands have accumulator as the destination address and any register,
memory or any immediate data as the source address.
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Architecture”.
1. 8051 series of microcontrollers are made by which of the following companies?
a) Atmel
b) Philips
c) Atmel & Philips
d) None of the mentioned
View Answer
Answer: d
Explanation: Atmel series AT89C2051 and Philips family P89C51RD2 are the two most
common microcontrollers of 8051 families.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
View Answer
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
View Answer
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) DPTR
b) SP
c) PC
d) PSW
View Answer
Answer: c
Explanation: When a program wakes up, then 0x00 is loaded to the program counter register
because at this place the first op code is burnt.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which
register are affected?
a) PSW
b) SP
c) DPTR
d) PC
View Answer
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow,
parity, register bank select bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
View Answer
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and
AC are set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
View Answer
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2
RS1=1 and RS0=0 which are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
View Answer
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push
of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
View Answer
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
View Answer
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
This set of 8051 Micro-controller Multiple Choice Questions & Answers
(MCQs) focuses on “Jump, Loop and Call Instructions”.
1. DJNZ R0, label is how many bit instructions?
a) 2
b) 3
c) 1
d) Can’t be determined
View Answer
Answer: a
Explanation: DJNZ R0, label has hex code, D8 and its corresponding label address. Hence, it is a
two byte instruction.
2. JZ, JNZ, DJNZ, JC, JNC instructions monitor the bits of which register?
a) DPTR
b) B
c) A
d) PSW
View Answer
Answer: d
Explanation: PSW register consists of flag bits like CY, P, Z etc so it is the one that is directly
being monitored by these instructions.
3. Calculate the jump code for again and here if code starts at 0000H
MOV R1,#0
MOV A,#0
MOV R0,#25H
AGAIN:ADD A,#0ECH
JNC HERE
HERE: INC R1
DJNZ R0,AGAIN
MOV R0,A
END
a) F3,02
b) F9,01
c) E9,01
d) E3,02
View Answer
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next
to the source address.
So here if we start with 0000H
then source address is 0008H and the destination address is 0004H
So loop address is 04-0A=E9
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
View Answer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call
instruction so that when RET is executed then PC is filled with that address and so the pointer
moves to the main program and continue with its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
View Answer
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte
instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
View Answer
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH
instructions the pointer does not move to any location specified by its address which is the
fundamental of CALL instruction, so it is not a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
View Answer
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal
frequency) /12
8. Find the number of times the following loop will be executed
MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a) 100
b) 200
c) 20000
d) 2000
View Answer
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
View Answer
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is
moved to it unlikely of using # used for storing data in any register.
10. Do the two instructions mean the same?
1) BACK: DEC R0
JZ BACK
2) BACK: DJNZ RO, BACK
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
View Answer
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves
back and in the second statement, when the result after decrements is not zero, then it jumps
back.
Unit No.1
Topic:Assembler Directives and ALP Tools
1. __________ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
View Answer
Answer: c
Explanation: An assembler is a software used to convert the programs into machine instructions.
2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
View Answer
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.
3. The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
View Answer
Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.
4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
View Answer
Answer: d
Explanation: The directives help the program in getting compiled and hence won’t be there in the
object code.
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
View Answer
Answer: b
Explanation: This basically is used to replace the variable with a constant value.
6. The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
View Answer
Answer: a
Explanation: This does the function similar to the main statement.
7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
View Answer
Answer: c
Explanation: None.
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
View Answer
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object code
of the program there.
9. _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
View Answer
Answer: b
Explanation: This instruction directive is used to terminate the program execution.
10. The last statement of the source program should be _______
a) Stop
b) Return
c) OP
d) End
View Answer
Answer: d
Explanation: This enables the processor to load some other process.
11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
View Answer
Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the branch
offset and replaces it with it.
12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
View Answer
Answer: b
Explanation: The table where the assembler stores the variable names along with their
corresponding memory locations and values.
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13. The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
View Answer
Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and
waits for further execution.
14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
View Answer
Answer: a
Explanation: The program is used to load the program into memory.
15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
View Answer
Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.
TOPICS: “Programming With An Assembler”.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
View Answer
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
View Answer
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
View Answer
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
View Answer
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
View Answer
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
View Answer
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
View Answer
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
View Answer
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
View Answer
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
View Answer
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.
11. The purpose of the ORIGIN directive is __________
• A. To indicate the starting position in memory, where the program block is to be stored
• B. To indicate the starting of the computation code
• C. To indicate the purpose of the code
• D. To list the locations of all the registers used
Answer: Option A
12. The last statement of the source program should be _______
• A. Stop
• B. Return
• C. OP
• D. End
Answer: Option D
13.DEBUG is able to troubleshoot only
• A. .EXE files
• B. .OBJ files
• C. .EXE file and .OBJ file
• D. .EXE flie and .LST file
Answer: Option A
TOPICS: Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
TOPIC: – Segmentation of 80386
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
View Answer
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
View Answer
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
View Answer
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
View Answer
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
View Answer
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
View Answer
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS(task state segment) descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
View Answer
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
View Answer
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
View Answer
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence
TOPIC:– Architecture and Signal Descriptions of 80386
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
View Answer
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
View Answer
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
View Answer
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
View Answer
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
View Answer
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
View Answer
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
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13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
View Answer
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
View Answer
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
View Answer
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
View Answer
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
View Answer
Answer: c
Explanation: The pip
TOPICS– Register Organisation of 80386 -1
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers
with a prefix of
a) X
b) E
c) 32
d) XX
View Answer
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register name with a
prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
View Answer
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
View Answer
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
View Answer
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
View Answer
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
View Answer
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
View Answer
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of se
TOPIC: – Register Organisation of 80386 -2
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
View Answer
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
View Answer
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register(s) that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
View Answer
Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and test
status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
View Answer
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
View Answer
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
View Answer
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
View Answer
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
View Answer
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers,
rather, they are internally used to store the descriptor information
TOPIC: Addressing Modes of 80386, Data Types of 80386
1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register to
get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
View Answer
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is added to a
base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
View Answer
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
View Answer
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
View Answer
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d) Offset
View Answer
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing mod
TOPIC– Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer.A
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task
Topic: – Paging
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
View Answer
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
View Answer
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by the segmentation unit, into physical addresses.
4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
View Answer
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
View Answer
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
View Answer
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
View Answer
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
10. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
View Answer
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
View Answer
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
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13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
View Answer
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
View Answer
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
MCQS on the INstruction
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
2. If the processor is executing a main program that calls a subroutine, then after executing the
main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) none
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
11. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
12. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) all of the mentioned
13. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
14. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
15. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
16. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
17. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
18. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
19. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
20. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
21. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
22. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
23. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
24. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
25. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
26. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
27. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
28. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
29. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
30. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answers
1-c 2-b 3-d 4-c 5-d
6-b 7-c 8-d 9-d 10-d
11-d 12-d 13-a 14-b 15-c
16-b 17-d 18-a 19-b 20-c
21-d 22-b 23-d 24-c 25-b
26-d 27-d 28-b 29-c 30-a
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC
to ____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller Watchdog
are ______ Timers ADC All of these D
5 Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access
data RAM in PIC 18 microcontroller. 4 8 12 16 C
9
___ address lines are used to access
program ROM in PIC 18 microcontroller. 18 19 20 21 D
10
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller
is ___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller
is ___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is 128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : deep sleep,
sleep, deep idle, deep
sleep, idle deep power A
sleep sleep
20 down
WDT stands for _______ Watch Watch Dog Width Delay Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master
Master Master
Synchronou Master Slave
Synchronou Synchronous C
s Serial Serial Port
s slave Port Serial Port
25 Peripheral
Flag 'N' in Status register of PIC18F452 d Negative
Zero Flag Overflow Flag Carry Flag B
26 Flag
How many banks are available in PIC 18F
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result Results saved Ressult
ADDWF F D a Undefined D
saved in F in F and W Saaved in W
28
BOD' stands for Brown OR Brown out
Brown out Board on Reset
Reset Reset B
Reset Debug Detection
29 Detection Detection
Circuit used for initialization of all values t Power-On Brown Out Power ON/
Reset Detection WDT circuit A
OFF circuit
30 Circuit Circuit
In Immediate (Literal) addressing mode
The operand is _____ that follows the a register a number a pointer an address B
31 opcode
PIC18F452 has power down modes as __ deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated
in____ oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in
OSCCONFI
PIC18F4550 is controlled through two CONFIG2 CONFIG1L
G1 and None of the
Configuration registers as _______ and and C
OSCCONFI above
CONFIG2 CONFIG1H
G2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral
Univeral Serial
Synchrnous Synchrnous Synchrnous
Asynchronous
Asynchrono Asymmatric Asynchronous C
Receive
us Register Receive Receive
Transmit
36 Transmit Transmit Transmit
CONFIG2L is used for Frequency Background Watch dog
Reset voltage D
Selection debugger timer
37
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontrol
Resets all the
for ler in Set all registers B
registers
peripherals standby
38 OFF mode
Where is the result stored after an
execution of increment and decrement Working None of the
File Register Both a & b C
operations over the special - purpose Register above
39 registers in PIC?
Which status bits exhibit carry from
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sheet1
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
Page 1
Sheet1
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
Page 2
Sheet1
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Page 3
Sheet1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
Page 1
Sheet1
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Page 2
Sheet1
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of TMRxON Tx8BIT TxCS TxSE C
Which of the following is not a Port SFR?
Timer0. PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is output input bidirectional None of B
____ reset content of TRISB register is
Upon 0000 0000 000 000 1111 1111 these
111 111 C
_______
Which of the following instruction is used to BSF BCG BTG BMF A
set a file
Which of register bit? instruction is used to
the following BSF BCG BTG BMF B
clear a file register
Which of the following bit?instruction is used to BSF BCG BTG BMF C
toggle a file register bit?
Page 3
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
By which of the following method(s)
devices receive service from the Interrupts Polling Both of these None of these C
microcontroller?
Asynchronous request for service by
peripherals to processor is known as Interrupt Polling Both of these None of these A
____
Which of the following can cause Serial data Serial data
Timer overflow All of these D
interrupt generation? reception transmission
In which of the following method(s)
priority can be assigned to the devices Interrupts Polling Both of these None of these A
demanding for service?
In which of the following method(s)
microcontroller can not ignore a device Interrupts Polling Both of these None of these B
request for service?
Which of the following method(s) waste
Interrupts Polling Both of these None of these B
microcontroller’s time
Input Interrupt Interrupt
Input Service
Full form of ISR is_______ Synchronous Synchronous Service D
Routine
Routine Routine Routine
Interrupt
Input Vector Inerrupt Input Vector
Full form of IVT is_______ Vector B
Table Vector Table Testbench
Testbench
Power on Reset Vector in PIC 18 is
0000 0008 0018 0028 A
_____h
High Priority Interrupt Vector in PIC 18 is
0000 0008 0018 0028 B
_____h
Low Priority Interrupt Vector vector in
0000 0008 0018 0028 C
PIC 18 is _____h
Fixed locations in memory that holds
IGT IMT IRT IVT D
addresses of ISRs are called as ____
Correct sequence of steps in executing an
interrupt is ______ Where 1=Execute ISR,
1-2-3-4 3-2-1-4 4-3-2-1 3-2-4-1 D
2= Consult IVT, 3=Save PC on stack and
4=Jump to ISR
While servicing an interrupt content of
PC MAR MBR IR A
____ register are saved on the stack
What is the status of interrupts in PIC 18 All are Some are
All are enabled None of these B
after power on or reset? disabled enabled
____ bit is used for enabling/disabling of
FIE GIE HIE JIE B
all interrupts
Global Interrupt Enable (GIE) bit is
INTCON RCON PIR PIE A
present in ______ register
Interrupt Priority Enable (IPEN) bit is
INTCON RCON PIR PIE B
present in ______ register
Peripheral Interrupt Enable (PEIE) bit is
INTCON RCON PIR PIE A
present in ______ register
To enable serial communication
interrupts which of the following bit(s) Only GIE Only PEIE Both of these None of these B
must be set?
To enable timer 0 interrupt which of the
Only GIE Only PEIE Both of these None of these A
following bit(s) must be set?
There are ___ registers to control
11 12 13 14 C
interrupt operation in PIC 18
In PIC18F, any interrupt source is enabled
0 1 X None of these D
when corresponding IE bit is ____.
Which of the following bit(s) control
operation of an interrupt source in PIC18 Flag bit Enable bit Priority bit All of these D
F?
The default ISR address in PIC18F is
0000 0008 0018 0028 B
_____ h
Which of the following bit(s) indicate that
Flag bit Enable bit Priority bit All of these A
an interrupt event has occurred?
Which of the following bit(s) is used to
Flag bit Enable bit Priority bit All of these C
assign priority to an interrupt?
Setting of ___ and ____ bit allows
Enable,
program execution to branch to the Flag, Enable Flag, Priority All of these A
Priority
interrupt vector address.
If the interrupt is one of the peripheral
(timers 1,2 , serial, etc. ) we need to set
TMR0IE INT0IE PEIE RBIE C
____ bit from INTCON register along with
GIE bit.
Which of the following interrupt has no
INT3 INT2 INT1 INT0 D
priority bit?
_____ interrupt has default high priority. INT0 INT1 INT2 All of these D
For any interrupt source, to assign high
priority the corresponding IP bit must be 0 1 X None of these B
____.
For any interrupt source, to assign low
priority the corresponding IP bit must be 0 1 X None of these A
____.
Which of the following is not a core Serial
TMR0 INT0 INT1 D
interrupt source? Transmit
Which of the following is not a peripheral
TMR3 TMR2 TMR1 TMR0 D
interrupt source?
Which of the following is not a peripheral Serial
TMR1 INT0 TMR2 B
interrupt source? Transmit
Upon power-on reset the external
Positive edge Negative edge Positive level Negative level
hardware interrupts INT0-INT2 are of A
triggered triggered triggered triggered
type _____.
Which of the following avoids tying down
Interrupts Polling Both of these None of these A
the microcontroller?
PIC 18 ha ____ external hardware
1 2 3 4 C
interrupts.
External hardware interrupts of PIC18F
E D C B D
are multiplexed with port ____ lines.
PORTB-change interrupt is assocaied with
4 3 2 1 A
_____ lines of PORTB.
PORTB-change interrupt is assocaied with
RB0-RB3 RB2-RB5 RB3-RB6 RB4-RB7 D
_____ lines of PORTB.
Register Select pin of LCD selects_____
Status Command Data Program B
register when it is 0.
Register Select pin of LCD selects_____
Status Command Data Program C
register when it is 1.
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these B
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit IV MCQs
Q.1 How does the pin RC2/CCP1 get configured while initializing the CCP module in the
compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans:d
Q.2 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans:a
Q.3 The capture operation in counter mode is feasible when mode of CCP module is
__ _ __
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
Ans:a
Q.4 Which register is suitable for the corresponding count, if the measurement of pul se
width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
Ans:c
Q.5 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR Ans:a
Q.6 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.7 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.8 Which among the below mentioned aspect issues are supported by
capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
Ans:d
Q.9 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.10 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.11 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
Ans:a
Q.12 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans: a
Q.13 How does the pin RC2/CCP1 get configured while initializing the CCP module in
the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans: b
Q.14 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0
Ans: a
Q.15 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
Ans: b
Q.16 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.17 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value
Ans: b
Q.18 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter ?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components
Ans: a
Q.19 In ____ _ data transfer, group of bits (usually 8 bits) of data is transferred at a
time.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.20 In ____ _ data transfer, only one bit of data is transferred at a time.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.21 In Parallel data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: a
Q.22 In Serial data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: b
Q.23 Most of the Microprocessor/Microcontrollers are designed for______ communication.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.24 In _____ data communication, during transmission parallel data is converted into
serial bits using a PISO shift register.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.25 At the receiver, the serial bits are connected into parallel data by another shift
register called SIPO register.
a. TRUE b. FALSE Ans: a
Q.26 In ____ __, the hardware exists such that data transfer takes place only in one
direction.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.27 The transmission form a computer to the printer is an example of ____ _ _
communication.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.28 The ______ transmission allows the data transfer in both directions, but not
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.29 Walkie-talkie is an example of ________ _.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.30 The ______ transmission allows the data transfer in both directions
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q. 31 Telephone lines is an example of ____ _ .
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q.32 Types of serial data communication:
a. Asynchronous serial data communication
b. Synchronous serial data communication
a. TRUE b. FALSE Ans: a
Q.33 The serial communication is
a. cheaper communication
b. requires less number of conductors
c. slow process of communication
d. all of the mentioned Ans: d
Q.34 The serial communication is used for
a. short distance communication
b. long distance communication
c. short and long distance communication
d. communication for a certain range of distance Ans: b
Q.35 The number of bits transmitted or received per second is defined as
a. transmission rate
b. reception rate
c. transceiver rate
d. baud rate Ans: d
Q.36 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.37 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.38 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0 Ans: a
Q.39 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above Ans: b
Q.40 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.41 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value Ans: b
Q.42 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components Ans: a
Q.43 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.44 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.45 What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave
mode by enabling SS pin control?
a. 0000 b. 0100 c. 0010 d. 0001 Ans: b
Q.46 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above Ans: a
Q.47 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.48 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above Ans: b
Q.49 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c. 16 d. 32 Ans: a
Q.50 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above Ans: a
Q.51 What is the purpose of a special function register SPBRG in USART?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above Ans: a
Q.52 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the
data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.53 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode?
a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1) Ans: b
Q.54 What is the status of shift clock supply in an USART synchronous mode?
a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally Ans: a
Q.55 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.56 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as
DT (data lines)?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.57 Which among the below assertions represent the salient features of PIC in C-18
compiler?
a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above Ans: d
Q.58 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above Ans: d
Q.59 Which flags of status register are most likely to get affected by the single-cycle
increment and decrement instructions?
a. P Flags b. C Flags c. OV Flags d. Z Flags Ans: d
Q.60 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.61 In ____ _ _ communication, transmitters and receivers are not synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: a
Q.62 In ____ _ _ communication, transmitters and receivers are synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: c
Q.63 In Asynchronous Serial communication, bits of data are transmitted at constant
rate.
a. TRUE b. FALSE Ans: a
Q.64 In Synchronous Serial communication, bits of data are transmitted with
synchronization of clock.
a. TRUE b. FALSE Ans: a
Q.65 In Asynchronous Serial communication, character may arrive at any rate at
receiver.
a. TRUE b. FALSE Ans: a
Q.66 In Synchronous Serial communication, is received at constant rate.
a. TRUE b. FALSE Ans: a
Q.67 In Asynchronous Serial communication, data transfer is character oriented.
a. TRUE b. FALSE Ans: a
Q.68 In Synchronous Serial communication, data transfer takes place in blocks.
a. TRUE b. FALSE Ans: a
Q.69 Baud Rate is data transmission speed.
a. TRUE b. FALSE Ans: a
Q.70 The rate at which the bits are transmitted (bits/second) is called ____ _.
a. speed b. bit rate c. baud d. sample Ans: c
Q.71 The common baud rates are multiplies of _____ bits/second.
a. 25 b. 50 c. 75 d. 100 Ans: c
Q.72 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.73 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.74 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD b. SSPBUF c. Both a & b d. None of the above Ans: a
Q.75 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.76 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line b. SDA line c. Both a & b d. None of the above Ans: b
Q.77 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c.16 d.32 Ans: a
Q.78 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA b. RCSTA c. SPBRG d. All of the above Ans: a
Q.79 What is the purpose of a special function register SPBRG in USART ?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bitr
d. All of the above Ans: a
Q.80 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all
the data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.81 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode ?
a. FOSC / 8 (X +1 )
b. FOSC / 16 (X +1 )
c. FOSC / 32 (X +1 )
d. FOSC / 64 (X +1 ) Ans: b
Q.82 What is the status of shift clock supply in an USART synchronous mode?
a. Master - internally, Slave - externally
b. Master - externally, Slave - internally
c. Master & Slave (both) - internally
d. Master & Slave (both)- externally Ans: a
Q.83 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode ?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.84 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins
as DT (data lines) ?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.85 Two wire interfaces is also called as _____ __
a. UART b. SPI c. I2C d. USART Ans: c
Q.86 I2c will address large number of slave devices.
a. True b. False Ans: a
Q.87 SDA is having a transition when the clock line SCL is high.
a. high to low b. low to high c. low to low d. high to high Ans: a
Q.88 Inter Integrated Circuit is a
a. Single master, single slave
b. Multi master, single slave
c. Single master, multi slave
d. Multi master, multi slave Ans: d
Q.89 Typical voltages used are _
a. 5v b. 3.3v c. 5v or 3.3v d. 2.5v Ans: c
Q.90 What is the speed of I2C bus?
a. 100 kbits/s b. 10 kbits/s c.75 kbits/s d.100 kbits/s and 10 kbits/s Ans: d
Q.91 Master transmits means
a. Master node is sending data to a slave
b. Master node is receiving data from slave
c. Slave node is transmitting data to master
d. Slave node is sending data to master Ans: a
Q.92 Who sends the start bit?
a. Master receive
b. Master transmit
c. Slave transmit
d. Slave receive Ans: b
Q.93 Which is the I2C messaging example?
a. 24c32 EPROM
b. 24c32 EEPROM
c. 24c33 EEPROM
d. 24c33 EPROM Ans: b
Q.94 Are pull up registers required in I2C?
a. True b. False Ans: a
Q.95 How many types of addressing structures are there in I2C?
a. 4 types b. 3 types c. 2 types d. 5 types Ans: c
Q.96 All operating modes work under
a. 11 kbit/s b. 100 kbit/s c. 15 kbit/s d. 150 kbit/s Ans: b
Q.97 Which mode is highly compatible and simply tightens?
a. Fast mode
b. High speed mode
c. Ultra fast mode
d. Both fast and high speed mode Ans: a
Q.98 What is the speed for fast mode?
a. 100 kbit/s b. 400 kbit/s c. 150 kbit/s d. 200 kbit/s Ans: b
Q.99 Which of the following is a synchronous serial interface protocol?
a. SPI b. I2C c. UART d. Both (a) and (b) Ans: d
Q.100 Synchronous interfaces make use of clock signal? State True or False
a. True b. False Ans: a
Q.101 Which of the following serial protocol is used for on-board serial communication?
a. USB b. I2C c. Wifi d. Bluetooth Ans: b
Q.102 Which of the following protocol make use of 7 bit address for its operation?
a. I2C b. SPI c. RS232 d. RS485 Ans: a
Q.103 Which of the following interface is used to 127 slave device to the master device?
a. SPI b. I2C c. RS232 d. RS485 Ans: b
Q.104 RS232 protocol makes use of clock signal for sending data? True or False
a. True b. False Ans: b
Q.105 Which serial communication interface is used to connect modems and for non
networked communication between computers and other devices?
a. SPI b. I2C c. UART d. USB Ans: c
Q.106 How many wires are used to connect I2C devices?
a. 1 wire b. 2 wires c. 3 wires d. 4 wires Ans: b
Q.107 Which of the following interface was developed by Motorola Company?
a. I2C b. SPI c. USB d. Bluetooth Ans: b
Q.108 Which of the following make use of 4 wires for its operation?
a. USB b. CAN c. SPI d. I2C Ans: c
Q.109 Which of the following is a full duplex communication interface?
a. I2C b. 1 – Wire c. SPI d. 2- Wire Ans: c
Q.110 Which of the following is true about MOSI signal?
a. Signal Line carrying the clock signal
b. Signal line for slave select
c. Signal line carrying the data from master to slave device
d. Signal line carrying the data from slave to master device Ans: c
Q.111 Which of the following supports only point to point communication and not
suitable for multi drop communication
a. RS485 b. RS232 c. RS422 d. Rs484 Ans: b
Q.112 Which of the following is a low cost, low power, short range wireless
communication for voice and data
a. Wi-Fi b. Infrared c. Zigbee d. Bluetooth Ans: d
Q.113 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.114 Which bits exhibit and signify the termination phase of the character
transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above Ans: b
Q.115 Two wire interfaces is also called as
a. UART b. SPI c. I2C d. USART Ans: c
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit I MCQs
Q.1 A computer accepts data from the user processes the data according to the
instructions given and produces the desired output result.
A. True B. False Ans: True
Q.2 RAM stands for
A. Rigid Access memory B. Register Accumulator Memory
C. Random Access Memory D. None of the above Ans:C
Q.3 A single IC which consists of ALU, control section and Register section is called
as
A.Microprocessor B. Microcontroller
C.Minicomputer D. None of the above Ans:A
Q.4 What is the name of the system which carries only the control and timing
signals
A. Address Bus B. Data Bus C. Control Bus D. System Bus Ans:C
Q.5 The various ways of specifying the data is called .
A. Instruction B. Assembler Directive C. Addressing Mode Ans:C
Q.6 Interpreter translates language into machine level language and the
translation is done line by line.
A. Low B. High Ans:B
Q.7 Complier translates high-level language into .
A. Machine level language B. Assembly Level Language
C. C Language D. Low Level Language Ans:A
Q.8 enables the programmers to run the program step by step so that the
programmer can find out the exact location of the error.
A. Assembler B. Linker C. Loader D. Debugger Ans:D
Q.9 Memory addressing mode can be divide into groups.
A. 1 B. 2 C. 3 D. 4 Ans:B
Q. 10 CALL instruction transfers the control of execution of the program to the
subroutine or procedure
A. True B. False Ans:A
Q.11 A macro is unlike a in that the machine instructions are repeated each
time the macro is referenced.
A. Procedure B. Call C. Return D. Assembler Ans:A
Q.12 The meaning of ‘interrupts’ is to break the sequence of operation.
A. True B. False Ans:A
Q.13 The process of interrupting the normal program execution to carry out a specific
task/work is referred to as .
A. Interrupt B. ISR C. Macro D. Procedure Ans:A
Q.14 Register that is used to hold the memory address of the next instruction to be
executed is
A. Program Memory B. Program Counter
C. Control Unit D. Instruction Decoder Ans:B
Q.15 Which register is used to store the output generated by ALU?
A. SFR B. GPR C. Accumulator (W) D. SP Ans:C
Q.16 The has built-in ROM,RAM, Parallel I/O, Serial I/O, counters and
clock circuit.
A. Microcontroller B. Microprocessor
C. Mainframe computers D. none of the above Ans: A
Q.17 PIC uses architecture.
A. Von Neumann B. Harvard Ans: B
Q.18 The PIC can control up to independent interrupt sources.
A. 6 B. 8 C. 10 D. 12 Ans: D
Q.19 The instruction set of PIC consists of instructions.
A. 66 B. 77 C. 88 D. 99 Ans:B
Q.20 In PIC memory sizes from 8 to 128 KB.
A. ROM B. Flash Program C. RAM Ans:B
Q.21 The PIC is High performance processor.
A. RISC B. CISC Ans: A
Q.22 The PIC has bit ADC.
A. 8 B. 9 C. 10 D. 12 Ans: C
Q.23 The PIC has CCP Modules
A. 4 B. 5 C. 6 D. 7 Ans: B
Q.24 Out of 40 Pins, 33 pins are dedicated to Ports of PIC.
A.4 B. 5 C. 6 D. 7 Ans: B
Q.25 RESET pin is in the PIC.
A. WR’ B. OSC C. MCLR’ D. ECCP Ans: C
Q.26 used for control and status of the controller and peripheral functions.
A. SFRs B. GPRs C. WREG D. FSRs Ans: A
Q.27 used for data storage and scratchpad operations in the user’s
application.
A. SFRs B. GPRs C. WREG D. FSRs Ans: B
Q.28 acts as an Accumulator.
A. SFRs B. GPRs C. WREG D. FSRs Ans: C
Q.29 register that stores flags- indicates the status of the operation done
by ALU.
A. Status B. SFR C.GPR D. FSR Ans:A
Q.30 is a 4 bit register used in Direct addressing the data memory.
A. Status B. SFR C.GPR D. BSR Ans:D
Q.31 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.32 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.33 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.34 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.35 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.36 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.37 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.38 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C.Over Flow D. Zero Ans:D
Q.39 Flag is set whenever the result of signed number operation is too large,
causing the high order bit to over flow in to sign bit.
A. Carry B. Negative C.Over Flow D. Zero Ans:C
Q. 40 After execution of ALU operations, if bit 7 of the result is 1, the flag is set
indicating result is negative.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:D
Q. 41 In PIC, the data memory is implemented as static RAM. It is also known as _
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q. 42 When using addressing, the BSR is used to select the desired bank.
A. Direct B. Indirect C. Implied D. Immediate Ans: A
Q. 43 Indirect addressing requires use of .
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q.44 Each FSR holds a bit address value that can be used to access any location
in the data memory map without banking.
A. 10 B. 11 C. 12 D. 13 Ans: C
Q.45 Upon reset BSR= H.
A. 001B B. 0000 C. 0FFF D. FFFF Ans:B
Q.46 Immediate data is also called Literal in PIC18.
A. True B. False Ans:A
Q.47 In addressing mode, the letter ‘F’ in the instruction means the address of
the File Register location.
A. Direct B. Indirect C. Immediate D. Register Ans:D
Q.48 The ECIO oscillator mode functions like the EC mode, except that the
OSC2 pin becomes an additional general purpose I/O pin.
A. True B. False Ans:A
Q.49 The PLL can only be enabled when the oscillator configuration bits are
programmed for HS mode.
A. True B. False Ans:A
Q.50 In the Sleep mode, the on-chip clocks and oscillator are turned off.
A. True B. False Ans:A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit II MCQs
Q.1 When does it become possible for a bit to get accessed from bank '0' in the direct
addressing mode of PICs?
A. Only when RPO bit is set 'zero'
B. Only when RPO bit is set '1'
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.2 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to
turn on the weak internal pull-ups of port B?
A. RPO’ B. RPBU’ C. RBIF D. All of the above Ans:B
Q.3 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of 'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.4 Which digital operations are performed over the detected mismatch outputs with
an intention to generate a single output RB port change output?
A. OR B. AND C. EXOR D. NAND Ans: A
Q.5 How many clock pulses are confined by each machine cycle of Peripheral-Interface
Controllers?
A. 4 B. 8 C.12 D. 16 Ans:A
Q.6 Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
A. Carry (C) Flags B. Zero (Z) Flags
C. Digit Carry (DC) Flags D. All of the above Ans:D
Q.7 What is the execution speed of instructions in PIC especially while operating at the
maximum value of clock rate?
A. 0.1 μs B. 0.2 μs C. 0.4 μs D. 0.8 μs Ans: B
Q.8 Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?
A. Built-in Power-on-reset B. Brown-out reset
C. Both a & b D. None of the above Ans:B
Q.9 Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
A. Improvement in bandwidth
B. Instruction fetching becomes possible over a single instruction cycle
C. Independent bus access provision to data memory even while accessing the
program memory
D. All of the above Ans:D
Q.10 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C
B. C&D
C. A, B & D
D. A, B & C Ans:D
Q.11 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT)
B. Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT)
D. All of the above Ans:C
Q. 12 Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
A. Status Register
B. Program Counter Latch (PCLATH) Register
C. Program Counter Low Byte (PCL) Register
D. File Selection Register (FSR) Ans: B
Q.13 Which register/s is/are mandatory to get loaded at the beginning before loading or
transferring the contents to corresponding destination registers?
A. W B. INDF C. PCL D. All of the above Ans: A
Q.14 How many RPO status bits are required for the selection of two register banks?
A. 1 B.2 C. 8 D. 16 Ans: A
Q.15 The RPO status register bit has the potential to determine the effective address
of
A. Direct Addressing Mode
B. Indirect Addressing Mode
C. Immediate Addressing Mode
D. Indc. Watchdog Timer (WDT) exed Addressing Mode Ans:A
Q.16 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B. Digits Carry bit (DC)
C. Both A & B D. None of the above Ans:B
Q.17 Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
A. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
B. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
C. Address byte must be written in FSR at the same time during the execution of
INDF instruction in indirect addressing mode
D. Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode
A. Only A B. Only B C. Only A & B D. A & D Ans:A
Q.18 Which among the below stated registers specify the address reachability within 7
bits of address independent of RP0 status bit register?
A. PCL B. FSR C. INTCON D. All of the above Ans:D
Q.19 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th Bit B. 12th Bit C. 13th Bit D. 14th Bit Ans:C
Q.20 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B. Low C. Moderate D. All of the above Ans:B
Q.21 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor Ans:A
Q.22 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 Cycles B. 1024 Cycles C. 2048 Cycles D.4096 Cycles Ans:B
Q.23 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode
B. Sleep mode
C. Power-down mode
D. Any flexible mode Ans:B
Q.24 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A. For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.25 Which program location is allocated to the program counter by the reset function
in Power-on-Reset (POR) action modes?
A. Initial address
B. Middle address
C. Final address
D. At any address reliable for reset operations Ans:A
Q.26 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans:B
Q. 27 Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
A. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
A. A & B B. C & D C. A & C D. B & D Ans:B
Q.28 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.29 What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
A. (1/2) x frequency of OSC1
B. (1/4) x frequency of OSC1
C. (1/8) x frequency of OSC1
D. (1/16) x frequency of OSC1 Ans:C
Q.30 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC
B. LP (Low-Power Clocking)
C. XT
D. HS (High Speed) Ans:B
Q.31 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy
B. Proficiency in time generation
C. Applicability in real-time operations
D. All of the above Ans:A
Q.32 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ ceramic/ resonator or any other external clock source?
A.0-4 MHz B. 5-200 KHz C.100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.33 How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
A. 4 & 8 bits B. 8 & 16 bits C. 11 & 12 bits D. 12 & 16 bits Ans:C
Q.34 When do the special address 004H get automatically loaded into the program
counter?
A. After the execution of RESET action in program counter
B. After the execution of ‘goto Mainline ‘ instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.35 How many bits are utilized by the instruction of direct addressing mode in order to
address the register files in PIC?
A. 2 B.5 C.7 D.8 Ans:C
Q.36 Which registers are adopted by CPU and peripheral modules so as to control and
handle the operation of device inhibited in RFS?
A. General Purpose Register
B. Special Purpose Register
C. Special Function Register
D. All of the above Ans:C
Q.37 Which among the below specified registors are addressable only from bank1 of
RFS?
A. PORTA (05H)
B. PORTB (06H)
C. FSR (04H)
D. ADCON0 (07H) Ans:A
Q.38 Which register acts as an input-output control as well as data direction register for
PORTA in bank 2 of RFS?
A. INDF (80H) B. TRISB (85H) C. TRISA (85H) D. PCLATH (8A) Ans:C
Q.39 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1
B. Only Bank 2
C. Either Bank 1 or Bank 2
D. Neither Bank 1 nor Bank 2 Ans:C
Q.40 Which bit of OPTION register has a potential to decide the falling or rising edge
sensitivity for the external interrupt INT?
A. RBPU B.INTEDG C.PSA D.RTS Ans:B
Q.41 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC
B. Only Watchdog timer
C. Either RTCC or Watchdog timer
D. Neither RTCC nor Watchdog timer Ans:C
Q.42 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C.ADRES D.PCLATH Ans:B
Q.43 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B.ADIE C.RBIE D.TOIE Ans:A
Q.44 When does it become possible for a bit to get accessed from bank ‘0’ in the direct
addressing mode of PICs?
A. Only when RPO bit is set ‘zero’
B. Only when RPO bit is set ‘1’
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.45 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of ‘interrupt on change’?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.46 What is the purpose of acquiring two different bits from INTCON register for
performing any interrupt operation in PIC 16C61 / 71?
A. One for enabling & one for disabling the interrupt
B. One for enabling the interrupt & one for its occurrence detection
C. One for setting or clearing the RBIE bit
D. None of the above Ans:B
Q.47 What kind of external edge-sensitive interrupt is generated due to transition effect
at pin RBO/INT?
A. INT
B. RBO
C. INTF
D. All of the above Ans:A
Q.48 Consider the following statements. Which of them is /are incorrect?
A. By enabling INTE bit of an external interrupt can wake up the processor before
entering into sleep mode.
B. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
C. During the occurrence of interrupt, GIE bit is set in order to prevent any further
interrupts.
D. goto instruction written in program memory cannot direct the program control to
ISR.
A. A & B
B. C & D
C. Only A
D. Only C Ans:B
Q.49 What is the purpose of setting TOIE bit in INTCON along with GIE bit?
A. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow
interrupt
B. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow
interrupt
C. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
D. None of the above Ans:A
Q.50 Which command enables the PIC to enter into the power down mode during the
operation of watchdog timer (WDT)?
A. SLEEP B. RESET C. STATUS D. CLR Ans:A
Q.51 How much delay is required to sunchronize the externalclock at TOCKI in Timer 0
of Pic16FXXX?
A. 2 cycles B. 4cycles C. 6cycles D. 8cycles Ans:A
Q.52 How much time is required for conversion per channel if PIC possesses four analog
channels, each comprising of 8 bits?
A. 10 µs B.15 µs C.20 µs D. 25µs Ans: C
Q.53 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT) B.Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT) D.All of the above
Ans:C
Q.54 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B.Digits Carry bit (DC)
C. Both a & b D.None of the above Ans:B
Q.55 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th bit B.12th bit C.13th bit D.14th bit Ans:C
Q.56 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B.Low C. Moderate D. All of the above Ans:B
Q.57 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor
Ans:A
Q.58 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode B.Sleep mode C.Power-down mode D.Any flexible mode Ans:B
Q.59 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 cycles B.1024 cycles C.2048 cycles D. 4096 cycles Ans:B
Q.60 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A.For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.61 Which program location is allocated to the program counter by the reset function
in Power-onReset (POR) action modes?
A. Initial address B.Middle address
C.Final address D.At any address reliable for reset operations Ans: A
Q.62 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans: B
Q.63 What output is generated by OSC2 pin in PIC oscillator comprising RC components
for sychronizing the peripherals with PIC microcontroller?
A.(1/2) x frequency of OSC1
B.(1/4) x frequency of OSC1
C.(1/8) x frequency of OSC1
D.(1/16) x frequency of OSC1 Ans: C
Q.64 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans: A
Q.65 What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
A.CPU resets PIC once again in BOR mode
B.BOR reset mode gets disabled
C.PIC does not remain in BOR mode until the voltage increases irrespective of
stability
D.Power-up timer kills 72ms more again
Ans: A
Q.66 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC B.LP (Low-Power Clocking) C. XT D. HS (High Speed) Ans: B
Q.67 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy B.Proficiency in time generation
C. Applicability in real-time operations D.All of the above Ans:D
Q.68 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ceramic/ resonator or any other external clock source?
A. 0-4 MHz B. 5-200 KHz C. 100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.69 Which bits play a crucial role in specifying the details or reasons associated with
the system wake-up in WDT?
A. PD’ & TO’ B. C & Z C. DC & RPO D. All of the above Ans:A
Q.70 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B. ADIE C. RBIE D. TOIE Ans: A
Q.71 Which instruction is applicable to set any bit while performing bitwise operation
settings?
A. bcf B. bsf C. Both A & B D. None of the above Ans:B
Q.72 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
A. Provision of MPLAB specific extensions
B. Floating-point Format Support
C. Data in Program Memory
D. All of the above Ans:D
Q.73 What does the 'program idata' section of data memory contain in C-18 Compiler?
A. statically assigned/allocated initialized user variables
B. statically assigned /allocated uninitialized user variables
C. only executable instructions
D. variables as well as constants Ans:A
Q.74 Where is the result stored after an execution of increment and decrement operations over
the special - purpose registers in PIC?
A. File Register B. Working Register C. Both A & B D. None of the above Ans:C
Q.75 Which flags of status register are most likely to get affected by the single-cycle increment
and decrement instructions?
A. P Flags B. C Flags C. OV Flags D. Z Flags Ans:D
Q.76 Which command-line option of compiler exhibits the banner comprising overall number of
errors, messages, warnings and version number after an accomplishment of the
compilation process?
A. help B. verbose C. overlay D. char Ans:B
Q.77 Which among the below assertions represent the salient features of PIC in C-18 compiler?
A. Transparent read/ write access to an external memory
B. Provision of supporting an inline assembly during the necessity of an overall control
C. Integration with MPLAB IDE for source-level debugging
D. All of the above Ans:D
Q.78 Which bit plays a salient role in defining the master or slave mode in TXSTA register
especially in synchronous mode?
A. RSRC B. CSRC C. SPEN D. SYNC Ans:B
Q.79 What is the status of shift clock supply in an USART synchronous mode?
A. Master-internally, Slave-externally
B. Master-externally, Slave-internally
C. Master & Slave (both) - internally
D. Master & Slave (both) – externally Ans:A
Q.80 When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of
'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.81 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn
on the weak internal pull-ups of port B?
A.RPO B.RPBU’ C. RBIF D.All of the above Ans:B
Q.82 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C. ADRES D.PCLATH Ans:B
Q.83 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC B. Only Watchdog timer
C. Either RTCC or Watchdog timer D. Neither RTCC nor Watchdog timer Ans:C
Q.84 Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity
for the external interrupt INT?
A. RBPU B. INTEDG C. PSA D. RTS Ans:B
Q.85 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1 B. Only Bank 2
C. Either Bank 1 or Bank 2 D. Neither Bank 1 nor Bank 2 Ans:C
Q.86 Which register acts as an input-output control as well as data direction register for PORTA
in bank 2 of RFS?
A. INDF B. TRISB C.TRISA D.PCLATH Ans:C
Q.87 Which registers are adopted by CPU and peripheral modules so as to control and handle
the operation of device inhibited in RFS?
A. General Purpose Register B. Special Purpose Register
C. Special Function Registers D. All of the above Ans:C
Q.88 How many bits are utilized by the instruction of direct addressing mode in order to address
the register files in PIC?
A. 2 B. 5 C. 7 D. 8 Ans:C
Q.89 When do the special address 004H get automatically loaded into the program counter?
A. After the execution of RESET action in program counter
B. After the execution of 'goto Mainline ' instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.90 Which significant feature/s of crystal source contribute/s to its maximum predilection and
utility as compared to other clock sources?
A. High accuracy B. Proficiency in time generation
C. Applicability in real-time operations D. All of the above Ans:D
Q.91 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely
unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.92 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C B. C & D C. A, B & D D. A, B & C Ans:D
Q.93 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.94 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.95 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.96 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.97 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.98 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.99 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.100 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C. Over Flow D. Zero Ans:D
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator
on OSC1 and OSC2 pins is divided by 1 2 3 4 D
_____ and fed to timer.
Which of the following timers have both 8
Timer 0 Timer 1 Timer 2 Timer 3 A
and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8
Timer 0 Timer 1 Timer 2 Timer 3 A
pre-scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of
TMR0ON T08BIT T0CS T0SE A
Timer0.
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by
Timer0 if FFF6 h is loaded into it. 5.6 μS 5.2 μS 4.6 μS 4 μS D
Assume crystal frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
frequency = 16 MHz and prescaler of 0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
1:16
Find timer's clock period with crystal
frequency = 32 MHz and prescaler of 1 μS 2 μS 3 μS 4 μS A
1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair FFFF h 1234 h 0000 h 4321 h C
for generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller
5 6 7 8 B
is ___ bits.
Size of Port E in PIC 18 microcontroller
3 4 5 6 A
is ___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of
TMRxON Tx8BIT TxCS TxSE A
Timerx.
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
MICROPROCESSOR
BCA
IV Sem
MULTIPLE CHOICE QUESTIONS
1) Which is the microprocessor comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
2) What is the store by register?
a. data
b. operands
c. memory
d. None of these
3) Accumulator based microprocessor example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
4) A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
5) There are primarily two types of register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
6) Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
7) BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
8) Which is used to store critical pieces of data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
9) The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
10) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a. 16
b. 32
c. 36
d. 64
12) Which is not the control bus signal:
a. READ
b. WRITE
c. RESET
d. None of these
13) PROM stands for:
a. Programmable read‐only memory
b. Programmable read write memory
c. Programmer read and write memory
d. None of these
14) EPROM stands for:
a. Erasable Programmable read‐only memory
b. Electrically Programmable read write memory
c. Electrically Programmable read‐only memory
d. None of these
15) Each memory location has:
a. Address
b. Contents
c. Both A and B
d. None of these
16) Which is the type of microcomputer memory:
a. Processor memory
b. Primary memory
c. Secondary memory
d. All of these
17) Secondary memory can store____:
a. Program store code
b. Compiler
c. Operating system
d. All of these
18) Secondary memory is also called____:
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
19) Customized ROMS are called:
a. Mask ROM
b. Flash ROM
c. EPROM
d. None of these
20) The RAM which is created using bipolar transistors is called:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. DDR RAM
21) Which type of RAM needs regular referred:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
22) Which RAM is created using MOS transistors:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
23) A microprocessor retries instructions from :
a. Control memory
b. Cache memory
c. Main memory
d. Virtual memory
24) The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
a. Address bus
b. System bus
c. Control bus
d. Data bus
25) The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
a. Read
b. Write
c. Both A and B
d. None of these
26) The CPU removes the ___ signal to complete the memory write operation:
a. Read
b. Write
c. Both A and B
d. None of these
27) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
28) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
29) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
30) Eight of the register are known as:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
31) The four index register can be used for:
a. Arithmetic operation
b. Multipulation operation
c. Subtraction operation
d. All of these
32) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
33) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
34) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
36) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
37) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
38) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
39) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
40) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
41) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
42) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
43) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
44) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
45) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
46) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
47) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
48) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
49) ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a. Data segment
b. Code segment
c. Stack segment
d. Extra segment
50) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
51) Which are the factor of cache memory:
a. Architecture of the microprocessor
b. Properties of the programs being executed
c. Size organization of the cache
d. All of these
52) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
53) Which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
54) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
55) Microprocessor reference that are available in the cache are called______:
a. Cache hits
b. Cache line
c. Cache memory
d. All of these
56) Microprocessor reference that are not available in the cache are called_________:
a. Cache hits
b. Cache line
c. Cache misses
d. Cache memory
57) Which causes the microprocessor to immediately terminate its present activity:
a. RESET signal
b. INTERUPT signal
c. Both
d. None of these
58) Which is responsible for all the outside world communication by the microprocessor:
a. BIU
b. PIU
c. TIU
d. LIU
59) INTR: it implies the__________ signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
60) Which of the following are the two main components of the CPU?
a. Control Unit and Registers
b. Registers and Main Memory
c. Control unit and ALU
d. ALU and bus
61) Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
a. Conductors
b. Buses
c. Connectors
d. Consecutives
62) The language that the computer can understand and execute is called
a. Machine language
b. Application software
c. System program
d. All of the above
63) Which of the following is used as a primary storage device?
a. Magnetic drum
b. PROM
c. Floppy disk
d. All of these
64) Which of the following memories needs refresh?
a. SRAM
b. DRAM
c. ROM
d. All of above
65) The memory which is programmed at the time it is manufactured
a. PROM
b. RAM
c. PROM
d. EPROM
66) Which of the following memory medium is not used as main memory system?
a. Magnetic core
b. Semiconductor
c. Magnetic tape
d. Both a and b
67) Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
68) One of the main feature that distinguish microprocessors from micro‐computers is
a. Words are usually larger in microprocessors
b. Words are shorter in microprocessors
c. Microprocessor does not contain I/O devices
d. Exactly the same as the machine cycle time
69) The first microprocessor built by the Intel Corporation was called
a. 8008
b. 8080
c. 4004
d. 8800
70) An integrated circuit is
a. A complicated circuit
b. An integrating device
c. Much costlier than a single transistor
d. Fabricated on a tiny silicon chip
71) Most important advantage of an IC is its
a. Easy replacement in case of circuit failure
b. Extremely high reliability
c. Reduced cost
d. Low powers consumption
72) Which of the following items are examples of storage devices?
a. Floppy / hard disks
b. CD‐ROMs
c. Tape devices
d. All of the above
73) The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
a. 8 bits
b. 12 bits
c. 16 bits
d. 32 bits
74) Which is the type of memory for information that does not change on your computer?
a. RAM
b. ROM
c. ERAM
d. RW / RAM
75) What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
a. Extended
b. Expanded
c. Base
d. Conventional
76) Before a disk can be used to store data. It must be…….
a. Formatted
b. Reformatted
c. Addressed
d. None of the above
77) Which company is the biggest player in the microprocessor industry?
a. Motorola
b. IBM
c. Intel
d. AMD
78) A typical personal computer used for business purposes would have… of RAM.
a. 4 KB
b. 16 K
c. 64 K
d. 256 K
78) The word length of a computer is measured in
a. Bytes
b. Millimeters
c. Meters
d. Bits
79) What are the three decisions making operations performed by the ALU of a computer?
a. Grater than
b. Less than
c. Equal to
d. All of the above
80) Which part of the computer is used for calculating and comparing?
a. Disk unit
b. Control unit
c. ALU
d. Modem
81) Can you tell what passes into and out from the computer via its ports?
a. Data
b. Bytes
c. Graphics
d. Pictures
82) What is the responsibility of the logical unit in the CPU of a computer?
a. To produce result
b. To compare numbers
c. To control flow of information
d. To do math’s works
83) The secondary storage devices can only store data but they cannot perform
a. Arithmetic Operation
b. Logic operation
c. Fetch operations
d. Either of the above
84) Which of the following memories allows simultaneous read and write operations?
a. ROM
b. RAM
c. EPROM
d. None of above
85) Which of the following memories has the shortest access times?
a. Cache memory
b. Magnetic bubble memory
c. Magnetic core memory
d. RAM
86) A 32 bit microprocessor has the word length equal to
a. 2 byte
b. 32 byte
c. 4 byte
d. 8 byte
87) An error in computer data is called
a. Chip
b. Bug
c. CPU
d. Storage device
88) The silicon chips used for data processing are called
a. RAM chips
b. ROM chips
c. Micro processors
d. PROM chips
89) The metal disks, which are permanently housed in, sealed and contamination free containers
are called
a. Hard disks
b. Floppy disk
c. Winchester disk
d. Flexible disk
90) A computer consists of
a. A central processing unit
b. A memory
c. Input and output unit
d. All of the above
91) The instructions for starting the computer are house on
a. Random access memory
b. CD‐Rom
c. Read only memory chip
d. All of above
92) The ALU of a computer normally contains a number of high speed storage element called
a. Semiconductor memory
b. Registers
c. Hard disks
d. Magnetic disk
93) The first digital computer built with IC chips was known as
a. IBM 7090
b. Apple – 1
c. IBM System / 360
d. VAX‐10
94) Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
95) Which of the following is used for manufacturing chips?
a. Control bus
b. Control unit
c. Parity unit
d. Semiconductor
96) To locate a data item for storage is
a. Field
b. Feed
c. Database
d. Fetch
97) A directly accessible appointment calendar is feature of a … resident package
a. CPU
b. Memory
c. Buffer
d. ALU
98) The term gigabyte refers to
a. 1024 bytes
b. 1024 kilobytes
c. 1024 megabytes
d. 1024 gigabyte
99) A/n …. Device is any device that provides information, which is sent to the CPU
a. Input
b. Output
c. CPU
d. Memory
100) Current SIMMs have either … or … connectors (pins)
a. 9 or 32
b. 30 or 70
c. 28 or 72
d. 30 or 72
101) Which is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
102) Which technology using the microprocessor is fabricated on a single chip:
a. POS
b. MOS
c. ALU
d. ABM
103) MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
104) In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
105) The register section is related to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
106) In Microprocessor one of the operands holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
107) Which register is a temporary storage location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
108) PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
109) IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
110) SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
111) The act of acquiring an instruction is referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
112) How many bit of instruction on our simple computer consist of one____:
a. 2‐bit
b. 6‐bit
c. 12‐bit
d. None of these
113) How many parts of single address computer instruction :
a. 1
b. 2
c. 3
d. 4
114) Single address computer instruction has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
115) LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
116) Which are the flags of status register:
a. Over flow flag
b. Carry flag
c. Half carry flag
d. Zero flag
e. Interrupt flag
f. Negative flag
g. All of these
117) The carry is operand by:
a. C
b. D
c. S
d. O
118) The sign is operand by:
a. S
b. D
c. C
d. O
119) The zero is operand by:
a. Z
b. D
c. S
d. O
120) The overflow is operand by:
a. O
b. D
c. S
d. C
121) _________ Stores the instruction currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
122) In which register instruction is decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
123) The status register is also called the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
124) The area of memory with addresses near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
125) The processor uses the stack to keep track of where the items are stored on it this by using
the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
126) Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
127) Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
128) SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
129) How many bit stored by status register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
130) The 16 bit register is separated into groups of 4 bit where each groups is called:
a. BCD
b. Nibble
c. Half byte
d. None of these
131) A nibble can be represented in the from of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
132) The left side of any binary number is called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
133) MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
134) _____ a subsystem that transfer data between computer components inside a computer
or between computer:
a. Chip
b. Register
c. Processor
d. Bus
135) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
136) Which bus carry addresses:
a. System bus
b. Address bus
c. Control bus
d. Data bus
137) A 16 bit address bus can generate___ addresses:
a. 32767
b. 25652
c. 65536
d. none of these
138) CPU can read & write data by using :
a. Control bus
b. Data bus
c. Address bus
d. None of these
139) Which bus transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a. Control bus
b. Data bus
c. Address bus
d. None of these
140) When memory read or I/O read are active data is to the processor :
a. Input
b. Output
c. Processor
d. None of these
141) When memory write or I/O read are active data is from the processor:
a. Input
b. Output
c. Processor
d. None of these
142) CS stands for:
a. Cable select
b. Chip select
c. Control select
d. Cable system
143) WE stands for:
a. Write enable
b. Wrote enable
c. Write envy
d. None of these
144) MAR stands for:
a. Memory address register
b. Memory address recode
c. Micro address register
d. None of these
145) MDR stands for:
a. Memory data register
b. Memory data recode
c. Micro data register
d. None of these
146) Which are the READ operation can in simple steps:
a. Address
b. Data
c. Control
d. All of these
147) DMA stands for:
a. Direct memory access
b. Direct memory allocation
c. Data memory access
d. Data memory allocation
148) The ____ place the data from a register onto the data bus:
a. CPU
b. ALU
c. Both A and B
d. None of these
149) The microcomputer system by using the ____device interface:
a. Input
b. Output
c. Both A and B
d. None of these
150) The standard I/O is also called:
a. Isolated I/O
b. Parallel I/O
c. both a and b
d. none of these
151) The external device is connected to a pin called the ______ pin on the processor chip.
a. Interrupt
b. Transfer
c. Both
d. None of these
152) Which interrupt has the highest priority?
a) INTR
b) TRAP
c) RST6.5
d) none of these
153) In 8085 name the 16 bit registers?
a) Stack pointer
b) Program counter
c) a & b
d) none of these
154) What are level Triggering interrupts?
a) INTR&TRAP
b) RST6.5&RST5.5
c) RST7.5&RST6.5
d) none of these
155) Which stack is used in 8085?
a) FIFO
b) LIFO
c) FILO
d) none of these
156) What is SIM?
a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask.
d) none of these
157) RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
d) none of these
158) In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR d) none of these
159) In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
160) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
161) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
162) Which are the part of architecture of 8086:
a. The bus interface unit
b. The execution unit
c. Both A and B
d. None of these
163) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
164) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
165) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
166) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
167) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
168) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
169) The upper 8 bit are called______:
a. BH
b. BL
c. AH
d. CH
170) The lower 8 bit are called_______:
a. AL
b. CL
c. BL
d. DL
171) IP stand for:
a. Industry pointer
b. Instruction pointer
c. Index pointer
d. None of these
172) Which has great important in modular programming:
a. Stack segment
b. Queue segment
c. Array segment
d. All of these
173) Which register containing the 8086/8088 flag:
a. Status register
b. Stack register
c. Flag register
d. Stand register
174) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
175) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
176) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
177) The physical address of memory is :
a. 20 bit
b. 16 bit
c. 32 bit
d. 64 bit
178) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
179) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
180) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
181) PA stand for:
a. Project address
b. Physical address
c. Pin address
d. Pointer address
182) SBA stand for:
a. Segment bus address
b. Segment bit address
c. Segment base address
d. Segment byte address
183) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
184) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
185) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
186) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
187) DS stand for:
a. Default segment
b. Defect segment
c. Delete segment
d. Definition segment
188) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
189) AD stand for:
a. Address data
b. Address delete
c. Address date
d. Address deal
190) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
191) PC stand for:
a. program counter
b. project counter
c. protect counter
d. planning counter
192) AH stand for:
a. Accumulator high
b. Address high
c. Appropriate high
d. Application high
193) AL stand for:
a. Accumulator low
b. Address low
c. Appropriate low
d. Application low
194) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
195) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
196) which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
197) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
198) How many type of cache memory:
a. 1
b. 2
c. 3
d. 4
199) Which is the type of cache memory:
a. Fully associative cache
b. Direct‐mapped cache
c. Set‐associative cache
d. All of these
200) ) Which memory is used to holds the address of the data stored in the cache :
a. Associative memory
b. Case memory
c. Ordinary memory
d. None of these
PAI UNIT -2 MCQ
1. 1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
2.
1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
3. 3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor
4. The unit that decodes the instructions concurrently and translate them into micro-
operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
4. 5. In complex instructions, when the instruction needs to be translated into more than 4
micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
5. 6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
6. 8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
7. 9. If complex instructions like interrupt handling, string manipulation appear, then the
control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
8. 10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
9. 11. The mechanism to provide protection, that is accomplished with the help of
read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
10. 12. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
11. 13. The mechanism that is accomplished using descriptor usages limitations, and rules of
privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
12. 14. The mechanism that is executed at certain privilege levels, determined by CPL
(Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
13. 15. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) none of the mentioned
14. 16. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
15. 17. The condition, “CPL not equals to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) all of the mentioned
16. 18. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) all of the mentioned
17. 19. The instruction at which the exception is generated, but the processor extension
registers containthe address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
18. 20. The exception that has no error code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
19. 21. By using privilege mechanism the protection from unauthorised accesses is done to
a) operating system
b) interrupt handlers
c) system softwares
d) all of the mentioned
20. 22. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) none of the mentioned
21. 23. Once the CPL is selected, it can be changed by
a) HOLD
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
22. 24. The data segments defined in GDT (global descriptor table) and the LDT (local
descriptor table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
23. 25. A task with privilege level 0, doesnot refer to all the lower level privilege descriptors
in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) none of the mentioned
24. 26. The selector RPL that uses a less trusted privilege than the current privilege level for
further use is known as
a) Least task privilege level
b) descriptor privilege level
c) effective privilege level
d) none of the mentioned
25. 27. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
26. 28. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
27. 29. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) all of the mentioned
28. 30. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
29. Answers
1-d 2-c 3-d 4-b 5-cc
6-a 7-d 8-b 9-a 10-a
11-a 12-c 13-b 14-c 15-c
16-c 17-d 18-c 19-d 20-b
21-d 22-b 23-c 24-a 25-b
26-c 27-c 28-c 29-b 30-c
TOPICS– Privilege
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Privilege”.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
View Answer
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be protected
from unauthorized accesses in virtual address space of each task using the privilege mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) None of the mentioned
View Answer
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task privilege level
at that instant is called the Current Privilege Level (CPL).
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
View Answer
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a single
code segment. It can only be changed by transferring the control, using gate descriptors, to a new
segment.
4. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor
table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
View Answer
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data segments
defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) None of the mentioned
View Answer
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors which apply
to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
View Answer
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for further use.
This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
View Answer
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of RPL
and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
View Answer
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level(CPL, RPL, DPL).
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned
View Answer
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with DPL equal to
CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
View Answer
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same privilege as
CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than
the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
View Answer
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with DPL equal
to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must
be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
View Answer
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment(TSS) descriptor, then
DPL must be less or equally privileged than CPL.
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13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
View Answer
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data segment
access.
14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
View Answer
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an exception 13
is generated. If the referenced segment is not present in physical memory, an exception 11 is ge
Topic – Protection
1. The mechanism to provide protection, that is accomplished with the help of read/write
privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
View Answer
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are restricted by
classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege
check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is accomplished
using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL (Current
Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
View Answer
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
View Answer
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
View Answer
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this
condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
View Answer
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT,
LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
View Answer
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI
and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
View Answer
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers
contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
View Answer
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
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11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
View Answer
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun, processor
extension segment overrun, are the protected mode exceptions.
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TOPIc– Protected Virtual Address Mode (PVAM) -2
This set of Advanced Microprocessors Questions and Answers focuses on “Protected Virtual
Address Mode (PVAM) -2”.
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
View Answer
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called system
descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate and trap
gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control transfer,
required stack manipulations, privilege level and its type.
4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d) trap gate
View Answer
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
View Answer
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
View Answer
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
View Answer
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number of bytes
to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM (read only memory)
View Answer
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor information,
from the main memory, cache memory is used in which the most frequently required data for execution
is stored.
9. The selector field consists of
a) requested privilege level (RPL)
b) table indicator
c) index
d) all of the mentioned
View Answer
Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as selectors. The
selector field consists of three fields namely, RPL, table indicator (TI) and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
View Answer
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero (0) is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
View Answer
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at privilege level
0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
View Answer
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table, containing
the base address, and limit for LDT.
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13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
View Answer
14. The number of interrupt descriptors that the interrupt descriptor table (IDT) handles is
a) 16
b) 64
c) 128
d) 256
View Answer
Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
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1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.
3. The number of debug registers that are available in 80386, for hardware debugging and control is a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware debugging and
control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging and four
levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is known as a)
segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organise the available
physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
Explanation: The 80386 has on-chip address translation cache, and instruction set is upward compatible
with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode of
operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286 (to be
executed under the control of memory management and protection abilities of 80386).
11. Which of the units is not a part of internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
12. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
Explanation: The central processing unit is further divided into execution unit and instruction unit.
13. The unit that is used for handling data, and calculate offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
14. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
15. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
16. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
17. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
18. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
19. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
Explanation: The paging unit works under the control of segmentation unit; i.e. each segment is further
divided into pages.
20. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
21. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
22. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
23. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
24. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) none of the mentioned
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
25. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
26. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
27. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.
28. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a
prefix of
a) X
b) E
c) 32
d) XX
Answer: b
Explanation: A 32 bit register, known as extended register, is represented by the register name with a
prefix of E.
29. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) none of the mentioned
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
30. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) all of the mentioned
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
31. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
32. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) none of the mentioned
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
33. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
34. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) task switch operation
c) IRET instruction or task switch operation
d) none of the mentioned
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
35. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
36. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
37. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of segments.
38. The 32-bit control register, that is used to hold global machine status, independent of the executed
task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
39. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) TSS (Task state segment descriptor)
e) all of the mentioned
Answer: e
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
40. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
41. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
42. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
Answer: c
Explanation: Two test registers are provided by 80386 for page cacheing, namely test control and test
status registers.
43. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
44. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
45. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
46. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
47. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers, rather, they
are internally used to store the descriptor information.
48. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
49. Contents of an index register are multiplied by a scale factor that may be added further to get the
operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
50. Contents of an index register are multiplied by a scale factor and then added to base register to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
51. In based scaled indexed mode with displacement mode, the contents of an index register are
multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is addedto a
base register and a displacement to get the offset of an operand.
52. The following statement of ALP is an example of MOV EBX, [EDX*4] [ECX]
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
53. The following statement is an example of MOV EBX, LIST [ESI*2] MUL ECX, LIST [EBP*4] a) base
scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
54. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
55. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
56. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
Answer: c
Explanation: The integer word is the signed 16-bit data.
57. A 16-bit displacement that references a memory location using any of the addressing modes is
a) pointer
b) character
c) BCD
d) offset
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing modes.
58. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
59. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
60. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
Answer: c
Explanation: The paging unit is disabled in real address mode.
61. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
62. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
63. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
64. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
65. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
66. If the paging unit is enabled, then it converts linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The paging unit when enabled, it converts linear address into physical address.
67. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The linear address is used as physical address if the paging unit is disabled.
68. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
Answer: c
Explanation: The paging unit is enabled only in protected mode.
69. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
70. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granulary bit
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
71. The TYPE field of descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
72. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
73. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
74. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
75. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
76. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Answer: d
Explanation: The five types of segment descriptors of 80386 are: 1. Code or data segment descriptors 2.
System descriptors 3.Local descriptors 4.TSS(task state segment) descriptors 5. Gate descriptors
77. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
78. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
79. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
80. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
81. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
Answer: b
Explanation: The paging divides the memory into fixed size pages.
82. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by segmentation unit, into physical addresses.
83. The control register that stores the 32-bit linear address, at which the previous page fault is detected
is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
84. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
85. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
86. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
87. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
88. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
89. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
90. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) all of the mentioned
Answer: c
Explanation: The D-bit is undefined for page directory entries.
91. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
92. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
93. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
Answer: c
Explanation: The page table cache is also known as translation look aside buffer
The internal RAM memory of the 8051 is:
A. 32 bytes
B. 64 bytes
C. 128 bytes
D.256 bytes
Answer: Option C
2. This program code will be executed continuously:
STAT: MOV A, #01H
JNZ STAT
A.True
B. False
Answer: Option A
3. The 8051 has ________ 16-bit counter/timers.
A. 1
B. 2
C. 3
D.4
Answer: Option B
4. The address space of the 8051 is divided into four distinct areas: internal data, external data,
internal code, and external code.
A.True
B. False
Answer: Option A
5. Data transfer from I/O to external data memory can only be done with the MOVX command.
A.True
B. False
Answer: Option A
6. The 8051 can handle ________ interrupt sources.
A. 3
B. 4
C. 5
D.6
Answer: Option C
Explanation:
There are five interrupt sources for the 8051, which means that they can recognize 5 different events
that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting
bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of
the same register.
7. The special function registers are maintained in the next 128 locations after the general-
purpose data storage and stack.
A.True
B. False
Answer: Option A
8. This statement will set the address of the bit to 1 (8051 Micro-controller):
SETB 01H
A.True
B. False
Answer: Option B
9. MOV A, @ R1 will:
A. copy R1 to the accumulator
B. copy the accumulator to R1
C. copy the contents of memory whose address is in R1 to the accumulator
D.copy the accumulator to the contents of memory whose address is in R1
Answer: Option C
10. A label is used to name a single line of code.
A.True
B.False
Answer: Option A
11. The following program will receive data from port 1, determine whether bit 2 is high, and
then send the number FFH to port 3:
READ: MOV A,P1
ANL A,#2H
CJNE A,#02H,READ
MOV P3,#FFH
A.True
B.False
Answer: Option A
12. Device pins XTAL1 and XTAL2 for the 8051 are used for connections to an external
oscillator or crystal.
A.True
B.False
Answer: Option A
13. When the 8051 is reset and the line is HIGH, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option A
14. An alternate function of port pin P3.4 in the 8051 is:
A. Timer 0
B. Timer 1
C. interrupt 0
D.interrupt 1
Answer: Option A
15. Both registers TL0 and TL1 are needed to start Timer 0.
A.True
B.False
Answer: Option B
16. The I/O ports that are used as address and data for external memory are:
A. ports 1 and 2
B. ports 1 and 3
C. ports 0 and 2
D.ports 0 and 3
Answer: Option C
17. The last 96 locations in the internal data memory are reserved for general-purpose data
storage and stack.
A.True
B.False
Answer: Option B
18. Microcontrollers often have:
A. CPUs
B. RAM
C. ROM
D.all of the above
Answer: Option D
19. The 8051 has ________ parallel I/O ports.
A. 2
B. 3
C. 4
D.5
Answer: Option C
20. The total external data memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
21. Which of the following instructions will load the value 35H into the high byte of timer 0?
A. MOV TH0, #35H
B. MOV TH0, 35H
C. MOV T0, #35H
D.MOV T0, 35H
Answer: Option A
23. The 8-bit address bus allows access to an address range of:
A. 0000 to FFFFH
B. 000 to FFFH
C. 00 to FFH
D.0 to FH
Answer: Option C
24. The contents of the accumulator after this operation
MOV A,#0BH
ANL A,#2CH
will be
A. 11010111
B. 11011010
C. 00001000
D.00101000
Answer: Option C
25. The start-conversion on the ADC0804 is done by using the:
A.
B. CS line
C. INTR line
D.V ref/2 line
Answer: Option A
26. This program code will be executed once:
STAT: MOV A, #01H
JNZ STAT
A.True
B.False
Answer: Option B
27. Which of the following instructions will move the contents of register 3 to the accumulator?
A. MOV 3R, A
B. MOV R3, A
C. MOV A, R3
D.MOV A, 3R
Answer: Option C
28. Which of the following statements will add the accumulator and register 3?
A. ADD @R3, @A
B. ADD @A, R3
C. ADD R3, A
D.ADD A, R3
Answer: Option D
29. Data transfer from I/O to external data memory can only be done with the MOV command.
A.True
B.False
Answer: Option B
30. Which of the following commands will move the number 27H into the accumulator?
A. MOV A, P27
B. MOV A, #27H
C. MOV A, 27H
D.MOV A, @27
Answer: Option B
31. This program code will read data from port 0 and write it to port 2, and it will stop looping
when bit 3 of port 2 is set:
STAT: MOV A, PO
MOV P2,A
JNB P2.3, STAT
A.True
B.False
Answer: Option A
32. Which of the following commands will move the value at port 3 to register 2?
A. MOV P2, R3
B. MOV R3, P2
C. MOV 3P, R2
D.MOV R2, P3
Answer: Option D
33. The number of data registers is:
A. 8
B. 16
C. 32
D.64
Answer: Option C
34. When the 8051 is reset and the EA line is LOW, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option B
35. The designs of a centigrade thermometer and a PWM speed-control circuit can be
implemented by the 8051.
A.True
B.False
Answer: Option A
36. What is the difference between the 8031 and the 8051?
A. The 8031 has no interrupts.
B. The 8031 is ROM-less.
C. The 8051 is ROM-less.
D.The 8051 has 64 bytes more memory.
Answer: Option B
37. The I/O port that does not have a dual-purpose role is:
A. port 0
B. port 1
C. port 2
D.port 3
Answer: Option B
38. To interface external EPROM memory for applications, it is necessary to demultiplex the
address/data lines of the 8051.
A.True
B.False
Answer: Option A
39. The following command will copy the accumulator to the location whose address is 23H:
MOV 23H,A
A.True
B.False
Answer: Option A
40. The special function registers can be referred to by their hex addresses or by their register
names.
A.True
B.False
Answer: Option A
41. The contents of the accumulator after this operation
MOV A,#2BH
ORL A,00H
will be:
A. 1B H
B. 2B H
C. 3B H
D.4B H
Answer: Option B
42. The following program will cause the 8051 to be stuck in a loop:
LOOP: MOV A, #00H
JNZ LOOP
A.True
B.False
Answer: Option B
43. Which of the following commands will copy the contents of RAM whose address is in
register 0 to port 1?
A. MOV @ P1, R0
B. MOV @ R0, P1
C. MOV P1, @ R0
D.MOV P1, R0
Answer: Option C
44. The statement LCALL READ passes control to the line labelled READ.
A.True
B.False
Answer: Option A
45. Which of the following commands will copy the contents of location 4H to the accumulator?
A. MOV A, 04H
B. MOV A, L4
C. MOV L4, A
D.MOV 04H, A
Answer: Option A
46. The microcontroller is useful in systems that have nonvariable programs for dedicated
applications.
A.True
B.False
Answer: Option A
47. The total amount of external code memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
48. The ADC0804 has ________ resolution.
A. 4-bit
B. 8-bit
C. 16-bit
D.32-bit
Answer: Option B
49. A HIGH on which pin resets the 8051 microcontroller?
A. RESET
B. RST
C. PSEN
D.RSET
50. An alternate function of port pin P3.1 in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option B
51. Which of the following instructions will move the contents of the accumulator to register 6?
A. MOV 6R, A
B. MOV R6, A
C. MOV A, 6R
D.MOV A, R6
Answer: Option B
52. The following command will rotate the 8 bits of the accumulator one position to the left:
RL A
A.True
B.False
Answer: Option A
53. An alternate function of port pin P3.0 (RXD) in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option A
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Arithmetic and Logic Instructions”.
1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
View Answer
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator.
Example- ADD A,R0; ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
View Answer
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
View Answer
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of
the register or some immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
View Answer
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
View Answer
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to
1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
View Answer
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is
important and in signed number operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
View Answer
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the
data copy instructions, so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
View Answer
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to
mask the status of the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
View Answer
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not
equal and it resets CY if the destination address is larger then the source address and sets CY if
the destination address is smaller then the source address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the
source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the
source address
d) any register as the destination address and any immediate data as the source address
View Answer
Answer: a
Explanation: These commands have accumulator as the destination address and any register,
memory or any immediate data as the source address.
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Architecture”.
1. 8051 series of microcontrollers are made by which of the following companies?
a) Atmel
b) Philips
c) Atmel & Philips
d) None of the mentioned
View Answer
Answer: d
Explanation: Atmel series AT89C2051 and Philips family P89C51RD2 are the two most
common microcontrollers of 8051 families.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
View Answer
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
View Answer
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) DPTR
b) SP
c) PC
d) PSW
View Answer
Answer: c
Explanation: When a program wakes up, then 0x00 is loaded to the program counter register
because at this place the first op code is burnt.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which
register are affected?
a) PSW
b) SP
c) DPTR
d) PC
View Answer
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow,
parity, register bank select bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
View Answer
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and
AC are set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
View Answer
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2
RS1=1 and RS0=0 which are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
View Answer
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push
of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
View Answer
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
View Answer
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
This set of 8051 Micro-controller Multiple Choice Questions & Answers
(MCQs) focuses on “Jump, Loop and Call Instructions”.
1. DJNZ R0, label is how many bit instructions?
a) 2
b) 3
c) 1
d) Can’t be determined
View Answer
Answer: a
Explanation: DJNZ R0, label has hex code, D8 and its corresponding label address. Hence, it is a
two byte instruction.
2. JZ, JNZ, DJNZ, JC, JNC instructions monitor the bits of which register?
a) DPTR
b) B
c) A
d) PSW
View Answer
Answer: d
Explanation: PSW register consists of flag bits like CY, P, Z etc so it is the one that is directly
being monitored by these instructions.
3. Calculate the jump code for again and here if code starts at 0000H
MOV R1,#0
MOV A,#0
MOV R0,#25H
AGAIN:ADD A,#0ECH
JNC HERE
HERE: INC R1
DJNZ R0,AGAIN
MOV R0,A
END
a) F3,02
b) F9,01
c) E9,01
d) E3,02
View Answer
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next
to the source address.
So here if we start with 0000H
then source address is 0008H and the destination address is 0004H
So loop address is 04-0A=E9
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
View Answer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call
instruction so that when RET is executed then PC is filled with that address and so the pointer
moves to the main program and continue with its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
View Answer
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte
instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
View Answer
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH
instructions the pointer does not move to any location specified by its address which is the
fundamental of CALL instruction, so it is not a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
View Answer
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal
frequency) /12
8. Find the number of times the following loop will be executed
MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a) 100
b) 200
c) 20000
d) 2000
View Answer
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
View Answer
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is
moved to it unlikely of using # used for storing data in any register.
10. Do the two instructions mean the same?
1) BACK: DEC R0
JZ BACK
2) BACK: DJNZ RO, BACK
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
View Answer
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves
back and in the second statement, when the result after decrements is not zero, then it jumps
back.
Unit No.1
Topic:Assembler Directives and ALP Tools
1. __________ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
View Answer
Answer: c
Explanation: An assembler is a software used to convert the programs into machine instructions.
2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
View Answer
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.
3. The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
View Answer
Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.
4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
View Answer
Answer: d
Explanation: The directives help the program in getting compiled and hence won’t be there in the
object code.
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
View Answer
Answer: b
Explanation: This basically is used to replace the variable with a constant value.
6. The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
View Answer
Answer: a
Explanation: This does the function similar to the main statement.
7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
View Answer
Answer: c
Explanation: None.
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
View Answer
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object code
of the program there.
9. _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
View Answer
Answer: b
Explanation: This instruction directive is used to terminate the program execution.
10. The last statement of the source program should be _______
a) Stop
b) Return
c) OP
d) End
View Answer
Answer: d
Explanation: This enables the processor to load some other process.
11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
View Answer
Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the branch
offset and replaces it with it.
12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
View Answer
Answer: b
Explanation: The table where the assembler stores the variable names along with their
corresponding memory locations and values.
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13. The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
View Answer
Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and
waits for further execution.
14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
View Answer
Answer: a
Explanation: The program is used to load the program into memory.
15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
View Answer
Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.
TOPICS: “Programming With An Assembler”.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
View Answer
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
View Answer
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
View Answer
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
View Answer
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
View Answer
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
View Answer
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
View Answer
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
View Answer
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
View Answer
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
View Answer
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.
11. The purpose of the ORIGIN directive is __________
• A. To indicate the starting position in memory, where the program block is to be stored
• B. To indicate the starting of the computation code
• C. To indicate the purpose of the code
• D. To list the locations of all the registers used
Answer: Option A
12. The last statement of the source program should be _______
• A. Stop
• B. Return
• C. OP
• D. End
Answer: Option D
13.DEBUG is able to troubleshoot only
• A. .EXE files
• B. .OBJ files
• C. .EXE file and .OBJ file
• D. .EXE flie and .LST file
Answer: Option A
TOPICS: Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
TOPIC: – Segmentation of 80386
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
View Answer
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
View Answer
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
View Answer
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
View Answer
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
View Answer
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
View Answer
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS(task state segment) descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
View Answer
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
View Answer
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
View Answer
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence
TOPIC:– Architecture and Signal Descriptions of 80386
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
View Answer
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
View Answer
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
View Answer
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
View Answer
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
View Answer
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
View Answer
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
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13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
View Answer
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
View Answer
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
View Answer
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
View Answer
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
View Answer
Answer: c
Explanation: The pip
TOPICS– Register Organisation of 80386 -1
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers
with a prefix of
a) X
b) E
c) 32
d) XX
View Answer
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register name with a
prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
View Answer
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
View Answer
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
View Answer
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
View Answer
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
View Answer
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
View Answer
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of se
TOPIC: – Register Organisation of 80386 -2
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
View Answer
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
View Answer
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register(s) that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
View Answer
Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and test
status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
View Answer
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
View Answer
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
View Answer
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
View Answer
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
View Answer
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers,
rather, they are internally used to store the descriptor information
TOPIC: Addressing Modes of 80386, Data Types of 80386
1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register to
get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
View Answer
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is added to a
base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
View Answer
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
View Answer
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
View Answer
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d) Offset
View Answer
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing mod
TOPIC– Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer.A
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task
Topic: – Paging
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
View Answer
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
View Answer
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by the segmentation unit, into physical addresses.
4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
View Answer
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
View Answer
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
View Answer
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
View Answer
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
10. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
View Answer
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
View Answer
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
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13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
View Answer
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
View Answer
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
MCQS on the INstruction
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
2. If the processor is executing a main program that calls a subroutine, then after executing the
main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) none
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
11. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
12. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) all of the mentioned
13. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
14. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
15. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
16. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
17. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
18. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
19. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
20. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
21. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
22. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
23. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
24. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
25. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
26. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
27. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
28. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
29. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
30. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answers
1-c 2-b 3-d 4-c 5-d
6-b 7-c 8-d 9-d 10-d
11-d 12-d 13-a 14-b 15-c
16-b 17-d 18-a 19-b 20-c
21-d 22-b 23-d 24-c 25-b
26-d 27-d 28-b 29-c 30-a
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC
to ____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller Watchdog
are ______ Timers ADC All of these D
5 Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access
data RAM in PIC 18 microcontroller. 4 8 12 16 C
9
___ address lines are used to access
program ROM in PIC 18 microcontroller. 18 19 20 21 D
10
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller
is ___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller
is ___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is 128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : deep sleep,
sleep, deep idle, deep
sleep, idle deep power A
sleep sleep
20 down
WDT stands for _______ Watch Watch Dog Width Delay Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master
Master Master
Synchronou Master Slave
Synchronou Synchronous C
s Serial Serial Port
s slave Port Serial Port
25 Peripheral
Flag 'N' in Status register of PIC18F452 d Negative
Zero Flag Overflow Flag Carry Flag B
26 Flag
How many banks are available in PIC 18F
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result Results saved Ressult
ADDWF F D a Undefined D
saved in F in F and W Saaved in W
28
BOD' stands for Brown OR Brown out
Brown out Board on Reset
Reset Reset B
Reset Debug Detection
29 Detection Detection
Circuit used for initialization of all values t Power-On Brown Out Power ON/
Reset Detection WDT circuit A
OFF circuit
30 Circuit Circuit
In Immediate (Literal) addressing mode
The operand is _____ that follows the a register a number a pointer an address B
31 opcode
PIC18F452 has power down modes as __ deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated
in____ oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in
OSCCONFI
PIC18F4550 is controlled through two CONFIG2 CONFIG1L
G1 and None of the
Configuration registers as _______ and and C
OSCCONFI above
CONFIG2 CONFIG1H
G2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral
Univeral Serial
Synchrnous Synchrnous Synchrnous
Asynchronous
Asynchrono Asymmatric Asynchronous C
Receive
us Register Receive Receive
Transmit
36 Transmit Transmit Transmit
CONFIG2L is used for Frequency Background Watch dog
Reset voltage D
Selection debugger timer
37
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontrol
Resets all the
for ler in Set all registers B
registers
peripherals standby
38 OFF mode
Where is the result stored after an
execution of increment and decrement Working None of the
File Register Both a & b C
operations over the special - purpose Register above
39 registers in PIC?
Which status bits exhibit carry from
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sheet1
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
Page 1
Sheet1
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
Page 2
Sheet1
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Page 3
Sheet1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
Page 1
Sheet1
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Page 2
Sheet1
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of TMRxON Tx8BIT TxCS TxSE C
Which of the following is not a Port SFR?
Timer0. PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is output input bidirectional None of B
____ reset content of TRISB register is
Upon 0000 0000 000 000 1111 1111 these
111 111 C
_______
Which of the following instruction is used to BSF BCG BTG BMF A
set a file
Which of register bit? instruction is used to
the following BSF BCG BTG BMF B
clear a file register
Which of the following bit?instruction is used to BSF BCG BTG BMF C
toggle a file register bit?
Page 3
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
By which of the following method(s)
devices receive service from the Interrupts Polling Both of these None of these C
microcontroller?
Asynchronous request for service by
peripherals to processor is known as Interrupt Polling Both of these None of these A
____
Which of the following can cause Serial data Serial data
Timer overflow All of these D
interrupt generation? reception transmission
In which of the following method(s)
priority can be assigned to the devices Interrupts Polling Both of these None of these A
demanding for service?
In which of the following method(s)
microcontroller can not ignore a device Interrupts Polling Both of these None of these B
request for service?
Which of the following method(s) waste
Interrupts Polling Both of these None of these B
microcontroller’s time
Input Interrupt Interrupt
Input Service
Full form of ISR is_______ Synchronous Synchronous Service D
Routine
Routine Routine Routine
Interrupt
Input Vector Inerrupt Input Vector
Full form of IVT is_______ Vector B
Table Vector Table Testbench
Testbench
Power on Reset Vector in PIC 18 is
0000 0008 0018 0028 A
_____h
High Priority Interrupt Vector in PIC 18 is
0000 0008 0018 0028 B
_____h
Low Priority Interrupt Vector vector in
0000 0008 0018 0028 C
PIC 18 is _____h
Fixed locations in memory that holds
IGT IMT IRT IVT D
addresses of ISRs are called as ____
Correct sequence of steps in executing an
interrupt is ______ Where 1=Execute ISR,
1-2-3-4 3-2-1-4 4-3-2-1 3-2-4-1 D
2= Consult IVT, 3=Save PC on stack and
4=Jump to ISR
While servicing an interrupt content of
PC MAR MBR IR A
____ register are saved on the stack
What is the status of interrupts in PIC 18 All are Some are
All are enabled None of these B
after power on or reset? disabled enabled
____ bit is used for enabling/disabling of
FIE GIE HIE JIE B
all interrupts
Global Interrupt Enable (GIE) bit is
INTCON RCON PIR PIE A
present in ______ register
Interrupt Priority Enable (IPEN) bit is
INTCON RCON PIR PIE B
present in ______ register
Peripheral Interrupt Enable (PEIE) bit is
INTCON RCON PIR PIE A
present in ______ register
To enable serial communication
interrupts which of the following bit(s) Only GIE Only PEIE Both of these None of these B
must be set?
To enable timer 0 interrupt which of the
Only GIE Only PEIE Both of these None of these A
following bit(s) must be set?
There are ___ registers to control
11 12 13 14 C
interrupt operation in PIC 18
In PIC18F, any interrupt source is enabled
0 1 X None of these D
when corresponding IE bit is ____.
Which of the following bit(s) control
operation of an interrupt source in PIC18 Flag bit Enable bit Priority bit All of these D
F?
The default ISR address in PIC18F is
0000 0008 0018 0028 B
_____ h
Which of the following bit(s) indicate that
Flag bit Enable bit Priority bit All of these A
an interrupt event has occurred?
Which of the following bit(s) is used to
Flag bit Enable bit Priority bit All of these C
assign priority to an interrupt?
Setting of ___ and ____ bit allows
Enable,
program execution to branch to the Flag, Enable Flag, Priority All of these A
Priority
interrupt vector address.
If the interrupt is one of the peripheral
(timers 1,2 , serial, etc. ) we need to set
TMR0IE INT0IE PEIE RBIE C
____ bit from INTCON register along with
GIE bit.
Which of the following interrupt has no
INT3 INT2 INT1 INT0 D
priority bit?
_____ interrupt has default high priority. INT0 INT1 INT2 All of these D
For any interrupt source, to assign high
priority the corresponding IP bit must be 0 1 X None of these B
____.
For any interrupt source, to assign low
priority the corresponding IP bit must be 0 1 X None of these A
____.
Which of the following is not a core Serial
TMR0 INT0 INT1 D
interrupt source? Transmit
Which of the following is not a peripheral
TMR3 TMR2 TMR1 TMR0 D
interrupt source?
Which of the following is not a peripheral Serial
TMR1 INT0 TMR2 B
interrupt source? Transmit
Upon power-on reset the external
Positive edge Negative edge Positive level Negative level
hardware interrupts INT0-INT2 are of A
triggered triggered triggered triggered
type _____.
Which of the following avoids tying down
Interrupts Polling Both of these None of these A
the microcontroller?
PIC 18 ha ____ external hardware
1 2 3 4 C
interrupts.
External hardware interrupts of PIC18F
E D C B D
are multiplexed with port ____ lines.
PORTB-change interrupt is assocaied with
4 3 2 1 A
_____ lines of PORTB.
PORTB-change interrupt is assocaied with
RB0-RB3 RB2-RB5 RB3-RB6 RB4-RB7 D
_____ lines of PORTB.
Register Select pin of LCD selects_____
Status Command Data Program B
register when it is 0.
Register Select pin of LCD selects_____
Status Command Data Program C
register when it is 1.
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these B
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit IV MCQs
Q.1 How does the pin RC2/CCP1 get configured while initializing the CCP module in the
compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans:d
Q.2 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans:a
Q.3 The capture operation in counter mode is feasible when mode of CCP module is
__ _ __
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
Ans:a
Q.4 Which register is suitable for the corresponding count, if the measurement of pul se
width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
Ans:c
Q.5 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR Ans:a
Q.6 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.7 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.8 Which among the below mentioned aspect issues are supported by
capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
Ans:d
Q.9 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.10 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.11 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
Ans:a
Q.12 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans: a
Q.13 How does the pin RC2/CCP1 get configured while initializing the CCP module in
the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans: b
Q.14 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0
Ans: a
Q.15 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
Ans: b
Q.16 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.17 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value
Ans: b
Q.18 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter ?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components
Ans: a
Q.19 In ____ _ data transfer, group of bits (usually 8 bits) of data is transferred at a
time.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.20 In ____ _ data transfer, only one bit of data is transferred at a time.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.21 In Parallel data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: a
Q.22 In Serial data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: b
Q.23 Most of the Microprocessor/Microcontrollers are designed for______ communication.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.24 In _____ data communication, during transmission parallel data is converted into
serial bits using a PISO shift register.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.25 At the receiver, the serial bits are connected into parallel data by another shift
register called SIPO register.
a. TRUE b. FALSE Ans: a
Q.26 In ____ __, the hardware exists such that data transfer takes place only in one
direction.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.27 The transmission form a computer to the printer is an example of ____ _ _
communication.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.28 The ______ transmission allows the data transfer in both directions, but not
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.29 Walkie-talkie is an example of ________ _.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.30 The ______ transmission allows the data transfer in both directions
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q. 31 Telephone lines is an example of ____ _ .
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q.32 Types of serial data communication:
a. Asynchronous serial data communication
b. Synchronous serial data communication
a. TRUE b. FALSE Ans: a
Q.33 The serial communication is
a. cheaper communication
b. requires less number of conductors
c. slow process of communication
d. all of the mentioned Ans: d
Q.34 The serial communication is used for
a. short distance communication
b. long distance communication
c. short and long distance communication
d. communication for a certain range of distance Ans: b
Q.35 The number of bits transmitted or received per second is defined as
a. transmission rate
b. reception rate
c. transceiver rate
d. baud rate Ans: d
Q.36 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.37 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.38 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0 Ans: a
Q.39 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above Ans: b
Q.40 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.41 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value Ans: b
Q.42 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components Ans: a
Q.43 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.44 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.45 What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave
mode by enabling SS pin control?
a. 0000 b. 0100 c. 0010 d. 0001 Ans: b
Q.46 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above Ans: a
Q.47 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.48 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above Ans: b
Q.49 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c. 16 d. 32 Ans: a
Q.50 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above Ans: a
Q.51 What is the purpose of a special function register SPBRG in USART?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above Ans: a
Q.52 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the
data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.53 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode?
a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1) Ans: b
Q.54 What is the status of shift clock supply in an USART synchronous mode?
a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally Ans: a
Q.55 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.56 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as
DT (data lines)?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.57 Which among the below assertions represent the salient features of PIC in C-18
compiler?
a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above Ans: d
Q.58 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above Ans: d
Q.59 Which flags of status register are most likely to get affected by the single-cycle
increment and decrement instructions?
a. P Flags b. C Flags c. OV Flags d. Z Flags Ans: d
Q.60 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.61 In ____ _ _ communication, transmitters and receivers are not synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: a
Q.62 In ____ _ _ communication, transmitters and receivers are synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: c
Q.63 In Asynchronous Serial communication, bits of data are transmitted at constant
rate.
a. TRUE b. FALSE Ans: a
Q.64 In Synchronous Serial communication, bits of data are transmitted with
synchronization of clock.
a. TRUE b. FALSE Ans: a
Q.65 In Asynchronous Serial communication, character may arrive at any rate at
receiver.
a. TRUE b. FALSE Ans: a
Q.66 In Synchronous Serial communication, is received at constant rate.
a. TRUE b. FALSE Ans: a
Q.67 In Asynchronous Serial communication, data transfer is character oriented.
a. TRUE b. FALSE Ans: a
Q.68 In Synchronous Serial communication, data transfer takes place in blocks.
a. TRUE b. FALSE Ans: a
Q.69 Baud Rate is data transmission speed.
a. TRUE b. FALSE Ans: a
Q.70 The rate at which the bits are transmitted (bits/second) is called ____ _.
a. speed b. bit rate c. baud d. sample Ans: c
Q.71 The common baud rates are multiplies of _____ bits/second.
a. 25 b. 50 c. 75 d. 100 Ans: c
Q.72 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.73 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.74 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD b. SSPBUF c. Both a & b d. None of the above Ans: a
Q.75 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.76 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line b. SDA line c. Both a & b d. None of the above Ans: b
Q.77 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c.16 d.32 Ans: a
Q.78 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA b. RCSTA c. SPBRG d. All of the above Ans: a
Q.79 What is the purpose of a special function register SPBRG in USART ?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bitr
d. All of the above Ans: a
Q.80 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all
the data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.81 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode ?
a. FOSC / 8 (X +1 )
b. FOSC / 16 (X +1 )
c. FOSC / 32 (X +1 )
d. FOSC / 64 (X +1 ) Ans: b
Q.82 What is the status of shift clock supply in an USART synchronous mode?
a. Master - internally, Slave - externally
b. Master - externally, Slave - internally
c. Master & Slave (both) - internally
d. Master & Slave (both)- externally Ans: a
Q.83 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode ?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.84 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins
as DT (data lines) ?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.85 Two wire interfaces is also called as _____ __
a. UART b. SPI c. I2C d. USART Ans: c
Q.86 I2c will address large number of slave devices.
a. True b. False Ans: a
Q.87 SDA is having a transition when the clock line SCL is high.
a. high to low b. low to high c. low to low d. high to high Ans: a
Q.88 Inter Integrated Circuit is a
a. Single master, single slave
b. Multi master, single slave
c. Single master, multi slave
d. Multi master, multi slave Ans: d
Q.89 Typical voltages used are _
a. 5v b. 3.3v c. 5v or 3.3v d. 2.5v Ans: c
Q.90 What is the speed of I2C bus?
a. 100 kbits/s b. 10 kbits/s c.75 kbits/s d.100 kbits/s and 10 kbits/s Ans: d
Q.91 Master transmits means
a. Master node is sending data to a slave
b. Master node is receiving data from slave
c. Slave node is transmitting data to master
d. Slave node is sending data to master Ans: a
Q.92 Who sends the start bit?
a. Master receive
b. Master transmit
c. Slave transmit
d. Slave receive Ans: b
Q.93 Which is the I2C messaging example?
a. 24c32 EPROM
b. 24c32 EEPROM
c. 24c33 EEPROM
d. 24c33 EPROM Ans: b
Q.94 Are pull up registers required in I2C?
a. True b. False Ans: a
Q.95 How many types of addressing structures are there in I2C?
a. 4 types b. 3 types c. 2 types d. 5 types Ans: c
Q.96 All operating modes work under
a. 11 kbit/s b. 100 kbit/s c. 15 kbit/s d. 150 kbit/s Ans: b
Q.97 Which mode is highly compatible and simply tightens?
a. Fast mode
b. High speed mode
c. Ultra fast mode
d. Both fast and high speed mode Ans: a
Q.98 What is the speed for fast mode?
a. 100 kbit/s b. 400 kbit/s c. 150 kbit/s d. 200 kbit/s Ans: b
Q.99 Which of the following is a synchronous serial interface protocol?
a. SPI b. I2C c. UART d. Both (a) and (b) Ans: d
Q.100 Synchronous interfaces make use of clock signal? State True or False
a. True b. False Ans: a
Q.101 Which of the following serial protocol is used for on-board serial communication?
a. USB b. I2C c. Wifi d. Bluetooth Ans: b
Q.102 Which of the following protocol make use of 7 bit address for its operation?
a. I2C b. SPI c. RS232 d. RS485 Ans: a
Q.103 Which of the following interface is used to 127 slave device to the master device?
a. SPI b. I2C c. RS232 d. RS485 Ans: b
Q.104 RS232 protocol makes use of clock signal for sending data? True or False
a. True b. False Ans: b
Q.105 Which serial communication interface is used to connect modems and for non
networked communication between computers and other devices?
a. SPI b. I2C c. UART d. USB Ans: c
Q.106 How many wires are used to connect I2C devices?
a. 1 wire b. 2 wires c. 3 wires d. 4 wires Ans: b
Q.107 Which of the following interface was developed by Motorola Company?
a. I2C b. SPI c. USB d. Bluetooth Ans: b
Q.108 Which of the following make use of 4 wires for its operation?
a. USB b. CAN c. SPI d. I2C Ans: c
Q.109 Which of the following is a full duplex communication interface?
a. I2C b. 1 – Wire c. SPI d. 2- Wire Ans: c
Q.110 Which of the following is true about MOSI signal?
a. Signal Line carrying the clock signal
b. Signal line for slave select
c. Signal line carrying the data from master to slave device
d. Signal line carrying the data from slave to master device Ans: c
Q.111 Which of the following supports only point to point communication and not
suitable for multi drop communication
a. RS485 b. RS232 c. RS422 d. Rs484 Ans: b
Q.112 Which of the following is a low cost, low power, short range wireless
communication for voice and data
a. Wi-Fi b. Infrared c. Zigbee d. Bluetooth Ans: d
Q.113 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.114 Which bits exhibit and signify the termination phase of the character
transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above Ans: b
Q.115 Two wire interfaces is also called as
a. UART b. SPI c. I2C d. USART Ans: c
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit I MCQs
Q.1 A computer accepts data from the user processes the data according to the
instructions given and produces the desired output result.
A. True B. False Ans: True
Q.2 RAM stands for
A. Rigid Access memory B. Register Accumulator Memory
C. Random Access Memory D. None of the above Ans:C
Q.3 A single IC which consists of ALU, control section and Register section is called
as
A.Microprocessor B. Microcontroller
C.Minicomputer D. None of the above Ans:A
Q.4 What is the name of the system which carries only the control and timing
signals
A. Address Bus B. Data Bus C. Control Bus D. System Bus Ans:C
Q.5 The various ways of specifying the data is called .
A. Instruction B. Assembler Directive C. Addressing Mode Ans:C
Q.6 Interpreter translates language into machine level language and the
translation is done line by line.
A. Low B. High Ans:B
Q.7 Complier translates high-level language into .
A. Machine level language B. Assembly Level Language
C. C Language D. Low Level Language Ans:A
Q.8 enables the programmers to run the program step by step so that the
programmer can find out the exact location of the error.
A. Assembler B. Linker C. Loader D. Debugger Ans:D
Q.9 Memory addressing mode can be divide into groups.
A. 1 B. 2 C. 3 D. 4 Ans:B
Q. 10 CALL instruction transfers the control of execution of the program to the
subroutine or procedure
A. True B. False Ans:A
Q.11 A macro is unlike a in that the machine instructions are repeated each
time the macro is referenced.
A. Procedure B. Call C. Return D. Assembler Ans:A
Q.12 The meaning of ‘interrupts’ is to break the sequence of operation.
A. True B. False Ans:A
Q.13 The process of interrupting the normal program execution to carry out a specific
task/work is referred to as .
A. Interrupt B. ISR C. Macro D. Procedure Ans:A
Q.14 Register that is used to hold the memory address of the next instruction to be
executed is
A. Program Memory B. Program Counter
C. Control Unit D. Instruction Decoder Ans:B
Q.15 Which register is used to store the output generated by ALU?
A. SFR B. GPR C. Accumulator (W) D. SP Ans:C
Q.16 The has built-in ROM,RAM, Parallel I/O, Serial I/O, counters and
clock circuit.
A. Microcontroller B. Microprocessor
C. Mainframe computers D. none of the above Ans: A
Q.17 PIC uses architecture.
A. Von Neumann B. Harvard Ans: B
Q.18 The PIC can control up to independent interrupt sources.
A. 6 B. 8 C. 10 D. 12 Ans: D
Q.19 The instruction set of PIC consists of instructions.
A. 66 B. 77 C. 88 D. 99 Ans:B
Q.20 In PIC memory sizes from 8 to 128 KB.
A. ROM B. Flash Program C. RAM Ans:B
Q.21 The PIC is High performance processor.
A. RISC B. CISC Ans: A
Q.22 The PIC has bit ADC.
A. 8 B. 9 C. 10 D. 12 Ans: C
Q.23 The PIC has CCP Modules
A. 4 B. 5 C. 6 D. 7 Ans: B
Q.24 Out of 40 Pins, 33 pins are dedicated to Ports of PIC.
A.4 B. 5 C. 6 D. 7 Ans: B
Q.25 RESET pin is in the PIC.
A. WR’ B. OSC C. MCLR’ D. ECCP Ans: C
Q.26 used for control and status of the controller and peripheral functions.
A. SFRs B. GPRs C. WREG D. FSRs Ans: A
Q.27 used for data storage and scratchpad operations in the user’s
application.
A. SFRs B. GPRs C. WREG D. FSRs Ans: B
Q.28 acts as an Accumulator.
A. SFRs B. GPRs C. WREG D. FSRs Ans: C
Q.29 register that stores flags- indicates the status of the operation done
by ALU.
A. Status B. SFR C.GPR D. FSR Ans:A
Q.30 is a 4 bit register used in Direct addressing the data memory.
A. Status B. SFR C.GPR D. BSR Ans:D
Q.31 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.32 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.33 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.34 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.35 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.36 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.37 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.38 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C.Over Flow D. Zero Ans:D
Q.39 Flag is set whenever the result of signed number operation is too large,
causing the high order bit to over flow in to sign bit.
A. Carry B. Negative C.Over Flow D. Zero Ans:C
Q. 40 After execution of ALU operations, if bit 7 of the result is 1, the flag is set
indicating result is negative.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:D
Q. 41 In PIC, the data memory is implemented as static RAM. It is also known as _
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q. 42 When using addressing, the BSR is used to select the desired bank.
A. Direct B. Indirect C. Implied D. Immediate Ans: A
Q. 43 Indirect addressing requires use of .
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q.44 Each FSR holds a bit address value that can be used to access any location
in the data memory map without banking.
A. 10 B. 11 C. 12 D. 13 Ans: C
Q.45 Upon reset BSR= H.
A. 001B B. 0000 C. 0FFF D. FFFF Ans:B
Q.46 Immediate data is also called Literal in PIC18.
A. True B. False Ans:A
Q.47 In addressing mode, the letter ‘F’ in the instruction means the address of
the File Register location.
A. Direct B. Indirect C. Immediate D. Register Ans:D
Q.48 The ECIO oscillator mode functions like the EC mode, except that the
OSC2 pin becomes an additional general purpose I/O pin.
A. True B. False Ans:A
Q.49 The PLL can only be enabled when the oscillator configuration bits are
programmed for HS mode.
A. True B. False Ans:A
Q.50 In the Sleep mode, the on-chip clocks and oscillator are turned off.
A. True B. False Ans:A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit II MCQs
Q.1 When does it become possible for a bit to get accessed from bank '0' in the direct
addressing mode of PICs?
A. Only when RPO bit is set 'zero'
B. Only when RPO bit is set '1'
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.2 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to
turn on the weak internal pull-ups of port B?
A. RPO’ B. RPBU’ C. RBIF D. All of the above Ans:B
Q.3 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of 'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.4 Which digital operations are performed over the detected mismatch outputs with
an intention to generate a single output RB port change output?
A. OR B. AND C. EXOR D. NAND Ans: A
Q.5 How many clock pulses are confined by each machine cycle of Peripheral-Interface
Controllers?
A. 4 B. 8 C.12 D. 16 Ans:A
Q.6 Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
A. Carry (C) Flags B. Zero (Z) Flags
C. Digit Carry (DC) Flags D. All of the above Ans:D
Q.7 What is the execution speed of instructions in PIC especially while operating at the
maximum value of clock rate?
A. 0.1 μs B. 0.2 μs C. 0.4 μs D. 0.8 μs Ans: B
Q.8 Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?
A. Built-in Power-on-reset B. Brown-out reset
C. Both a & b D. None of the above Ans:B
Q.9 Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
A. Improvement in bandwidth
B. Instruction fetching becomes possible over a single instruction cycle
C. Independent bus access provision to data memory even while accessing the
program memory
D. All of the above Ans:D
Q.10 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C
B. C&D
C. A, B & D
D. A, B & C Ans:D
Q.11 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT)
B. Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT)
D. All of the above Ans:C
Q. 12 Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
A. Status Register
B. Program Counter Latch (PCLATH) Register
C. Program Counter Low Byte (PCL) Register
D. File Selection Register (FSR) Ans: B
Q.13 Which register/s is/are mandatory to get loaded at the beginning before loading or
transferring the contents to corresponding destination registers?
A. W B. INDF C. PCL D. All of the above Ans: A
Q.14 How many RPO status bits are required for the selection of two register banks?
A. 1 B.2 C. 8 D. 16 Ans: A
Q.15 The RPO status register bit has the potential to determine the effective address
of
A. Direct Addressing Mode
B. Indirect Addressing Mode
C. Immediate Addressing Mode
D. Indc. Watchdog Timer (WDT) exed Addressing Mode Ans:A
Q.16 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B. Digits Carry bit (DC)
C. Both A & B D. None of the above Ans:B
Q.17 Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
A. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
B. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
C. Address byte must be written in FSR at the same time during the execution of
INDF instruction in indirect addressing mode
D. Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode
A. Only A B. Only B C. Only A & B D. A & D Ans:A
Q.18 Which among the below stated registers specify the address reachability within 7
bits of address independent of RP0 status bit register?
A. PCL B. FSR C. INTCON D. All of the above Ans:D
Q.19 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th Bit B. 12th Bit C. 13th Bit D. 14th Bit Ans:C
Q.20 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B. Low C. Moderate D. All of the above Ans:B
Q.21 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor Ans:A
Q.22 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 Cycles B. 1024 Cycles C. 2048 Cycles D.4096 Cycles Ans:B
Q.23 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode
B. Sleep mode
C. Power-down mode
D. Any flexible mode Ans:B
Q.24 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A. For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.25 Which program location is allocated to the program counter by the reset function
in Power-on-Reset (POR) action modes?
A. Initial address
B. Middle address
C. Final address
D. At any address reliable for reset operations Ans:A
Q.26 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans:B
Q. 27 Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
A. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
A. A & B B. C & D C. A & C D. B & D Ans:B
Q.28 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.29 What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
A. (1/2) x frequency of OSC1
B. (1/4) x frequency of OSC1
C. (1/8) x frequency of OSC1
D. (1/16) x frequency of OSC1 Ans:C
Q.30 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC
B. LP (Low-Power Clocking)
C. XT
D. HS (High Speed) Ans:B
Q.31 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy
B. Proficiency in time generation
C. Applicability in real-time operations
D. All of the above Ans:A
Q.32 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ ceramic/ resonator or any other external clock source?
A.0-4 MHz B. 5-200 KHz C.100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.33 How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
A. 4 & 8 bits B. 8 & 16 bits C. 11 & 12 bits D. 12 & 16 bits Ans:C
Q.34 When do the special address 004H get automatically loaded into the program
counter?
A. After the execution of RESET action in program counter
B. After the execution of ‘goto Mainline ‘ instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.35 How many bits are utilized by the instruction of direct addressing mode in order to
address the register files in PIC?
A. 2 B.5 C.7 D.8 Ans:C
Q.36 Which registers are adopted by CPU and peripheral modules so as to control and
handle the operation of device inhibited in RFS?
A. General Purpose Register
B. Special Purpose Register
C. Special Function Register
D. All of the above Ans:C
Q.37 Which among the below specified registors are addressable only from bank1 of
RFS?
A. PORTA (05H)
B. PORTB (06H)
C. FSR (04H)
D. ADCON0 (07H) Ans:A
Q.38 Which register acts as an input-output control as well as data direction register for
PORTA in bank 2 of RFS?
A. INDF (80H) B. TRISB (85H) C. TRISA (85H) D. PCLATH (8A) Ans:C
Q.39 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1
B. Only Bank 2
C. Either Bank 1 or Bank 2
D. Neither Bank 1 nor Bank 2 Ans:C
Q.40 Which bit of OPTION register has a potential to decide the falling or rising edge
sensitivity for the external interrupt INT?
A. RBPU B.INTEDG C.PSA D.RTS Ans:B
Q.41 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC
B. Only Watchdog timer
C. Either RTCC or Watchdog timer
D. Neither RTCC nor Watchdog timer Ans:C
Q.42 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C.ADRES D.PCLATH Ans:B
Q.43 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B.ADIE C.RBIE D.TOIE Ans:A
Q.44 When does it become possible for a bit to get accessed from bank ‘0’ in the direct
addressing mode of PICs?
A. Only when RPO bit is set ‘zero’
B. Only when RPO bit is set ‘1’
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.45 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of ‘interrupt on change’?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.46 What is the purpose of acquiring two different bits from INTCON register for
performing any interrupt operation in PIC 16C61 / 71?
A. One for enabling & one for disabling the interrupt
B. One for enabling the interrupt & one for its occurrence detection
C. One for setting or clearing the RBIE bit
D. None of the above Ans:B
Q.47 What kind of external edge-sensitive interrupt is generated due to transition effect
at pin RBO/INT?
A. INT
B. RBO
C. INTF
D. All of the above Ans:A
Q.48 Consider the following statements. Which of them is /are incorrect?
A. By enabling INTE bit of an external interrupt can wake up the processor before
entering into sleep mode.
B. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
C. During the occurrence of interrupt, GIE bit is set in order to prevent any further
interrupts.
D. goto instruction written in program memory cannot direct the program control to
ISR.
A. A & B
B. C & D
C. Only A
D. Only C Ans:B
Q.49 What is the purpose of setting TOIE bit in INTCON along with GIE bit?
A. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow
interrupt
B. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow
interrupt
C. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
D. None of the above Ans:A
Q.50 Which command enables the PIC to enter into the power down mode during the
operation of watchdog timer (WDT)?
A. SLEEP B. RESET C. STATUS D. CLR Ans:A
Q.51 How much delay is required to sunchronize the externalclock at TOCKI in Timer 0
of Pic16FXXX?
A. 2 cycles B. 4cycles C. 6cycles D. 8cycles Ans:A
Q.52 How much time is required for conversion per channel if PIC possesses four analog
channels, each comprising of 8 bits?
A. 10 µs B.15 µs C.20 µs D. 25µs Ans: C
Q.53 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT) B.Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT) D.All of the above
Ans:C
Q.54 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B.Digits Carry bit (DC)
C. Both a & b D.None of the above Ans:B
Q.55 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th bit B.12th bit C.13th bit D.14th bit Ans:C
Q.56 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B.Low C. Moderate D. All of the above Ans:B
Q.57 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor
Ans:A
Q.58 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode B.Sleep mode C.Power-down mode D.Any flexible mode Ans:B
Q.59 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 cycles B.1024 cycles C.2048 cycles D. 4096 cycles Ans:B
Q.60 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A.For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.61 Which program location is allocated to the program counter by the reset function
in Power-onReset (POR) action modes?
A. Initial address B.Middle address
C.Final address D.At any address reliable for reset operations Ans: A
Q.62 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans: B
Q.63 What output is generated by OSC2 pin in PIC oscillator comprising RC components
for sychronizing the peripherals with PIC microcontroller?
A.(1/2) x frequency of OSC1
B.(1/4) x frequency of OSC1
C.(1/8) x frequency of OSC1
D.(1/16) x frequency of OSC1 Ans: C
Q.64 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans: A
Q.65 What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
A.CPU resets PIC once again in BOR mode
B.BOR reset mode gets disabled
C.PIC does not remain in BOR mode until the voltage increases irrespective of
stability
D.Power-up timer kills 72ms more again
Ans: A
Q.66 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC B.LP (Low-Power Clocking) C. XT D. HS (High Speed) Ans: B
Q.67 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy B.Proficiency in time generation
C. Applicability in real-time operations D.All of the above Ans:D
Q.68 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ceramic/ resonator or any other external clock source?
A. 0-4 MHz B. 5-200 KHz C. 100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.69 Which bits play a crucial role in specifying the details or reasons associated with
the system wake-up in WDT?
A. PD’ & TO’ B. C & Z C. DC & RPO D. All of the above Ans:A
Q.70 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B. ADIE C. RBIE D. TOIE Ans: A
Q.71 Which instruction is applicable to set any bit while performing bitwise operation
settings?
A. bcf B. bsf C. Both A & B D. None of the above Ans:B
Q.72 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
A. Provision of MPLAB specific extensions
B. Floating-point Format Support
C. Data in Program Memory
D. All of the above Ans:D
Q.73 What does the 'program idata' section of data memory contain in C-18 Compiler?
A. statically assigned/allocated initialized user variables
B. statically assigned /allocated uninitialized user variables
C. only executable instructions
D. variables as well as constants Ans:A
Q.74 Where is the result stored after an execution of increment and decrement operations over
the special - purpose registers in PIC?
A. File Register B. Working Register C. Both A & B D. None of the above Ans:C
Q.75 Which flags of status register are most likely to get affected by the single-cycle increment
and decrement instructions?
A. P Flags B. C Flags C. OV Flags D. Z Flags Ans:D
Q.76 Which command-line option of compiler exhibits the banner comprising overall number of
errors, messages, warnings and version number after an accomplishment of the
compilation process?
A. help B. verbose C. overlay D. char Ans:B
Q.77 Which among the below assertions represent the salient features of PIC in C-18 compiler?
A. Transparent read/ write access to an external memory
B. Provision of supporting an inline assembly during the necessity of an overall control
C. Integration with MPLAB IDE for source-level debugging
D. All of the above Ans:D
Q.78 Which bit plays a salient role in defining the master or slave mode in TXSTA register
especially in synchronous mode?
A. RSRC B. CSRC C. SPEN D. SYNC Ans:B
Q.79 What is the status of shift clock supply in an USART synchronous mode?
A. Master-internally, Slave-externally
B. Master-externally, Slave-internally
C. Master & Slave (both) - internally
D. Master & Slave (both) – externally Ans:A
Q.80 When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of
'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.81 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn
on the weak internal pull-ups of port B?
A.RPO B.RPBU’ C. RBIF D.All of the above Ans:B
Q.82 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C. ADRES D.PCLATH Ans:B
Q.83 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC B. Only Watchdog timer
C. Either RTCC or Watchdog timer D. Neither RTCC nor Watchdog timer Ans:C
Q.84 Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity
for the external interrupt INT?
A. RBPU B. INTEDG C. PSA D. RTS Ans:B
Q.85 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1 B. Only Bank 2
C. Either Bank 1 or Bank 2 D. Neither Bank 1 nor Bank 2 Ans:C
Q.86 Which register acts as an input-output control as well as data direction register for PORTA
in bank 2 of RFS?
A. INDF B. TRISB C.TRISA D.PCLATH Ans:C
Q.87 Which registers are adopted by CPU and peripheral modules so as to control and handle
the operation of device inhibited in RFS?
A. General Purpose Register B. Special Purpose Register
C. Special Function Registers D. All of the above Ans:C
Q.88 How many bits are utilized by the instruction of direct addressing mode in order to address
the register files in PIC?
A. 2 B. 5 C. 7 D. 8 Ans:C
Q.89 When do the special address 004H get automatically loaded into the program counter?
A. After the execution of RESET action in program counter
B. After the execution of 'goto Mainline ' instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.90 Which significant feature/s of crystal source contribute/s to its maximum predilection and
utility as compared to other clock sources?
A. High accuracy B. Proficiency in time generation
C. Applicability in real-time operations D. All of the above Ans:D
Q.91 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely
unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.92 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C B. C & D C. A, B & D D. A, B & C Ans:D
Q.93 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.94 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.95 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.96 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.97 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.98 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.99 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.100 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C. Over Flow D. Zero Ans:D
Question Option A Option B Option C
By which of the following method(s)
devices receive service from the Interrupts Polling Both of these
microcontroller?
Asynchronous request for service by
peripherals to processor is known as Interrupt Polling Both of these
____
Which of the following can cause Serial data Serial data
Timer overflow
interrupt generation? reception transmission
In which of the following method(s)
priority can be assigned to the devices Interrupts Polling Both of these
demanding for service?
In which of the following method(s)
microcontroller can not ignore a device Interrupts Polling Both of these
request for service?
Which of the following method(s) waste
Interrupts Polling Both of these
microcontroller’s time
Input Interrupt
Input Service
Full form of ISR is_______ Synchronous Synchronous
Routine
Routine Routine
Input Vector Inerrupt Input Vector
Full form of IVT is_______
Table Vector Table Testbench
Power on Reset Vector in PIC 18 is
0000 0008 0018
_____h
High Priority Interrupt Vector in PIC 18 is
0000 0008 0018
_____h
Low Priority Interrupt Vector vector in
0000 0008 0018
PIC 18 is _____h
Fixed locations in memory that holds
IGT IMT IRT
addresses of ISRs are called as ____
Correct sequence of steps in executing
an interrupt is ______ Where 1=Execute
1-2-3-4 3-2-1-4 4-3-2-1
ISR, 2= Consult IVT, 3=Save PC on stack
and 4=Jump to ISR
While servicing an interrupt content of
PC MAR MBR
____ register are saved on the stack
What is the status of interrupts in PIC 18 All are Some are
All are enabled
after power on or reset? disabled enabled
____ bit is used for enabling/disabling of
FIE GIE HIE
all interrupts
Global Interrupt Enable (GIE) bit is
INTCON RCON PIR
present in ______ register
Interrupt Priority Enable (IPEN) bit is
INTCON RCON PIR
present in ______ register
Option D Answer
None of these C
None of these A
All of these D
None of these A
None of these B
None of these B
Interrupt
Service D
Routine
Interrupt
Vector B
Testbench
0028 A
0028 B
0028 C
IVT D
3-2-4-1 D
IR A
None of these B
JIE B
PIE A
PIE B
Peripheral Interrupt Enable (PEIE) bit is
INTCON RCON PIR
present in ______ register
To enable serial communication
interrupts which of the following bit(s) Only GIE Only PEIE Both of these
must be set?
To enable timer 0 interrupt which of the
Only GIE Only PEIE Both of these
following bit(s) must be set?
There are ___ registers to control
11 12 13
interrupt operation in PIC 18
In PIC18F, any interrupt source is
enabled when corresponding IE bit is 0 1 X
____.
Which of the following bit(s) control
operation of an interrupt source in Flag bit Enable bit Priority bit
PIC18 F?
The default ISR address in PIC18F is
0000 0008 0018
_____ h
Which of the following bit(s) indicate
Flag bit Enable bit Priority bit
that an interrupt event has occurred?
Which of the following bit(s) is used to
Flag bit Enable bit Priority bit
assign priority to an interrupt?
Setting of ___ and ____ bit allows
Enable,
program execution to branch to the Flag, Enable Flag, Priority
Priority
interrupt vector address.
If the interrupt is one of the peripheral
(timers 1,2 , serial, etc. ) we need to set
TMR0IE INT0IE PEIE
____ bit from INTCON register along
with GIE bit.
Which of the following interrupt has no
INT3 INT2 INT1
priority bit?
_____ interrupt has default high
INT0 INT1 INT2
priority.
For any interrupt source, to assign high
priority the corresponding IP bit must be 0 1 X
____.
For any interrupt source, to assign low
priority the corresponding IP bit must be 0 1 X
____.
Which of the following is not a core
TMR0 INT0 INT1
interrupt source?
Which of the following is not a
TMR3 TMR2 TMR1
peripheral interrupt source?
Which of the following is not a
TMR1 INT0 TMR2
peripheral interrupt source?
PIE A
None of these B
None of these A
14 C
None of these D
All of these D
0028 B
All of these A
All of these C
All of these A
RBIE C
INT0 D
All of these D
None of these B
None of these A
Serial
D
Transmit
TMR0 D
Serial
B
Transmit
Upon power-on reset the external Negative
Positive edge Positive level
hardware interrupts INT0-INT2 are of edge
triggered triggered
type _____. triggered
Which of the following avoids tying
Interrupts Polling Both of these
down the microcontroller?
PIC 18 ha ____ external hardware
1 2 3
interrupts.
External hardware interrupts of PIC18F
E D C
are multiplexed with port ____ lines.
PORTB-change interrupt is assocaied
4 3 2
with _____ lines of PORTB.
PORTB-change interrupt is assocaied
RB0-RB3 RB2-RB5 RB3-RB6
with _____ lines of PORTB.
Register Select pin of LCD selects_____
Status Command Data
register when it is 0.
Register Select pin of LCD selects_____
Status Command Data
register when it is 1.
In LCD, R/W = 0 is _____ mode Read Write Both of these
In LCD, R/W = 0 is _____ mode Read Write Both of these
Negative level
A
triggered
None of these A
4 C
B D
1 A
RB4-RB7 D
Program B
Program C
None of these B
None of these A
Question Option A Option B
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard
Neumann
1
PIC stands for _______ Peripheral Peripheral
Intelligent Interface
2 Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20
4
Genearl features of PIC 18F controller Watchdog
Timers
5 are ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC
6
PIC 18F452 has ____ program ROM
1 kB 2 kB
7
PIC 18F452 has ____ kB data RAM
1 2
8
___ address lines are used to access
4 8
9 data RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4
11
Which of the following is not a 8 bit
A B
12 port?
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4
14
FLASH Program Memory of PIC18F452 is _______
128K 64K
15
PIC18F452 has total _____ pins .
40 20
16
Instruction set of PIC18F452 has
_________instructions 33 35
17
PIC18F452 has _____ ADC 8 BIT 10 BIT
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4
19
PIC18F452 has power down modes :
sleep, deep
sleep, idle
sleep
20
Option C Option D Answer
Both of these None of these A
Programmabl Programmable
e Interface Intelligent B
Controller Controller
16 32 B
30 40 D
ADC All of these D
Both of these None of these A
1 MB 2 MB D
4 8 C
12 16 C
20 21 D
5 6 C
C D A
7 8 B
5 6 A
32K 16K C
16 8 A
40 75 D
12 BIT 14 BIT B
A,B,C,D,E A,B,C C
deep sleep,
idle, deep
deep power A
sleep
down
WDT stands for _______ Watch Watch Dog
21 Down Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit
22
Each instruction has two parts
Opcode and Opcode and
Register Operand
23
ADDWFC, SUBWF are
Move and
Arithmatic
Load
Instructions
instructions
24
MSSP stands for_____ Master
Master
Synchronou
Synchronou
s Serial
s slave Port
25 Peripheral
Flag 'N' in Status register of PIC18F452 denotes Negative
Zero Flag
26 Flag
How many banks are available in PIC 18F452
12 16
27
What is the significance of "d=0" bit in
Result
ADDWF F D a Undefined
saved in F
28
BOD' stands for Brown OR Brown out
Reset Reset
29 Detection Detection
Circuit used for initialization of all values to default is named
Brown
as Out
Power-On
Detection
Reset Circuit
30 Circuit
In Immediate (Literal) addressing mode
The operand is _____ that follows the a register a number
31 opcode
PIC18F452 has power down modes as ____ deep power
Idle and
down and
sleep
32
idle
PIC18F452device can be operated
in____ oscillator Configuration modes. 10 12
33
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and
Configuration registers as _______ and
OSCCONFIG
CONFIG2
34
2
MSSP module of PIC18F452 has ADC and
SPI and I2C
35 PWM
USART means Univeral Univeral
Synchrnous Synchrnous
Asynchrono Asymmatric
us Register Receive
36 Transmit Transmit
Width Delay Watch Delay
B
Timer Timer
20-bit 21-bit D
Operand and Opcode and
B
Register Pointer value
Branch Logical
A
instructions instructions
Master
Master Slave
Synchronous C
Serial Port
Serial Port
Overflow Flag Carry Flag B
10 14 B
Results saved Ressult Saaved
D
in F and W in W
Brown out Board on Reset
B
Reset Debug Detection
Power
ON/OFF WDT circuit A
circuit
a pointer an address B
deep sleep and
sleep and
deep power A
deep sleep
down
14 16 B
CONFIG1L and None of the
C
CONFIG1H above
USART and
I2C and PWM B
CCP
Univeral
Univeral Serial
Synchrnous
Asynchronous
Asynchronous C
Receive
Receive
Transmit
Transmit
CONFIG2L is used for Frequency Background
37
Selection debugger
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontr
for oller in
peripherals standby
38 OFF mode
Where is the result stored after an
execution of increment and decrement Working
File Register
operations over the special - purpose Register
39 registers in PIC?
Which status bits exhibit carry from
lower 4 bits during 8-bit addition and Digits Carry
Carry bit
are especially beneficial for BCD bit (DC)
40 addition ?
Watch dog
Reset voltage D
timer
Resets all the
Set all registers B
registers
None of the
Both a & b C
above
None of the
Both a & b B
above
Question Option A Option B Option C Option D
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32
registers
______ is a ON/OFF control bit of
TMR0ON T08BIT T0CS T0SE
Timer0.
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if
the oscillator frequency is F MHz with F Mhz F/2 Mhz F/4 Mhz F/8 Mhz
no prescalar?
In time delay generation for Timer1,
Fh FF h FFF h FFFF h
what is the Maximum count?
Calculate total delay generated by
Timer0 if FFF6 h is loaded into it. 5.6 μS 5.2 μS 4.6 μS 4 μS
Assume crystal frequency = 10 MHz
Answer
D
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of
FB h FC h FD h FE h
256 to generate time delay of 5
milliseconds. Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
frequency = 16 MHz and prescaler of 1: 0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz
16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair FFFF h 1234 h 0000 h 4321 h
for generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L
operation?
Which of the prescaler options are not
2 4 8 16
available in Timer1 programming?
Number of prescale options available in
16 8 4 2
Timer0 are ____
Number of prescale options available in
16 8 4 2
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6
I/O ports
Which of the following is not a 8 bit
A B C D
port?
Size of Port A in PIC 18 microcontroller is
5 6 7 8
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0
rollover?
A
B
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2
______ register.
Number of postscale options available in
16 8 4 2
Timer2 are ____
Number of prescale options available in
1 2 3 4
Timer2 are ____
______ is a ON/OFF control bit of
TMRxON Tx8BIT TxCS TxSE
Timerx.
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx
Upon reset every port of PIC 18 controller is None of
output input bidirectional
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111
_______
Which of the following instruction is used to
BSF BCG BTG BMF
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF
toggle a file register bit?
C
D
B
C
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit IV MCQs
Q.1 How does the pin RC2/CCP1 get configured while initializing the CCP module in the
compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans:d
Q.2 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans:a
Q.3 The capture operation in counter mode is feasible when mode of CCP module is
__ _ __
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
Ans:a
Q.4 Which register is suitable for the corresponding count, if the measurement of pul se
width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
Ans:c
Q.5 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR Ans:a
Q.6 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.7 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.8 Which among the below mentioned aspect issues are supported by
capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
Ans:d
Q.9 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.10 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.11 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
Ans:a
Q.12 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans: a
Q.13 How does the pin RC2/CCP1 get configured while initializing the CCP module in
the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans: b
Q.14 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0
Ans: a
Q.15 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
Ans: b
Q.16 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.17 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value
Ans: b
Q.18 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter ?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components
Ans: a
Q.19 In ____ _ data transfer, group of bits (usually 8 bits) of data is transferred at a
time.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.20 In ____ _ data transfer, only one bit of data is transferred at a time.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.21 In Parallel data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: a
Q.22 In Serial data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: b
Q.23 Most of the Microprocessor/Microcontrollers are designed for______ communication.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.24 In _____ data communication, during transmission parallel data is converted into
serial bits using a PISO shift register.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.25 At the receiver, the serial bits are connected into parallel data by another shift
register called SIPO register.
a. TRUE b. FALSE Ans: a
Q.26 In ____ __, the hardware exists such that data transfer takes place only in one
direction.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.27 The transmission form a computer to the printer is an example of ____ _ _
communication.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.28 The ______ transmission allows the data transfer in both directions, but not
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.29 Walkie-talkie is an example of ________ _.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.30 The ______ transmission allows the data transfer in both directions
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q. 31 Telephone lines is an example of ____ _ .
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q.32 Types of serial data communication:
a. Asynchronous serial data communication
b. Synchronous serial data communication
a. TRUE b. FALSE Ans: a
Q.33 The serial communication is
a. cheaper communication
b. requires less number of conductors
c. slow process of communication
d. all of the mentioned Ans: d
Q.34 The serial communication is used for
a. short distance communication
b. long distance communication
c. short and long distance communication
d. communication for a certain range of distance Ans: b
Q.35 The number of bits transmitted or received per second is defined as
a. transmission rate
b. reception rate
c. transceiver rate
d. baud rate Ans: d
Q.36 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.37 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.38 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0 Ans: a
Q.39 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above Ans: b
Q.40 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.41 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value Ans: b
Q.42 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components Ans: a
Q.43 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.44 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.45 What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave
mode by enabling SS pin control?
a. 0000 b. 0100 c. 0010 d. 0001 Ans: b
Q.46 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above Ans: a
Q.47 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.48 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above Ans: b
Q.49 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c. 16 d. 32 Ans: a
Q.50 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above Ans: a
Q.51 What is the purpose of a special function register SPBRG in USART?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above Ans: a
Q.52 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the
data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.53 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode?
a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1) Ans: b
Q.54 What is the status of shift clock supply in an USART synchronous mode?
a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally Ans: a
Q.55 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.56 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as
DT (data lines)?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.57 Which among the below assertions represent the salient features of PIC in C-18
compiler?
a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above Ans: d
Q.58 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above Ans: d
Q.59 Which flags of status register are most likely to get affected by the single-cycle
increment and decrement instructions?
a. P Flags b. C Flags c. OV Flags d. Z Flags Ans: d
Q.60 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.61 In ____ _ _ communication, transmitters and receivers are not synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: a
Q.62 In ____ _ _ communication, transmitters and receivers are synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: c
Q.63 In Asynchronous Serial communication, bits of data are transmitted at constant
rate.
a. TRUE b. FALSE Ans: a
Q.64 In Synchronous Serial communication, bits of data are transmitted with
synchronization of clock.
a. TRUE b. FALSE Ans: a
Q.65 In Asynchronous Serial communication, character may arrive at any rate at
receiver.
a. TRUE b. FALSE Ans: a
Q.66 In Synchronous Serial communication, is received at constant rate.
a. TRUE b. FALSE Ans: a
Q.67 In Asynchronous Serial communication, data transfer is character oriented.
a. TRUE b. FALSE Ans: a
Q.68 In Synchronous Serial communication, data transfer takes place in blocks.
a. TRUE b. FALSE Ans: a
Q.69 Baud Rate is data transmission speed.
a. TRUE b. FALSE Ans: a
Q.70 The rate at which the bits are transmitted (bits/second) is called ____ _.
a. speed b. bit rate c. baud d. sample Ans: c
Q.71 The common baud rates are multiplies of _____ bits/second.
a. 25 b. 50 c. 75 d. 100 Ans: c
Q.72 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.73 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.74 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD b. SSPBUF c. Both a & b d. None of the above Ans: a
Q.75 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.76 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line b. SDA line c. Both a & b d. None of the above Ans: b
Q.77 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c.16 d.32 Ans: a
Q.78 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA b. RCSTA c. SPBRG d. All of the above Ans: a
Q.79 What is the purpose of a special function register SPBRG in USART ?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bitr
d. All of the above Ans: a
Q.80 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all
the data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.81 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode ?
a. FOSC / 8 (X +1 )
b. FOSC / 16 (X +1 )
c. FOSC / 32 (X +1 )
d. FOSC / 64 (X +1 ) Ans: b
Q.82 What is the status of shift clock supply in an USART synchronous mode?
a. Master - internally, Slave - externally
b. Master - externally, Slave - internally
c. Master & Slave (both) - internally
d. Master & Slave (both)- externally Ans: a
Q.83 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode ?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.84 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins
as DT (data lines) ?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.85 Two wire interfaces is also called as _____ __
a. UART b. SPI c. I2C d. USART Ans: c
Q.86 I2c will address large number of slave devices.
a. True b. False Ans: a
Q.87 SDA is having a transition when the clock line SCL is high.
a. high to low b. low to high c. low to low d. high to high Ans: a
Q.88 Inter Integrated Circuit is a
a. Single master, single slave
b. Multi master, single slave
c. Single master, multi slave
d. Multi master, multi slave Ans: d
Q.89 Typical voltages used are _
a. 5v b. 3.3v c. 5v or 3.3v d. 2.5v Ans: c
Q.90 What is the speed of I2C bus?
a. 100 kbits/s b. 10 kbits/s c.75 kbits/s d.100 kbits/s and 10 kbits/s Ans: d
Q.91 Master transmits means
a. Master node is sending data to a slave
b. Master node is receiving data from slave
c. Slave node is transmitting data to master
d. Slave node is sending data to master Ans: a
Q.92 Who sends the start bit?
a. Master receive
b. Master transmit
c. Slave transmit
d. Slave receive Ans: b
Q.93 Which is the I2C messaging example?
a. 24c32 EPROM
b. 24c32 EEPROM
c. 24c33 EEPROM
d. 24c33 EPROM Ans: b
Q.94 Are pull up registers required in I2C?
a. True b. False Ans: a
Q.95 How many types of addressing structures are there in I2C?
a. 4 types b. 3 types c. 2 types d. 5 types Ans: c
Q.96 All operating modes work under
a. 11 kbit/s b. 100 kbit/s c. 15 kbit/s d. 150 kbit/s Ans: b
Q.97 Which mode is highly compatible and simply tightens?
a. Fast mode
b. High speed mode
c. Ultra fast mode
d. Both fast and high speed mode Ans: a
Q.98 What is the speed for fast mode?
a. 100 kbit/s b. 400 kbit/s c. 150 kbit/s d. 200 kbit/s Ans: b
Q.99 Which of the following is a synchronous serial interface protocol?
a. SPI b. I2C c. UART d. Both (a) and (b) Ans: d
Q.100 Synchronous interfaces make use of clock signal? State True or False
a. True b. False Ans: a
Q.101 Which of the following serial protocol is used for on-board serial communication?
a. USB b. I2C c. Wifi d. Bluetooth Ans: b
Q.102 Which of the following protocol make use of 7 bit address for its operation?
a. I2C b. SPI c. RS232 d. RS485 Ans: a
Q.103 Which of the following interface is used to 127 slave device to the master device?
a. SPI b. I2C c. RS232 d. RS485 Ans: b
Q.104 RS232 protocol makes use of clock signal for sending data? True or False
a. True b. False Ans: b
Q.105 Which serial communication interface is used to connect modems and for non
networked communication between computers and other devices?
a. SPI b. I2C c. UART d. USB Ans: c
Q.106 How many wires are used to connect I2C devices?
a. 1 wire b. 2 wires c. 3 wires d. 4 wires Ans: b
Q.107 Which of the following interface was developed by Motorola Company?
a. I2C b. SPI c. USB d. Bluetooth Ans: b
Q.108 Which of the following make use of 4 wires for its operation?
a. USB b. CAN c. SPI d. I2C Ans: c
Q.109 Which of the following is a full duplex communication interface?
a. I2C b. 1 – Wire c. SPI d. 2- Wire Ans: c
Q.110 Which of the following is true about MOSI signal?
a. Signal Line carrying the clock signal
b. Signal line for slave select
c. Signal line carrying the data from master to slave device
d. Signal line carrying the data from slave to master device Ans: c
Q.111 Which of the following supports only point to point communication and not
suitable for multi drop communication
a. RS485 b. RS232 c. RS422 d. Rs484 Ans: b
Q.112 Which of the following is a low cost, low power, short range wireless
communication for voice and data
a. Wi-Fi b. Infrared c. Zigbee d. Bluetooth Ans: d
Q.113 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.114 Which bits exhibit and signify the termination phase of the character
transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above Ans: b
Q.115 Two wire interfaces is also called as
a. UART b. SPI c. I2C d. USART Ans: c
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit I MCQs
Q.1 A computer accepts data from the user processes the data according to the
instructions given and produces the desired output result.
A. True B. False Ans: True
Q.2 RAM stands for
A. Rigid Access memory B. Register Accumulator Memory
C. Random Access Memory D. None of the above Ans:C
Q.3 A single IC which consists of ALU, control section and Register section is called
as
A.Microprocessor B. Microcontroller
C.Minicomputer D. None of the above Ans:A
Q.4 What is the name of the system which carries only the control and timing
signals
A. Address Bus B. Data Bus C. Control Bus D. System Bus Ans:C
Q.5 The various ways of specifying the data is called .
A. Instruction B. Assembler Directive C. Addressing Mode Ans:C
Q.6 Interpreter translates language into machine level language and the
translation is done line by line.
A. Low B. High Ans:B
Q.7 Complier translates high-level language into .
A. Machine level language B. Assembly Level Language
C. C Language D. Low Level Language Ans:A
Q.8 enables the programmers to run the program step by step so that the
programmer can find out the exact location of the error.
A. Assembler B. Linker C. Loader D. Debugger Ans:D
Q.9 Memory addressing mode can be divide into groups.
A. 1 B. 2 C. 3 D. 4 Ans:B
Q. 10 CALL instruction transfers the control of execution of the program to the
subroutine or procedure
A. True B. False Ans:A
Q.11 A macro is unlike a in that the machine instructions are repeated each
time the macro is referenced.
A. Procedure B. Call C. Return D. Assembler Ans:A
Q.12 The meaning of ‘interrupts’ is to break the sequence of operation.
A. True B. False Ans:A
Q.13 The process of interrupting the normal program execution to carry out a specific
task/work is referred to as .
A. Interrupt B. ISR C. Macro D. Procedure Ans:A
Q.14 Register that is used to hold the memory address of the next instruction to be
executed is
A. Program Memory B. Program Counter
C. Control Unit D. Instruction Decoder Ans:B
Q.15 Which register is used to store the output generated by ALU?
A. SFR B. GPR C. Accumulator (W) D. SP Ans:C
Q.16 The has built-in ROM,RAM, Parallel I/O, Serial I/O, counters and
clock circuit.
A. Microcontroller B. Microprocessor
C. Mainframe computers D. none of the above Ans: A
Q.17 PIC uses architecture.
A. Von Neumann B. Harvard Ans: B
Q.18 The PIC can control up to independent interrupt sources.
A. 6 B. 8 C. 10 D. 12 Ans: D
Q.19 The instruction set of PIC consists of instructions.
A. 66 B. 77 C. 88 D. 99 Ans:B
Q.20 In PIC memory sizes from 8 to 128 KB.
A. ROM B. Flash Program C. RAM Ans:B
Q.21 The PIC is High performance processor.
A. RISC B. CISC Ans: A
Q.22 The PIC has bit ADC.
A. 8 B. 9 C. 10 D. 12 Ans: C
Q.23 The PIC has CCP Modules
A. 4 B. 5 C. 6 D. 7 Ans: B
Q.24 Out of 40 Pins, 33 pins are dedicated to Ports of PIC.
A.4 B. 5 C. 6 D. 7 Ans: B
Q.25 RESET pin is in the PIC.
A. WR’ B. OSC C. MCLR’ D. ECCP Ans: C
Q.26 used for control and status of the controller and peripheral functions.
A. SFRs B. GPRs C. WREG D. FSRs Ans: A
Q.27 used for data storage and scratchpad operations in the user’s
application.
A. SFRs B. GPRs C. WREG D. FSRs Ans: B
Q.28 acts as an Accumulator.
A. SFRs B. GPRs C. WREG D. FSRs Ans: C
Q.29 register that stores flags- indicates the status of the operation done
by ALU.
A. Status B. SFR C.GPR D. FSR Ans:A
Q.30 is a 4 bit register used in Direct addressing the data memory.
A. Status B. SFR C.GPR D. BSR Ans:D
Q.31 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.32 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.33 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.34 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.35 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.36 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.37 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.38 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C.Over Flow D. Zero Ans:D
Q.39 Flag is set whenever the result of signed number operation is too large,
causing the high order bit to over flow in to sign bit.
A. Carry B. Negative C.Over Flow D. Zero Ans:C
Q. 40 After execution of ALU operations, if bit 7 of the result is 1, the flag is set
indicating result is negative.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:D
Q. 41 In PIC, the data memory is implemented as static RAM. It is also known as _
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q. 42 When using addressing, the BSR is used to select the desired bank.
A. Direct B. Indirect C. Implied D. Immediate Ans: A
Q. 43 Indirect addressing requires use of .
A. SFRs B. GPRs C. PC D. FSRs Ans: D
Q.44 Each FSR holds a bit address value that can be used to access any location
in the data memory map without banking.
A. 10 B. 11 C. 12 D. 13 Ans: C
Q.45 Upon reset BSR= H.
A. 001B B. 0000 C. 0FFF D. FFFF Ans:B
Q.46 Immediate data is also called Literal in PIC18.
A. True B. False Ans:A
Q.47 In addressing mode, the letter ‘F’ in the instruction means the address of
the File Register location.
A. Direct B. Indirect C. Immediate D. Register Ans:D
Q.48 The ECIO oscillator mode functions like the EC mode, except that the
OSC2 pin becomes an additional general purpose I/O pin.
A. True B. False Ans:A
Q.49 The PLL can only be enabled when the oscillator configuration bits are
programmed for HS mode.
A. True B. False Ans:A
Q.50 In the Sleep mode, the on-chip clocks and oscillator are turned off.
A. True B. False Ans:A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit II MCQs
Q.1 When does it become possible for a bit to get accessed from bank '0' in the direct
addressing mode of PICs?
A. Only when RPO bit is set 'zero'
B. Only when RPO bit is set '1'
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.2 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to
turn on the weak internal pull-ups of port B?
A. RPO’ B. RPBU’ C. RBIF D. All of the above Ans:B
Q.3 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of 'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.4 Which digital operations are performed over the detected mismatch outputs with
an intention to generate a single output RB port change output?
A. OR B. AND C. EXOR D. NAND Ans: A
Q.5 How many clock pulses are confined by each machine cycle of Peripheral-Interface
Controllers?
A. 4 B. 8 C.12 D. 16 Ans:A
Q.6 Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
A. Carry (C) Flags B. Zero (Z) Flags
C. Digit Carry (DC) Flags D. All of the above Ans:D
Q.7 What is the execution speed of instructions in PIC especially while operating at the
maximum value of clock rate?
A. 0.1 μs B. 0.2 μs C. 0.4 μs D. 0.8 μs Ans: B
Q.8 Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?
A. Built-in Power-on-reset B. Brown-out reset
C. Both a & b D. None of the above Ans:B
Q.9 Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
A. Improvement in bandwidth
B. Instruction fetching becomes possible over a single instruction cycle
C. Independent bus access provision to data memory even while accessing the
program memory
D. All of the above Ans:D
Q.10 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C
B. C&D
C. A, B & D
D. A, B & C Ans:D
Q.11 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT)
B. Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT)
D. All of the above Ans:C
Q. 12 Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
A. Status Register
B. Program Counter Latch (PCLATH) Register
C. Program Counter Low Byte (PCL) Register
D. File Selection Register (FSR) Ans: B
Q.13 Which register/s is/are mandatory to get loaded at the beginning before loading or
transferring the contents to corresponding destination registers?
A. W B. INDF C. PCL D. All of the above Ans: A
Q.14 How many RPO status bits are required for the selection of two register banks?
A. 1 B.2 C. 8 D. 16 Ans: A
Q.15 The RPO status register bit has the potential to determine the effective address
of
A. Direct Addressing Mode
B. Indirect Addressing Mode
C. Immediate Addressing Mode
D. Indc. Watchdog Timer (WDT) exed Addressing Mode Ans:A
Q.16 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B. Digits Carry bit (DC)
C. Both A & B D. None of the above Ans:B
Q.17 Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
A. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
B. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
C. Address byte must be written in FSR at the same time during the execution of
INDF instruction in indirect addressing mode
D. Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode
A. Only A B. Only B C. Only A & B D. A & D Ans:A
Q.18 Which among the below stated registers specify the address reachability within 7
bits of address independent of RP0 status bit register?
A. PCL B. FSR C. INTCON D. All of the above Ans:D
Q.19 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th Bit B. 12th Bit C. 13th Bit D. 14th Bit Ans:C
Q.20 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B. Low C. Moderate D. All of the above Ans:B
Q.21 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor Ans:A
Q.22 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 Cycles B. 1024 Cycles C. 2048 Cycles D.4096 Cycles Ans:B
Q.23 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode
B. Sleep mode
C. Power-down mode
D. Any flexible mode Ans:B
Q.24 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A. For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.25 Which program location is allocated to the program counter by the reset function
in Power-on-Reset (POR) action modes?
A. Initial address
B. Middle address
C. Final address
D. At any address reliable for reset operations Ans:A
Q.26 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans:B
Q. 27 Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
A. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
A. A & B B. C & D C. A & C D. B & D Ans:B
Q.28 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.29 What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
A. (1/2) x frequency of OSC1
B. (1/4) x frequency of OSC1
C. (1/8) x frequency of OSC1
D. (1/16) x frequency of OSC1 Ans:C
Q.30 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC
B. LP (Low-Power Clocking)
C. XT
D. HS (High Speed) Ans:B
Q.31 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy
B. Proficiency in time generation
C. Applicability in real-time operations
D. All of the above Ans:A
Q.32 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ ceramic/ resonator or any other external clock source?
A.0-4 MHz B. 5-200 KHz C.100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.33 How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
A. 4 & 8 bits B. 8 & 16 bits C. 11 & 12 bits D. 12 & 16 bits Ans:C
Q.34 When do the special address 004H get automatically loaded into the program
counter?
A. After the execution of RESET action in program counter
B. After the execution of ‘goto Mainline ‘ instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.35 How many bits are utilized by the instruction of direct addressing mode in order to
address the register files in PIC?
A. 2 B.5 C.7 D.8 Ans:C
Q.36 Which registers are adopted by CPU and peripheral modules so as to control and
handle the operation of device inhibited in RFS?
A. General Purpose Register
B. Special Purpose Register
C. Special Function Register
D. All of the above Ans:C
Q.37 Which among the below specified registors are addressable only from bank1 of
RFS?
A. PORTA (05H)
B. PORTB (06H)
C. FSR (04H)
D. ADCON0 (07H) Ans:A
Q.38 Which register acts as an input-output control as well as data direction register for
PORTA in bank 2 of RFS?
A. INDF (80H) B. TRISB (85H) C. TRISA (85H) D. PCLATH (8A) Ans:C
Q.39 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1
B. Only Bank 2
C. Either Bank 1 or Bank 2
D. Neither Bank 1 nor Bank 2 Ans:C
Q.40 Which bit of OPTION register has a potential to decide the falling or rising edge
sensitivity for the external interrupt INT?
A. RBPU B.INTEDG C.PSA D.RTS Ans:B
Q.41 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC
B. Only Watchdog timer
C. Either RTCC or Watchdog timer
D. Neither RTCC nor Watchdog timer Ans:C
Q.42 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C.ADRES D.PCLATH Ans:B
Q.43 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B.ADIE C.RBIE D.TOIE Ans:A
Q.44 When does it become possible for a bit to get accessed from bank ‘0’ in the direct
addressing mode of PICs?
A. Only when RPO bit is set ‘zero’
B. Only when RPO bit is set ‘1’
C. Only when RPO bit is utilized along with 7 lower bits of instruction code
D. Cannot Predict Ans:A
Q.45 When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of ‘interrupt on change’?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.46 What is the purpose of acquiring two different bits from INTCON register for
performing any interrupt operation in PIC 16C61 / 71?
A. One for enabling & one for disabling the interrupt
B. One for enabling the interrupt & one for its occurrence detection
C. One for setting or clearing the RBIE bit
D. None of the above Ans:B
Q.47 What kind of external edge-sensitive interrupt is generated due to transition effect
at pin RBO/INT?
A. INT
B. RBO
C. INTF
D. All of the above Ans:A
Q.48 Consider the following statements. Which of them is /are incorrect?
A. By enabling INTE bit of an external interrupt can wake up the processor before
entering into sleep mode.
B. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
C. During the occurrence of interrupt, GIE bit is set in order to prevent any further
interrupts.
D. goto instruction written in program memory cannot direct the program control to
ISR.
A. A & B
B. C & D
C. Only A
D. Only C Ans:B
Q.49 What is the purpose of setting TOIE bit in INTCON along with GIE bit?
A. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow
interrupt
B. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow
interrupt
C. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
D. None of the above Ans:A
Q.50 Which command enables the PIC to enter into the power down mode during the
operation of watchdog timer (WDT)?
A. SLEEP B. RESET C. STATUS D. CLR Ans:A
Q.51 How much delay is required to sunchronize the externalclock at TOCKI in Timer 0
of Pic16FXXX?
A. 2 cycles B. 4cycles C. 6cycles D. 8cycles Ans:A
Q.52 How much time is required for conversion per channel if PIC possesses four analog
channels, each comprising of 8 bits?
A. 10 µs B.15 µs C.20 µs D. 25µs Ans: C
Q.53 Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable
operation?
A. Power-Up Timer (PWRT) B.Oscillator Start-Up Timer (OST)
C. Watchdog Timer (WDT) D.All of the above
Ans:C
Q.54 Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
A. Carry bit (C) B.Digits Carry bit (DC)
C. Both a & b D.None of the above Ans:B
Q.55 Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?
A. 11th bit B.12th bit C.13th bit D.14th bit Ans:C
Q.56 Which condition/s of MCLR (master clear) pin allow to reset the PIC?
A. High B.Low C. Moderate D. All of the above Ans:B
Q.57 Generation of Power-on-reset pulse can occur only after
A. the detection of increment in VDD from 1.5 V to 2.1 V
B. the detection of decrement in VDD from 2.1 V to 1.5 V
C. the detection of variable time delay on power up mode
D. the detection of current limiting factor
Ans:A
Q.58 Which kind of mode is favorable for MCLR pin for indulging in reset operations?
A. Normal mode B.Sleep mode C.Power-down mode D.Any flexible mode Ans:B
Q.59 What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
A. 512 cycles B.1024 cycles C.2048 cycles D. 4096 cycles Ans:B
Q.60 What is the purpose of using the start-up timers in an oscillator circuit of PIC?
A.For ensuring the inception and stabilization of an oscillator in a proper manner
B. For detecting the rise in VDD
C. For enabling or disabling the power-up timers
D. For generating the fixed delay of 72ms on power-up timers Ans:A
Q.61 Which program location is allocated to the program counter by the reset function
in Power-onReset (POR) action modes?
A. Initial address B.Middle address
C.Final address D.At any address reliable for reset operations Ans: A
Q.62 When does it become very essential to use the external RC components for the
reset circuits?
A. Only if initialization is necessary for RAM locations
B. Only if VDD power-up slope is insufficient at a requisite level
C. Only if voltage drop exceeds beyond the limit
D. Only if current limiting factor increases rapidly Ans: B
Q.63 What output is generated by OSC2 pin in PIC oscillator comprising RC components
for sychronizing the peripherals with PIC microcontroller?
A.(1/2) x frequency of OSC1
B.(1/4) x frequency of OSC1
C.(1/8) x frequency of OSC1
D.(1/16) x frequency of OSC1 Ans: C
Q.64 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans: A
Q.65 What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
A.CPU resets PIC once again in BOR mode
B.BOR reset mode gets disabled
C.PIC does not remain in BOR mode until the voltage increases irrespective of
stability
D.Power-up timer kills 72ms more again
Ans: A
Q.66 Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
A. RC B.LP (Low-Power Clocking) C. XT D. HS (High Speed) Ans: B
Q.67 Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
A. High accuracy B.Proficiency in time generation
C. Applicability in real-time operations D.All of the above Ans:D
Q.68 What is the executable frequency range of High speed (HS) clocking method by
using cystal/ceramic/ resonator or any other external clock source?
A. 0-4 MHz B. 5-200 KHz C. 100kHz- 4 MHZ D. 4-20 MHz Ans:D
Q.69 Which bits play a crucial role in specifying the details or reasons associated with
the system wake-up in WDT?
A. PD’ & TO’ B. C & Z C. DC & RPO D. All of the above Ans:A
Q.70 Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?
A. GIE B. ADIE C. RBIE D. TOIE Ans: A
Q.71 Which instruction is applicable to set any bit while performing bitwise operation
settings?
A. bcf B. bsf C. Both A & B D. None of the above Ans:B
Q.72 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
A. Provision of MPLAB specific extensions
B. Floating-point Format Support
C. Data in Program Memory
D. All of the above Ans:D
Q.73 What does the 'program idata' section of data memory contain in C-18 Compiler?
A. statically assigned/allocated initialized user variables
B. statically assigned /allocated uninitialized user variables
C. only executable instructions
D. variables as well as constants Ans:A
Q.74 Where is the result stored after an execution of increment and decrement operations over
the special - purpose registers in PIC?
A. File Register B. Working Register C. Both A & B D. None of the above Ans:C
Q.75 Which flags of status register are most likely to get affected by the single-cycle increment
and decrement instructions?
A. P Flags B. C Flags C. OV Flags D. Z Flags Ans:D
Q.76 Which command-line option of compiler exhibits the banner comprising overall number of
errors, messages, warnings and version number after an accomplishment of the
compilation process?
A. help B. verbose C. overlay D. char Ans:B
Q.77 Which among the below assertions represent the salient features of PIC in C-18 compiler?
A. Transparent read/ write access to an external memory
B. Provision of supporting an inline assembly during the necessity of an overall control
C. Integration with MPLAB IDE for source-level debugging
D. All of the above Ans:D
Q.78 Which bit plays a salient role in defining the master or slave mode in TXSTA register
especially in synchronous mode?
A. RSRC B. CSRC C. SPEN D. SYNC Ans:B
Q.79 What is the status of shift clock supply in an USART synchronous mode?
A. Master-internally, Slave-externally
B. Master-externally, Slave-internally
C. Master & Slave (both) - internally
D. Master & Slave (both) – externally Ans:A
Q.80 When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of
'interrupt on change'?
A. By configuring all the pins (RB4-RB7) as inputs
B. By configuring all the pins (RB4-RB7) as outputs
C. By configuring any one of the pins as inputs
D. By configuring any one of the pins as outputs Ans:A
Q.81 Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn
on the weak internal pull-ups of port B?
A.RPO B.RPBU’ C. RBIF D.All of the above Ans:B
Q.82 Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?
A. INTCON B. ADCON0 C. ADRES D.PCLATH Ans:B
Q.83 Where are the prescalar assignments applied with a usage of PSA bit?
A. Only RTCC B. Only Watchdog timer
C. Either RTCC or Watchdog timer D. Neither RTCC nor Watchdog timer Ans:C
Q.84 Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity
for the external interrupt INT?
A. RBPU B. INTEDG C. PSA D. RTS Ans:B
Q.85 Which bank of RFS has a provision of addressing the status register?
A. Only Bank 1 B. Only Bank 2
C. Either Bank 1 or Bank 2 D. Neither Bank 1 nor Bank 2 Ans:C
Q.86 Which register acts as an input-output control as well as data direction register for PORTA
in bank 2 of RFS?
A. INDF B. TRISB C.TRISA D.PCLATH Ans:C
Q.87 Which registers are adopted by CPU and peripheral modules so as to control and handle
the operation of device inhibited in RFS?
A. General Purpose Register B. Special Purpose Register
C. Special Function Registers D. All of the above Ans:C
Q.88 How many bits are utilized by the instruction of direct addressing mode in order to address
the register files in PIC?
A. 2 B. 5 C. 7 D. 8 Ans:C
Q.89 When do the special address 004H get automatically loaded into the program counter?
A. After the execution of RESET action in program counter
B. After the execution of 'goto Mainline ' instruction in the program memory
C. At the occurrence of interrupt into the program counter
D. At the clearance of program counter with no value Ans:C
Q.90 Which significant feature/s of crystal source contribute/s to its maximum predilection and
utility as compared to other clock sources?
A. High accuracy B. Proficiency in time generation
C. Applicability in real-time operations D. All of the above Ans:D
Q.91 Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely
unique and distinct from other microcontrollers?
A. It can reset the PIC automatically in running condition
B. It can reset the PIC even when the supply voltage increases above 4V
C. It can reset the PIC without enabling the power-up timer
D. All of the above Ans:A
Q.92 Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
A. Excogitation of Inputs
B. Handling of Outputs
C. Interpretation of internal timing for program execution
D. Provision of OTP for large and small production runs
A. Only C B. C & D C. A, B & D D. A, B & C Ans:D
Q.93 is 16 bit register used as memory pointers in indirect addressing data
memory.
A. Status B. SFR C.GPR D. FSR Ans:D
Q.94 is a 21 bit register that holds the program memory address while executing
programs.
A. SFRs B. GPRs C. PC D. FSRs Ans: C
Q.95 is used to access the stack.
A. BP B. PC C.SP D. WREG Ans:C
Q.96 is not an addressable register.
A. SFR B. GPR C. WREG D. FSRs Ans: C
Q.97 Status register is also as register
A. WREG B. GPR C. SFR D. Flag Ans:D
Q.98 Flag is set if there is an overflow out of bit 7.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:B
Q.99 Flag is also known as Auxiliary Carry Flag.
A. Digit Carry B. Carry C. Over Flow D. Negative Ans:A
Q.100 Flag sets if the result of operation in ALU is zero.
A. Carry B. Negative C. Over Flow D. Zero Ans:D
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator
on OSC1 and OSC2 pins is divided by 1 2 3 4 D
_____ and fed to timer.
Which of the following timers have both 8
Timer 0 Timer 1 Timer 2 Timer 3 A
and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8
Timer 0 Timer 1 Timer 2 Timer 3 A
pre-scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of
TMR0ON T08BIT T0CS T0SE A
Timer0.
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by
Timer0 if FFF6 h is loaded into it. 5.6 μS 5.2 μS 4.6 μS 4 μS D
Assume crystal frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
frequency = 16 MHz and prescaler of 0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
1:16
Find timer's clock period with crystal
frequency = 32 MHz and prescaler of 1 μS 2 μS 3 μS 4 μS A
1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair FFFF h 1234 h 0000 h 4321 h C
for generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller
5 6 7 8 B
is ___ bits.
Size of Port E in PIC 18 microcontroller
3 4 5 6 A
is ___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of
TMRxON Tx8BIT TxCS TxSE A
Timerx.
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
MICROPROCESSOR
BCA
IV Sem
MULTIPLE CHOICE QUESTIONS
1) Which is the microprocessor comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
2) What is the store by register?
a. data
b. operands
c. memory
d. None of these
3) Accumulator based microprocessor example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
4) A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
5) There are primarily two types of register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
6) Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
7) BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
8) Which is used to store critical pieces of data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
9) The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
10) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a. 16
b. 32
c. 36
d. 64
12) Which is not the control bus signal:
a. READ
b. WRITE
c. RESET
d. None of these
13) PROM stands for:
a. Programmable read‐only memory
b. Programmable read write memory
c. Programmer read and write memory
d. None of these
14) EPROM stands for:
a. Erasable Programmable read‐only memory
b. Electrically Programmable read write memory
c. Electrically Programmable read‐only memory
d. None of these
15) Each memory location has:
a. Address
b. Contents
c. Both A and B
d. None of these
16) Which is the type of microcomputer memory:
a. Processor memory
b. Primary memory
c. Secondary memory
d. All of these
17) Secondary memory can store____:
a. Program store code
b. Compiler
c. Operating system
d. All of these
18) Secondary memory is also called____:
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
19) Customized ROMS are called:
a. Mask ROM
b. Flash ROM
c. EPROM
d. None of these
20) The RAM which is created using bipolar transistors is called:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. DDR RAM
21) Which type of RAM needs regular referred:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
22) Which RAM is created using MOS transistors:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
23) A microprocessor retries instructions from :
a. Control memory
b. Cache memory
c. Main memory
d. Virtual memory
24) The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
a. Address bus
b. System bus
c. Control bus
d. Data bus
25) The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
a. Read
b. Write
c. Both A and B
d. None of these
26) The CPU removes the ___ signal to complete the memory write operation:
a. Read
b. Write
c. Both A and B
d. None of these
27) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
28) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
29) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
30) Eight of the register are known as:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
31) The four index register can be used for:
a. Arithmetic operation
b. Multipulation operation
c. Subtraction operation
d. All of these
32) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
33) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
34) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
36) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
37) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
38) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
39) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
40) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
41) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
42) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
43) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
44) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
45) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
46) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
47) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
48) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
49) ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a. Data segment
b. Code segment
c. Stack segment
d. Extra segment
50) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
51) Which are the factor of cache memory:
a. Architecture of the microprocessor
b. Properties of the programs being executed
c. Size organization of the cache
d. All of these
52) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
53) Which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
54) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
55) Microprocessor reference that are available in the cache are called______:
a. Cache hits
b. Cache line
c. Cache memory
d. All of these
56) Microprocessor reference that are not available in the cache are called_________:
a. Cache hits
b. Cache line
c. Cache misses
d. Cache memory
57) Which causes the microprocessor to immediately terminate its present activity:
a. RESET signal
b. INTERUPT signal
c. Both
d. None of these
58) Which is responsible for all the outside world communication by the microprocessor:
a. BIU
b. PIU
c. TIU
d. LIU
59) INTR: it implies the__________ signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
60) Which of the following are the two main components of the CPU?
a. Control Unit and Registers
b. Registers and Main Memory
c. Control unit and ALU
d. ALU and bus
61) Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
a. Conductors
b. Buses
c. Connectors
d. Consecutives
62) The language that the computer can understand and execute is called
a. Machine language
b. Application software
c. System program
d. All of the above
63) Which of the following is used as a primary storage device?
a. Magnetic drum
b. PROM
c. Floppy disk
d. All of these
64) Which of the following memories needs refresh?
a. SRAM
b. DRAM
c. ROM
d. All of above
65) The memory which is programmed at the time it is manufactured
a. PROM
b. RAM
c. PROM
d. EPROM
66) Which of the following memory medium is not used as main memory system?
a. Magnetic core
b. Semiconductor
c. Magnetic tape
d. Both a and b
67) Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
68) One of the main feature that distinguish microprocessors from micro‐computers is
a. Words are usually larger in microprocessors
b. Words are shorter in microprocessors
c. Microprocessor does not contain I/O devices
d. Exactly the same as the machine cycle time
69) The first microprocessor built by the Intel Corporation was called
a. 8008
b. 8080
c. 4004
d. 8800
70) An integrated circuit is
a. A complicated circuit
b. An integrating device
c. Much costlier than a single transistor
d. Fabricated on a tiny silicon chip
71) Most important advantage of an IC is its
a. Easy replacement in case of circuit failure
b. Extremely high reliability
c. Reduced cost
d. Low powers consumption
72) Which of the following items are examples of storage devices?
a. Floppy / hard disks
b. CD‐ROMs
c. Tape devices
d. All of the above
73) The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
a. 8 bits
b. 12 bits
c. 16 bits
d. 32 bits
74) Which is the type of memory for information that does not change on your computer?
a. RAM
b. ROM
c. ERAM
d. RW / RAM
75) What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
a. Extended
b. Expanded
c. Base
d. Conventional
76) Before a disk can be used to store data. It must be…….
a. Formatted
b. Reformatted
c. Addressed
d. None of the above
77) Which company is the biggest player in the microprocessor industry?
a. Motorola
b. IBM
c. Intel
d. AMD
78) A typical personal computer used for business purposes would have… of RAM.
a. 4 KB
b. 16 K
c. 64 K
d. 256 K
78) The word length of a computer is measured in
a. Bytes
b. Millimeters
c. Meters
d. Bits
79) What are the three decisions making operations performed by the ALU of a computer?
a. Grater than
b. Less than
c. Equal to
d. All of the above
80) Which part of the computer is used for calculating and comparing?
a. Disk unit
b. Control unit
c. ALU
d. Modem
81) Can you tell what passes into and out from the computer via its ports?
a. Data
b. Bytes
c. Graphics
d. Pictures
82) What is the responsibility of the logical unit in the CPU of a computer?
a. To produce result
b. To compare numbers
c. To control flow of information
d. To do math’s works
83) The secondary storage devices can only store data but they cannot perform
a. Arithmetic Operation
b. Logic operation
c. Fetch operations
d. Either of the above
84) Which of the following memories allows simultaneous read and write operations?
a. ROM
b. RAM
c. EPROM
d. None of above
85) Which of the following memories has the shortest access times?
a. Cache memory
b. Magnetic bubble memory
c. Magnetic core memory
d. RAM
86) A 32 bit microprocessor has the word length equal to
a. 2 byte
b. 32 byte
c. 4 byte
d. 8 byte
87) An error in computer data is called
a. Chip
b. Bug
c. CPU
d. Storage device
88) The silicon chips used for data processing are called
a. RAM chips
b. ROM chips
c. Micro processors
d. PROM chips
89) The metal disks, which are permanently housed in, sealed and contamination free containers
are called
a. Hard disks
b. Floppy disk
c. Winchester disk
d. Flexible disk
90) A computer consists of
a. A central processing unit
b. A memory
c. Input and output unit
d. All of the above
91) The instructions for starting the computer are house on
a. Random access memory
b. CD‐Rom
c. Read only memory chip
d. All of above
92) The ALU of a computer normally contains a number of high speed storage element called
a. Semiconductor memory
b. Registers
c. Hard disks
d. Magnetic disk
93) The first digital computer built with IC chips was known as
a. IBM 7090
b. Apple – 1
c. IBM System / 360
d. VAX‐10
94) Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
95) Which of the following is used for manufacturing chips?
a. Control bus
b. Control unit
c. Parity unit
d. Semiconductor
96) To locate a data item for storage is
a. Field
b. Feed
c. Database
d. Fetch
97) A directly accessible appointment calendar is feature of a … resident package
a. CPU
b. Memory
c. Buffer
d. ALU
98) The term gigabyte refers to
a. 1024 bytes
b. 1024 kilobytes
c. 1024 megabytes
d. 1024 gigabyte
99) A/n …. Device is any device that provides information, which is sent to the CPU
a. Input
b. Output
c. CPU
d. Memory
100) Current SIMMs have either … or … connectors (pins)
a. 9 or 32
b. 30 or 70
c. 28 or 72
d. 30 or 72
101) Which is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
102) Which technology using the microprocessor is fabricated on a single chip:
a. POS
b. MOS
c. ALU
d. ABM
103) MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
104) In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
105) The register section is related to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
106) In Microprocessor one of the operands holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
107) Which register is a temporary storage location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
108) PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
109) IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
110) SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
111) The act of acquiring an instruction is referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
112) How many bit of instruction on our simple computer consist of one____:
a. 2‐bit
b. 6‐bit
c. 12‐bit
d. None of these
113) How many parts of single address computer instruction :
a. 1
b. 2
c. 3
d. 4
114) Single address computer instruction has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
115) LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
116) Which are the flags of status register:
a. Over flow flag
b. Carry flag
c. Half carry flag
d. Zero flag
e. Interrupt flag
f. Negative flag
g. All of these
117) The carry is operand by:
a. C
b. D
c. S
d. O
118) The sign is operand by:
a. S
b. D
c. C
d. O
119) The zero is operand by:
a. Z
b. D
c. S
d. O
120) The overflow is operand by:
a. O
b. D
c. S
d. C
121) _________ Stores the instruction currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
122) In which register instruction is decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
123) The status register is also called the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
124) The area of memory with addresses near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
125) The processor uses the stack to keep track of where the items are stored on it this by using
the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
126) Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
127) Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
128) SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
129) How many bit stored by status register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
130) The 16 bit register is separated into groups of 4 bit where each groups is called:
a. BCD
b. Nibble
c. Half byte
d. None of these
131) A nibble can be represented in the from of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
132) The left side of any binary number is called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
133) MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
134) _____ a subsystem that transfer data between computer components inside a computer
or between computer:
a. Chip
b. Register
c. Processor
d. Bus
135) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
136) Which bus carry addresses:
a. System bus
b. Address bus
c. Control bus
d. Data bus
137) A 16 bit address bus can generate___ addresses:
a. 32767
b. 25652
c. 65536
d. none of these
138) CPU can read & write data by using :
a. Control bus
b. Data bus
c. Address bus
d. None of these
139) Which bus transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a. Control bus
b. Data bus
c. Address bus
d. None of these
140) When memory read or I/O read are active data is to the processor :
a. Input
b. Output
c. Processor
d. None of these
141) When memory write or I/O read are active data is from the processor:
a. Input
b. Output
c. Processor
d. None of these
142) CS stands for:
a. Cable select
b. Chip select
c. Control select
d. Cable system
143) WE stands for:
a. Write enable
b. Wrote enable
c. Write envy
d. None of these
144) MAR stands for:
a. Memory address register
b. Memory address recode
c. Micro address register
d. None of these
145) MDR stands for:
a. Memory data register
b. Memory data recode
c. Micro data register
d. None of these
146) Which are the READ operation can in simple steps:
a. Address
b. Data
c. Control
d. All of these
147) DMA stands for:
a. Direct memory access
b. Direct memory allocation
c. Data memory access
d. Data memory allocation
148) The ____ place the data from a register onto the data bus:
a. CPU
b. ALU
c. Both A and B
d. None of these
149) The microcomputer system by using the ____device interface:
a. Input
b. Output
c. Both A and B
d. None of these
150) The standard I/O is also called:
a. Isolated I/O
b. Parallel I/O
c. both a and b
d. none of these
151) The external device is connected to a pin called the ______ pin on the processor chip.
a. Interrupt
b. Transfer
c. Both
d. None of these
152) Which interrupt has the highest priority?
a) INTR
b) TRAP
c) RST6.5
d) none of these
153) In 8085 name the 16 bit registers?
a) Stack pointer
b) Program counter
c) a & b
d) none of these
154) What are level Triggering interrupts?
a) INTR&TRAP
b) RST6.5&RST5.5
c) RST7.5&RST6.5
d) none of these
155) Which stack is used in 8085?
a) FIFO
b) LIFO
c) FILO
d) none of these
156) What is SIM?
a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask.
d) none of these
157) RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
d) none of these
158) In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR d) none of these
159) In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
160) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
161) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
162) Which are the part of architecture of 8086:
a. The bus interface unit
b. The execution unit
c. Both A and B
d. None of these
163) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
164) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
165) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
166) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
167) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
168) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
169) The upper 8 bit are called______:
a. BH
b. BL
c. AH
d. CH
170) The lower 8 bit are called_______:
a. AL
b. CL
c. BL
d. DL
171) IP stand for:
a. Industry pointer
b. Instruction pointer
c. Index pointer
d. None of these
172) Which has great important in modular programming:
a. Stack segment
b. Queue segment
c. Array segment
d. All of these
173) Which register containing the 8086/8088 flag:
a. Status register
b. Stack register
c. Flag register
d. Stand register
174) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
175) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
176) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
177) The physical address of memory is :
a. 20 bit
b. 16 bit
c. 32 bit
d. 64 bit
178) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
179) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
180) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
181) PA stand for:
a. Project address
b. Physical address
c. Pin address
d. Pointer address
182) SBA stand for:
a. Segment bus address
b. Segment bit address
c. Segment base address
d. Segment byte address
183) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
184) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
185) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
186) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
187) DS stand for:
a. Default segment
b. Defect segment
c. Delete segment
d. Definition segment
188) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
189) AD stand for:
a. Address data
b. Address delete
c. Address date
d. Address deal
190) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
191) PC stand for:
a. program counter
b. project counter
c. protect counter
d. planning counter
192) AH stand for:
a. Accumulator high
b. Address high
c. Appropriate high
d. Application high
193) AL stand for:
a. Accumulator low
b. Address low
c. Appropriate low
d. Application low
194) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
195) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
196) which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
197) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
198) How many type of cache memory:
a. 1
b. 2
c. 3
d. 4
199) Which is the type of cache memory:
a. Fully associative cache
b. Direct‐mapped cache
c. Set‐associative cache
d. All of these
200) ) Which memory is used to holds the address of the data stored in the cache :
a. Associative memory
b. Case memory
c. Ordinary memory
d. None of these
PAI UNIT -2 MCQ
1. 1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
2.
1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
3. 3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor
4. The unit that decodes the instructions concurrently and translate them into micro-
operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
4. 5. In complex instructions, when the instruction needs to be translated into more than 4
micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
5. 6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
6. 8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
7. 9. If complex instructions like interrupt handling, string manipulation appear, then the
control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
8. 10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
9. 11. The mechanism to provide protection, that is accomplished with the help of
read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
10. 12. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
11. 13. The mechanism that is accomplished using descriptor usages limitations, and rules of
privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
12. 14. The mechanism that is executed at certain privilege levels, determined by CPL
(Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
13. 15. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) none of the mentioned
14. 16. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
15. 17. The condition, “CPL not equals to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) all of the mentioned
16. 18. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) all of the mentioned
17. 19. The instruction at which the exception is generated, but the processor extension
registers containthe address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
18. 20. The exception that has no error code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
19. 21. By using privilege mechanism the protection from unauthorised accesses is done to
a) operating system
b) interrupt handlers
c) system softwares
d) all of the mentioned
20. 22. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) none of the mentioned
21. 23. Once the CPL is selected, it can be changed by
a) HOLD
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
22. 24. The data segments defined in GDT (global descriptor table) and the LDT (local
descriptor table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
23. 25. A task with privilege level 0, doesnot refer to all the lower level privilege descriptors
in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) none of the mentioned
24. 26. The selector RPL that uses a less trusted privilege than the current privilege level for
further use is known as
a) Least task privilege level
b) descriptor privilege level
c) effective privilege level
d) none of the mentioned
25. 27. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
26. 28. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
27. 29. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) all of the mentioned
28. 30. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
29. Answers
1-d 2-c 3-d 4-b 5-cc
6-a 7-d 8-b 9-a 10-a
11-a 12-c 13-b 14-c 15-c
16-c 17-d 18-c 19-d 20-b
21-d 22-b 23-c 24-a 25-b
26-c 27-c 28-c 29-b 30-c
TOPICS– Privilege
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Privilege”.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
View Answer
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be protected
from unauthorized accesses in virtual address space of each task using the privilege mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) None of the mentioned
View Answer
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task privilege level
at that instant is called the Current Privilege Level (CPL).
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
View Answer
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a single
code segment. It can only be changed by transferring the control, using gate descriptors, to a new
segment.
4. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor
table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
View Answer
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data segments
defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) None of the mentioned
View Answer
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors which apply
to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
View Answer
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for further use.
This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
View Answer
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of RPL
and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
View Answer
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level(CPL, RPL, DPL).
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned
View Answer
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with DPL equal to
CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
View Answer
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same privilege as
CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than
the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
View Answer
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with DPL equal
to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must
be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
View Answer
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment(TSS) descriptor, then
DPL must be less or equally privileged than CPL.
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13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
View Answer
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data segment
access.
14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
View Answer
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an exception 13
is generated. If the referenced segment is not present in physical memory, an exception 11 is ge
Topic – Protection
1. The mechanism to provide protection, that is accomplished with the help of read/write
privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
View Answer
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are restricted by
classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege
check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is accomplished
using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL (Current
Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
View Answer
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
View Answer
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
View Answer
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this
condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
View Answer
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT,
LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
View Answer
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI
and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
View Answer
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers
contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
View Answer
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
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11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
View Answer
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun, processor
extension segment overrun, are the protected mode exceptions.
Fallowing link to find the MCQS
https://books.google.co.in/books?id=5tatBaRplIgC&pg=PA239&lpg=PA239&dq=Privileged+in
structions+mcqs&source=bl&ots=VIJC4knrU_&sig=ACfU3U0va-
uuuq0yOhx41nSN1fF8MqDF8Q&hl=en&sa=X&ved=2ahUKEwjw_9aszufoAhU8zTgGHZySC
3IQ6AEwCnoECA0QLg
TOPIc– Protected Virtual Address Mode (PVAM) -2
This set of Advanced Microprocessors Questions and Answers focuses on “Protected Virtual
Address Mode (PVAM) -2”.
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
View Answer
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called system
descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate and trap
gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control transfer,
required stack manipulations, privilege level and its type.
4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d) trap gate
View Answer
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
View Answer
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
View Answer
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
View Answer
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number of bytes
to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM (read only memory)
View Answer
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor information,
from the main memory, cache memory is used in which the most frequently required data for execution
is stored.
9. The selector field consists of
a) requested privilege level (RPL)
b) table indicator
c) index
d) all of the mentioned
View Answer
Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as selectors. The
selector field consists of three fields namely, RPL, table indicator (TI) and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
View Answer
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero (0) is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
View Answer
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at privilege level
0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
View Answer
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table, containing
the base address, and limit for LDT.
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13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
View Answer
14. The number of interrupt descriptors that the interrupt descriptor table (IDT) handles is
a) 16
b) 64
c) 128
d) 256
View Answer
Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
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1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.
3. The number of debug registers that are available in 80386, for hardware debugging and control is a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware debugging and
control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging and four
levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is known as a)
segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organise the available
physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
Explanation: The 80386 has on-chip address translation cache, and instruction set is upward compatible
with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode of
operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286 (to be
executed under the control of memory management and protection abilities of 80386).
11. Which of the units is not a part of internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
12. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
Explanation: The central processing unit is further divided into execution unit and instruction unit.
13. The unit that is used for handling data, and calculate offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
14. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
15. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
16. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
17. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
18. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
19. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
Explanation: The paging unit works under the control of segmentation unit; i.e. each segment is further
divided into pages.
20. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
21. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
22. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
23. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
24. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) none of the mentioned
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
25. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
26. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
27. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.
28. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a
prefix of
a) X
b) E
c) 32
d) XX
Answer: b
Explanation: A 32 bit register, known as extended register, is represented by the register name with a
prefix of E.
29. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) none of the mentioned
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
30. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) all of the mentioned
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
31. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
32. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) none of the mentioned
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
33. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
34. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) task switch operation
c) IRET instruction or task switch operation
d) none of the mentioned
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
35. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
36. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
37. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of segments.
38. The 32-bit control register, that is used to hold global machine status, independent of the executed
task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
39. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) TSS (Task state segment descriptor)
e) all of the mentioned
Answer: e
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
40. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
41. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
42. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
Answer: c
Explanation: Two test registers are provided by 80386 for page cacheing, namely test control and test
status registers.
43. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
44. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
45. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
46. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
47. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers, rather, they
are internally used to store the descriptor information.
48. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
49. Contents of an index register are multiplied by a scale factor that may be added further to get the
operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
50. Contents of an index register are multiplied by a scale factor and then added to base register to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
51. In based scaled indexed mode with displacement mode, the contents of an index register are
multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is addedto a
base register and a displacement to get the offset of an operand.
52. The following statement of ALP is an example of MOV EBX, [EDX*4] [ECX]
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
53. The following statement is an example of MOV EBX, LIST [ESI*2] MUL ECX, LIST [EBP*4] a) base
scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
54. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
55. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
56. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
Answer: c
Explanation: The integer word is the signed 16-bit data.
57. A 16-bit displacement that references a memory location using any of the addressing modes is
a) pointer
b) character
c) BCD
d) offset
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing modes.
58. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
59. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
60. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
Answer: c
Explanation: The paging unit is disabled in real address mode.
61. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
62. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
63. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
64. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
65. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
66. If the paging unit is enabled, then it converts linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The paging unit when enabled, it converts linear address into physical address.
67. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The linear address is used as physical address if the paging unit is disabled.
68. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
Answer: c
Explanation: The paging unit is enabled only in protected mode.
69. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
70. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granulary bit
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
71. The TYPE field of descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
72. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
73. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
74. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
75. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
76. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Answer: d
Explanation: The five types of segment descriptors of 80386 are: 1. Code or data segment descriptors 2.
System descriptors 3.Local descriptors 4.TSS(task state segment) descriptors 5. Gate descriptors
77. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
78. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
79. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
80. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
81. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
Answer: b
Explanation: The paging divides the memory into fixed size pages.
82. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by segmentation unit, into physical addresses.
83. The control register that stores the 32-bit linear address, at which the previous page fault is detected
is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
84. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
85. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
86. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
87. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
88. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
89. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
90. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) all of the mentioned
Answer: c
Explanation: The D-bit is undefined for page directory entries.
91. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
92. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
93. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
Answer: c
Explanation: The page table cache is also known as translation look aside buffer
The internal RAM memory of the 8051 is:
A. 32 bytes
B. 64 bytes
C. 128 bytes
D.256 bytes
Answer: Option C
2. This program code will be executed continuously:
STAT: MOV A, #01H
JNZ STAT
A.True
B. False
Answer: Option A
3. The 8051 has ________ 16-bit counter/timers.
A. 1
B. 2
C. 3
D.4
Answer: Option B
4. The address space of the 8051 is divided into four distinct areas: internal data, external data,
internal code, and external code.
A.True
B. False
Answer: Option A
5. Data transfer from I/O to external data memory can only be done with the MOVX command.
A.True
B. False
Answer: Option A
6. The 8051 can handle ________ interrupt sources.
A. 3
B. 4
C. 5
D.6
Answer: Option C
Explanation:
There are five interrupt sources for the 8051, which means that they can recognize 5 different events
that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting
bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of
the same register.
7. The special function registers are maintained in the next 128 locations after the general-
purpose data storage and stack.
A.True
B. False
Answer: Option A
8. This statement will set the address of the bit to 1 (8051 Micro-controller):
SETB 01H
A.True
B. False
Answer: Option B
9. MOV A, @ R1 will:
A. copy R1 to the accumulator
B. copy the accumulator to R1
C. copy the contents of memory whose address is in R1 to the accumulator
D.copy the accumulator to the contents of memory whose address is in R1
Answer: Option C
10. A label is used to name a single line of code.
A.True
B.False
Answer: Option A
11. The following program will receive data from port 1, determine whether bit 2 is high, and
then send the number FFH to port 3:
READ: MOV A,P1
ANL A,#2H
CJNE A,#02H,READ
MOV P3,#FFH
A.True
B.False
Answer: Option A
12. Device pins XTAL1 and XTAL2 for the 8051 are used for connections to an external
oscillator or crystal.
A.True
B.False
Answer: Option A
13. When the 8051 is reset and the line is HIGH, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option A
14. An alternate function of port pin P3.4 in the 8051 is:
A. Timer 0
B. Timer 1
C. interrupt 0
D.interrupt 1
Answer: Option A
15. Both registers TL0 and TL1 are needed to start Timer 0.
A.True
B.False
Answer: Option B
16. The I/O ports that are used as address and data for external memory are:
A. ports 1 and 2
B. ports 1 and 3
C. ports 0 and 2
D.ports 0 and 3
Answer: Option C
17. The last 96 locations in the internal data memory are reserved for general-purpose data
storage and stack.
A.True
B.False
Answer: Option B
18. Microcontrollers often have:
A. CPUs
B. RAM
C. ROM
D.all of the above
Answer: Option D
19. The 8051 has ________ parallel I/O ports.
A. 2
B. 3
C. 4
D.5
Answer: Option C
20. The total external data memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
21. Which of the following instructions will load the value 35H into the high byte of timer 0?
A. MOV TH0, #35H
B. MOV TH0, 35H
C. MOV T0, #35H
D.MOV T0, 35H
Answer: Option A
23. The 8-bit address bus allows access to an address range of:
A. 0000 to FFFFH
B. 000 to FFFH
C. 00 to FFH
D.0 to FH
Answer: Option C
24. The contents of the accumulator after this operation
MOV A,#0BH
ANL A,#2CH
will be
A. 11010111
B. 11011010
C. 00001000
D.00101000
Answer: Option C
25. The start-conversion on the ADC0804 is done by using the:
A.
B. CS line
C. INTR line
D.V ref/2 line
Answer: Option A
26. This program code will be executed once:
STAT: MOV A, #01H
JNZ STAT
A.True
B.False
Answer: Option B
27. Which of the following instructions will move the contents of register 3 to the accumulator?
A. MOV 3R, A
B. MOV R3, A
C. MOV A, R3
D.MOV A, 3R
Answer: Option C
28. Which of the following statements will add the accumulator and register 3?
A. ADD @R3, @A
B. ADD @A, R3
C. ADD R3, A
D.ADD A, R3
Answer: Option D
29. Data transfer from I/O to external data memory can only be done with the MOV command.
A.True
B.False
Answer: Option B
30. Which of the following commands will move the number 27H into the accumulator?
A. MOV A, P27
B. MOV A, #27H
C. MOV A, 27H
D.MOV A, @27
Answer: Option B
31. This program code will read data from port 0 and write it to port 2, and it will stop looping
when bit 3 of port 2 is set:
STAT: MOV A, PO
MOV P2,A
JNB P2.3, STAT
A.True
B.False
Answer: Option A
32. Which of the following commands will move the value at port 3 to register 2?
A. MOV P2, R3
B. MOV R3, P2
C. MOV 3P, R2
D.MOV R2, P3
Answer: Option D
33. The number of data registers is:
A. 8
B. 16
C. 32
D.64
Answer: Option C
34. When the 8051 is reset and the EA line is LOW, the program counter points to the first
program instruction in the:
A. internal code memory
B. external code memory
C. internal data memory
D.external data memory
Answer: Option B
35. The designs of a centigrade thermometer and a PWM speed-control circuit can be
implemented by the 8051.
A.True
B.False
Answer: Option A
36. What is the difference between the 8031 and the 8051?
A. The 8031 has no interrupts.
B. The 8031 is ROM-less.
C. The 8051 is ROM-less.
D.The 8051 has 64 bytes more memory.
Answer: Option B
37. The I/O port that does not have a dual-purpose role is:
A. port 0
B. port 1
C. port 2
D.port 3
Answer: Option B
38. To interface external EPROM memory for applications, it is necessary to demultiplex the
address/data lines of the 8051.
A.True
B.False
Answer: Option A
39. The following command will copy the accumulator to the location whose address is 23H:
MOV 23H,A
A.True
B.False
Answer: Option A
40. The special function registers can be referred to by their hex addresses or by their register
names.
A.True
B.False
Answer: Option A
41. The contents of the accumulator after this operation
MOV A,#2BH
ORL A,00H
will be:
A. 1B H
B. 2B H
C. 3B H
D.4B H
Answer: Option B
42. The following program will cause the 8051 to be stuck in a loop:
LOOP: MOV A, #00H
JNZ LOOP
A.True
B.False
Answer: Option B
43. Which of the following commands will copy the contents of RAM whose address is in
register 0 to port 1?
A. MOV @ P1, R0
B. MOV @ R0, P1
C. MOV P1, @ R0
D.MOV P1, R0
Answer: Option C
44. The statement LCALL READ passes control to the line labelled READ.
A.True
B.False
Answer: Option A
45. Which of the following commands will copy the contents of location 4H to the accumulator?
A. MOV A, 04H
B. MOV A, L4
C. MOV L4, A
D.MOV 04H, A
Answer: Option A
46. The microcontroller is useful in systems that have nonvariable programs for dedicated
applications.
A.True
B.False
Answer: Option A
47. The total amount of external code memory that can be interfaced to the 8051 is:
A. 32K
B. 64K
C. 128K
D.256K
Answer: Option B
48. The ADC0804 has ________ resolution.
A. 4-bit
B. 8-bit
C. 16-bit
D.32-bit
Answer: Option B
49. A HIGH on which pin resets the 8051 microcontroller?
A. RESET
B. RST
C. PSEN
D.RSET
50. An alternate function of port pin P3.1 in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option B
51. Which of the following instructions will move the contents of the accumulator to register 6?
A. MOV 6R, A
B. MOV R6, A
C. MOV A, 6R
D.MOV A, R6
Answer: Option B
52. The following command will rotate the 8 bits of the accumulator one position to the left:
RL A
A.True
B.False
Answer: Option A
53. An alternate function of port pin P3.0 (RXD) in the 8051 is:
A. serial port input
B. serial port output
C. memory write strobe
D.memory read strobe
Answer: Option A
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Arithmetic and Logic Instructions”.
1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
View Answer
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator.
Example- ADD A,R0; ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
View Answer
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
View Answer
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of
the register or some immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
View Answer
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
View Answer
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to
1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
View Answer
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is
important and in signed number operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
View Answer
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the
data copy instructions, so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
View Answer
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to
mask the status of the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
View Answer
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not
equal and it resets CY if the destination address is larger then the source address and sets CY if
the destination address is smaller then the source address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the
source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the
source address
d) any register as the destination address and any immediate data as the source address
View Answer
Answer: a
Explanation: These commands have accumulator as the destination address and any register,
memory or any immediate data as the source address.
This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on
“Architecture”.
1. 8051 series of microcontrollers are made by which of the following companies?
a) Atmel
b) Philips
c) Atmel & Philips
d) None of the mentioned
View Answer
Answer: d
Explanation: Atmel series AT89C2051 and Philips family P89C51RD2 are the two most
common microcontrollers of 8051 families.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
View Answer
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
View Answer
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) DPTR
b) SP
c) PC
d) PSW
View Answer
Answer: c
Explanation: When a program wakes up, then 0x00 is loaded to the program counter register
because at this place the first op code is burnt.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which
register are affected?
a) PSW
b) SP
c) DPTR
d) PC
View Answer
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow,
parity, register bank select bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
View Answer
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and
AC are set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
View Answer
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2
RS1=1 and RS0=0 which are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
View Answer
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push
of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
View Answer
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
View Answer
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
This set of 8051 Micro-controller Multiple Choice Questions & Answers
(MCQs) focuses on “Jump, Loop and Call Instructions”.
1. DJNZ R0, label is how many bit instructions?
a) 2
b) 3
c) 1
d) Can’t be determined
View Answer
Answer: a
Explanation: DJNZ R0, label has hex code, D8 and its corresponding label address. Hence, it is a
two byte instruction.
2. JZ, JNZ, DJNZ, JC, JNC instructions monitor the bits of which register?
a) DPTR
b) B
c) A
d) PSW
View Answer
Answer: d
Explanation: PSW register consists of flag bits like CY, P, Z etc so it is the one that is directly
being monitored by these instructions.
3. Calculate the jump code for again and here if code starts at 0000H
MOV R1,#0
MOV A,#0
MOV R0,#25H
AGAIN:ADD A,#0ECH
JNC HERE
HERE: INC R1
DJNZ R0,AGAIN
MOV R0,A
END
a) F3,02
b) F9,01
c) E9,01
d) E3,02
View Answer
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next
to the source address.
So here if we start with 0000H
then source address is 0008H and the destination address is 0004H
So loop address is 04-0A=E9
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
View Answer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call
instruction so that when RET is executed then PC is filled with that address and so the pointer
moves to the main program and continue with its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
View Answer
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte
instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
View Answer
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH
instructions the pointer does not move to any location specified by its address which is the
fundamental of CALL instruction, so it is not a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
View Answer
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal
frequency) /12
8. Find the number of times the following loop will be executed
MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a) 100
b) 200
c) 20000
d) 2000
View Answer
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
View Answer
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is
moved to it unlikely of using # used for storing data in any register.
10. Do the two instructions mean the same?
1) BACK: DEC R0
JZ BACK
2) BACK: DJNZ RO, BACK
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
View Answer
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves
back and in the second statement, when the result after decrements is not zero, then it jumps
back.
Unit No.1
Topic:Assembler Directives and ALP Tools
1. __________ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
View Answer
Answer: c
Explanation: An assembler is a software used to convert the programs into machine instructions.
2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
View Answer
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.
3. The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
View Answer
Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.
4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
View Answer
Answer: d
Explanation: The directives help the program in getting compiled and hence won’t be there in the
object code.
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
View Answer
Answer: b
Explanation: This basically is used to replace the variable with a constant value.
6. The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
View Answer
Answer: a
Explanation: This does the function similar to the main statement.
7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
View Answer
Answer: c
Explanation: None.
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
View Answer
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object code
of the program there.
9. _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
View Answer
Answer: b
Explanation: This instruction directive is used to terminate the program execution.
10. The last statement of the source program should be _______
a) Stop
b) Return
c) OP
d) End
View Answer
Answer: d
Explanation: This enables the processor to load some other process.
11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
View Answer
Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the branch
offset and replaces it with it.
12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
View Answer
Answer: b
Explanation: The table where the assembler stores the variable names along with their
corresponding memory locations and values.
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13. The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
View Answer
Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and
waits for further execution.
14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
View Answer
Answer: a
Explanation: The program is used to load the program into memory.
15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
View Answer
Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.
TOPICS: “Programming With An Assembler”.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
View Answer
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
View Answer
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
View Answer
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
View Answer
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
View Answer
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
View Answer
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
View Answer
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
View Answer
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
View Answer
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
View Answer
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.
11. The purpose of the ORIGIN directive is __________
• A. To indicate the starting position in memory, where the program block is to be stored
• B. To indicate the starting of the computation code
• C. To indicate the purpose of the code
• D. To list the locations of all the registers used
Answer: Option A
12. The last statement of the source program should be _______
• A. Stop
• B. Return
• C. OP
• D. End
Answer: Option D
13.DEBUG is able to troubleshoot only
• A. .EXE files
• B. .OBJ files
• C. .EXE file and .OBJ file
• D. .EXE flie and .LST file
Answer: Option A
TOPICS: Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are shifted by
left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in
same way as in the 80386 real address mode.
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task.
TOPIC: – Segmentation of 80386
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
View Answer
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by
the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
View Answer
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
View Answer
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
View Answer
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
View Answer
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits
along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
View Answer
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS(task state segment) descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
View Answer
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
View Answer
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory is
decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
View Answer
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence
TOPIC:– Architecture and Signal Descriptions of 80386
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing
unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
View Answer
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
View Answer
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are
either used for handling the data or calculating the offset addresses.
4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code
queue, after decoding them so as to pass it to the control section, for deriving the necessary control
signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
View Answer
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
View Answer
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and
offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
View Answer
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
View Answer
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
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13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
View Answer
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
View Answer
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus
cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
View Answer
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of
slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
View Answer
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data
word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
View Answer
Answer: c
Explanation: The pip
TOPICS– Register Organisation of 80386 -1
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers
with a prefix of
a) X
b) E
c) 32
d) XX
View Answer
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register name with a
prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
View Answer
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP,
SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
View Answer
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS,
ES, FS and GS are the four data segment registers.
4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
View Answer
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of
80386.
6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
View Answer
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is
to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the
protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
View Answer
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
View Answer
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET
and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL
and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like attributes,
limit and base addresses of se
TOPIC: – Register Organisation of 80386 -2
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine
status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
View Answer
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
View Answer
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register(s) that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
View Answer
Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and test
status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
View Answer
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
View Answer
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
View Answer
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control
information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
View Answer
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
View Answer
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers,
rather, they are internally used to store the descriptor information
TOPIC: Addressing Modes of 80386, Data Types of 80386
1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid
scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that
may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register to
get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor
and then added to base register to get the operand offset.
4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
View Answer
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is added to a
base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
View Answer
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
View Answer
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
View Answer
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d) Offset
View Answer
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the
addressing mod
TOPIC– Real Address Mode of 80386, Protected Mode of 80386
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to work
with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer.A
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection is
available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte of the segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
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11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual
memory per task
Topic: – Paging
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments, which are required currently for the
execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
View Answer
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
View Answer
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses
provided by the segmentation unit, into physical addresses.
4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous
page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
View Answer
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory,
page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store
the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
View Answer
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
View Answer
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
View Answer
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
10. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
View Answer
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
View Answer
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
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13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
View Answer
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided,
which stores the 32 recently accessed page table entries.
14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
View Answer
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
MCQS on the INstruction
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
2. If the processor is executing a main program that calls a subroutine, then after executing the
main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) none
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
11. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned
12. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) all of the mentioned
13. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
14. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) none of the mentioned
15. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
16. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
17. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
18. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
19. The flag bits that indicate the privilege level of current IO operations are
a) virtual mode flag bits
b) IOPL flag bits
c) resume flag bits
d) none of the mentioned
20. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
21. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
22. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
23. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
24. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
25. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
26. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
27. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
28. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
29. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
30. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answers
1-c 2-b 3-d 4-c 5-d
6-b 7-c 8-d 9-d 10-d
11-d 12-d 13-a 14-b 15-c
16-b 17-d 18-a 19-b 20-c
21-d 22-b 23-d 24-c 25-b
26-d 27-d 28-b 29-c 30-a
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC
to ____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller Watchdog
are ______ Timers ADC All of these D
5 Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access
data RAM in PIC 18 microcontroller. 4 8 12 16 C
9
___ address lines are used to access
program ROM in PIC 18 microcontroller. 18 19 20 21 D
10
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller
is ___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller
is ___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is 128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : deep sleep,
sleep, deep idle, deep
sleep, idle deep power A
sleep sleep
20 down
WDT stands for _______ Watch Watch Dog Width Delay Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master
Master Master
Synchronou Master Slave
Synchronou Synchronous C
s Serial Serial Port
s slave Port Serial Port
25 Peripheral
Flag 'N' in Status register of PIC18F452 d Negative
Zero Flag Overflow Flag Carry Flag B
26 Flag
How many banks are available in PIC 18F
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result Results saved Ressult
ADDWF F D a Undefined D
saved in F in F and W Saaved in W
28
BOD' stands for Brown OR Brown out
Brown out Board on Reset
Reset Reset B
Reset Debug Detection
29 Detection Detection
Circuit used for initialization of all values t Power-On Brown Out Power ON/
Reset Detection WDT circuit A
OFF circuit
30 Circuit Circuit
In Immediate (Literal) addressing mode
The operand is _____ that follows the a register a number a pointer an address B
31 opcode
PIC18F452 has power down modes as __ deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated
in____ oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in
OSCCONFI
PIC18F4550 is controlled through two CONFIG2 CONFIG1L
G1 and None of the
Configuration registers as _______ and and C
OSCCONFI above
CONFIG2 CONFIG1H
G2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral
Univeral Serial
Synchrnous Synchrnous Synchrnous
Asynchronous
Asynchrono Asymmatric Asynchronous C
Receive
us Register Receive Receive
Transmit
36 Transmit Transmit Transmit
CONFIG2L is used for Frequency Background Watch dog
Reset voltage D
Selection debugger timer
37
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontrol
Resets all the
for ler in Set all registers B
registers
peripherals standby
38 OFF mode
Where is the result stored after an
execution of increment and decrement Working None of the
File Register Both a & b C
operations over the special - purpose Register above
39 registers in PIC?
Which status bits exhibit carry from
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of
TMRxON Tx8BIT TxCS TxSE C
Timer0.
Which of the following is not a Port SFR? PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is None of
output input bidirectional B
____ these
Upon reset content of TRISB register is
0000 0000 000 000 1111 1111 111 111 C
_______
Which of the following instruction is used to
BSF BCG BTG BMF A
set a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF B
clear a file register bit?
Which of the following instruction is used to
BSF BCG BTG BMF C
toggle a file register bit?
Sheet1
Question Option A Option B Option C Option D Answer
PIC 18 Microcontroller is based on ____
architecture. Von
Harvard Both of these None of these A
Neumann
1
PIC stands for _______ Peripheral Peripheral Programmable Programmable
Intelligent Interface Interface Intelligent B
2 Controller Controller Controller Controller
PIC 18 F is _____ bit microcontroller.
4 8 16 32 B
3
Operating frequency for PIC 18F is DC to
____ MHz 10 20 30 40 D
4
Genearl features of PIC 18F controller are Watchdog
Timers ADC All of these D
5 ______ Timers
PIC 18F452 uses ______ architecture.
RISC CISC Both of these None of these A
6
PIC 18F452 has ____ program ROM
1 kB 2 kB 1 MB 2 MB D
7
PIC 18F452 has ____ kB data RAM
1 2 4 8 C
8
___ address lines are used to access data
4 8 12 16 C
9 RAM in PIC 18 microcontroller.
___ address lines are used to access
18 19 20 21 D
10 program ROM in PIC 18 microcontroller.
40 pin PIC 18 F microcontroller has ____
I/O ports 3 4 5 6 C
11
Which of the following is not a 8 bit port?
A B C D A
12
Size of Port A in PIC 18 microcontroller is
___ bits. 5 6 7 8 B
13
Size of Port E in PIC 18 microcontroller is
___ bits. 3 4 5 6 A
14
FLASH Program Memory of PIC18F452 is _______
128K 64K 32K 16K C
15
PIC18F452 has total _____ pins .
40 20 16 8 A
16
Instruction set of PIC18F452 has
_________instructions 33 35 40 75 D
17
Page 1
Sheet1
PIC18F452 has _____ ADC 8 BIT 10 BIT 12 BIT 14 BIT B
18
PORT names of PIC18F452 are
0,1 0,1,2,3,4 A,B,C,D,E A,B,C C
19
PIC18F452 has power down modes : sleep, deep idle, deep deep sleep,
sleep, idle A
20 sleep sleep deep power
WDT stands for _______ Watch Watch Dog Width Delay down
Watch Delay
B
21 Down Timer Timer Timer Timer
PIC18F542 has ____program counter
8-bit 16-bit 20-bit 21-bit D
22
Each instruction has two parts
Opcode and Opcode and Operand and Opcode and
B
Register Operand Register Pointer value
23
ADDWFC, SUBWF are
Move and
Arithmatic Branch Logical
Load A
Instructions instructions instructions
instructions
24
MSSP stands for_____ Master Master Master Master Slave
C
25 Synchronous Synchronou Synchronous Serial Port
Flag 'N' in Status register of PIC18F452 denotesSerial sNegative
slave Port Serial Port
Zero Flag Overflow Flag Carry Flag B
26 Peripheral Flag
How many banks are available in PIC 18F452
12 16 10 14 B
27
What is the significance of "d=0" bit in
Result saved Results saved Ressult Saaved
ADDWF F D a Undefined D
in F in F and W in W
28
BOD' stands for Brown OR Brown out Brown out Board on Reset
B
29 Reset Reset Reset Debug Detection
Detection
Circuit used for initialization of all values to default
Power-On Detection
is named
Brown
as Out Power
WDT circuit A
30 Reset Circuit Detection ON/OFF circuit
In Immediate (Literal) addressing mode Circuit
a register a number a pointer an address B
31 The operand is _____ that follows the
opcode has power down modes as ____
PIC18F452 deep power deep sleep and
Idle and sleep and
down and deep power A
sleep deep sleep
idle down
32
PIC18F452device can be operated in____
oscillator Configuration modes. 10 12 14 16 B
33
Page 2
Sheet1
The operation of the oscillator in OSCCONFIG
PIC18F4550 is controlled through two CONFIG2
1 and CONFIG1L and None of the
Configuration registers as _______ and C
OSCCONFIG CONFIG1H above
CONFIG2
2
34
MSSP module of PIC18F452 has ADC and USART and
SPI and I2C I2C and PWM B
35 PWM CCP
USART means Univeral Univeral Univeral Univeral Serial
C
36 Synchrnous Synchrnous Synchrnous Asynchronous
CONFIG2L is used for Asynchrono
Frequency Asymmatric
Background Asynchronous
Watch dog Receive
usSelection
Register Receive Receive Reset voltage
Transmit D
debugger timer
37 Transmit Transmit Transmit
The instruction SLEEP in PIC 18F458 : Keeps Keeps
Oscillator Microcontro Resets all the Set all registers B
for ller in registers
38
peripherals standby
Where is the result stored after an Working None of the
File Register
OFF mode Both a & b C
39 execution of increment and decrement Register above
operations
Which statusover
bitsthe special
exhibit - purpose
carry from
registers in PIC?
lower 4 bits during 8-bit addition and are Digits Carry None of the
Carry bit Both a & b B
especially beneficial for BCD addition ? bit (DC) above
40
Page 3
Sheet1
Question Option A Option B Option C Option D Answer
Frequency of the crystal oscillator on
OSC1 and OSC2 pins is divided by _____ 1 2 3 4 D
and fed to timer.
Which of the following timers have both
Timer 0 Timer 1 Timer 2 Timer 3 A
8 and 16 bit mode of operation?
Which of the following timers is not
Timer 0 Timer 1 Timer 2 Timer 3 C
available as counter?
Which of the following timers has 8 pre-
Timer 0 Timer 1 Timer 2 Timer 3 A
scaling factors?
_____ timer has post-scaling factor
Timer 0 Timer 1 Timer 2 Timer 3 C
option.
None of
Timer 0 is _____ timer/counter. only 8 bit only 16 bit 8 / 16 bit C
these
Timers/counters in PIC 18 controller are Up Down Up/down None of
C
_____. counters counrers counters these
TMR0H and TMR0L are _____ bit
4 8 16 32 B
registers
______ is a ON/OFF control bit of Timer0. TMR0ON T08BIT T0CS T0SE A
______ is a 8 bit / 16 bit selector bit of
TMR0ON T08BIT T0CS T0SE B
Timer0.
______ is a clock source selector bit of
TMR0ON T08BIT T0CS T0SE C
Timer0.
______ is a source edge selector bit of
TMR0ON T08BIT T0CS T0SE D
Timer0.
Timer 0 Interrupt flag bit is present in
T0CON INTCON TMR0H TMR0L B
______ register.
____ status of TMR0IF bit indicates that None of
0 1 X B
Timer 0 has overflowed. these
TMR0IF flag is set when TMR0H:TMR0L FFFF h to 0000 h to Both of None of
A
overflows from _____ to _______. 0000 h FFFF h these these
What is the timer's clock frequency if the
oscillator frequency is F MHz with no F Mhz F/2 Mhz F/4 Mhz F/8 Mhz C
prescalar?
Page 1
Sheet1
In time delay generation for Timer1, what
Fh FF h FFF h FFFF h D
is the Maximum count?
Calculate total delay generated by Timer0
if FFF6 h is loaded into it. Assume crystal 5.6 μS 5.2 μS 4.6 μS 4 μS D
frequency = 10 MHz
Calculate initial count to be loaded in
timer0 (8 bit mode) with prescaler of 256
FB h FC h FD h FE h A
to generate time delay of 5 milliseconds.
Assume crystal F = 10 MHz
Find timer's clock frequency with crystal
0.2 MHz 0.25 MHz 0.4 MHz 0.45 MHz B
frequency = 16 MHz and prescaler of 1:16
Find timer's clock period with crystal
1 μS 2 μS 3 μS 4 μS A
frequency = 32 MHz and prescaler of 1:8
For generation of largest time delay with
Timer0, which of the following prescaler 8 64 128 256 D
option to be selected?
Which of the following values to be
loaded in TMR0H:TMR0L register pair for FFFF h 1234 h 0000 h 4321 h C
generation of largest time delay?
Which of the following registers is used
for loading initial value in 8 bit Timer0 TMR1L INTCON TMR0H TMR0L D
operation?
Which of the prescaler options are not
2 4 8 16 D
available in Timer1 programming?
Number of prescale options available in
16 8 4 2 B
Timer0 are ____
Number of prescale options available in
16 8 4 2 C
Timer1 are ____
Which of the following register is used in None of
TMR2H TMR2L TMR2 C
Timer2 programming? these
Period Register is present in _____ Timer 0 Timer 1 Timer 2 Timer 3 C
Which timer has both options of
Timer 3 Timer 2 Timer 1 Timer 0 B
prescaler and postscaler?
40 pin PIC 18 F microcontroller has ____
3 4 5 6 C
I/O ports
Page 2
Sheet1
Which of the following is not a 8 bit port? A B C D A
Size of Port A in PIC 18 microcontroller is
5 6 7 8 B
___ bits.
Size of Port E in PIC 18 microcontroller is
3 4 5 6 A
___ bits.
In which of the following timers the
associated interrupt flag is not set upon Timer 3 Timer 2 Timer 1 Timer 0 B
rollover?
Timer 1 Interrupt flag bit is present in
T1CON INTCON PIR1 TMR1L C
______ register.
Timer 2 Interrupt flag bit is present in
T2CON INTCON PIR1 TMR2 C
______ register.
Number of postscale options available in
16 8 4 2 A
Timer2 are ____
Number of prescale options available in
1 2 3 4 C
Timer2 are ____
______ is a ON/OFF control bit of Timerx. TMRxON Tx8BIT TxCS TxSE A
______ is a clock source selector bit of TMRxON Tx8BIT TxCS TxSE C
Which of the following is not a Port SFR?
Timer0. PORTx LATx TRISx TMRx D
Upon reset every port of PIC 18 controller is output input bidirectional None of B
____ reset content of TRISB register is
Upon 0000 0000 000 000 1111 1111 these
111 111 C
_______
Which of the following instruction is used to BSF BCG BTG BMF A
set a file
Which of register bit? instruction is used to
the following BSF BCG BTG BMF B
clear a file register
Which of the following bit?instruction is used to BSF BCG BTG BMF C
toggle a file register bit?
Page 3
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
Question Option A Option B Option C Option D Answer
By which of the following method(s)
devices receive service from the Interrupts Polling Both of these None of these C
microcontroller?
Asynchronous request for service by
peripherals to processor is known as Interrupt Polling Both of these None of these A
____
Which of the following can cause Serial data Serial data
Timer overflow All of these D
interrupt generation? reception transmission
In which of the following method(s)
priority can be assigned to the devices Interrupts Polling Both of these None of these A
demanding for service?
In which of the following method(s)
microcontroller can not ignore a device Interrupts Polling Both of these None of these B
request for service?
Which of the following method(s) waste
Interrupts Polling Both of these None of these B
microcontroller’s time
Input Interrupt Interrupt
Input Service
Full form of ISR is_______ Synchronous Synchronous Service D
Routine
Routine Routine Routine
Interrupt
Input Vector Inerrupt Input Vector
Full form of IVT is_______ Vector B
Table Vector Table Testbench
Testbench
Power on Reset Vector in PIC 18 is
0000 0008 0018 0028 A
_____h
High Priority Interrupt Vector in PIC 18 is
0000 0008 0018 0028 B
_____h
Low Priority Interrupt Vector vector in
0000 0008 0018 0028 C
PIC 18 is _____h
Fixed locations in memory that holds
IGT IMT IRT IVT D
addresses of ISRs are called as ____
Correct sequence of steps in executing an
interrupt is ______ Where 1=Execute ISR,
1-2-3-4 3-2-1-4 4-3-2-1 3-2-4-1 D
2= Consult IVT, 3=Save PC on stack and
4=Jump to ISR
While servicing an interrupt content of
PC MAR MBR IR A
____ register are saved on the stack
What is the status of interrupts in PIC 18 All are Some are
All are enabled None of these B
after power on or reset? disabled enabled
____ bit is used for enabling/disabling of
FIE GIE HIE JIE B
all interrupts
Global Interrupt Enable (GIE) bit is
INTCON RCON PIR PIE A
present in ______ register
Interrupt Priority Enable (IPEN) bit is
INTCON RCON PIR PIE B
present in ______ register
Peripheral Interrupt Enable (PEIE) bit is
INTCON RCON PIR PIE A
present in ______ register
To enable serial communication
interrupts which of the following bit(s) Only GIE Only PEIE Both of these None of these B
must be set?
To enable timer 0 interrupt which of the
Only GIE Only PEIE Both of these None of these A
following bit(s) must be set?
There are ___ registers to control
11 12 13 14 C
interrupt operation in PIC 18
In PIC18F, any interrupt source is enabled
0 1 X None of these D
when corresponding IE bit is ____.
Which of the following bit(s) control
operation of an interrupt source in PIC18 Flag bit Enable bit Priority bit All of these D
F?
The default ISR address in PIC18F is
0000 0008 0018 0028 B
_____ h
Which of the following bit(s) indicate that
Flag bit Enable bit Priority bit All of these A
an interrupt event has occurred?
Which of the following bit(s) is used to
Flag bit Enable bit Priority bit All of these C
assign priority to an interrupt?
Setting of ___ and ____ bit allows
Enable,
program execution to branch to the Flag, Enable Flag, Priority All of these A
Priority
interrupt vector address.
If the interrupt is one of the peripheral
(timers 1,2 , serial, etc. ) we need to set
TMR0IE INT0IE PEIE RBIE C
____ bit from INTCON register along with
GIE bit.
Which of the following interrupt has no
INT3 INT2 INT1 INT0 D
priority bit?
_____ interrupt has default high priority. INT0 INT1 INT2 All of these D
For any interrupt source, to assign high
priority the corresponding IP bit must be 0 1 X None of these B
____.
For any interrupt source, to assign low
priority the corresponding IP bit must be 0 1 X None of these A
____.
Which of the following is not a core Serial
TMR0 INT0 INT1 D
interrupt source? Transmit
Which of the following is not a peripheral
TMR3 TMR2 TMR1 TMR0 D
interrupt source?
Which of the following is not a peripheral Serial
TMR1 INT0 TMR2 B
interrupt source? Transmit
Upon power-on reset the external
Positive edge Negative edge Positive level Negative level
hardware interrupts INT0-INT2 are of A
triggered triggered triggered triggered
type _____.
Which of the following avoids tying down
Interrupts Polling Both of these None of these A
the microcontroller?
PIC 18 ha ____ external hardware
1 2 3 4 C
interrupts.
External hardware interrupts of PIC18F
E D C B D
are multiplexed with port ____ lines.
PORTB-change interrupt is assocaied with
4 3 2 1 A
_____ lines of PORTB.
PORTB-change interrupt is assocaied with
RB0-RB3 RB2-RB5 RB3-RB6 RB4-RB7 D
_____ lines of PORTB.
Register Select pin of LCD selects_____
Status Command Data Program B
register when it is 0.
Register Select pin of LCD selects_____
Status Command Data Program C
register when it is 1.
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these B
In LCD, R/W = 0 is _____ mode Read Write Both of these None of these A
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
Unit IV MCQs
Q.1 How does the pin RC2/CCP1 get configured while initializing the CCP module in the
compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans:d
Q.2 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans:a
Q.3 The capture operation in counter mode is feasible when mode of CCP module is
__ _ __
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
Ans:a
Q.4 Which register is suitable for the corresponding count, if the measurement of pul se
width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
Ans:c
Q.5 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR Ans:a
Q.6 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.7 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.8 Which among the below mentioned aspect issues are supported by
capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
Ans:d
Q.9 Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
Ans:a
Q.10 What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
Ans:b
Q.11 What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of
CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H
respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
Ans:a
Q.12 What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
Ans: a
Q.13 How does the pin RC2/CCP1 get configured while initializing the CCP module in
the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Ans: b
Q.14 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0
Ans: a
Q.15 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
Ans: b
Q.16 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.17 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value
Ans: b
Q.18 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter ?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components
Ans: a
Q.19 In ____ _ data transfer, group of bits (usually 8 bits) of data is transferred at a
time.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.20 In ____ _ data transfer, only one bit of data is transferred at a time.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.21 In Parallel data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: a
Q.22 In Serial data transfer, data transfer rate is _ _ _
a. HIGH b. LOW c. MODERATE d. None of the above Ans: b
Q.23 Most of the Microprocessor/Microcontrollers are designed for______ communication.
a. Parallel b. Serial c. simplex d. None of the above Ans: a
Q.24 In _____ data communication, during transmission parallel data is converted into
serial bits using a PISO shift register.
a. Parallel b. Serial c. simplex d. None of the above Ans: b
Q.25 At the receiver, the serial bits are connected into parallel data by another shift
register called SIPO register.
a. TRUE b. FALSE Ans: a
Q.26 In ____ __, the hardware exists such that data transfer takes place only in one
direction.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.27 The transmission form a computer to the printer is an example of ____ _ _
communication.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: a
Q.28 The ______ transmission allows the data transfer in both directions, but not
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.29 Walkie-talkie is an example of ________ _.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: b
Q.30 The ______ transmission allows the data transfer in both directions
simultaneously.
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q. 31 Telephone lines is an example of ____ _ .
a. Simplex b. Half Duplex C. Full Duplex D. None of the above Ans: c
Q.32 Types of serial data communication:
a. Asynchronous serial data communication
b. Synchronous serial data communication
a. TRUE b. FALSE Ans: a
Q.33 The serial communication is
a. cheaper communication
b. requires less number of conductors
c. slow process of communication
d. all of the mentioned Ans: d
Q.34 The serial communication is used for
a. short distance communication
b. long distance communication
c. short and long distance communication
d. communication for a certain range of distance Ans: b
Q.35 The number of bits transmitted or received per second is defined as
a. transmission rate
b. reception rate
c. transceiver rate
d. baud rate Ans: d
Q.36 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.37 The task of converting the byte into serial form and transmitting it bit by bit along
with start, stop and parity bits is carried out by
a. reception unit
b. serial communication unit
c. transmission unit
d. all of the mentioned Ans: c
Q.38 Where does the comparison level occur for 16-bit contents in the compare mode
operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0 Ans: a
Q.39 Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above Ans: b
Q.40 What would be the resolution value if oscillator and PWM frequencies are 16MHz
and 2 MHz respectively?
a. 2 b. 3 c. 4 d. 8 Ans: b
Q.41 How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value Ans: b
Q.42 Which among the below stated components should be filtered for determining the
cut-off frequency corresponding to the PW period of low-pass filter?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components Ans: a
Q.43 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.44 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.45 What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave
mode by enabling SS pin control?
a. 0000 b. 0100 c. 0010 d. 0001 Ans: b
Q.46 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above Ans: a
Q.47 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.48 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above Ans: b
Q.49 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c. 16 d. 32 Ans: a
Q.50 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above Ans: a
Q.51 What is the purpose of a special function register SPBRG in USART?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above Ans: a
Q.52 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the
data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.53 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode?
a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1) Ans: b
Q.54 What is the status of shift clock supply in an USART synchronous mode?
a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally Ans: a
Q.55 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.56 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as
DT (data lines)?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.57 Which among the below assertions represent the salient features of PIC in C-18
compiler?
a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above Ans: d
Q.58 In which aspects do the output functions specified in stdio.h differ from ANSI
specified versions?
a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above Ans: d
Q.59 Which flags of status register are most likely to get affected by the single-cycle
increment and decrement instructions?
a. P Flags b. C Flags c. OV Flags d. Z Flags Ans: d
Q.60 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.61 In ____ _ _ communication, transmitters and receivers are not synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: a
Q.62 In ____ _ _ communication, transmitters and receivers are synchronized by
clock.
a. Asynchronous Serial
b. Asynchronous Parallel
c. Synchronous Serial
d. Synchronous Parallel Ans: c
Q.63 In Asynchronous Serial communication, bits of data are transmitted at constant
rate.
a. TRUE b. FALSE Ans: a
Q.64 In Synchronous Serial communication, bits of data are transmitted with
synchronization of clock.
a. TRUE b. FALSE Ans: a
Q.65 In Asynchronous Serial communication, character may arrive at any rate at
receiver.
a. TRUE b. FALSE Ans: a
Q.66 In Synchronous Serial communication, is received at constant rate.
a. TRUE b. FALSE Ans: a
Q.67 In Asynchronous Serial communication, data transfer is character oriented.
a. TRUE b. FALSE Ans: a
Q.68 In Synchronous Serial communication, data transfer takes place in blocks.
a. TRUE b. FALSE Ans: a
Q.69 Baud Rate is data transmission speed.
a. TRUE b. FALSE Ans: a
Q.70 The rate at which the bits are transmitted (bits/second) is called ____ _.
a. speed b. bit rate c. baud d. sample Ans: c
Q.71 The common baud rates are multiplies of _____ bits/second.
a. 25 b. 50 c. 75 d. 100 Ans: c
Q.72 Which among the below stated conditions are selected by the SSPCON & SSPSTAT
control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above Ans: d
Q.73 Which bit of SSPCON must be necessarily set so as to enable the synchronization
of serial port?
a. WCOL b. SSPOV c. CKP d. SSPEN Ans: d
Q.74 Which bits assist in determining the I2C bit rate during the initialization process of
MSSP module in I2C mode?
a. SSPADD b. SSPBUF c. Both a & b d. None of the above Ans: a
Q.75 Which command/s should be essentially written for I2C input threshold selection
and slew rate control operations?
a. SSPSTAT b. SSPIF c. ACKSTAT d. All of the above Ans: a
Q.76 Where does the baud rate generation occur and begins to count the bits required
to get transmitted, after an execution (set) of BF flag?
a. SCL line b. SDA line c. Both a & b d. None of the above Ans: b
Q.77 How many upper bits of SSPSR are comparable to the address located in SSPADD
especially after the shifting of 8 bits into SSPSR under the execution of START
condition?
a. 7 b. 8 c.16 d.32 Ans: a
Q.78 Where should the value of TX9 bit be loaded during the 9 bit transmission in an
asynchronous mode?
a. TXSTA b. RCSTA c. SPBRG d. All of the above Ans: a
Q.79 What is the purpose of a special function register SPBRG in USART ?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bitr
d. All of the above Ans: a
Q.80 Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all
the data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity Ans: a
Q.81 How is the baud rate specified for high-speed (BRGH = 1) operation in an
asynchronous mode ?
a. FOSC / 8 (X +1 )
b. FOSC / 16 (X +1 )
c. FOSC / 32 (X +1 )
d. FOSC / 64 (X +1 ) Ans: b
Q.82 What is the status of shift clock supply in an USART synchronous mode?
a. Master - internally, Slave - externally
b. Master - externally, Slave - internally
c. Master & Slave (both) - internally
d. Master & Slave (both)- externally Ans: a
Q.83 Which bit plays a salient role in defining the master or slave mode in TXSTA
register especially in synchronous mode ?
a. RSRC b. CSRC c. SPEN d. SYNC Ans: b
Q.84 Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins
as DT (data lines) ?
a. TXSTA b. RCSTA c. Both a & b d. None of the above Ans: b
Q.85 Two wire interfaces is also called as _____ __
a. UART b. SPI c. I2C d. USART Ans: c
Q.86 I2c will address large number of slave devices.
a. True b. False Ans: a
Q.87 SDA is having a transition when the clock line SCL is high.
a. high to low b. low to high c. low to low d. high to high Ans: a
Q.88 Inter Integrated Circuit is a
a. Single master, single slave
b. Multi master, single slave
c. Single master, multi slave
d. Multi master, multi slave Ans: d
Q.89 Typical voltages used are _
a. 5v b. 3.3v c. 5v or 3.3v d. 2.5v Ans: c
Q.90 What is the speed of I2C bus?
a. 100 kbits/s b. 10 kbits/s c.75 kbits/s d.100 kbits/s and 10 kbits/s Ans: d
Q.91 Master transmits means
a. Master node is sending data to a slave
b. Master node is receiving data from slave
c. Slave node is transmitting data to master
d. Slave node is sending data to master Ans: a
Q.92 Who sends the start bit?
a. Master receive
b. Master transmit
c. Slave transmit
d. Slave receive Ans: b
Q.93 Which is the I2C messaging example?
a. 24c32 EPROM
b. 24c32 EEPROM
c. 24c33 EEPROM
d. 24c33 EPROM Ans: b
Q.94 Are pull up registers required in I2C?
a. True b. False Ans: a
Q.95 How many types of addressing structures are there in I2C?
a. 4 types b. 3 types c. 2 types d. 5 types Ans: c
Q.96 All operating modes work under
a. 11 kbit/s b. 100 kbit/s c. 15 kbit/s d. 150 kbit/s Ans: b
Q.97 Which mode is highly compatible and simply tightens?
a. Fast mode
b. High speed mode
c. Ultra fast mode
d. Both fast and high speed mode Ans: a
Q.98 What is the speed for fast mode?
a. 100 kbit/s b. 400 kbit/s c. 150 kbit/s d. 200 kbit/s Ans: b
Q.99 Which of the following is a synchronous serial interface protocol?
a. SPI b. I2C c. UART d. Both (a) and (b) Ans: d
Q.100 Synchronous interfaces make use of clock signal? State True or False
a. True b. False Ans: a
Q.101 Which of the following serial protocol is used for on-board serial communication?
a. USB b. I2C c. Wifi d. Bluetooth Ans: b
Q.102 Which of the following protocol make use of 7 bit address for its operation?
a. I2C b. SPI c. RS232 d. RS485 Ans: a
Q.103 Which of the following interface is used to 127 slave device to the master device?
a. SPI b. I2C c. RS232 d. RS485 Ans: b
Q.104 RS232 protocol makes use of clock signal for sending data? True or False
a. True b. False Ans: b
Q.105 Which serial communication interface is used to connect modems and for non
networked communication between computers and other devices?
a. SPI b. I2C c. UART d. USB Ans: c
Q.106 How many wires are used to connect I2C devices?
a. 1 wire b. 2 wires c. 3 wires d. 4 wires Ans: b
Q.107 Which of the following interface was developed by Motorola Company?
a. I2C b. SPI c. USB d. Bluetooth Ans: b
Q.108 Which of the following make use of 4 wires for its operation?
a. USB b. CAN c. SPI d. I2C Ans: c
Q.109 Which of the following is a full duplex communication interface?
a. I2C b. 1 – Wire c. SPI d. 2- Wire Ans: c
Q.110 Which of the following is true about MOSI signal?
a. Signal Line carrying the clock signal
b. Signal line for slave select
c. Signal line carrying the data from master to slave device
d. Signal line carrying the data from slave to master device Ans: c
Q.111 Which of the following supports only point to point communication and not
suitable for multi drop communication
a. RS485 b. RS232 c. RS422 d. Rs484 Ans: b
Q.112 Which of the following is a low cost, low power, short range wireless
communication for voice and data
a. Wi-Fi b. Infrared c. Zigbee d. Bluetooth Ans: d
Q.113 Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above Ans: d
Q.114 Which bits exhibit and signify the termination phase of the character
transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above Ans: b
Q.115 Two wire interfaces is also called as
a. UART b. SPI c. I2C d. USART Ans: c
Sinhgad College of Engineering, Pune41
Department of Information Technology
Course – Processor Architecture
PIC Microcontroller MCQs
Q1. In PIC18Fxxxx Microcontroller IC , letter F indicates
Option A: File register
Option B: Flash memory
Option C: Number of Flip flops
Option D: Flag register
Q2. In PIC18 microcontroller instruction set 74 instructions are _ length and
03 instructions are __ length.
Option A: 16 bit, 32 bit
Option B: 8 bit, 16 bit
Option C: 64 bit, 32 bit
Option D: 32bit, 8 bit
Q3. When the carry is generated by D3 bit to D4 bit in arithmetic operation,
which of the STATUS flag will set?
Option A: Carry ( C)
Option B: Digit Carry (DC)
Option C: Overflow (OV)
Option D: Negative (N)
Q4. The Program Counter (PC) of PIC18 microcontroller is _bit wide.
Option A: 8 bit
Option B: 15bit
Option C: 16 bit
Option D: 21 bit
Q5. The File select registers (FSRx) of PIC18 microcontroller are _bit wide.
Option A: 8 bit
Option B: 12bit
Option C: 16 bit
Option D: 21 bit
Q6. If the user attempts to retrieve more address that are stored in stack, which
flag of stack pointer will set?
Option A: Stack overflow
Option B: Stack Underflow
Option C: PUSH
Option D: POP
Q7. In PIC18 microcontroller an auto-increment feature is assigned to which of
the following register?
Option A: Bank select Register
Option B: File Select Registers
Option C: Table Pointer
Option D: Program Counter
Q8. MOVFF Fs, Fd is __________ byte instruction.
Option A: 2
Option B: 4
Option C: 6
Option D: 8
Q9. SUBWF f, d, a
In a given instruction syntax, the letter ‘ d ’ stand for
Option A: Destination of result
Option B: Direct addressing
Option C: Address of data bank
Option D: Number of digits
Q10. Specify the category of the given instruction syntax TBLRD*
Option A: Literal instruction
Option B: Table read/write
Option C: Branch instruction
Option D: Bit manipulation
Q11. Select the correct description for the given instruction TBLRD*+
Option A: Read the data from program memory pointed by TBLPTR
Option B: Read the data from program memory pointed by TBLPTR and increment
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Write the data to program memory pointed by TBLPTR and increment
TBLPTR
Q12. Select the correct description for the given instruction TBLWT+*
Option A: Read the data from program memory pointed by TBLPTR
Option B: Increment the TBLPTR then Read the data from program memory pointed by
TBLPTR
Option C: Write the data to program memory pointed by TBLPTR
Option D: Increment the TBLPTR then Write the data to program memory pointed by
TBLPTR
Q13. The control register of timer0 i.e. T0CON is _ bit register.
Option A: 4
Option B: 6
Option C: 8
Option D: 10
Q14. Write an instruction in C language to clear the Timer0 interrupt flag?
Option A: T0CONbits. TMR0IF =0;
Option B: T0CONbits. TMR0IF =1;
Option C: INTCONbits.TMR0IF = 0;
Option D: INTCONbits.TMR0IF = 1;
Q15. The Pic18 family of microcontroller USART module is capable to convert
……….
Option A: Only parallel data to serial data
Option B: Only serial data to parallel data
Option C: Both Parallel data to serial data as well as serial data to parallel data
Option D: Only serial data to serial data
Q16. If the SPBRG register of serial communication is loaded with 07H and the
clock frequency (Fosc) is 10MHz. Select the most appropriate Baud are set by
serial communication module.
Option A: 2400
Option B: 4800
Option C: 9600
Option D: 19200
Q17. To which register the does the GIE bit is belong?
Option A: INTCON
Option B: INTCON1
Option C: INTCON2
Option D: PIR1
Q18. To which register the does the TMR1IE bit is belong?
Option A: INTCON
Option B: PIE1
Option C: PIR2
Option D: PIR3
Q19. To read the 8 bit data from Command Register of LCD, select the appropriate
status to be maintained at RS and RW pin respectively.
Option A: RS =0, RW = 0
Option B: RS =0, RW =1
Option C: RS =1, RW = 0
Option D: RS =1, RW = 1
Q20. While interfacing 16X2 LCD with microcontroller, +5V and ground are to be
connected to _ &_ pin respectively.
Option A: VEE & VCC
Option B: VCC & VEE
Option C: VSS & VCC
Option D: VCC & VSS
Q21. If the TRISB = 0x00; then PORTB will be set as ___ _
Option A: Input Port
Option B: Bidirectional Port
Option C: Output Port
Option D: Work as buffer
Q22. PORTx, TRISx and LATx are which type of registers associated with ports?
Option A: GPRs
Option B: SFRs
Option C: FSRs
Option D: CPURs
Q23. Which instruction is used to clear single bit?
Option A: BSF
Option B: BCF
Option C: BTFSS
Option D: BTFSC
Q24. Write an instruction in C language to Start Analog to Digital conversion of
ADC module of Pic18 microcontroller.
Option A: ADCON0bits.GO = 1;
Option B: ADCON0bits.ADON = 0;
Option C: ADCON0bits.GO = 0;
Option D: ADCON0bits.ADON= 1;
Q25. To which register does the Channel selection bits of ADC module are belong?
Option A: PIR1
Option B: PIR2
Option C: ADCON0
Option D: ADCON1
Unit I MCQ Question Bank
Subject: PA Class: SE
Course Outcomes:
CO1: Apprehend architecture and memory organization of PIC 18 microcontroller.
CO2: Implement embedded C programming for PIC 18.
Bloom’s Level:
Understanding
Sr. Question Marks CO Complexity
No. No. Level
Unit I
1. PIC 18 F is-------------bit microcontroller 1 1,2 I
a) 8
b) 16
c) 32
d) 64
2. There are how many I/O ports in PIC 18 microcontroller 1 1,2 I
a) 3
b) 4
c) 5
d) 6
3. SFR stand for 1 1,2 I
a) Special function register
b) Standard function register
c) Both of the above
d) None of the above
4. Size of each access bank in PIC 18 microcontroller------ 1 1,2 I
a) 24 bytes
b) 256 bytes
c) 64 bytes
d) 124 bytes
5. In PIC 18 microcontroller, program counter is-----bit wide 1 1,2 I
a) 8
b) 12
c) 21
d) 32
6. PIC18 microcontroller’s architecture is based on Harward 1 1,2 I
architecture
a) True
b) False
7. Size of program memory in PIC 18 microcontroller 1 1,2 I
a) 4096 bytes
b) 124 bytes
c) 12 bytes
d) 1024 bytes
8. WREG in PIC 18 microcontroller stands for 1 1,2 I
a) Working register
b) Write register
c) Wrong register
d) None of the above
9. Which flag registers will be set when intermediate carry is generated 1 1,2 I
a) Carry flag
b) Digit carry flag
c) Zero flag
d) Overflow flag
10. Which flags are more likely to get affected in status registers by 1 1,2 I
Arithmetic and Logical Unit (ALU) of PIC 16 CXX on the basis of
instructions execution?
a) Carry( C) Flag
b) Zero (Z) Flag
c) Digit Carry (DC) Flags
d) All of the above
11. Which operational feature of PIC allows it to reset especially when 1 1,2 II
the power supply drops the voltage below 4V?
a) Built-in Power-on-reset
b) Brown-out reset
c) Both a & b
d) None of the above
12. Which among the below assertions represent the salient features 1 1,2 II
of PIC in C-18 compiler?
a) Transparent read/ write access to an external memory
b) Provision of supporting an inline assembly during the necessity
of an overall control
c) Integration with MPLAB IDE for source-level debugging
d) All of the above
13. IC PIC 18F4550 has--------no of pins 1 1,2 II
a) 50
b) 100
c) 40
d) 120
14. The RPO status register bit has the potential to determine the 1 1,2 II
effective address of______
a) Direct Addressing Mode
b) Indirect Addressing Mode
c) Immediate Addressing Mode
d) Indc. Watchdog Timer (WDT) exed Addressing Mode
15. Which condition/s of MCLR (master clear) pin allows resetting of 1 1,2 II
the PIC?
a) High
b) Low
c) Moderate
d) All of the above
16. Which command enables the PIC to enter into the power down 1 1,2 II
mode during the operation of watchdog timer (WDT)?
a) SLEEP
b) RESET
c) STATUS
d) CLR
17. Which among the below specified registers are addressable only 1 1,2 II
from bank1 of SFR?
a) PORTA (05H)
b) PORTB (06H)
c) FSR(04H)
d)ADCON0 (07H)
18. Which data memory control and handle the operation of several 1 1,2 II
peripherals by assigning them in the category of special function
registers?
a) Internal on-chip RAM
b) External off-chip RAM
c) Both a & b
d) None of the above
19. Which register bank is supposed to get selected if the values of 1 1,2 II
register bank select bits RS1 & Rs0 are detected to be ‘1’ & ‘0’
respectively?
a) Bank 0
b) Bank 1
c) Bank 2
d) Bank 3
20. If we say microcontroller is 8-bit then here 8-bit denotes size of: 1 1,2 II
a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
21. What is the most appropriate criterion for choosing the right 2 1,2 III
microcontroller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
22. Which among the below stated reasons is/are responsible for the 2 1,2 III
selection of PIC implementation/design on the basis of Harvard
architecture instead of Von-Newman architecture?
a) Improvement in bandwidth
b) Instruction fetching becomes possible over a single
instruction cycle
c) Independent bus access provision to data memory even while
accessing the program memory
d) All of the above
23. Generation of Power-on-reset pulse can occur only after 2 1,2 III
__________
a) the detection of increment in VDD from 1.5 V to 2.1 V
b) the detection of decrement in VDD from 2.1 V to 1.5 V
c) the detection of variable time delay on power up mode
d) the detection of current limiting factor
24. Which among the below mentioned PICs do not support the Brown- 2 1,2 III
Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a) A&B
b) C & D
c) A & C
d) B & D
25. When does it become possible for a bit to get accessed from bank 2 1,2 III
‘0’ in the direct addressing mode of PICs?
a) Only when RPO bit is set ‘zero’
b) Only when RPO bit is set ‘1’
c) Only when RPO bit is utilized along with 7 lower bits of
instruction code
d) Cannot Predict
Unit Wise MCQ Question Bank
Subject: PA Class: SE
Sr. Question Ma CO Complexity
No. rks No. Level
Unit II
26. There are total -----I/O ports in PIC18F4550 1 2,3 I
a) 3
b) 4
c) 5
d) 6
27. All I/O ports are of size 8 bits 1 2,3 I
a) True
b) False
28. To make PORT B in output mode,you must place-----in----register 1 2,3 I
a) 0,TRISB
b) 1,TRISB
c) 0,TRISA
d) 1,TRISA
29. The instruction BSF PORTB,1 makes pin RB! High 1 2 I
a) True
b) False
30. Timer 0 can use only in 16 bit mode 1 3 I
a) True
b) False
31. T0CON is bit addressable register 1 3 I
a) True
b) False
32. How many timers are in PIC 18F? 1 3 I
a) 2
b) 3
c) 4
d) 5
33. Timer1 supports highest prescaler value as------- 1 3 I
a) 1:2
b) 1:4
c) 1:8
d) 1:16
34. What is the range of unsigned char in 1 3 I
a) -128 to127
b) 0 to 255
c) 0 to 65535
d) To 1
35. Both Timer 2 and Timer 3 are 16 bit 1 3 I
a) True
b) False
36. Which control register is used for TIMER2 in PIC18F458? 1 3 II
a) T2CON
b) ADCON
c) TRIST2
d) TMR2
37. Which bit from T0CON decides whether timer 0 will be working in 8 bit or 16 1 3 II
bit mode?
a) T0CS
b) PSA
c) TMR0ON
d) T08BIIT
38. What is the range for data type unsigned int in embedded C? 1 2 II
a) 0 to 65535
b) 0 to 255
c) -128 to +128
d) None of above
39. How to create time delay in PIC18C : 1 3 II
a) Using for loop
b) Using timers
c) Using oscillator
d) Both a and b
40. Which condition/s of MCLR (master clear) pin allow to reset the PIC? 1 2 II
a) HIGH
b) LOW
c) MODERATE
d) All of the above
41. BTFSC means: 1 2 II
a) Bit test f,skip if clear.
b) Bit test flag ,skip test
c) Bit test first skip test
42. What action will happen after execution of the following instruction: 1 2 II
BCF TRISC,2
a) Make pin 2 of port D as o/p pin
b) Make pin 2 of port C as o/p pin
c) Clear all pins of PORT C
d) Make pin 2 of port C as i/p pin
43. What is the formula to calculate timer frequency(F timer)? 1 3 II
a) Fosc/4
b) Fosc*1/4
c) (Fosc/4)*(prescalar Ratio)
d) none
44. T3CON is ----- bit control register 1 3 II
a) 8 bit
b) 16 bit
c) 32 bit
d) 4 bit
45. TRISD=0 will make: 1 2 II
a) Port D o/p port
b) Port C o/p port
c) Port D i/p port
d) Port D 0/p port
46. When TMR3CS=1 (bit 1)from T3CON register what does it mean: 2 3 III
a) Enables TIMER3
b) Prescale value
c) External clock input from timer1 oscillator
d) R/w mode enable
47. Find the frequency of timer when Fosc=10MHz. 2 3 III
a) 625
b) 125
c) 225
d) 312
48. XTAL=10 MHz,Prescaler ratio:1:81 desired delay is 1000ms what will be the 2 3 III
value to be loaded in 8 bit timer0 register:
a) 85EEH
b) E796H
c) 3DH
d) 0CH
49. By using which of the following instructionwe can write a code which will 2 3 III
toggle the pin 2 of PORT C?
a) BCF,BTG,BRA
b) BRA
c) MOLW
BSF
50. XTAL=10 MHZ,Prescaler ratio:1:8, desired delay is 20ms what will be the value 2 3 III
to be loaded in 16 bit timer register:
e) 85EEH
f) E796H
g) 3DH
h) 0CH
Unit III and IV MCQ Question Bank
Subject: PA Class: SE
Course Outcomes:
CO2: Implement embedded C programming for PIC 18.
CO3: Use concepts of timers and interrupts of PIC 18.
CO 4: Demonstrate real life applications using PIC 18.
Bloom’s Level:
CO2 and CO3: Applying
CO4: Understanding
Sr. Question Marks CO Compl
No. No. exity
Level
Unit III
51. The return address from the interrupt-service routine is stored on the 1 2,3,4 I
___________
a) System heap
b) Processor register
c) Processor stack
d) Memory
52. The time between the receiver of an interrupt and its service is ______ 1 2,3,4 I
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
53. The signal sent to the device from the processor to the device after receiving 1 2,3,4 I
an interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
54. A single Interrupt line can be used to service n different devices. 1 2,3,4 I
a) True
b) False
55. An interrupt that can be temporarily ignored is ___________ 1 2,3,4 I
a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
56. Which interrupt is unmaskable? 1 2,3,4 I
a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5
57. Give the name of interrupt in INTCON register. 1 2,3,4 I
a) TMR0
b) INT0
c) TMR1
d) INT1
58. How is a software interrupt created? 1 2,3,4 I
a) instruction set
b) sequential code
c) concurrent code
d) porting
59. What does NMI stand for? 1 2,3,4 I
a) non-machine interrupt
b) non-maskable interrupt
c) non-massive interrupt
d) non-memory interrupt
60. While CPU is executing a program, an interrupt exists then it 1 2,3,4 I
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
61. Which of the following instruction will enable the TMR0 interrupt? 1 2,3,4 II
a) INTCONbits.TMR0IF=1;
b) TCONbits.TMR0IF=0;
c) INTCONbits.TMR0IE=1;
d) INTCONbits.TMR0IE=0;
62. What memory address in the interrupt vector table is assigned to high-priority 1 2,3,4 II
interrupts?
a) 0x0008
b) 0x0018
c) 0x0080
d) 0x0081
63. The INT1IF bit belongs to the ___________________ register. 1 2,3,4 II
a) INTCON1
b) INTCON2
c) INTCON3
d) PIR1
64. After RETI instruction is executed then the pointer will move to which 1 2,3,4 II
location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
65. While executing the main program, if two or more interrupts occur, then the 1 2,3,4 II
sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
66. The input and output operations are respectively similar to the operations, 1 2,3,4 II
a) read, read
b) write, write
c) read, write
d) write, read
67. How many rows and columns are present in a 16*2 alphanumeric LCD? 1 2,3,4 II
a) rows=16, columns=2
b) rows=2, columns=12
c) rows=16, columns=16
d) rows=2, columns=16
68. For writing commands on an LCD, RS bit is 1 2,3,4 II
a) set
b) reset
c) both
d)none
69. Which command of an LCD is used to shift the entire display to the right? 1 2,3,4 II
a) 0x1C
b) 0x18
c) 0x50
d)0x07
70. What is the principle on which electromagnetic relays operate? 1 2,3,4 II
a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
71. How can we control the speed of a stepper motor? 2 2,3,4 III
a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) can’t be controlled
72. Which of the following step/s is/are correct to perform reading operation from 2 2,3,4 III
an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
73. Which instruction is used to select the first row first column of an LCD? 2 2,3,4 III
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
74. To identify that which key is being pressed, we need to: 2 2,3,4 III
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
75. How can we change the speed of a DC motor using PWM? 2 2,3,4 III
a) By changing amplitude of PWM
b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
UNIT IV
1. Which among the below mentioned aspect issues are supported by 1 2,4 I
capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
2. Which mode allows to deliver the contents of 16-bit timer into a SFR based on 1 2,4 I
rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
3. What among the below specified functions is related to PWM mode? 1 2,4 I
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an
user assigned frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
4. What happens when the program control enters the Interrupt Service 1 2,4 I
Subroutine (ISS) due to enabling of CCP1IE bit in PIE1 especially during the
initialization of CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L &
TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
5. The capture operation in counter mode is feasible when mode of CCP module 1 2,4 I
is _________
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
6. Speed of DC motors are controlled by 1 2,4 I
a. Flux control method
b. Rheostatic control method
c. Voltage control method
d. All of these
7. The rotor of a stepper motor has no 1 2,4 I
a) Windings
b) Commutator
c) Brushes
d) All of the mentioned
8. A stepper motor may be considered as a ____________ converter. 1 2,4 I
a) Dc to dc
b) Ac to ac
c) Dc to ac
d) Digital-to-analogue
9. Which of the following can be used for long distance communication? 1 2,4 I
a) I2C
b) Parallel port
c) SPI
d) RS232
10. Which type of motor is suitable for computer printer device? 1 2,4 I
a. Reluctance motor
b. Hysteresis motor
c. Stepper motor
d. Shaded pole motor
11. Stepper motors are widely used because…. 1 2,4 II
a. Wide speed range
b. Large rating
c. No need for field control
d. Compatibility with digital systems.
12. Which is most commonly used UART? 1 2,4 II
a. 8253
b. 8254
c. 8259
d. 8250
13. Which of the following are the three hardware signals? 1 2,4 II
a) START, STOP, ACKNOWLEDGE
b) STOP, TERMINATE, END
c) START, SCL, SDA
d) STOP, SCL, SDA
14. SDA is having a ____________transition when the clock line SCL is high. 1 2,4 II
a) high to low
b) low to high
c) low to low
d) high to high
15. Which of the following is an advantage of SPI? 1 2,4 II
a) No start and stop bits
b) Use 4 wires
c) Allows for single master
d) Error checking is not present
16. What rate can define the timing in the UART? 1 2,4 II
a) bit rate
b) baud rate
c) speed rate
d) voltage rate
17. The serial communication is used for 1 2,4 II
a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
18. I2C protocol supports ……..types of addressing structures 1 2,4 II
a. 2
b. 3
c. 4
d. 5
19. Which lines are utilized during the enable state of hardware flow control in 1 2,4 II
DTE and DCE devices of RS232 ?
a. CD & IR
b. DSR & DTR
c. RTS & CTS
d. None of the above
20. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data 1 2,4 II
bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
21. The disadvantage of RS232 is 2 2,4 III
a. Limited speed of communication
b. High voltage level signaling
c. Big size communication adapter
d. All of the above
22. Why are the pulse width modulated outputs required in most of the 2 2,4 III
applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
23. What is the difference between UART and USART communication? 2 2,4 III
a) they are the names of the same particular thing, just the difference of A and
S is there in it
b) one uses asynchronous means of communication and the other uses
synchronous means of communication
c) one uses asynchronous means of communication and the other uses
asynchronous and synchronous means of communication
d) one uses angular means of the communication and the other uses linear
means of communication
24. Which of the following signals are active low in the 8250 UART? 2 2,4 III
a) BAUDOUT
b) DDIS
c) INTR
d) MR
25. How does the pin RC2/CCP1 get configured while initializing the CCP 2 2,4 III
module in the compare mode of operation?
a. As an input by writing, it in TRISC register
b. As an output by writing, it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC
register
d. Compare mode does not support pin RC2/CCP1 configuration CCP
initialization
Unit-1 PIC Microcontroller Architecture
Difficulty
Sr. Level (Low- Correct
Item Text Option Text 1 Option Text 2 Option Text 3 Option Text 4
No. 1,Medium- Option
2,High -3)
High Combination of
PIC 18f452 Miceocontroller has High performance
performance both RISC and
______ RISC CPU
1 1 CISC CPU CISC CPU Advanced RISC CPU 1
PIC 18f452 Microcontroller has _____
2 1 Timer modules 1 2 3 4 4
FLASH Program Memory of
3 1 PIC18F452 is _______ 128K 64K 32K 16K 3
PIC 18f452 is
4 1 ________Microcontroller 8 16 32 64 1
5 1 PIC18F452 has total _____ pins . 40 20 16 8 1
Instruction set of PIC18F452 has
6 1 _________instructions 33 35 40 75 4
7 1 PIC18F452 has _____ ADC 8 bit 10 bit 12 bit 14 bit 2
8 1 PORT names of PIC18F452 are 0,1 0,1,2,3,4 A,B,C,D,E A,B,C 3
deep sleep, deep
PIC18F452 has power down modes :
9 1 sleep, idle sleep, deep sleep idle, deep sleep power down 1
Watch Down Width Delay
WDT stands for ________
10 1 Timer Watch Dog Timer Timer Watch Delay Timer 2
PIC18F542 has ____program
11 1 counter 8-bit 16-bit 20-bit 21-bit 4
Each instruction has two parts Opcode and Opcode and Operand and Opcode and Pointer
12 1 __________ Register Operand Register value 2
Arithmatic Move and Load Branch
ADDWFC, SUBWF are
13 1 Instructions instructions instructions Logical instructions 1
BNZ n : Instruction of PIC 18F452 Branch if Z flag = Branch if Z flag = Branch if Z
14 1 1 0 Accumulator is 0 None of the above 2
PIC18F 4552 has MSSP Master Master Master
(_____________)module. Synchronous Synchronous Synchronous Master Slave Serial
15 1 Serial Peripheral slave Port Serial Port Port 3
Flag 'N' in Status register of
16 1 PIC18F452 denotes Zero Flag Negative Flag Overflow Flag Carry Flag 2
17 1 Clock frequency of PIC is DC to 20MHZ AC to 20MHZ 1 to 20MHZ DC to 25MHZ 1
How many banks are available in PIC
18 1 18F452 12 16 10 14 2
What is the significance of "d=0" bit Results saved in F
19 1 in ADDWF F D a Undefined Result saved in F and W Ressult Saaved in W 4
BOD' stands for Brown OR Reset Brown out Reset Brown out Reset Board on Reset
20 1 Detection Detection Debug Detection 2
Circuit used for initialization of all Power-On Reset
Brown Out Power ON/OFF
values to default is named as Circuit
21 2 Detection Circuit circuit WDT circuit 1
In Immediate (Literal) addressing
mode The operand is _____ that
22 2 follows the opcode a register a number a pointer an address 2
Program Program
Program
Three types of memory in PIC18 Memory, Data Memory, Data Program ROM, Data
Memory, Data
enhanced microcontroller are _____ ROM, Data RAM, Data RAM, Data EEPROM
RAM, Data ROM
23 2 EEPROM EEPROM 3
Immediate,
Name of Addressing Modes in Immediate, Immediate, Immediate, Direct
Register and
PIC18F4550 are ______ Direct and Offset Direct and Index and Indirect
24 2 Indirect 4
8-bit/16-bit
timer/counter 8-bit
Timer 0 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
25 2 prescaler timer/counter register 8-bit timer/counter 1
8-bit/16-bit
timer/counter 8-bit
Timer 1 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
26 2 prescaler timer/counter register 8-bit timer/counter 2
8-bit/16-bit
timer/counter 8-bit
Timer 2 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 16-bit with 8-bit period
27 2 prescaler timer/counter register 8-bit timer/counter 3
8-bit/16-bit
timer/counter 8-bit
Timer 3 module of PIC 18F458 uses
with 8-bit timer/counter
______
programmable 8-bit with 8-bit period
28 2 prescaler timer/counter register 16-bit timer/counter 4
PIC18F452 has power down modes as deep power sleep and deep deep sleep and deep
29 2 _____ idle and sleep down and idle sleep power down 1
PIC18F452 device can be operated in
____ oscillator Configuration modes.
30 2 10 12 14 16 2
The operation of the oscillator in
PIC18F4550 is controlled through
two Configuration registers as OSCCONFIG1 and CONFIG2 and CONFIG1L and
31 2 ________ OSCCONFIG2 CONFIG2 CONFIG1H None of the above 3
PIC 18F458 has ____ External
32 2 Interrupts Five Four Six Two 4
33 2 MSSP module of PIC18F452 has ADC and PWM SPI and I2C USART and CCP I2C and PWM 2
TIMER0 TIMER0 TIMER0
T0CON Register of Timer is
CONTINUOUS CONSTANT CONTROL TIMER0 CONFIG.
__________
34 2 REGISTER REGISTER REGISTER REGISTER 3
Resets all the
The instruction RESET in PIC 18F458 : Resets the registers and Resets all the Resets all the
35 2 Microcontroller flags flags registers 2
All the Timer module Registers of PIC
36 2 18F 4550 are 64 bit 16 bit 32 bit 8 bit 1
Univeral Univeral Univeral
USART means : Synchrnous Synchrnous Synchrnous Univeral Serial
Asynchronous Asymmatric Asynchronous Asynchronous
37 2 Register Transmit Receive Transmit Receive Transmit Receive Transmit 3
Operating Frequency of PIC 18F452 is
38 2 Dc-20 MHz Dc-48MHz Dc-40 MHz Dc-60 MHz 2
EEPROM Data Memory of PIC 18F458
256 Bytes
39 2 is 128 Bytes 1KByte 128 Kbytes 2
Enhanced Enhanced Enhanced Enhanced
ECCP peropheral module of PIC
Capture/Control/ Capture/Compar Control/Compare Capture/Compare/P
18F458 has
40 2 PWM e/Power /PWM WM 4
What is program memory size of PIC
41 2 2K 8k 2MB 64KB 3
Load an 8 bit
The instruction "MOVLW 8- bits" of
address into Load an 8 bit Move an 8 bit Move an 8 bit literal
PIC18F4550 signifies :
42 3 WREG literal into WREG literal into WREG into any register 2
Frequency Background
CONFIG2L is used for Reset voltage
43 3 Selection debugger Watch dog timer 4
Timer1 , Timer3 Timer1 , Timer3 Timer1 , Timer2
Timer1 ,Timer2 and
for PWN mode for Capture or for Capture or
Which of the following is TRUE for Timer3 for Capture
and Timer2 for Compare modes Compare modes
PIC18F458 Timer modules or Compare and
Capture or and Timer2 for and Time3 for
PWM mode.
Compare modes. PWM mode. PWM mode.
44 3 2
Decrement F and
Decrement F and Decrement F and Decrement S and skip
The instruction of DECFSZ F,d,a skip the next
go to the next skip the next the next instruction if
means : instruction if F is
instruction if F=0 instruction if F=0 F=0
not Zero
45 3 3
Keeps Oscillator Keeps
The instruction SLEEP in PIC 18F458 :
for peripherals Microcontroller Resets all the
46 3 OFF in standby mode registers Set all registers 2
In T1CON register , BIT 0 is _____and TMR1CS,TMR1O T1CKPS0,T1CKPS
47 3 BIT1 is _______ T1CKPS1,T1CKPS0 N 1 TMR1ON,TMR1CS 4
to store the Hex
TMR0H and TMR0L registers of PIC to set bits of values to
18F458 are used ____ to control On and Timer Control generate delay of to initialize the Timer
48 3 OFF of TIMER0 Register specific time settings 3
Clear Timer0
"INTCONbits.TMR0IF = 0" statement
Clears Timer0 Interrupt enable
for PIC 18F458 :
49 3 overflow flag flag Clear Timer0 Overflow detect 1
1) How many clock pulses are confined by each machine cycle of Peripheral-
Interface Controllers?
a. 4
b. 8
c. 12
d. 16
Answer Explanation Related Ques
ANSWER: 4
Explanation:
No explanation is available for this question!
2) Which flags are more likely to get affected in status registers by Arithmetic and
Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
Answer Explanation Related Ques
3) What is the execution speed of instructions in PIC especially while operating at
the maximum value of clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
Answer Explanation Related Ques
ANSWER: 0.2 μs
Explanation:
No explanation is available for this question!
4) Which operational feature of PIC allows it to reset especially when the power
supply drops the voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Brown-out reset
Explanation:
No explanation is available for this question!
5) Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program
memory
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
6) Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs
a. Only C
b. C & D
c. A, B & D
d. A, B & C
Answer Explanation Related Ques
ANSWER: A, B & C
Explanation:
No explanation is available for this question!
7) Which timer/s possess an ability to prevent an endless loop hanging condition of
PIC along with its own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
Answer Explanation Related Ques
ANSWER: Watchdog Timer (WDT)
Explanation:
No explanation is available for this question!
8) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
Answer Explanation Related Ques
ANSWER: Program Counter Latch (PCLATH) Register
Explanation:
No explanation is available for this question!
9) Which register/s is/are mandatory to get loaded at the beginning before loading
or transferring the contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
Answer Explanation Related Ques
ANSWER: W
Explanation:
No explanation is available for this question!
10) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
Answer Explanation Related Ques
ANSWER: 1
Explanation:
No explanation is available for this question!
11) Which among the below mentioned bits specify the reset status of register in
readable format and are usually utilized in sleep mode of PIC?
a. TO
b. PD
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Both a & b
Explanation:
No explanation is available for this question!
12) The RPO status register bit has the potential to determine the effective address
of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
Answer Explanation Related Ques
ANSWER: Direct Addressing Mode
Explanation:
No explanation is available for this question!
13) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
Answer Explanation Related Ques
ANSWER: Digits Carry bit (DC)
Explanation:
No explanation is available for this question!
14) Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect
addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect
addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF
instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction
in indirect addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
Answer Explanation Related Ques
ANSWER: Only A
Explanation:
No explanation is available for this question!
15) Which among the below stated registers specify the address reachability within
7 bits of address independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
16) Where do the contents of PCLATH get transferred in the higher location of
program counter while writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
Answer Explanation Related Ques
ANSWER: 13th bit
Explanation:
No explanation is available for this question!
17) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
Answer Explanation Related Ques
ANSWER: Low
Explanation:
No explanation is available for this question!
18) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
Answer Explanation Related Ques
ANSWER: the detection of increment in VDD from 1.5 V to 2.1 V
Explanation:
No explanation is available for this question!
19) What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
Answer Explanation Related Ques
ANSWER: 1024 cycles
Explanation:
No explanation is available for this question!
20) Which kind of mode is favourable for MCLR pin for indulging in reset
operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
Answer Explanation Related Ques
ANSWER: Sleep mode
Explanation:
No explanation is available for this question!
21) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
Answer Explanation Related Ques
ANSWER: For ensuring the inception and stabilization of an oscillator in a proper manner
Explanation:
No explanation is available for this question!
22) Which program location is allocated to the program counter by the reset
function in Power-on-Reset (POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
Answer Explanation Related Ques
ANSWER: Initial address
Explanation:
No explanation is available for this question!
23) When does it become very essential to use the external RC components for the
reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
Answer Explanation Related Ques
ANSWER: Only if VDD power-up slope is insufficient at a requisite level
Explanation:
No explanation is available for this question!
24) Which among the below mentioned PICs do not support the Brown-Out-Reset
(BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
Answer Explanation Related Ques
ANSWER: C & D
Explanation:
No explanation is available for this question!
25) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be
completely unique and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
Answer Explanation Related Ques
ANSWER: It can reset the PIC automatically in running condition
Explanation:
No explanation is available for this question!
26) What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
Answer Explanation Related Ques
ANSWER: CPU resets PIC once again in BOR mode
Explanation:
No explanation is available for this question!
27) What output is generated by OSC2 pin in PIC oscillator comprising RC
components for sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
Answer Explanation Related Ques
ANSWER: (1/8) x frequency of OSC1
Explanation:
No explanation is available for this question!
28) Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
Answer Explanation Related Ques
ANSWER: LP (Low-Power Clocking)
Explanation:
No explanation is available for this question!
29) Which significant feature/s of crystal source contribute/s to its maximum
predilection and utility as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
Answer Explanation Related Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
30) What is the executable frequency range of High speed (HS) clocking
method by using cystal/ ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
Answer Explanation Related Ques
ANSWER: 4-20 MHz
Explanation:
No explanation is available for this question!
31) How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
Answer Explanation Related Ques
ANSWER: 11 & 12 bits
Explanation:
No explanation is available for this question!
32) What location is attributed to 'goto Mainline' instruction in the program memory
of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
Answer Explanation Related Ques
ANSWER: 000H
Explanation:
No explanation is available for this question!
33) When do the special address 004H get automatically loaded into the program
counter?
a. After the execution of RESET action in program counter
b. After the execution of 'goto Mainline ' instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
Answer Explanation Related Ques
ANSWER: At the occurrence of interrupt into the program counter
Explanation:
No explanation is available for this question!
34) How many bits are utilized by the instruction of direct addressing mode in order
to address the register files in PIC?
a. 2
b. 5
c. 7
d. 8
Answer Explanation Related Ques
ANSWER: 7
Explanation:
No explanation is available for this question!
35) Which registers are adopted by CPU and peripheral modules so as to control
and handle the operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
Answer Explanation Related Ques
ANSWER: Special Function Registers
Explanation:
No explanation is available for this question!
Related Content
https://www.careerride.com/mcq-daily/microcontrollers-applications-test-questions-set-7-565.aspx
Sinhgad College of Engineering
Dept. of Information Technology
Class - SE
Processor Architecture
(214451)
Unit 2 : PIC I/O Ports and Timer
Faculty – Prof. Madhukar V. Nimbalkar
[email protected]
9890586765
SYLLABUS : UNIT 2
I/O Port: I/O Port structure with programming: I/O Port
structure, I/O Port programming, I/O Bit manipulation
Programming.
Timer/Counter: Registers used for Timer/Counter operation,
Delay calculations, Programming of Timers using Embedded
C.
Introduction
□ PIC18 has two to five timers
■ Depending on the family number
□ These timers can be used as
■ Timers to generate a time delay
■ Counters to count events happening outside the uC
□ Every timer needs a clock pulse to tick
□ Clock source can be
■ Internal 1/4th of the frequency of the crystal oscillator on
OSC1 and OSC2 pins (Fosc/4) is fed into timer
■ External: pulses are fed through one of the PIC18’s pins
Counter
TIMER Comparison
Parameter TIMER0 TIMER1 TIMER2 TIMER3
Refer TIMER0 Block Refer TIMER1 Block Refer TIMER2 Block Refer TIMER3 Block
Block Diagram
Diagram Diagram Diagram Diagram
Refer T0CON Refer T1CON Refer T2CON Refer T3CON
Control Register
Register Register Register Register
Structure
structure structure structure structure
Special Function
TMR0H, TMR0L TMR1H, TMR1L TMR2, PR2 TMR3H, TMR3L
Registers associated
Timer Mode of
8-bit / 16-bit 16-bit 8-bit 16-bit
Operation
Counter Mode of 8-bit / 16-bit Counter Not Available as
16-bit Counter 1 Counter 3
Operation 0 Counter
2, 4, 8, 16, 32, 64,
Pre-Scaling Factor 1, 2, 4, 8 1, 4, 16 1, 2, 4, 8
128, 256
1, 2, 3, 4, 5, 6. 7, 8,
Post-Scaling Factor Not Available Not Available 9, 10, 11, 12, 13, Not Available
14,15, 16
Capture, Compare Capture, Compare
Clock Source for PWM mode of CCP
Can't use mode mode
CCP Module module
of CCP module of CCP module
Timer Module.
□ The Timer0 module timer/counter which can work as timer/
counter has the following features:
• 8-bit or 16 bit timer/counter
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
□ Timer1 is 16 bit timer/ counter and cannot be operated in 8 bit.
□ Timer2 is an 8-bit timer with a prescaler. It can be used as the
PWM time-base for the PWM mode of the CCP module(s).
□ Timer3 is 16 bit timer/ counter and cannot be operated in 8 bit. It
also works in CCP mode
Timer0 registers and programming
□ TMR0L & TMR0H are 8-bit Reg.
T0CON
Reg
□ Determine the timer
operations modes
□ Example
□ If T0CON=
□ 0000 1000
■ 16-bit
■ No prescaler
T0CON (Timer0 Control) Register
TMR0IF flag bit
□ Part of INTCON
INTCON (Interrupt Control Register) has the TMR0IF
Flag
Characteristics and operations of 16-bit mode
1. 16-bit timer, 0000 to FFFFH.
2. After loading TMR0H and TMR0L, the timer must
be started.
3. Count up, till it reaches FFFFH, then it rolls over to
0000 and activate TMR0IF bit.
4. Then TMR0H and TMR0L must be reloaded with
the original value and deactivate TMR0IF bit.
Steps to program Timer0 in 16-bit mode to
generate time delay
1. Load the appropriate value into the T0CON register
2. Load reg. TMR0H followed by reg. TMR0L with initial
value
3. Start the timer with instruction
BSF T0CON, TMR0ON
4. Keep monitoring the timer flag (TMR0IF) to see if it is
raised.
5. Stop the timer
6. Clear the TMR0IF flag
7. Go Back to step 2
Timer Delay Calculation for XTAL = 10 MHz
with No Prescaler
□ General formula for delay calculation
□ Time Delay Generated = (Max. Count – Initial Count + 1) x Time period
■ Time Period = (1 / (10 MHz/4)) = 0.4 microseconds
Timer Calculation
□ Calculate total delay generated by Timer 0 if (FFF2)H is
loaded into it. Assume Crystal F = 10 MHz
Time Delay Generated = (Max. Count – Initial Count + 1) x Time period
■ Time Period = (1 / (10 MHz/4)) = 0.4 microseconds
Time Delay Generated = (FFFF – FFF2+1) X 0.4 microseconds
= 14 X 0.4 microseconds
= 5.6 microseconds
□ Calculate initial count to be loaded in timer0 with
prescaler of 256 to generate time delay 0f 2 milliseconds.
Assume crystal F = 10 MHz
Time Delay Generated = (Max. Count – Initial Count +
1) x Time period
TD = 2 ms, Max Count = 255
Time period = 1 / (10/4 ) = 1 / (2.5 MHz / 256 ) =
1 / (2500000/256) = 1/ 9765.625 Hz = 1024 microseconds =
1.024 ms
2 = (255 – IC+1) x 1.024
2/1.024 = (255 – IC+1)
1.953 = (255 – IC+1)
IC = 256 – 1.953 = 254
□ Generate square wave of 10Khz frequency with Timer
1. assume crystal F = 10 MHz
Prescaler and generating larger delay
□ The size of delay depend on
■ The Crystal frequency
■ Count in the timer’s 16-bit register.
□ The largest time delay happens when TMR0L=TMR0H=0
□ Prescaler option is used to duplicate the delay by
dividing the clock by a factor of 2,4, 8,16, 32,64 ,
128,256
■ If T0CON=0000 0101, then T = 4*64/f
XTAL Osc ÷4 ÷ 64 TMRx9-17
TIMER 0 IN 8BIT MODE
Timer1 Programming
9-22
T1CON
(Timer 1
Control )
Register
Timer1 Block Diagram
PIR1 (Interrupt Control Register 1) Contains the
TMR1IF Flag
Counter Programming
□ Used to counts event outside the PIC
■ Increments the TMR0H and TMR0L registers
□ TMR1CS in T1CON reg. determines the clock
source,
■ If TMR1CS = 1, the timer is used as a counter
■ Counts up as pulses are fed from pin RC0 (T1CKI)
■ What does T1CON=0110 1000 mean?
□ If TMR1CS=1, the timer 1 counts up as clock pulses
are fed into pin RC0
Using external Crystal for Timer1
External
clock Source
Timer1 comes with two options,
■ clock fed into T1CKI
□ T1OSCEN=0
■ Clock from a crystal connected
Internal Source
to T1OSI-T1OSO (additional)
□ T1OSCEN=1
□ 32 kHz Crystal is connected
□ Used for saving power during
SLEEP mode doesn’t disable
Timer1 while the main crystal is
shut down
9-29
9-33
9-35
Port Structure
Ports Available For PIC18F Family
Port SFRs of PIC18FXX
Every Port has 3 SFRs
associated with it
1.PORTX
2.LATX
3.TRISX
Port value after RESET
Sr. PORT Value
No Name
1 TRISA (111 1111)b
2 TRISB (11111111)
b
3 TRISC (11111111)
b
4 TRISD (11111111)
b
Outputting (Writing) ‘0’ on PORT
• Setting a TRISX bit (= 1) will
make the corresponding PORTX
pin an input (i.e., put the
corresponding output driver in
a high-impedance mode).
• Clearing a TRISX bit (= 0) will
make the corresponding PORTX
pin an output (i.e., put the
contents of the output latch on
the selected pin).
• On a Power-on Reset, these
pins are configured as inputs
and read as ‘0’.
• Reading the PORTX register
reads the status of the pins,
whereas writing to it will write
Outputting (Writing) ‘1’ on PORT
Inputting (Reading) ‘0’ on PORT
Inputting (Reading) ‘1’ on PORT
I/O PORTs
AND
BIT ADDRESSABILITY
Write embedded C program to toggle LEDs
connected to port B with specific delay (2ms).
#include<P18F4550.h>
voidT0Delay(void);
voidmain(void)
{
TRISB=0; //configure Port B as output
While(1)
{
PORTB=0x55; //load Bit Pattern
T0Delay();
PORTB=0xAA;
T0Delay();
}
} T0CON Register Format
voidT0Delay()
{
Time Delay Calculations
(Assume Crystal Frequency = 10 MHz )
Time Delay Generated = (Max. Count – Initial Count + 1) x
Time period
TD = 2 ms = 2000 microseconds, Max Count = 65535,
Prescalor = 256
Time period = 1 / (10/4 ) = 1 / (2.5 MHz / 256 ) =
1 / (2500000/256) = 1/ 9765.625 Hz = 1024 microseconds =
1.024 ms
2 = (65535 – IC+1) x 1.024
2/1.024 = (65535 – IC+1)
1.953 = (65535 – IC+1)
IC = 65536 – 1.953 = 254.047 = 65534 = FFFEh
Write embedded C program to toggle LEDs
connected to port B with specific delay (2ms).
#include<P18F4550.h>
voidT0Delay(void);
voidmain(void)
{
TRISB=0; //configure Port B as output
While(1)
{
PORTB=0x55; //load Bit Pattern
T0Delay();
PORTB=0xAA;
T0Delay();
}
} T0CON Register Format
voidT0Delay()
{
Time Delay Calculations
(Assume Crystal Frequency = 10 MHz )
Time Delay Generated = (Max. Count – Initial Count + 1) x
Time period
TD = 2 ms = 2000 microseconds, Max Count = 255,
Prescalor = 256
Time period = 1 / (10/4 ) = 1 / (2.5 MHz / 256 ) =
1 / (2500000/256) = 1/ 9765.625 Hz = 1024 microseconds =
1.024 ms
2 = (255 – IC+1) x 1.024
2/1.024 = (255 – IC+1)
1.953 = (255 – IC+1)
IC = 256 – 1.953 = 254.047 = 254 = FEh
Thank you
Sinhgad College of Engineering
Dept. of Information Technology
Class - SE
Processor Architecture
(214451)
Unit-4: PIC 18F Microcontroller
CCP Module
Faculty – Prof. Madhukar V.
Nimbalkar
[email protected]
9890586765
SYLLABUS : UNIT 4 - PIC
Interfacing-II
CCP modes: Capture, Compare and PWM generation;
DC Motor speed control with CCP, Stepper motor
interfacing with PIC
Basics of Serial communication protocols: Study of
RS232, I2C, SPI, UART, Serial communication
programming using Embedded C.
Introduction
▪ Capture and compare features allow the user to time
and control different events.
▪ PIC18F4550 has a built-in peripheral module called
the CCP (Capture/Compare/PWM) module for this
purpose.
▪ The CCP module in PIC18F4550 supports two
independent instances of Capture, Compare and
PWM feature.
Capture / Compare / PWM PIC18F4550
The abbreviation CCP stands for Capture/Compare/PWM
PIC18F4550 has an in-built CCP (Capture / Compare / PWM)
module which has input capture mode.
• CCP Modules
It is a hardware module inside the PIC microcontroller
helps to trigger events based on time.
The Capture, Compare, and PWM (CCP) modules that are
found on many of Microchip's microcontrollers are used
Primarily for the measurement and control of
time-based pulse signals.
• The input capture of the signal has applications like finding
frequency, calculating the duty cycle of the input signal,
etc.
• A PIC18 device may have one, two, or five CCP modules.
Each CCP module can be configured to perform capture,
compare, or PWM function.
CCP MODULES
• In capture operation
• The CCP module copy the contents of a timer register
into a capture register CCPR on an signal edge.
• The input pulse should be connected to CCP1 which is
multiplexed with PORTC.2 (RC2) and configure it as the
input pin.
• In compare operation
• The CCP module compares the contents of a CCPR
register with that of Timer1 (or Timer3) in every clock
cycle.
• When these two registers are equal, the associated pin
may be pulled high or low or toggled.
• PWM –
• Pulse Width Modulation can generate signals of varying
frequency and duty cycle.
CCP Modules
CCPI module is able
to use only the
following two timers
Timer1
Timer3
Capture/Compare/PWM (CCP) Modules
• Each CCP module requires the use of timer resource.
• In Capture/compare,Timer1 or Timer3 is used.
• In PWM mode, Timer2 is used.
• The operation of a CCP module is controlled by the
CCPxCON register.
• A data register (CCPRx), is comprised of two 8-bit
registers:
CCPRxL (low byte) and CCPRxH (high byte). All
registers are readable and writable.
• The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
T3CON register
CCPxCON: CCPx CONTROL REGISTER
T3CON
CCP2 PIN ASSIGNMENT
• In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding TRIS
direction bit.
• The CCP2MX Configuration bit determines which pin
CCP2 is multiplexed to. By default, it is assigned to RC1
(CCP2MX = 1).
• If the Configuration bit is cleared, CCP2 is multiplexed
with RB3.
• Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring the
port pin.
• Users must always verify that the appropriate TRIS
register is configured correctly for CCP2 operation,
regardless of where it is located.
Introduction – Capture Mode
▪ Input Capture is widely used in many applications such
as:
▪ Capturing the arrival time of an event
▪ Measuring pulse width
▪ Measuring period
▪ An event can be represented by the rising and falling
edges of a pulse. The PIC18 event can be one of the
following:
▪ 1. every falling edge
▪ 2. every rising edge
▪ 3. every 4th rising edge
▪ 4. every 16th rising edge
▪ The time of an event occurrence can be recorded by
latching the count when an edge is detected (rising or
falling). This can be done using input capture mode in
the microcontrollers.
CAPTURE MODE OPERATION BLOCK
DIAGRAM
CAPTURE MODE OPERATION BLOCK
▪ Timer1 or Timer3 are initialized to count the value in the capture
DIAGRAM
operation.
▪ T3CON register is used for selecting the Timer1 / Timer3 for input
capture. Timer must run in Timer/synchronous mode.
▪ When the event selected by the mode select bits, CCPxM<3:0>
(CCPxCON<3:0>) is detected at the CCP1 pin, the interrupt flag
CCP1IF bit of the Peripheral Interrupt (PIRx) register is set. It is
cleared through software.
▪ When an interrupt occurs, the value of the timer is copied into CCP
register CCPR1 (CCPR1H and CCPR1L), and by looking at this value
we are able to find the arrival time of that event.
▪ The interrupt flag can be monitored via software or an automatic
interrupt can be initiated if enabled, sending the program control to an
interrupt service routine. The interrupt flag must be cleared in
software.
▪ The prescaler can delay reaction to an event on the CCPx pin. The
capture of the Timer1 value can be delayed to capture on the first
edge (falling or rising), the fourth edge (rising only), or the 16th edge
(rising only).
▪ These three prescaler settings are determined by the
• Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter is
cleared. Any Reset will also clear the prescaler counter.
• Capture mode depends upon the Timer1 module for
proper operation. Two of the Timer1 clock source options
will work with the Capture mode:
• FOSC/4 instruction clock
• External clock option.
Each clock source has a different effect on Capture
mode during sleep.
• If Timer1 is driven by the instruction clock (FOSC/4),
Timer1 will not increment during sleep. This means that
the Capture mode will not work during sleep. When the
device wakes from sleep, Timer1 will continue from its
previous state.
• If Timer1 is driven by an external clock, then Timer1
will continue to increment in Sleep mode and Capture
mode will also operate during sleep.
CCP1IF Interrupt
After a capture event occurs, the interrupt flag is set.
Flag
This interrupt flag is CCP1IF (CCP interrupt flag) which is
located in the PIR1 register. The PIR1 register is shown
below.
PIR1 Register: Peripheral Interrupt Register
CCP1IF :
1 = TMR1 or TMR3 register capture occurred
(at falling or rising edge of pulse)
0 = No TMR1 or TMR3 capture occurred.
We need to enable this (CCP1IF) flag by enabling the
CCP1IE bit (CCP Interrupt enable bit) in the PIE1 register.
PIE1 Register: Peripheral Interrupt Enable
Steps for Programming Capture (CCP) Mode
Initialization of PIC18F4550 Capture mode
• Initialize the CCPCON1 register for capturing the rising or
falling edge.
• Configure the CCP1 pin as an input pin.
• If you are using Timer3, then configure the T3CON
register to select Timer3 for input capture; otherwise,
Timer1 is a default.
• Also, set the value of the T1CON or T3CON register for
deciding whether the timer register should be two 8-bit
(TMRxL and TMRxH) or 16-bit (TMRx). Note: ’x’ is for 1 or
3.
• Set CCPR1 and TMR3 / TMR1 register to 0.
• Make timer ON.
• Monitor until CCP1IF flag==1, which is set when capture
occurs.
• Copy the value of the CCPR1 register to any data
Example - Period measurement
Use the CCP channel 1 in capture mode to measure the period of an
unknown signal assuming that the PIC18 MCU is running with a 16
MHz crystal oscillator. Use the number of clock cycles as the unit of
period. The period of the unknown signal is shorter than 65536 clock
cycles.
Solution:
Either two consecutive rising edges or two falling edges must be
captured.
The difference of these two edges becomes the period of the signal.
The required timers settings are
• CCP1 (RC2): input
• Timer1CON: 16-bit mode, use instruction clock as clock
source, 1:1 pre-scaler
• Timer3CON: select Timer1 as base timer for the CCP1
capture mode
• CCP1CON: capture on every rising edge
Program
#include <p18F8720.h>
void main (void)
{
unsigned int period;
TRISCbits.TRISC2 = 1; /* configure CCP1(RC2) pin for input */
T3CON = 0x81; /* use Timer1 as the time base for CCP1 capture
*/
PIE1bits.CCP1IE = 0; /* disable CCP1 capture interrupt */
PIR1bits.CCP1IF = 0; /* clear the CCP1IF flag */
T1CON = 0x81; /* enable 16-bit Timer1, pre-scaler set to 1 */
CCP1CON = 0x05; /* capture on every rising edge */
while (!(PIR1bits.CCP1IF)); /* wait for 1st rising edge */
PIR1bits.CCP1IF = 0; /* clear the CCP1IF flag */
period = CCPR1; /* save the first edge (CCPR1 is accessed as a 16-bit
value) */
while (!(PIR1bits.CCP1IF)); /* wait for the 2nd rising edge */
CCP1CON = 0x00; /* disable CCP1 capture */
period = CCPR1 - period;
}
Example 1
Write a program to measure the period of the pulse being
fed to CCP pin. Display CCPR1 register contents 0n 7
segment display.
PORTB
PIC18F
CCP1(RC2)
PORTD
19
Example 1: Program
#include <p18f4550.h>
__CONFIG (FOSC_HS & WDTE_OFF & PWRTE_OFF & BOREN_OFF & LVP_OFF);
#define _XTAL_FREQ 10000000
void pic_init(void);
void timer_init(void);
void ccp_init(void);
main()
{
pic_init(); //initialize PIC
timer_init(); //initialize Timer Module
ccp_init(); //initialize CCP Module
while(1)
{
while(PIR1bits.CCP1IF==0)
{
T1CON=0b00000001; //start Timer1
PIR1=0b00000000;
}
20
Example 1: Program
while(PIR1bits.CCP1IF==1)
{
T1CON=0b00000000; //stop Timer1
PIR1bits.CCP1IF=0;
PORTB=CCPR1L;
PORTD=CCPR1H;
}
}
}
void pic_init(void)
{
TRISB=0b00000000;
PORTB=0b00000000;
TRISC=0b11111111;
PORTC=0b00000000;
TRISD=0b00000000;
PORTD=0b00000000;
}
21
Example 1: Program
void timer_init(void)
{
T1CON=0b00000000;
PIR1=0b00000000;
TMR1H=0;
TMR1L=0;
}
void ccp_init(void)
{
CCP1CON=0b00000100; //Capture rising edge
CCPR1H=0;
CCPR1L=0;
}
22
Example 1: Circuit Layout
23
Example1: Simulation Result
□ When clock at 150cyc high and 150cyc low, PIR will
interrupt at CCPR1L=DFH(High to low).
24
Example1: Simulation Result
□ After 2nd cycle
□ PIR will interrupt at CCPR1H=2H and CCPR1L=0BH.
25
Example1: Simulation Result
□ Subtracting these two values:
□ 20BH-DFH=12CH→300d
26
Applications of Capture Mode
▪ Event arrival time recording
▪ Period measurement
▪ Pulse width measurement
▪ Interrupt generation
▪ Event counting
▪ Time reference
▪ Duty cycle measurement
PIC18F4550 Compare Mode
• "Compare" mode continually compares the value in the
CCP register with the timer value, and triggers an
interrupt or a transition on the CCP pin when the two
values match.
• CCP in Compare mode is used to generate a waveform
of various duty cycles like PWM and also used to trigger
an event when the pre-determined time expires.
• Also, it is used to generate specific time delay.
• Output (e.g. Waveform generation) of CCP2 and CCP1
in compare mode is generated on two pins i.e. RC1 and
RC2 respectively.
Compare Mode
• In compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or the
TMR3 register pair value.
• When a match occurs between the CCPR1 Register value
and Timer value, the CCP1IF interrupt flag is generated
and one of the following actions may occur on the
associated RC2 pin:
• Toggle output on the RC2 pin.
• RC2 pin drives to a High level.
• RC2 pin drives to a low level.
• Generate software interrupt
• Generate a special trigger event.
• Remain unchanged (that is, reflects the state of the I/O
latch)
• The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the interrupt
flag bit, CCPxIF, is set.
Block diagram of Compare Mode
• Both CCP modules are equipped with a Special Event Trigger. This is an
internal hardware signal generated in Compare mode to trigger actions by
other modules. The Special Event Trigger is enabled by selecting the
Compare Special Event Trigger mode (CCPxM<3:0> = 1011).
• For either CCP module, the Special Event Trigger resets the Timer
register pair for whichever timer resource is currently assigned as the
module’s time base.
• This allows the CCPRx registers to serve as a programmable Period
register for either timer.
• The Special Event Trigger for CCP2 can also start an A/D conversion. In
order to do this, the A/D Converter must already be enabled.
CCP1CON Register: CCP1 Control Register
DC1B1:DC1B0:
Used for PWM mode.
CCP1M3:CCP1M0: CCP1 module mode select bit
These bits decide which action takes on compare match.
0010 = Toggle output on match
1000 = Initialize CCP1 pin low, on compare match this pin is set to high.
1001 = Initialize CCP1 pin high, on compare match this pin is set to low.
1010 = On compare match generates software interrupt.
1011 = On compare match trigger special event, reset the timer, start
ADC.
So Configure compare mode as per application using CCP1CON
Register.
Now How to calculate Count for CCPR1?
The following figure illustrates steps to calculate count for
the desired delay which to be load into CCPR1 Register.
Steps for Programming
• Set the CCP1 pin as an output.
• Configure T3CON Register for Timer1 or Timer 3
• If Timer1 is used then configure T1CON Register
also.
• Configure CCP1CON Register for compare mode.
• Load desired count in CCPR1 (CCPR1H: CCPR1L)
Register.
• Also, initialize TMR1 or TMR3 register value.
• Start Timer
• Wait for CCP1IF (PIR1<2>) interrupt flag to set.
• Then Clear Timer Register (TMR1 or TMR3).
Example
Use CCP1 to generate a periodic waveform with 40% duty
cycle and 1 KHz frequency assuming that the instruction cycle
clock frequency is 4 MHz.
Solution: For the 1 KHz waveform with 40% duty cycle
T= 1/1KHz = 1 ms = 1000 us
TON = 400 us
TOFF = 600 us
Instruction clock cycle period = 1/ 4MHz = 0.25us
CCPR Count for ON period = 400 us / 0.25 us = 1600
CCPR Count for OFF period = 600 us / 0.25 us = 2400
400
μs
600
μs
Program
#include <p18F8720.h>
void main (void)
{
TRISCbits.TRISC2 = 0; /* configure CCP1 pin for output */
T3CON = 0xC9; /* turn on TMR3 in 16-bit mode, TMR3 as base timer
for all CCP modules */
CCP1CON = 0x09; /* configure CCP1 pin set high initially and pull low on
match */
CCPR1 = TMR3 + 1600; /* start CCP1 compare operation with 1600 cycles delay */
PIR1bits.CCP1IF = 0;
while (1) {
while (!(PIR1bits.CCP1IF));
PIR1bits.CCP1IF = 0;
CCP1CON = 0x08; /* set CCP1 pin low initially, pull high on match */
CCPR1 += 2400; /* start CCP1 compare with 2400 as delay */
while (!(PIR1bits.CCP1IF));
PIR1bits.CCP1IF = 0;
CCP1CON = 0x09; /* change CCP1 setting */
CCPR1 += 1600;
}
}
Example
Generate a square wave of 1 kHz having a 50% duty
cycle.
For 50% Duty Cycle
Assume Oscillator frequency = 8MHz
Period of waveform = 1ms (1 KHz given)
So Instruction Cycle = 1/ (FOSC/4) = 1/ (8MHz/4) = 0.5
us
That means Timer will increment its count continuously
after each 0.5us delay.
Calculate CCPR1 count.
For 50% Duty Cycle
ON time=OFF time=0.5ms
CCPR1 count = 0.5ms/0.5us = 1000 i.e. 0x03E8
CCPR1 count = 0x03E8
Compare operation Program
#include <p18f4550.h>
void main()
{ int i;
TMR3H=0x00;
TMR3L=0x00;
CCP1CON=0x02; //compare mode
TRISC=0x00; //RC2 output
PORTC=0x00;
T3CON=0xc1;
CCPR1L=0x06;
CCPR1H=0x00;
TRISD=0x00;
PIR1bits.CCP1IF=0;
INTCONbits.GIE=1;
INTCONbits.PEIE=1;
for(i=0;i<2;i++)
{ }
//PORTCbits.RC2=1;
if (PIR1bits.CCP1IF==1)
{
PORTD=~PORTD;
PIR1bits.CCP1IF=0;
// PORTCbits.RC2=0;
}
}
What is Pulse Width Modulation
• Pulse Width Modulation (PWM) is a technique by which the
width of a pulse is varied while keeping the frequency of the
wave constant.
• The applications such as motor speed control, for encoding
messages in telecommunication systems and for controlled
switching in switch mode power supplies and for sound
synthesis in audio amplifiers etc.
• If a logic zero (0) represents switch-off and logic one (1)
represents switch on, the power that the load consumes will be
directly proportional to the pulse duration. This ratio is often
called Duty Cycle.
Duty Cycle
A period of a pulse consists of an ON cycle (5V) and
an OFF cycle (0V). The fraction for which the signal is
ON over a period is known as a duty cycle.
E.g. A pulse with a period of 10ms will remain ON
(high) for 2ms.Therefore, the duty cycle will be
D = 2ms / 10ms = 20%
• Through the PWM technique, we can control the power
delivered to the load by using the ON-OFF signal.
• The PWM signals can be used to control the speed of DC
motors and to change the intensity of the LED. Moreover, it
can also be used to generate sine signals.
• In the image, the green lines represent a regular time period.
This duration or period is the inverse of the PWM frequency.
PWM
Create pulses with variable widths.
A PWM output is basically a square waveform with a
specified period and duty cycle.
The pulse width modulation (PWM) mode produces a PWM
output.
CCPx pin produces up to a 10-bit resolution PWM output.
41
PWM-Period
The PWM period is specified by writing to the PR2 register.
The PWM period can be calculated using the following
formula:
PWM Period = [(PR2) + 1] • 4 • TOSC •(TMR2 Pre-scale
Value)
Where:
PR2 is the value loaded into Timer 2 register
TMR2PS is the Timer 2 pre-scaler value (1/4/16)
TOSC is the clock oscillator period (seconds)
The PWM frequency is defined as 1/(PWM period).
42
PWM-Period
Example:
If XTAL=20MHz and FPWM=1.22kHz;
PR2 = 4,097 –which is larger than 256(8bit)
Reducing the FOSC through pre-scaler value (set to 16)
PR2 = 255 43
PWM-Duty Cycle
• Portion of pulse that stays HIGH relative to the entire
period.
• Supports up to 10 bit resolution.
• CCPx pin TRIS bit must be cleared to configure the pin as
output.
• PWM mode is enabled by placing CCPxM3:CCPxM0 =
b’11xx.
• Specified by writing to the CCPR1L register and to the
CCP1CON<5:4> bits.
• The CCPR1L contains the eight LSbs and the
The following equation
CCP1CON<5:4> is used
contains totwo
the calculate
MSbs.the PWM duty cycle
in time:
PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) •4 •TOSC • (TMR2 Pre-scaler)
44
Timer2 Register
Working of PWM in CCP module
• Load the period value in a PR2
register and the duty cycle value
in CCPR1L: CCP1CON<5: 4>
registers and initialize the CCP1
pin as an output.
• Configure the T2CON register
and set the TMR2 register to 0.
Also, start the Timer2.
• Now when a match occurs
between registers PR2 and
TMR2, pin CCP1 is pulled high
and TMR2 is cleared.
• The value of CCPR1L along with
the CCP1CON<5: 4> which is a
count for duty cycle is moved to
the CCPR1H.
• Finally, TMR2 is compared with
the CCPR1H along with two
lower bits of a duty cycle. When
matched, the pin CCP1goes
low.
Programming in PWM mode
1. Set PWM period through PR2 register.
PR2=0x37;
2. Set PWM duty cycle through CCPR1L for the first 8-bits.
CCPR1L=0b00011011;
3. Set CCP pin as an output.
TRISCbits.CCP1=0;
4. Set pre-scale value through T2CON.
T2CON= 0b00000000;
5. Clear TMR2 register.
TMR2=0;
6. Configure CCP1CON for PWM, CCPxX and CCPxY for
the remaining 10-bits
CCP1CON=0b00001100;
7. Start Timer2.
T2CON=0b00000101;
47
Example 3
PWM pulses must be generated from pin CCP1 of a
PIC18F microcontroller. The required pulse period is 44μs
and the required duty cycle is 50%. Assuming that the
microcontroller operates with a 20MHz crystal, calculate
the values to be loaded into the various registers. The
pre-scaler of timer2 is 4.
TOSC = 1/20MHz = 5x10-8s
PWM duty cycle period = 44μs * 0.5 = 22μs.
48
Example 3
Which is equivalent to 10-bit binary : “00 00011011”
CCPR1L:CCP1CON<5:4>
PWM Mode
XX111100
CCP1CON=0b00111100;
CCPR1L=0b00000110
49
Example 3-Program
#include <p18f4550.h>
__CONFIG (FOSC_HS & WDTE_OFF & PWRTE_OFF & BOREN_OFF & LVP_OFF);
#define _XTAL_FREQ 20000000
void pic_init(void);
void timer_init(void);
void ccp_init(void);
main()
{
pic_init(); //initialize PIC
timer_init(); //initialize Timer Module
ccp_init();
while(1)
{
T2CON=0b00000101; //start Timer2
while(PIR1bits.TMR2IF==0)
{
PIR1bits.TMR2IF=0;
}
}
}
50
Example 3-Program
void pic_init(void)
{
TRISC=0b00000000;
PORTC=0b00000000;
}
void timer_init(void)
{
T2CON=0b00000000;
PR2=0x36;
TMR2=0;
}
void ccp_init(void)
{
CCPR1L=0b00000110;
CCP1CON=0b00111100; //PWM mode
}
51
Example 3-Circuit Layout
52
Example 3-Simulation Result
53
Example 3-Simulation Result
54
Example
Generate 10KHz PWM with a 20% duty cycle.
#include "osc_config.h"
#include <pic18f4550.h>
void main()
{
OSCCON = 0x72; /* Set internal clock to 8MHz */
TRISC2 = 0; /* Set CCP1 pin as output for PWM out */
PR2 = 199; /* Load period value */
CCPR1L = 40; /* load duty cycle value */
T2CON = 0; /* No pre-scalar, timer2 is off */
CCP1CON = 0x0C; /* Set PWM mode and no decimal for PWM */
TMR2 = 0; /* Clear Timer2 initially */
TMR2ON = 1; /* Timer ON for start counting*/
while(1);
}
DC Motor Control using PWM mode of CCP
• DC Motor Driver is a L293D based motor driver
interface board.
• The main aim of interfacing DC motor with any
microcontroller is to control the direction and speed of a
DC motor.
• But due to high voltage and current requirement of DC
motors, it cannot be interfaced directly with
microcontrollers.
• For to interface DC motor with any microcontroller, we
need a motor driver.
Motor driver is basically a current amplifier which takes a
low-current signal from the microcontroller and gives out a
proportionally higher current signal which can control and
drive a motor.
• L293D is a dual H-Bridge motor driver IC. With one
L293D IC we can interface two DC motors which can be
controlled in both clockwise and counter clockwise
L293D – Motor driver
• The PWM mode is used to control
the speed of DC motors.
• Higher the duty cycle of the PWM
signal higher is the speed of DC
motor.
• The PIC18 microcontroller will
generate PWM signals of different
duty cycle using its PWM mode of
CCP module and will give the
PWM signal to the two enable pins
of the L293D.
• Here, use the DC Motor Driver to
control the speed of two DC motor.
• In this way, the microcontroller will
run the DC motor in forward
direction with different speeds.
DC Motor Driver L293
V
SS
1 1 L29
CE 1 16
L29 16 VSS 0
2 3 1
1 15
1 2 3 0 M
15 IN 0 3 3
IN
3 14 4 14
1 1 13
4 13 OUT 4
M 12
OUT 5
5 12 4
1 11
6 11 GND
GND 6 4
7 10 GND 1 7
2 10 1
GND 9 0 M
VS 8 9 OUT 0
8 1
OUT 0
3
2 (a) Pin (b) Motor
IN3 VS
Assignment connection
IN2 CE2
Motor driver L293 pin assignment and motor connection
PIC18F452 V V
CC CC
1
316
8 15
CCP1 2 6.8μF
13
RB4 7 12 0.33 μF
L293
54
9 M
NC 10 6
VCC 11 14
6.8μF
V
CC
CCP2 1
30137
10KΩ 3 2
All diodes are the same and could be any one of the 1N4000 Hall-effect
series switch
PIC18-based motor-control system
Pin 2 and pin 7 drives the two terminals of the DC motor.
Depending on the voltages applied to pin 2 and pin 7, the
motor can be rotating in clockwise or counterclockwise
direction as shown in Figure.
L293
PWM (CCP1)
A When A = B,
torque
applied to motor =
A 0
Moto When A ≠ B, motor
r B runs
of of
f f
Port Pin (RB4)
B clockwis counterclockwi
e se
The L293 motor driver
Algorithm
• START
• Configure RC0, RC2 pins as output pins
• Select PWM mode of operation by writing into CCP1CON
• Load initial value into PR2 register
• Configure T2CON register for Pre-scaler
• Write value into CCPR1L (Duty cycle register) to generate 25%
duty cycle waveform on pin RC2
• Provide some delay
• Write value into CCPR1L (Duty cycle register) to generate 50%
duty cycle waveform on pin RC2
• Provide some delay
• Write value into CCPR1L (Duty cycle register) to generate 75%
duty cycle waveform on pin RC2
• Provide some delay
• Write value into CCPR1L (Duty cycle register) to generate 100%
duty cycle waveform on pin RC2
• END
Program
The following Program will generate PWM waveform with 25%, 50%, 75%, 100% duty cycle on Pin RC2 using
CCP Module
#include<p18f458.h>
#pragma config OSC=HS
#pragma config PWRT=OFF
#pragma config WDT=OFF
#pragma config DEBUG=OFF, LVP=OFF
void DELAY();
#define IN1 PORTCbits.RC0
#define IN2 PORTCbits.RC2
void main()
{
TRISC=0x00; ///RC0,RC2 pin as PWM output pin
CCP1CON=0X0C;///PWM mode
PR2=100; ////PR2=(Fosc/4xNxFpwm)
T2CON=0X05; ///Prescaler=4
while(1) ///forever loop
{
IN1=1;// CLOCKWISE Direction
IN2=0;
CCPR1L=25; //25% Duty cycle
DELAY(1000);
CCPR1L=50; //50% Duty cycle
DELAY(1000);
CCPR1L=75; //75% Duty cycle
DELAY(1000);
Sinhgad College of Engineering
Dept. of Information Technology
Class - SE
Processor Architecture
(214451)
Unit-3: PIC Microcontroller
Interrupts
Faculty – Prof. Madhukar V.
Nimbalkar
[email protected]
9890586765
Introduction
▪ Interrupts can be defined as asynchronous request
for service by peripherals to processor.
▪ Interrupts are mechanisms which enable instant
response to events such as counter overflow, pin
change, data received, etc.
▪ In normal mode, microcontroller executes the main
program as long as there are no occurrences that
would cause an interrupt.
▪ Upon interrupt, microcontroller stops the execution of
main program and commences the special part of the
program(ISR) which will analyze and handle the
interrupt.
The PIC uCs
PIC18 interrupts
▪ PIC can serve multiple devices using mechanisms of
▪ Polling
▪ PIC continuously monitors the status of each
device
▪ Each device get the attention of the CPU as the
same level of priority
▪ Wastes u-Controllers time by polling devices that
do not need service.
▪ Interrupt
▪ Devices get the attention of the CPU only when it
needs a service
▪ Can service many devices with different level of
priorities
The PIC uCs
Interrupt service routine (ISR)
▪ When an interrupt is
invoked the uC runs the
Interrupt Service
Routine(ISR)
▪ Interrupt vector table
holds the address of ISRs
▪ Power-on Reset 0000h
▪ High priority interrupt
0008h
▪ Low priority interrupt
0018h
The PIC uCs
Steps in executing an interrupt
▪ Upon activation of interrupt the microcontroller
▪ Finishes executing the current instruction
▪ Pushes the PC of next instruction in the stack
▪ Jumps to the interrupt vector table to get the
address of ISR and jumps to it
▪ Begin executing the ISR instructions to the last
instruction of ISR (RETFIE)
▪ Executes RETFIE
▪ Pops the PC from the stack
▪ Starts to execute from the address of that PC
The PIC uCs
Sources of interrupts in PIC18
▪ External hardware interrupts
▪ Pin RB0(INT0),RB1(INT1), RB2(INT2)
▪ PORTB change (RB4- RB7)
▪ Peripheral Interrupts
▪ Timers Overflow Interrupt
▪ Timer0 , Timer1 ,Timer2
▪ Comparator Change Interrupt
▪ Parallel Slave Port Interrupt
▪ CCP Interrupt
▪ USART Interrupts
▪ Receive Interrupt
▪ Transmit Interrupt
All are Maskable & Vectored Interrupts
▪ A/D Conversion Complete Interrupt
The PIC uCs
Enabling and disabling an interrupt
▪ When the PIC is powered on (or resets)
▪ All interrupts are masked (disabled)
▪ The default ISR address is 0008h
▪ No interrupt priorities for interrupts
The PIC uCs
Enabling and disabling an interrupt
In general, interrupt sources have three bits to control
their operation. They are:
▪ Flag bit
▪ to indicate that an interrupt event occurred
▪ Enable bit
▪ that allows program execution to branch to the
interrupt vector address when the Flag bit is set
▪ Priority bit
▪ to select high priority or low priority
The PIC uCs
Steps in enabling an interrupt
▪ Set the GIE bit from INTCON register
▪ Set the IE bit for that interrupt
▪ If the interrupt is one of the peripheral (timers 1,2 , serial,
etc. ) set PEIE bit from INTCON register
The PIC uCs
Assigning priorities to an interrupt
▪ Set the IPEN bit, bit7 from RCON register
▪ Use P - priority bit for that interrupt to assign either HIGH or
LOW priority
▪ P = 1, HIGH priority
▪ P = 0, LOW priority
▪ To enable priority interrupts (when IPEN = 1), set GIE /
GIEH bit of INTCON reg. = 1 for HIGH priority interrupts &
set PEIE / GIEL bit of INTCON reg. = 0 for LOW priority
interrupts
For INT0 interrupt – no priority bit because it is having default
high priority
The PIC uCs
PIC18 interrupts
▪ The PIC18FXX8 devices have multiple interrupt sources
and an interrupt priority feature that allows each interrupt
source to be assigned a high priority level or a low
priority level.
▪ The high priority interrupt vector is at 000008h and the
low priority interrupt vector is at 000018h.
▪ High priority interrupt events will override any low priority
interrupts that may be in progress.
▪ There are 13 registers that are used to control interrupt
operation. These registers are:
•RCON
•INTCON, INTCON2, INTCON3
•PIR1, PIR2, PIR3
•PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
The PIC •uCs
RCON,INTCON, INTCON2, INTCON3
The PIC uCs
RCON – Reset Control Register
The PIC uCs
INTCON – Interrupt Control Register
The PIC uCs
INTCON2 – Interrupt Control Register2
The PIC uCs
INTCON3 – Interrupt Control Register3
The PIC uCs
PIR1, PIE1, IPR1
Used to programme TMR1, TMR2, CCP,
SSP,USART- TX, USART – RC, ADC, PSP
Peripheral Interrupts
The PIC uCs
PIR1 – Peripheral Interrupt Request
Register1
The PIC uCs
PIE1 – Peripheral Interrupt Enable Register1
The PIC uCs
IPR1 – Peripheral Interrupt Priority Register1
The PIC uCs
PIR2, PIE2, IPR2
Used to programme ECCP, TMR3, LVD, BCL,
EEPROM-Write, CM Peripheral Interrupts
The PIC uCs
PIR2 – Peripheral Interrupt Request
Register2
The PIC uCs
PIE2 – Peripheral Interrupt Enable Register2
The PIC uCs
IPR2 – Peripheral Interrupt Priority Register2
The PIC uCs
PIR3, PIE3, IPR3
Used to programme CAN Invalid message, CAN
Bus Wakeup, CAN Error, Transmit Buffer 0,1,2,
Receive Buffer 0,1 Peripheral Interrupts
The PIC uCs
PIR3 – Peripheral Interrupt Request
Register3
The PIC uCs
PIE3 – Peripheral Interrupt Enable Register3
The PIC uCs
IPR3 – Peripheral Interrupt Priority Register3
The PIC uCs
The PIC uCs
The PIC uCs
PIC18F Interrupt Logic for TIMER
Interrupts without priorities
The PIC uCs
PIC18F Interrupt Logic – Detailed
Diagram
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
Program organization in
Assembly
The PIC uCs
Embedded C - #pragma section directive
Assembler allows placing code/data at a specific ROM address using ORG
directive.
To do the same in Embedded C , use #pragma section directive, where
Section is portion of an application (code/data) that can be assigned specific
memory address location. In case of on-chip ROM program memory, section
can be either code or romdata
#pragma code– used for program with executable instructions &
#pragma romdata – used for fixed data such as strings and look-up tables.
Ex.
#include <p18f458.h>
#pragma code main = 0X50
Void msdelay
Void main (void)
{
}
#pragma code msdelay = 0X30
Void msdelay
{
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
The PIC uCs
Programming timer using interrupt
Write down a program to generate a square wave
on RB5 of frequency 1KHz by using Timer 0
interrupt method ,while data is being transferred
from PORTC to PORTD.
RB Square Wave =
5 1KHz
By Interrupt
PORTC PORTD
P18F452 Method
The PIC uCs
Program
# include <p18f452.h>
#define mybit PORTBbits.RB5
void T0_ISR(void)
#pragma code HighVector=0x08
void HighVector(void)
{
_asm
GOTO HighISR
_endasm
}
The PIC uCs
void main (void)
{
TRISBbits.TRISB5 = 0; // Make RB5 as output pin
TRISC=0xFF; // Make Port C as Input
TRISD =0x00; // Make Port D as output
T0CON = 0x08; // Timer 0, 16 bit mode , no pre-scaler
TMR0H=0xFE; // for freq. = 1 KHz , Delay = 0.5 ms, count =
FE0C
TMR0L=0x0C;
INTCONbits.TMR0IF=0; // Timer overflow bit
INTCONbits.GIE=1; // enable all interrupts globally
INTCONbits.PEIE=1 // enable all peripheral interrupt
INTCONbits.TMR0IE=1; // enable Timer 0 Interrupt
T0CONbits.TMRON=1 ; // start timer 0
while (1) //keep looping until interrupt comes
{
PORTD= PORTC
}
}
The PIC uCs
Programming timer using interrupt
Write an Embedded C program for Timer programming ISR
based buzzer on/off.
RB
5 Buzzer
P18F452
The PIC uCs
Program
# include <p18f452.h>
#define mybit PORTBbits.RB5
void T0_ISR(void)
#pragma code HighVector=0x08
void HighVector(void)
{
_asm
GOTO HighISR
_endasm
}
The PIC uCs
void main (void)
{
TRISBbits.TRISB5 = 0; // Make RB5 as output pin
T0CON = 0x08; // Timer 0, 16 bit mode , no pre-scaler
TMR0H=0xFE; // Delay = 0.5 ms, count = FE0C
TMR0L=0x0C;
INTCONbits.TMR0IF=0; // Timer overflow bit
INTCONbits.GIE=1; // enable all interrupts globally
INTCONbits.PEIE=1 // enable all peripheral interrupt
INTCONbits.TMR0IE=1; // enable Timer 0 Interrupt
T0CONbits.TMRON=1 ; // start timer 0
while (1) //keep looping until interrupt comes
}
The PIC uCs
Programming external hardware interrupt
Connect a switch to INT0 (RB0) and an LED to PIN
RB7.
Every time INT0 is activated, it toggles the LED while at
the same time data is transferred from PORTC to
PORTD
NOTE: By default or on power on reset, INT0,INT1 and INT2
are positive edge triggered. LED (RB7)
SW(INT0/RB0)
Port C Port D
The PIC uCs
Program
#include <p18f452.h>
#define mybit PORTBbits.RB7
void chk_isr(void);
void INT0_ISR(void);
# pragma interrupt chk_isr
void chk_isr(void)
{
if (INTCONbits.INT0IF==1)
INT0_ISR();
}
#pragma code My_HiPrio_Int=0x0008
void My_HiPrio_Int (void)
The PIC uCs
void main(void)
{
TRISBbits.TRISB7=0;
TRISBbits.TRISB0=1;
TRISC =0xFF;
TRISD=0;
INTCONbits.INT0IF=0; // clear TF1
INTCONbits.INT0IE=1; //Enable Timer0 interrupt
INTCONbits.GIE=1; //enable all interrupts
While(1) //keep looping until interrupt comes
{
PORTD=PORTC;
}
}
The PIC uCs
Programming external hardware interrupt
Write an Embedded C program for External interrupt
input switch press, output at relay.
NOTE: By default or on power on reset, INT0,INT1 and INT2
are positive edge triggered.
SW(INT0/RB0) LED (RB7)
The PIC uCs
Program
#include <p18f452.h>
#define mybit PORTBbits.RB7
void chk_isr(void);
void INT0_ISR(void);
# pragma interrupt chk_isr
void chk_isr(void)
{
if (INTCONbits.INT0IF==1)
INT0_ISR();
}
#pragma code My_HiPrio_Int=0x0008
void My_HiPrio_Int (void)
The PIC uCs
void main(void)
{
TRISBbits.TRISB7=0;
TRISBbits.TRISB0=1;
INTCONbits.INT0IF=0; // clear TF1
INTCONbits.INT0IE=1; //Enable Timer0 interrupt
INTCONbits.GIE=1; //enable all interrupts
While(1) //keep looping until interrupt comes
The PIC uCs
PORTB change interrupt
Connect SW1 and SW2 to pins RB4 and RB5
respectively. Upon activation of SW1 and
SW2 will result in changing the state of LED1
and LED2 respectively.
SW1(RB4) LED1(RC4)
SW2(RB5) LED2(RC5)
The PIC uCs
Program
#include <p18f458.h>
#define LED1 PORTCbits.RC4
#define LED2 PORTCbits.RC5
void chk_isr(void);
void RBINT_ISR(void);
# pragma interrupt chk_isr
void chk_isr(void)
{
if (INTCONbits.RBIF==1)
RBINT_ISR();
}
The PIC uCs
void main(void)
{
TRISCbits.TRISC4=0;
TRISCbits.TRISC5=0;
TRISBbits.TRISB4=1;
TRISBbits.TRISB5=1;
INTCONbits.RBIF=0; // clear RBIF
INTCONbits.RBIE=1; //Enable RB interrupt
INTCONbits.GIE=1; //enable all interrupts
While(1); //keep looping until interrupt comes
}
The PIC uCs
UNIT-
VI
Current Trends in processor architecture
◻ Refer
◻ Pgs:
Syllabus
•ARM & RISC :
ARM and RISC design philosophy,
Introduction to ARM processor & its versions ARM 7, ARM 9, ARM 11
Features & advantages of ARM processor
Suitability of ARM processor in embedded applications
ARM 7 dataflow model & Programmers model
CPSR & SPSR registers
Modes of operation
Difference between PIC and ARM
RISC Design Philosophy
Features of RISC
• RISC is an acronym for Reduced Instruction Set Computer.
• It is intended as a contrast with CISC machines which are Complex Instruction Set Computers
• Most RISC processors use hardwired control.
• The most of the RISC processors use 32-bit instructions.
• They have very few instructions.
• The instructions are predominantly register-based.
• The limited (3 to 5) addressing modes are used by these processors.
• The memory access cycle is broken into pipelined access operations.
• This involves the use of caches and working registers.
• A large register file and separate instruction and data caches are used. This benefits internal data
forwarding and eliminates unnecessary storage of intermediate results.
• Using hardwired control, the clock Cycles Per Instruction (CPI) are reduced to I for most RISC
instructions. This is the advantage of having all instructions of equal size.
• RISC architecture is used in ARM cores.
RISC Design
• RISC processors are designed to execute simple but powerful instructions within a single
cycle at a high clock speed.
• RISC processors follow the four major design rules.
Major Design Rules
1. Instructions
Reduced number of instructions:
RISC processor provides limited number of instructions, which simplifies the design of
control unit.
Simple instruction format:
RISC processor uses simple instruction formats with fixed instruction length. The
instruction length is aligned on word boundaries Field locations especially opcodes are
fixed.
• This architecture provides following benefits:
• With fixed fields, opcode decoding and register operand addressing can occur
simultaneously.
• It simplifies the design of control unit.
• Instruction fetching is optimized since word-length units are fetched.
Hardwired instructions:
• With simple, one cycle instruction, there is no need for microinstructions. The machine
instructions can be hardwired. These instructions are executed faster than the instructions
implemented with microinstructions, since it is not necessary to access a microprogram
control memory during instruction execution.
One instruction per cycle:
RISC processor execute one instruction in a single cycle. In RISC processors, there is an one
instruction per machine cycle. A machine cycle is defined to be the time it takes to fetch two
operands from registers, performs an ALU operation, and stores the result in a register. Due to
this, RISC machine instructions are not complicated and can execute about as fast as,
microinstructions on CISC machines.
2. Pipelines
• Recall the concept of pipelining. The CPU contains several independent units that work in parallel.
One of them fetches the instructions, and other ones decode and execute them. At any instant, several
instructions are in various stages of processing. All RISC processors provide this pipelining feature.
• In RISC processor most instructions are register to register. These instructions have the following two
phases:
•Instruction Fetch (I)
•Execute (E)
• The instruction fetch phase fetches the instruction to be executed from memory and then execute
phase performs an ALU operation with register input and output to execute the instruction.
• In case of load and store instructions, three phases are required:
•Instruction fetch (I)
•Execute (E)
•Data transfer (D)
• Here, also the instruction fetch phase fetches the instruction to be executed. In execution phase
address of memory is calculated and in data transfer phase actual data is transferred from
register-to-memory or from memory-to-register depending upon the instruction.
• The Fig shows that how these phases can be overlapped in RISC processors to achieve the
pipelining. The Fig. (a) shows the two-way pipelining and the Fig (b) shows the three way
pipelining.
• In two way instruction pipelining, I and E phases of two different instructions are performed
simultaneously. In three way instruction pipelining, three instructions can be overlapped. Therefore,
maximum execution rate in two way instruction pipelining is twice the normal execution rate and it
is three times the normal execution rate in case of three way instruction pipelining.
3. Registers
• Register to Register Operations: Risc processors have a large number of general
purpose registers and they use efficient compiler technology to optimize register
usage. It is the most important characteristics of RISC processor. This architecture
encourages the optimization of register use, so that frequently accessed operands
remain in high-speed storage.
4. Load-store architecture
• RISC processors operate on data held in registers. Separate load and store
instructions transfer data between the register bank and external memory.
The advantage is that the use of data items which are held in the register does not
need memory access.
Comparison between RISC and CISC
ARM Design Philosophy
•The features of RISC which are accepted as well as rejected by ARM processors are discussed below.
•The features of RISC which are accepted by ARM processors are given below:
A large uniform register file
• An ARM processor contains a large number of registers like a RISC.
A load-store architecture
• ARM processor uses a RISC architecture. It contains a large number of registers The
instruction set contains separate load and store instructions for transferring data between the
register bank and external memory. When the data is to be operated, it is stored in the register
and then processed. The memory accesses are separated from data processing. So we can use
data items stored in registers multiple times without multiple memory accesses. This is
advantageous since memory accesses are costly. In contract, with a CISC architecture, the
data processing instructions can operate on memory directly.
• Simple addressing modes, with all load/store addresses being determined from register
contents and instruction fields only.
Uniform and fixed-length (32-bit) instruction fields
• ARM processor instruction set contains a reduced number of instructions. Also, these
instructions perform simple operations which can be executed in a single cycle. If the
complicated operations, such as division, are to be performed, the compiler or
programmer synthesizes them by combining several simple instructions. Each
instruction is a fixed length. This allows the pipeline to fetch future instructions
before decoding the current instruction in contrast, the CISC processor contains the
instructions of variable size, complex and take more cycles to execute. So in CISC
complexity is in processor hardware whereas in RISC, complexity is in compiler.
The uniform and fixed-length instruction fields simplify the instruction decoding.
Three-address instruction formats
• Most instructions of RISC and ARM processor have three address instruction
formats. That is, two source operands are stored in two different address locations
and third operand in a third address location.
The features of RISC which are rejected by ARM processors.
Register windows
• The main problem with register windows is the large chip area occupied by the large number
of registers. This feature is therefore rejected by ARM processors to reduce cost.
Delayed branches
• When branch instruction appears in a program and hence in a pipeline, a delay slot is
created. This causes pipeline problems since this is the disturbance to the smooth flow of
instructions. This delay slot is filled with some useful instruction which in most cases will be
executed. In most RISC processors, this problem is tried to reduce by using delayed
branches. Here, the branch takes place after the following instruction has executed. This
delayed branching technique works well when the processor uses single pipeline. However,
it may create problem for super-scalar implementations and also can not work well with
branch prediction mechanisms.
• Original ARM does not use delayed branch since they make exception handling more
complex.
Single cycle execution of all instructions
• ARM processor executes most of the data processing instructions in a single cycle However,
many other instructions need multiple clock cycles for their execution. More than one clock
cycle becomes the requirement even for a simple load and store instruction. At least two
memory accesses one for the instruction and one for the data, are needed.
In addition, the ARM architecture gives you :
• Control over both the Arithmetic Logic Unit (ALU) and shifter in every data-processing
instruction to maximize the use of an ALU and a shifter.
• Auto-increment and auto-decrement addressing modes to optimize program loops.
• Load and store multiple instructions to maximize data throughput.
• Conditional execution of all instructions to maximize execution throughput.
These enhancements to a basic RISC architecture allow ARM processors to achieve a good
balance of high performance, low code size, low power consumption and low silicon area.
Introduction to ARM Processor
• ARM has several processors that are grouped into number of families based on the
processor core they are implemented with.
• The architecture of ARM processors has continued to evolve with every family. Some of
the famous ARM Processor families are ARM7, ARM9, ARD10 and ARM11. Every
ARM processor implementation executes a specific instruction Architecture (ISA).
• The ISA has evolved to keep up compatibility so that code written to execute on an earlier
architecture revision will also execute on a later revision of the architecture.
ARM Nomenclature
• ARM Nomenclature identifies individual processors and provides basic information about
the feature set.
• The letters or words after "ARM" are used to indicate the features of a processor.
ARMxyzTDMIEJF-S
• x - Family or series
• y-Memory Management/Protection Unit
• z-Cache
• T-16 bit Thumb decoder
• D-JTAG Debugger
• M-Fast Multiplier
• I- Embedded In-circuit Emulator (ICE) Macrocell .
• E-Enhanced Instructions for DSP (assumes TDMI)
• J- Jazelle (for accelerated JAVA execution)
• F-Vector Floating-point Unit
• S-Synthesizable Version
T-Thumb Instruction Set:
• ARM Processors support both the 32-bit ARM Instruction Set and 16-bit Thumb Instruction
Set. The original 32-bit ARM Instructions consist of 32-bit opcodes which turns out to be a
4-byte binary pattern. The 16-bit Thumb Instructions consist of 16-bit opcodes or 2-byte
binary pattern to improve the code density.
D-JTAG Debug:
• JTAG is a serial protocol used by ARM to transfer information between the processor and
the test equipment.
M- Fast Multiplier:
• Older ARM Processors used a small and simple multiplier unit. This multiplier unit required
more clock cycles to complete a single multiplication. With the introduction of Fast
Multiplier unit, the clock cycles required for multiplication are significantly reduced and
modern ARM Processors are capable of calculating a 32-bit product in a single cycle
I- Embedded ICE Macrocell:
• ARM Processors have on-chip debug hardware that allows the processor to set break points
and watch points.
E-Enhanced Instructions:
• ARM Processors with this mode will support the extended DSP Instruction Set for high
performance DSP applications. With these extended DSP instructions, the DSP performance
of the ARM Processors can be increased without high clock frequencies.
J-Jazelle:
• ARM Processors with Jazelle Technology can be used in accelerated execution of Java
bytecodes. Jazelle DBX or Direct Bytecode execution is used in mobile phones and other
consumer devices for high performance Java execution without affecting memory or battery.
F-Vector Floating-point Unit:
• The Floating Point Architecture in AM Processors provide execution of floating point
arithmetic operations. The Dynamic Range and Precision offered by the floating Point
Architecture in ARM Processors are used in many real time applications in the industrial and
automotive areas.
S-Synthesizable :
• The ARM Processor Core is available as source code. This software core can be compiled
into a format that can be easily understood by the EDA Tools. Using the processor source
code, it is possible to modify the architecture of the ARM Processor.
Architecture
Evolution
• The architecture has
continued to evolve
since the first ARM
processor
implementation was
introduced in 1985.
• Table shows the
significant
architecture
enhancements from
the original
architecture version
1 to the current
version 6
architecture.
ARM Processor Families - ARM 7, ARM 9 and ARM 11
• ARM has several processors that are grouped into number of families based on the
processor core they are implemented with.
• The families are based on the ARM7, ARM9, and ARM11 cores. The postfix numbers 7,
9, and 11 indicate different core designs.
ARM7
• ARM7 family is introduced in 1994 (ARM7TDMI, ARM7EJ-S ARM720T)
• This family has been immensely successful and has established ARM as the architecture
of choice in digital word.
• Over the years more than 10 billion ARM7 processor family based devices have powered
a verity of cost and power sensitive applications.
• Due the availability of more advanced ARM processors, the ARM7 processor family
(ARM7 TDMD) is not recommended for new designs.
Features of ARM7
1. Pipeline depth: 3 stage (Fetch, Decode. Execute)
2. Operating frequency: 80 MHz
3. Power consumption: 0.06 mW/MHz.
4. MIPS/MH : 0.97
5. Architecture used: Von-Neumann
6. MMU/MPU: Not present
7. Cache memory : Not present
8. Jazelle Instruction : Not present
9. Thumb instruction: Yes (16 bit instruction set)
10. ARM instruction set : Yes (32 bit)
11. ISA (Instruction set architecture): V4T (4 TH Version)
12. Interrupt Controller: Not Present
13. ISR entry: Non Deterministic ISR entry
14. Power management: No in built Power Management
15. Instruction Set performance v/s code size: Optimal performance code size balance requires interworking between
ARM & Thumb code.
16. Ease of application porting from one device to another: Lack of standardization inhibits application porting.
ARM9 Processor Family
• The ARM9 family was announced in 1997.
• ARM9 family enables single processor solution for microcontroller, DSP & JAVA
applications, offering savings in chip area and complexity, power consumption and time to
market.
• ARM9 family has enhanced processors and these processors are well suited for applications
requiring a mix of DSP+ Microcontroller performance.
• ARM9 family includes - ARM920T, ARM922T, ARM940T, ARM946E-S, ARM966E-S,
and ARM926EJ-S processors.
Features of ARM9
Pipeline Depth : 5 stage (Fetch, Decode, Execute, Decode, Write)
Operating frequency: 150 MHz
Power Consumption: 0.19 mW/MHz
MIPS/MHz: 1.1
• Architecture used: Harvard. It separates the data D and instruction I buses.
• MMU/MPU : Present
• Cache Memory: Present (separate 16 K/8 K)
• ARM/ Thumb Instruction : Support both
ARM920T
• The first processor in the ARM9 family
• It includes a separate D+ I cache and an MMU.
• Provides virtual memory support to operating systems.
• It executes the architecture v4T instructions.
• ARM922T is a variation on the ARM920T with half the D+ I cache size.
ARM940T
• It includes a smaller D+I cache and an MPU.
• It is designed for applications that do not require a platform operating system.
• It executes the architecture v4T instructions
ARM946E-S and ARM966E-S
• Both execute architecture v5TE instructions.
• They support the optional Embedded Trace Macrocell (ETM), which allows a developer
to trace instruction and data execution in real time on the processor.
• The ARM946E-S includes TCM (Tightly Coupled Memory), cache, and an MPU. The
sizes of the TCM and caches are configurable. It is designed for use in embedded control
applications that require deterministic real-time response.
• On the other hand, the ARM966E does not have the MPU and cache extensions but does
have configurable TCMs.
ARM926EJ-S
• It is synthesizable processor core, announced in 2000.
• It is designed for use in small portable Java-enabled devices such as 3G phones and
Personal Digital Assistants (PDAs).
• Supports the Jazelle technology, which accelerates Java bytecode execution. It features an
MMU, configurable TCMs, and D+I caches with zero or nonzero wait state memories.
ARM11 Processors Family
• This family provides the engine that power many smartphones, also widely used in
consumer, home and embedded applications.
• It delivers low power and a range of performance from 350 MHz to 1 GHz.
• ARM11 processor software is compatible with all previous generations of ARM processors.
• ARM11 family includes ARM1176JZ (F)-S and ARM11MP core, ARM1136J(F)-S,
ARM1156T2-S processors.
Features of ARM11
• Pipeline depth : 8 stage pipeline with separate loadstore and arithmetic pipelines.
• Operating frequency : 335 MHz
• Power Consumption: 0.4 mW/MHz.
• MIPS/MHz: 1.2
• Architecture used: Harvard
• MMU/MPU : Present
• Multiplier unit: 16 x 32 (16 bits of 32-bit size register)
• Cache Memory: Present (4- 64 K size)
ARM1136J-S
• It was announced in 2003.
• Designed for high performance and power efficient applications.
• It executes architecture ARMv6 instructions.
• Supports Single Instruction Multiple Data SIMD) extensions for media processing,
specifically designed to increase video processing performance.
• The ARM1136JF-S is an ARM1136J-S with the addition of the vector floating-point unit
for fast floating-point operations.
• Supports the thumb instruction set-memory BW & Size requirements up to 35 %.
• Supports Jazelle Technology for efficient embedded JAVA execution.
• Supports the DSP extensions.
• Supports ARM Trust-Zone Technology for on chip security.
• Physically tagged caches to improve OS context switch performance.
• Tightly coupled memories for real-time applications.
Comparison between ARM7, ARM9 and ARM11 Cores
Table shows a comparison between the ARM7, ARM9, and ARM11 cores.
Features and Advantages of ARM Processor
• The features of ARM microcontroller are as follows:
• Consists of a large uniform register file.
• Supports load-store architecture.
• Uses simple addressing modes.
• Contains a reduced number of instructions.
• Instructions perform simple but powerful operations which can be executed in a single
cycle. If the complicated operations, such as division, are to be performed, the compiler or
programmer synthesizes them by combining several simple instructions.
• It has uniform and fixed-length (32-bit) instruction fields.
• Each instruction is a fixed length. This allows the pipeline to fetch future instructions
before decoding the current instruction. In contrast, the CISC processor contains the
instructions of variable size, complex and take more cycles to execute. So in CISC
complexity is in processor hardware whereas in RISC, complexity is in compiler. The
uniform and fixed-length instruction fields simplify the instruction decoding.
• Most instructions have three-address instruction format.
• Does not use delayed branch since they make exception handling more complex.
• Does not use register windows to keep chip area small and hence the cost.
• It has control over both the Arithmetic Logic Unit (ALU) and shifter in every
data-processing instruction to maximize the use of an ALU and a shifter.
• Supports auto-increment and auto-decrement addressing modes to optimize
program loops.
• Supports Load and Store Multiple instructions to maximize data throughput.
• Supports condition execution of all instructions to maximize execution throughput.
These enhancements to a basic RISC architecture allow ARM processors to achieve a
good balance of high performance, low code size, low power consumption and low
silicon area.
Suitability of ARM Processor in Embedded Applications
• The ARM instruction set differs from the pure RISC definition make the ARM
instruction set suitable for embedded applications:
Variable cycle execution for certain instructions:
• Some ARM instructions like load-store-multiple instructions vary in the number of
execution cycles depending upon the number of registers being transferred.
Load-store-multiple instructions transfer data on sequential memory addresses, which
increases performance since sequential memory accesses are often faster than random
accesses Multiple register transfers also improve the code density.
Inline shifter to improve core performance and code density:
• The ARM arithmetic logic unit has a barrel shifter that is capable of shift and rotate
operations. This inline barrel shifter preprocesses one of the input registers before it is
used by an instruction. This expands the capability of many instructions to improve core
performance and code density.
Thumb 16-bit instruction set:
• The Thumb instruction set consists of 16-bit instructions that act as a compact shorthand for
a subset of the 32-bit instructions of the standard ARM. These instructions permit the ARM
core to execute either 16- or 32-bit instructions. The 16-bit instructions improve code:
density by about 30 % over 32-bit fixed-length instructions.
Conditional execution:
• These instructions are executed when a specific condition has been satisfied. This feature
improves performance and code density by reducing branch instructions.
Enhanced instructions:
• RM instruction set also supports the enhanced Digital Signal Processor (DSP) instructions
(fast 16x16-bit multiplier operations and saturation). These instructions allow ARM
processor to serve as a combination of a processor plus a DSP.
ARM7 Dataflow Model
• An ARM7 core is an engine within a system that fetches ARM instructions from
• memory and executes them.
• ARM 7 cores are very small. Typically they occupy a few square millimeters of
chip area.
• With advances in modern VLSI technology, it became possible to build additional
system components such as cache memory, memory management unit or
application specific hardware on the same chip. Application specific hardware
may include signal processing hardware or further ARM processor cores.
• While designing a new system, selecting the correct processor core is one of the
most critical decision.
ARM7 Core Dataflow Model
• Fig. shows the basic structure of ARM7 core
and how data moves between its different
parts.
• The ARM7 core dataflow model shown in
Fig. 10.7.1 is Von Neumann implementation
of the ARM.
• Since ARM7 processor is basically a RISC
processor, it uses a load-store architecture.
This means, it has two instruction types, load
and store, for transferring data in and out of
the processor respectively.
LOAD: This instruction copies data from
memory to registers in the processor core
STORE: This instruction copies data from
registers in the processor core to memory.
• The ARM processor instruction set does not include the instructions that directly manipulate
data in memory. The data processing is carried out only in registers.
Data bus:
• The data enters the ARM7 core through the data bus. The data is either in the form of an
instruction opcode or a data item.
• Since Von Neumann architecture is used, data items and instructions share the same bus.
This is in contrast with Hardvard architecture which uses two different buses.
Instruction decoder:
• This unit decodes the instruction opcode read from the memory and then the instruction is
executed.
Register file:
• This is a bank of 32-bit registers used for storing data items.
Sign extend:
• The ARM7 core is a 32-bit processor. So most instructions of the ARM processor treat
registers as holding signed or unsigned 32-bit values.
When the processor reads signed 8-bit or 16-bit numbers from memory, the sign extend hardware converts
these numbers to 32-bit values and then places them in a register file.
ALU (Arithmetic Logic Unit) and MAC (Multiply-Accumulate Unit):
• Most of the ARM instructions are two operand instructions. The two source registers
Rn, and Rm are used to store these operands. These source operands are read from
the Rn, and Rm registers using the internal buses A and B respectively.
• The ALU or MAC reads the operand values from Rn, and Rm registers via A and B
buses respectively, performs the operation and stores the computed result via internal
C bus in destination register, Rd and then to the register file.
• The load and store instructions generate address using ALU and stores it in the
address register.
Address register :
• This holds the address generated by the load and store instructions and places it on
the address bus.
Barrel shifter:
• The contents of the Rm register alternatively can be preprocessed in the barrel
shifter before applying as an input to the ALU.
• A wide range of expressions and addresses can be calculated using the barrel
shifter and ALU.
Incrementer
• For load and store instructions, the incrementer updates the contents of the
address register before the processor core reads or writes the next register value
from or to the consecutive memory location.
• The processor core continues the execution of instruction. Only when an
exception or interrupt occurs, the normal execution flow is changed.
Programmers Model
• The register file in the
ARM7 core contains all
the registers, available
to a programmer. The
current mode of the
processor decides the
availability of the
registers to the
programmer.
• Fig. shows the
programming model of
ARM processor.
• The ARM processor has a total of 37 registers. All registers are 32-bits wide. They can be
classified into two groups as,
• General purpose registers
• Special purpose registers.
General Purpose Registers
• Registers r0 to r12 are used as general purpose registers. Depending upon context,
registers r13 to r15 can also be used as general purpose registers.
• The general purpose registers hold either data or an address.
Special Purpose Registers
• Registers r13 to r15, CPSR (Current Program Status Register) and SPSR (Saved Program
Status Register) are the special purpose registers.
Registers r13 to r15
• In user mode, registers r13 to r15 are labeled as r13 sp, r14 lr and r15 pc respectively to
differentiate them from other registers. The functions of these registers are given below.
•Stack pointer (r13 sp): Register r13 is the stack pointer. It stores the top of the stack in
the current processor mode.
Link register (r14 lr):
• Register r14 is the link register. The processor stores the return address in this register
when a subroutine is called.
Program counter (r15 pc):
• Register r15 is the program counter and stores the address of the next instruction to be
fetched from the memory by the processor.
• It is used in most instructions as a pointer to the instruction which is two
instructions after the instruction being executed.
• All ARM instructions are four bytes long (one 32-bit word) and are always
aligned on a word boundary. This means that the bottom two bits of the PC are
always zero, and therefore the PC contains only 30 non-constant bits.
• It can often be used in place of one of the general-purpose registers r0 to r14, and
is therefore considered one of the general-purpose registers. However, there are
also many instruction-specific restrictions or special cases about its use. Usually,
the instruction is unpredictable if r15 is used in a manner that breaks these
The Unbanked Registers r0-r7
• Registers r0 to r7 are unbanked registers. This means that each of them refers to the same
32-bit physical register in all processor modes.
• They are completely general-purpose registers, with no special uses implied by the
architecture, and can be used wherever an instruction allows a general-purpose register to be
specified.
The Banked Registers, r8 - r14
• Registers r8 to r14 are banked registers.
• The physical register referred to by each of them depends on the current processor mode.
Where a particular physical register is intended, without depending on the current processor
mode, a more specific name (as described below) is used. Almost all instructions allow the
banked registers to be used wherever a general-purpose register is allowed.
• Out of 37 registers, 20 registers which are shown shaded in Fig. 10.8.1 are the banked
registers. Fig. 10.8.1 also shows which banked registers are used in which mode. Banked
registers of a particular mode are denoted by, r number_mode.
• For example, supervisor, mode has banked registers r13 svc, r14_svc and spsr_svc.
• Registers r8 to r12 have two banked physical registers each. The first group of
physical registers are referred to as r8 usr to r12 usr and the second group as r8 fiq
to r12 fiq. The r8_usr to r12 usr group is used in all processor modes other than
FIQ mode, and the other is used in FIQ mode.
• Registers r13 and r14 have six banked physical registers each. One is used in User
and System modes, while each of the remaining five is used in one of the five
exception modes.
• The registers r0 to r13 are orthogonal. This means, any instruction which you can
apply to r0, you can equally well apply to any of the r1 to r13 registers. This is not
the case with r14 and r15 registers.
CPSR and
SPSR
Registers
• The current program status register (cpsr) is accessible in all processor modes. It contains
condition code flags, interrupt disable bits, the current processor mode, and other status and
control information.
• Each exception mode also has a saved program status register (spsr), that is used to preserve
the value of the cpsr when the associated exception occurs.
Note: User mode and System mode do not have an SPSR, because they are not exception
modes All instructions which read of UNPREDICTABLE when executed in User mode or
System mode.
• Fig shows the format of the cpsr and spsr.
Control flags (Bits 0-7)
• The control bits change when an
exception arises and can be
altered by software only when the
processor is in a privileged mode.
Bits 0-4 (Mode Select Bits):
Processor modes
• These bits determine the
processor mode as shown in
Table.
Bit 5 (Thumb State Bit):
• This bit gives the state of the core. The state of the core determines which instruction set is
being executed.
• There are three instruction sets, ARM, Thumb and Jazelle. One of the three instruction set
is active when the processor is in ARM state, Thumb state and Jazelle state respectively.
Thumb
• Thumb instructions are 16 bits (instead of the usual 32 bit). This allows for greater code
density in places where memory is restricted.
• The Thumb set can only address the first eight registers, and there are no conditional
execution instructions. Also, the Thumb cannot do a number of things required for
low-level processor exceptions, so the Thumb instruction set will always come alongside
the full ARM instruction set.
• Exceptions and the like can be handled in ARM code, with Thumb used for the more
regular code.
Table gives the comparison of ARM and Thumb instruction set features.
Jazelle
• The third instruction set introduced by ARM designers is Jazelle. The J bit is the additional
flag bit in the flags field only available on Jazelle-enabled processors.
• The Jazelle J and Thumb T bits in the cpsr decide the state of the processor. When both, J and
T bits are 0, the processor is in ARM state and executes ARM instructions. When the T bit is
1, the processor is in Thumb state and executes Thumb instructions. When T bit is 0 and J bit
is 1, the processor is in Jazelle state and executes Jazelle instructions.
• Jazelle executes 8-bit instructions. It is a hybrid mix of software and hardware It is designed to
increase the speed of execution of Java byte codes. The Jazelle technology and a specially
modified version of the Java virtual machine is needed
• to execute Java byte codes.
The Jazelle instruction set features are given below.
• Jazelle instructions are 8-bit in size.
• Over 60% of the Java bytecodes are implemented in hardware and remaining codes are
implemented in software.
• The Jazelle instruction set is a closed instruction set and is not openly available. An extra
software licensed from both, ARM Limited and Sun Microsystems is required to use Jazelle.
Bits 6 and 7 (Interrupt Masks)
• There are two interrupts available on the ARM processor core:
• Interrupt Request (IRQ) and
• Fast Interrupt Request (FIQ).
• These are maskable interrupts and their masking is controlled by bits 6 and 7 of cpsr. Bit
6(F) controls FIQ and bit 7(1) controls IRQ.
• When the bit is set to binary 1, the corresponding interrupt request is masked and when bit
is 0, the interrupt is available.
Condition code flags
• These flags in the cpsr can be tested by most instructions to determine whether the
instruction is to be executed.
• The condition code flags are usually modified by Execution of a comparison instruction
(CMN, CMP, TEQ or TST),
• Execution of some other arithmetic, logical or move instruction, where the destination
register of the instruction is not r15. Most of these instructions have both a flag-preserving
and a flag-setting variant, with the latter being selected by adding an S qualifier to the
instruction mnemonic. Some of these instructions only have a flag-preserving version.
Bit 27 (Saturation flag, Q)
• This flag is available for the ARM processor cores which include the DSP extensions. If an overflow
and/or saturation occurs in an enhanced DSP instruction, the Q bit is set to 1. The flag is sticky
which means the hardware only sets this flag.
• We need to write to the cpsr directly to clear the flag bit.
• Similarly, bit [27] of each spsr is a Q flag and is used to preserve and restore the cpsr Q flag if an
exception occurs.
Bit 28 (Overflow flag, V)
• It is set in one of two ways:
• For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding the operands and
result as two's complement signed integers.
• For non-addition/subtractions, V is normally left unchanged.
Bit 29 (Carry flag. C)
• It is set in one of four ways:
• For an addition, including the comparison instruction CMN, C is set to 1 if the addition produced a
carry (that is, an unsigned overflow), and to 0 otherwise.
• For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction
produced a borrow (that is, an unsigned underflow), and to 1otherwise.
• For non-addition/subtractions that incorporate a shift operation, C is set to the Last bit shifted out of the value
by the shifter.
• For other non-addition/subtractions, C is normally left unchanged.
Bit 30 (Zero flag, Z)
• It is set to 1 if the result of the instruction is zero (which often indicates an equal result from a
comparison), and to 0 otherwise.
Bit 31 (Negative flag. N)
• It is set to bit 31 of the result of the instruction. If this result is regarded as a two's complement signed
integer, then N 1 if the result is negative and NO it is positive or zero
• The N. Z. C and V flags can be modified in these additional ways:
• Execution of an MSR instruction, as part of its function of writing a new value to the cpsr or spsr. .
Execution of MRC instructions with destination register r15. The purpose of such instructions is to
transfer coprocessor-generated condition code flag values to the ARM processor.
• Execution of some variants of the LDM instruction. These variants copy the spsr to the spsr, and their
main intended use is for returning from exceptions.
• Execution of flag-setting variants of arithmetic and logical instructions whose destination register is r15.
These also copy the spsr to the cpsr and are mainly intended for returning from exceptions.
Other Bits
Modes of Operation
In the ARM7, there are seven operating modes. These modes are protected or exception modes which have
associated interrupt sources and their own register set.
1. Supervisor mode (Default): This is protected mode for running system level code to access hardware or run OS
calls. The ARM7 enters this mode after reset.
2. FIQ (Fast Interrupt reQuest): This mode supports high speed interrupt handling.
3. IRQ (Interrupt ReQuest): This mode supports all other interrupt sources in a system.
4. Abort: If an instruction or data is fetched from an invalid memory location, an abort exception will be generated.
5. Undefined: If a fetched opcode is not an ARM instruction, an undefined instruction exception will be generated.
6. User: This mode is used to run the application code. In the user mode we cannot change the contents of CPSR
(Current Program Status Register) and modes can only be changed when an exception is generated. This mode is
also known as Unprivileged mode.
7. System: This mode is used for running operating system tasks. It uses the same registers as user mode.
All the above modes, except user mode, are privilege modes.
For all operating modes, user registers r0 - r7 are common. However, FIQ mode replaces the r0 - r7
registers by its own registers r8 to r14. Similarly, each of the other modes have their own r13 and r14
registers so that each operating mode has its own unique stack pointer and link register.
Difference between PIC and ARM
Difference between PIC and ARM
Thank you
Sinhgad College of Engineering
Dept. of Information Technology
Class - SE
Processor Architecture (214451)
Unit-3: PIC Microcontroller LED,
LCD & Keypad Interfacing
Faculty – Prof. Madhukar V.
Nimbalkar
[email protected]
9890586765
Introduction of LED
▪ A light-emitting diode (LED)
is a two-lead
semiconductor light source.
It is a p–n junction diode
that emits light when
activated.
▪ When operated in a
forward biased direction
Light Emitting Diodes are
semiconductor devices that
convert electrical energy
into light energy.
The PIC uCs
LED Circuit Connection
▪ The LED is to be connected in a forward bias condition
across a power supply.
▪ it should be current limited using a series resistor to
protect it from excessive current flow. Never connect an
LED directly to a battery or power supply as it will be
destroyed almost instantly because too much current will
pass through and burn it out.
▪ LED Series Resistor Circuit
The series resistor value RS is calculated by simply
using Ohm´s Law, by knowing the required forward
current IF of the LED, the supply voltage VS across the
combination and the expected forward voltage drop of
the LED, VF at the required current level, the current
limiting resistor is calculated as:
The PIC uCs
LED Circuit Connection
series resistor required at 10mA:
An LED can be interfaced with
PIC18FXXX Microcontroller for various
purpose. The Port Pins are configured
in the output direction. So, once the
Logic "1" is the at O/P pin, then an
LED will be turned "ON". And when
Logic "0" is given the LED will be
turned "OFF".
Simply: Logic "1" -> 5V DC to output
pin
Logic "0" -> 0 V to output pin.
So, as discussed in earlier, the LED
with common cathode mode can be
connected with PIC18FXX along with a
resistor.
Thus, using the current limiting
resistor, the LED will blink according to
The PIC uCs the written program.
Interfacing diagram
The PIC uCs
Embedded C Program
#include<p18f4520.h>
void DELAY();
#pragma config OSC=HS
#pragma config PWRT=OFF
#pragma config WDT=OFF
#pragma config DEBUG=OFF, LVP=OFF
void main()
{
TRISDbits.RD0 = 0x00; //set RD0 pin direction as an output
The PIC uCs
LCD (4-bit Mode & 8-bit Mode) Interfacing
Introduction to LCD
The LCDs have a parallel interface, meaning that the
microcontroller has to manipulate several interface pins at once
to control the display. The interface consists of the following
pins:
The PIC uCs
LCD Pin Description
Pin no. Pin name LCD pin Description
1 Vss Ground pin of the LCD module.
2 Vcc Power to LCD module (+5V supply)
3 VEE Contrast adjustment pin
4 RS Register select pin RS=0 command register. RS=1
data register.
5 R/W Read/Write modes R/W=1; Read mode R/W=0;
Write mode
6 EN This pin is meant for enabling the LCD module
7-14 DB0 to DB7 8 data pins
15 LED+ Anode of the back light LED
16 LED- Cathode of the back light LED
The PIC uCs 11-8
Controlling LCD
The process of controlling the display involves putting the
data that form the image of what you want to display into
the data registers, then putting instructions in the instruction
register.
The three control lines are referred to as EN, RS, and
RW.
The EN line is called “Enable.” - to tell the LCD that you
are sending in data.
▪ To send data to the LCD, your program should make
sure this line is low (0) and then set the other two
control lines and/or put data on the data bus.
▪ When the other lines are completely ready, bring EN
high (1) and wait for the minimum amount of time
required by the LCD datasheet and end by bringing it
The PIC uCs
low (0) again.
Mostly used commands or instructions for
LCD
▪ Function Set: 8-bit mode, 1 Line, 5x7 Dots matrix for each character display
0x30
• Function Set: 8-bit mode, 2 Line, 5x7 Dots matrix for each character display
0x38
• Function Set: 4-bit mode, 1 Line, 5x7 Dots matrix for each character display
0x20
• Function Set: 4-bit mode, 2 Line, 5x7 Dots matrix for each character display
0x28
• Clear display screen 0x01
• Return Home 0x02
• Decrement cursor(Shift to left) 0x04
• Increment cursor(Shift to Right) 0x06
• Display off Cursor off 0x08
• Display on Cursor on 0x0E
• Display on Cursor off 0x0C
• Display on Cursor blinking 0x0F
• Shift entire display left 0x18
• Shift entire display right 0x1C
• Move cursor left by one character 0x10
• Move cursor right by one character 0x14
The• PIC
Clear
uCsDisplay (also clear DDRAM content) 0x01
• Force cursor position on first position of first 0x80
LCD Interfacing
For 4 Bits Mode
For 8 Bits Mode
The PIC uCs
Interfacing Diagram
The PIC uCs 11-12
Embedded C Program for the interfacing – 1/4
#include<p18f4520.h>
#pragma config OSC=HS
#pragma config PWRT=OFF
#pragma config WDT=OFF
#pragma config DEBUG=OFF, LVP=OFF
void lcdcmd(unsigned char value); //Function Prototype declaration
void lcddata(unsigned char value);
void msdelay(unsigned int itime);
#define ldata PORTD //Declare ldata variable for PORTD
#define rs PORTEbits.RE0 //Declare rs variable for pin RE0
#define rw PORTEbits.RE1 //Declare rw variable for pin RE1
#define en PORTEbits.RE2 //Declare en variable for pin RE2
The PIC uCs
void main()
{
TRISD = 0x00; //Set direction of PORTD as output
ADCON1=0X0F;
TRISE=0X00; //set direction of PORTE as output
msdelay(50);
lcdcmd(0x38); //16x2 LCD Embedded C Program
msdelay(50); for the interfacing – 2/4
lcdcmd(0x0E); // Display cursor ON
msdelay(15); Main Function
lcdcmd(0x01); //clear Display screen
msdelay(15);
lcdcmd(0x06); //Increment cursor and shift right
msdelay(15);
lcdcmd(0x80); //Force cursor on first row first position
lcddata(‘M'); //Display character ‘M'
msdelay(50);
lcddata(‘N'); //Display character ‘N'
msdelay(50);
}
The PIC uCs
Embedded C Program for the interfacing – 3/4
LCDCMD & LCDDATA function
void lcdcmd (unsigned char value)
{
ldata=value; //Send the command value to PORTD
rs=0; //selection of command register of LCD
rw=0;
en=1; //Generate High to Low pulse on Enable pin
msdelay(1);
en=0;
}
void lcddata (unsigned char value)
{
ldata=value; //Send the command value to PORTD
rs=1; //selection of DATA register of LCD
rw=0;
en=1; //Generate High to Low pulse on Enable pin
msdelay(1);
en=0;
}
The PIC uCs
Embedded C Program for the interfacing –
4/4 Delay Function
void msdelay (unsigned int itime)
{
int i,j;
for(i=0;i<itime;i++)
for(j=0;j<135;j++);
}
The PIC uCs
Keypad Interfacing
Matrix keypads are very useful when designing certain
system which needs user input.
• By arranging push button switches in rows and
columns.
• To scan which button is pressed, we need to scan it
column by column and row by row.
• Make rows as input and columns as output.
• For keypad wiring , need to pull up or pull down to
avoid floating.
Pull-up R
Active HIGH
Pull-down R
Active LOW
The PIC uCs
Keypad Interfacing
Pull-up
Resistor
COL(OUTPUT) =
HIGH
The PIC uCs
Keypress Detection?
The PIC uCs
Keyboard Interfacing – Interfacing
Diagram
RC0,RC1,RC2,RC3 pins are Configured in Output Direction and act as First
row, Second Row, Third Row, Fourth Row Respectively
RC4,RC5,RC6,RC7 pins are Configured in Input Direction and act as First
column, Second column, Third column, Fourth column Respectively
The PIC uCs
Embedded C Program – 1/7, Declarations
#include<p18f4520.h>
#pragma config OSC=HS
#pragma config PWRT=OFF
#pragma config WDT=OFF
#pragma config DEBUG=OFF, LVP=OFF
void lcdcmd(unsigned char value);
void lcddata(unsigned char value);
void msdelay(unsigned int itime);
#define ldata PORTD
#define rs PORTBbits.RB0
#define rw PORTBbits.RB1
#define en PORTBbits.RB2
The PIC uCs
Embedded C Program – 2/7 Main function –
1/5
int main(void)
{
TRISD = 0x00; // PORTD as output
TRISB = 0x00; // PORTB as output
ADCON1 = 0x0F; // All analog input channel pins are used as Digital I/O pin
TRISC = 0xF0; //Columns as input i.e.RC4-RC7
PORTC =0x00; // Initial value, RC0-RC7 as low
msdelay(15);
lcdcmd(0x38); // 16x2 LCD with 8-bit mode of operation
msdelay(15);
lcdcmd(0x0E); // display on, cursor blinking
msdelay(15);
lcdcmd(0x01); // clear display screen
msdelay(15);
lcdcmd(0x06); // increment cursor and shift right
msdelay(15);
The PIC uCs
Embedded C Program – 3/7 Main function –
2/5
while(1)
{
lcdcmd(0x83); // force cursor on row first 4th position
msdelay(15);
PORTC = 0xFE; // Ground first row
if(( PORTC & 0xf0 )!= 0xf0) // check status of first row and all column's
{
switch(PORTC & 0xf0) // check column status and enter in particular case
{
case 0xe0: lcddata('0');
break;
case 0xd0: lcddata('1');
break;
case 0xb0: lcddata('2');
break;
case 0x70: lcddata('3');
break;
}
}
The PIC uCs
Embedded C Program – 4/7 Main function –
3/5
PORTC= 0xfd; // Ground second row
if(( PORTC & 0xf0 )!= 0xf0) // check status of second row and all column's
{
switch(PORTC & 0xf0) // check column status and enter in particular
case
{
case 0xe0: lcddata('4');
break;
case 0xd0: lcddata('5');
break;
case 0xb0 : lcddata('6');
break;
case 0x70 : lcddata('7');
break;
}
}
The PIC uCs
Embedded C Program – 5/7 Main function –
4/5
PORTC = 0xfb; // Ground Third row
if(( PORTC & 0xf0 )!= 0xf0) // check status of Third row and all column's
{
switch(PORTC & 0xf0) // check column status and enter in particular case
{
case 0xe0 : lcddata('8');
break;
case 0xd0 : lcddata('9');
break;
case 0xb0 : lcddata('A');
break;
case 0x70 : lcddata('B');
break;
}
}
The PIC uCs
Embedded C Program – 6/7 Main function –
5/5
PORTC = 0xF7; // Ground Third row
if(( PORTC & 0xf0 )!= 0xf0) // check status of fourth row and all column's
{
switch(PORTC & 0xf0) // check column status and enter in particular case
{
case 0xe0 : lcddata('C');
break;
case 0xd0 : lcddata('D');
break;
case 0xb0 : lcddata('E');
break;
case 0x70 : lcddata('F');
break;
}
}
msdelay(15);
}
}
The PIC uCs
Embedded C Program – 7/7 LCDCMD,
LCDDATA & MSDELAY functions
void lcdcmd (unsigned char value)
{
ldata=value;
rs=0; // command register
rw=0;
en=1; // high
msdelay(1);
en=0; //low
}
void lcddata (unsigned char value)
{
ldata=value;
rs=1; //data rgister
rw=0;
en=1; //high
msdelay(1);
en=0; // low
}
void msdelay (unsigned int itime)
The PIC uCs
{
Sinhgad College of Engineering
Dept. of Information Technology
Class - SE
Processor Architecture
(214451)
Unit-4: PIC 18F Microcontroller
Serial Port Programming
Faculty – Prof. Madhukar V.
Nimbalkar
[email protected]
9890586765
SYLLABUS : UNIT 4 - PIC
Interfacing-II
CCP modes: Capture, Compare and PWM generation;
DC Motor speed control with CCP, Stepper motor
interfacing with PIC
Basics of Serial communication protocols: Study of
RS232, I2C, SPI, UART, Serial communication
programming using Embedded C.
Serial Vs. Parallel Communication
• The microcontroller is parallel device that transfers eight bits of
data
simultaneously over eight data lines to parallel I/O devices.
• However, in many situations, parallel data transfer is impractical.
For example, parallel data transfer over a long distance is very
expensive.
• Hence, a serial communication is widely used in long distance
communication. In serial data communication, 8-bit data is
converted to serial bits using a parallel in serial out shift register
and then it is transmitted over a single data line.
Serial versus Parallel Data Transfer
Communication links:
• Serial communication is classified into three
types of communication.
• a. Simplex communication link: In
simplex transmission, the line is
dedicated for transmission. The
transmitter sends and the receiver
receives the data.
• b. Half duplex communication link: In half
duplex, the communication link can be
used for either transmission or reception.
Data is transmitted in only one direction
at a time.
• c. Full duplex communication link: If the
data is transmitted in both ways at the
same time, it is a full duplex i.e.
transmission and reception can proceed
simultaneously. This communication link
requires two wires for data, one for
transmission and one for reception.
Types of Serial communication:
Serial data communication uses two types of
communication.
a. Synchronous serial data communication:
In this transmitter and receiver are synchronized. It
uses a common clock to synchronize the receiver and
the transmitter. First the synch character is sent and
then the data is transmitted. This format is generally
used for high speed transmission. In Synchronous
serial data communication a block of data is
transmitted at a time.
b. Asynchronous Serial data transmission:
In this, different clock sources are used for
transmitter and receiver. In this mode, data is
transmitted with start and stop bits. A transmission
begins with start bit, followed by data and then stop
bit. For error checking purpose parity bit is included
just prior to stop bit. In Asynchronous serial data
Serial Data Format
• The serial data format includes one start bit, between five and eight
data bits, and one stop bit. A parity bit and an additional stop bit might
be included in the format as well.
• The format for serial port data is often expressed using the following
notation: Number of data bits - parity type - number of stop bits. For
example,
• 8-N-1 is interpreted as eight data bits, no parity bit, and one stop
bit, while
• 7-E-2 is interpreted as seven data bits, even parity, and two stop
bits.
• The data bits are often referred to as a character because these bits
usually represent an ASCII character. The remaining bits are called
framing bits because they frame the data bits
Baud Rate
• The rate at which the bits are transmitted is called
baud or transfer rate.
• For example, in synchronous transmission, if data is
transmitted with 9600 baud, it means that 9600 bits
are transmitted in one second.
• For bit transmission time = 1 second/ 9600 = 0.104
ms.
RS-232 standards:
• To allow compatibility among data communication equipment made by
various manufactures, an interfacing standard called Rs232 was set
by the Electronics Industries Association (EIA) in 1960.
• In 1963 it was modified and called RS232A. RS232B and RS232C
were issued in 1965 and 1969, respectively.
• Today RS232 is the most widely used serial I/O interfacing
standard. This standard is used in PCs and numerous equipments.
• However, since the standard was set long before the advent of logic
family, its input and output voltage levels are not TTL compatible.
• In RS232, a logic one (1) is represented by -3 to -25V and referred as
MARK while logic zero (0) is represented by +3 to +25V and referred
as SPACE.
• For this reason to connect any RS232 to a microcontroller system we
must use voltage converters such as MAX232/3 to convert the TTL
logic level to RS232/3 voltage levels and vice-versa.
• MAX232/3 IC chips are commonly referred as line drivers.
RS232 Pins
Connectors:
Minimally, 3 wires: RxD, TxD, GND
Could have 9-pin or 25-pin
DB-25 DB-9
25-Pin Connector 9-Pin Connector
10-9
RS232 Pins DB 9 Connector
IBM PC DB-9 Signals
Data in Data out Pin 1 – Data Carrier Detect (DCD)
Pin 2 – Received Data (RxD)
Pin 3 – Transmitted Data (TxD)
Pin 4 – Data Terminal Ready (DTR)
Pin 5 – Signal Ground (GND)
Pin 6 – Data Set Ready (/DSR)
Pin 7 – Request to Send (/RTS)
Pin 8 – Clear to Send (/CTS)
Pin 9 – Ring Indicator (RI)
DB-9
9-Pin Connector
Null Modem Connection
10-10
Serial Port Pin Function
PIC18 Connection to RS232 (MAX 232)
Line
driver
(a) Inside MAX232 (b) its Connection to the PIC18
10-12
PIC18 Connection to RS232 (MAX233)
Line
(a) Inside MAX233 driver
(b) Its Connection to the PIC18
10-13
EUSART Module in PIC Microcontroller
The Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART) module is one of the two serial I/O modules.
(Generically, the USART is also known as a Serial Communications
Interface or SCI.)
The EUSART can be configured in the following modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on Break signal
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable clock polarity
The pins of the Enhanced USART are
multiplexed with PORTC. In order to
configure RC6/TX/CK and
RC7/RX/DT/SDO as an EUSART:
• bit SPEN (RCSTA<7>) must be set (=
1)
• bit TRISC<7> must be set (= 1)
• bit TRISC<6> must be set (= 0)
EUSART Register Map:
The operation of the Enhanced USART module is controlled
through six registers:
Transmit Status & Control Register
Receive Status & Control Register
Baud rate control register
TXREG & RCREG Register
TXREG
• 8-bit register used for serial communication in the PIC18
• For a byte of data to be transferred via the Tx pin, it must
be placed in the TXREG register first.
• The moment a byte is written into TXREG, it is fetched into
a non-accessible register TSR
• The frame contains 10 bits
RCREG
• 8-bit register used for serial communication in the PIC18
• When the bits are received serially via the Rx pin, the
PIC18 de-frames them by eliminating the START and
STOP bit, making a byte out of data received and then
placing it in the RCREG register
Baud Rate Generator (BRG)
• The BRG is a dedicated 8-bit, or 16-bit, generator that supports both
the Asynchronous and Synchronous modes of the EUSART. By
default, the BRG operates in 8-bit mode.
• Setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The
SPBRGH:SPBRG register pair controls the period of a free-running
timer.
• In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16
(BAUDCON<3>) also control the baud rate.
• In Synchronous mode, BRGH is ignored.
• Writing a new value to the SPBRGH:SPBRG registers causes the
BRG timer to be reset (or cleared).
• Formula for computation of the baud rate for different EUSART
modes
Baud Rate Calculation
• Mode selection
a. BRG Mode = 16-bit by setting BRG16 bit in BAUDCON Register
b. EUSART mode = Asynchronous by clearing SYNC bit in TXSTA
Register
c. Formulae
Desired Baud Rate = Fosc / [4(SPBRGH:SPBRG+1)]
• For Fosc = 20MHz, Baud rate = 9600
SPBRGH:SPBRG = [Fosc/4(Baud rate)]-1
= [20x106/(4x9600)] – 1
= [519]10 = [0207]16
• % Error = (Calculated baud rate - Desired Baud Rate)/Desired
Baud Rate
= (Fosc / [4(SPBRGH:SPBRG+1)] – 9600)/Desired Baud Rate
= ([20x106/[4x(519+1)]] – 9600)/Desired Baud Rate
= (9615 – 9600)/9600
% Error = 0.16 %
• Therefore to reduce error select
• SPBRGH = 0x02 and SPBRG = 0x08
Steps to set up an Asynchronous
1.Reception
Initialize the SPBRGH:SPBRG registers for the appropriate baud
rate. Set or clear the BRGH and BRG16 bits, as required, to
achieve the desired baud rate.
2. Enable the asynchronous serial port by clearing bit SYNC and
setting bit SPEN.
3. If the signal at the RX pin is to be inverted, set the RXDTP bit.
4. If interrupts are desired, set enable bit RCIE.
5. Enable 9-bit reception if desired, by setting bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit, RCIF, will be set when reception is complete and an
interrupt will be generated if enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (if enabled) and
determine if any error occurred during reception.
9. Read the 8-bit received data by reading the RCREG register.
10. If any error occurred, clear the error by clearing enable bit
CREN.
11. If using interrupts, ensure that the GIE and PEIE bits in the
INTCON register (INTCON<7:6>) are set.
Steps to set up an Asynchronous
Transmission
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH and BRG16
bits, as required, to achieve the desired baud rate.
2. Enable the asynchronous serial port by clearing bit SYNC
and setting bit SPEN.
3. If the signal from the TX pin is to be inverted, set the
TXCKP bit.
4. If interrupts are desired, set enable bit TXIE.
5. If 9-bit transmission is desired, set transmit bit TX9.
6. If 9-bit transmission is selected, the ninth bit should be
loaded in bit TX9D.
7. Enable the transmission by setting bit TXEN which will
also set bit TXIF.
8. Load data to the TXREG register (starts transmission).
9. If using interrupts, ensure that the GIE and PEIE bits in the
INTCON register (INTCON<7:6>) are set.
Simplified USART Transmit Block Diagram
Interfacing Diagram
Algorithm
1. Calculate the SPBRGH: SPBRG value for desired baud rate.
Load the calculated value in SPBRGH: SPBRG.
2. Configure Port pin RC6 as output and port pin RC7 as input.
3. Set BRG Mode = 8-bit by setting BRG16 bit in BAUDCON
Register
4. Set EUSART mode = Asynchronous by clearing SYNC bit in
TXSTA Register
5. Enable the Serial Port by setting SPEN bit in RCSTA Register
6. Enable the Transmission by setting TXEN bit in TXSTA Register
7. Check TRMT bit in TXSTA register for TXREG empty. Load data
to the TXREG register if TRMT = 1;
8. Repeat the step 6 until complete message transmitted.
9. Enable the continuous reception by setting CREN bit in RCSTA
register.
10. Poll the RCIF bit in PIR1 register to check data is received.
11. Read the 8-bit received data by reading the RCREG register.
12. Do the control action as per data received.
13. Repeat the steps from 10.
1) Which operations are performed by the bit manipulating instructions of boolean processor?
a. Complement bit
b. Set bit
c. Clear bit
d. All of the above
ANSWER: (d) All of the above
2) Which data memory control and handle the operation of several peripherals by assigning them
in the category of special function registers?
a. Internal on-chip RAM
b. External off-chip RAM
c. Both a & b
d. None of the above
ANSWER: (a) Internal on-chip RAM
3) Why is the speed accessibility of external data memory slower than internal on-chip RAM?
a. Due to multiplexing of lower order byte of address-data bus
b. Due to multiplexing of higher order byte of address-data bus
c. Due to demultiplexing of lower order byte of address-data bus
d. Due to demultiplexing of higher order byte of address-data bus
ANSWER: (a) Due to multiplexing of lower order byte of address-data bus
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4) Which control signal/s is/are generated by timing and control unit of 8051 microcontroller in
order to access the off-chip devices apart from the internal timings?
a. ALE
b. PSEN
c. RD & WR
d. All of the above
ANSWER: (d) All of the above
5) Which register usually store the output generated by ALU in several arithmetic and logical
operations?
a. Accumulator
b. Special Function Register
c. Timer Register
d. Stack Pointer
ANSWER: (a) Accumulator
6) Why is CHMOS technology preferred over HMOS technology for designing the devices of MCS-
51 family?
a. Due to higher noise immunity
b. Due to lower power consumption
c. Due to higher speed
d. All of the above
ANSWER: (d) All of the above
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7) Which condition approve to prefer the EPROM/ROM versions for mass production in order to
prevent the external memory connections?
a. size of code < size of on-chip program memory
b. size of code > size of on-chip program memory
c. size of code = size of on-chip program memory
d. None of the above
ANSWER: (a) size of code < size of on-chip program memory
8) Which among the below mentioned devices of MCS-51 family does not possess two 16 -bit
timers/counters?
a. 8031
b. 8052
c. 8751
d. All of the above
ANSWER: (b) 8052
9) Which characteristic/s of accumulator is /are of greater significance in terms of its
functionality?
a. Ability to store one of the operands before the execution of an instruction
b. Ability to store the result after the execution of an instruction
c. Both a & b
d. None of the above
ANSWER: © Both a & b
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10) Which general purpose register holds eight bit divisor and store the remainder especially after
the execution of division operation?
a. A-Register
b. B-Register
c. Registers R0 through R7
d. All of the above
ANSWER: (b) B-Register
11) How many registers can be utilized to write the programs by an effective selection of register
bank in program status word (PSW)?
a. 8
b. 16
c. 32
d. 64
ANSWER: © 32
12) Which operations are performed by stack pointer during its incremental phase?
a. Push
b. Pop
c. Return
d. All of the above
ANSWER: (a) Push
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13) Which is the only register without internal on-chip RAM address in MCS-51?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. Timer Register
ANSWER: (b) Program Counter
14) What kind of instructions usually affect the program counter?
a. Call & Jump
b. Call & Return
c. Push & Pop
d. Return & Jump
ANSWER: (a) Call & Jump
15) What is the default value of stack once after the system undergoes the reset condition?
a. 07H
b. 08H
c. 09H
d. 00H
ANSWERa) 07H
16) Which bit/s play/s a significant role in the selection of a bank register of Program Status Word
(PSW)?
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a. RS1
b. RS0
c. Both a & b
d. None of the above
ANSWER: © Both a & b
17) Which flags represent the least significant bit (LSB) and most significant bit (MSB) of Program
Status Word (PSW) respectively?
a. Parity Flag & Carry Flag
b. Parity Flag & Auxiliary Carry Flag
c. Carry Flag & Overflow Flag
d. Carry Flag & Auxiliary Carry Flag
ANSWER: (a) Parity Flag & Carry Flag
18) Which register bank is supposed to get selected if the values of register bank select bits RS1 &
Rs0 are detected to be ‘1’ & ‘0’ respectively?
a. Bank 0
b. Bank 1
c. Bank 2
d. Bank 3
ANSWER: © Bank 2
19) It is possible to set the auxiliary carry flag while performing addition or subtraction operations
only when the carry exceeds _______
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a. 1st bit
b. 2nd bit
c. 3rd bit
d. 4th bit
ANSWER: © 3rd bit
20) Which locations of 128 bytes on-chip additional RAM are generally reserved for special
functions?
a. 80H to 0FFH
b. 70H to 0FFH
c. 90H to 0FFH
d. 60H to 0FFH
ANSWER: (a) 80H to 0FFH
21) Which commands are used for addressing the off-chip data and associated codes respectively
by data pointer?
a. MOVX & MOVC
b. MOVY & MOVB
c. MOVZ & MOVA
d. MOVC & MOVY
ANSWER: (a) MOVX & MOVC
22) Which instruction find its utility in loading the data pointer with 16 bits immediate data?
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a. MOV
b. INC
c. DEC
d. ADDC
ANSWER: (a) MOV
23) What is the maximum capability of addressing the off-chip data memory & off-chip program
memory in a data pointer?
a. 8K
b. 16K
c. 32K
d. 64K
ANSWER: (d) 64K
24) Which among the below stated registers does not belong to the category of special function
registers?
a. TCON & TMOD
b. TH0 & TL0
c. P0 & P1
d. SP & PC
ANSWER: (d) SP & PC
25) Which timer is attributed to the register pair of RCAP2H & RCAP2L for capture mode
operation?
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a. Timer 0
b. Timer 1
c. Timer 2
d. Timer 3
ANSWERc) Timer 2
26) Which registers are supposed to get copied into RCAP2H & RCAP2L respectively due to the
transition at 8052 T2EX pin in the capture mode operation?
a. TH0 & TH1
b. TH1 & TH1
c. TH2 & TH2
d. All of the above
ANSWER: © TH2 & TH2
27) Which mode of timer 2 allow to hold the reload values with an assistance of RCAP2H & RCAP2L
register pair?
a. 8 bit auto-reload mode
b. 16 bit auto reload mode
c. 8 bit capture mode
d. 16 bit capture mode
ANSWER: (b) 16 bit auto reload mode
28) Where should the pin 19 (XTAL1), acting as an input of inverting amplifier as well as part of an
oscillator circuit, be connected under the application of external clock?
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a. to XTAL2
b. to Vcc
c. to GND
d. to ALE
ANSWER: © to GND
29) Which port does not represent quasi-bidirectional nature of I/O ports in accordance to the pin
configuration of 8051 microcontroller?
a. Port 0 (Pins 32-39)
b. Port 1 (Pins 1-8)
c. Port 2 (Pins 21-28)
d. Port 3 (Pins 10-17)
ANSWER: (a) Port 0 (Pins 32-39)
30) What is the required baud rate for an efficient operation of serial port devices in 8051
microcontroller?
a. 1200
b. 2400
c. 4800
d. 9600
ANSWER: (d) 9600
31) Which among the below mentioned functions does not belong to the category of alternate
functions usually performed by Port 3 (Pins 10-17)?
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a. External Interrupts
b. Internal Interrupts
c. Serial Ports
d. Read / Write Control signals
ANSWER: (b) Internal Interrupts
32) What is the constant activation rate of ALE that is optimized periodically in terms of an
oscillator frequency?
a. 1 / 8
b. 1 / 6
c. 1 / 4
d. 1 / 2
ANSWERb) 1 / 6
33) Which output control signal is activated after every six oscillator periods while fetching the
external program memory and almost remains high during internal program execution?
a. ALE
b. PSEN
c. EA
d. All of the above
ANSWER: (b) PSEN
34) Which memory allow the execution of instructions till the address limit of 0FFFH especially
when the External Access (EA) pin is held high?
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a. Internal Program Memory
b. External Program Memory
c. Both a & b
d. None of the above
ANSWER: (a) Internal Program Memory
35) Which value of disc capacitors is preferred or recommended especially when the quartz crystal
is connected externally in an oscillator circuit of 8051?
a. 10 pF
b. 20 pF
c. 30 pF
d. 40 pF
ANSWER: © 30 pF
36) Why are the resonators not preferred for an oscillator circuit of 8051?
a. Because they do not avail for 12 MHz higher order frequencies
b. Because they are unstable as compared to quartz crystals
c. Because cost reduction due to its utility is almost negligible in comparison to total cost of
microcontroller board
d. All of the above
ANSWER: (d) All of the above
37) Which version of MCS-51 requires the necessary connection of external clock source to XTAL2
in addition to the XTAL1 connectivity to ground level?
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a. HMOS
b. CHMOS
c. CMOS
d. All of the abov
ANSWER: (a) HMOS
38) Which signal from CPU has an ability to respond the clocking value of D- flipflop (bit latch) from
the internal bus?
a. Write-to-Read Signal
b. Write-to-Latch Signal
c. Read-to-Write Signal
d. Read-to-Latch Signal
ANSWER: (b) Write-to-Latch Signal
39) Which among the below mentioned statements are precisely related to quasi-bidirectional
port?
a. Fixed high pull-up resistors are internally connected
b. Configuration in the form of input pulls the port at higher position whereas they get pulled lower
when configured as a source current
c. It is possible to drive the pin as output at any duration when FET gets turned OFF for an input function
d. Upper pull-up FET is always OFF with the provision of ‘open-drain’ output pin for normal operation of
port
a. A, B, C, D
b. A, B & C
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c. A & B
d. C & D
ANSWER: (b) A, B & C
40) What happens when the pins of port 0 & port 2 are switched to internal ADDR and ADDR /
DATA bus respectively while accessing an external memory?
a. Ports cannot be used as general-purpose Inputs/Outputs
b. Ports start sinking more current than sourcing
c. Ports cannot be further used as high impedance input
d. All of the above
ANSWER: (a) Ports cannot be used as general-purpose Inputs/Outputs
41) The upper 128 bytes of an internal data memory from 80H through FFH usually represent
_______.
a. general-purpose registers
b. special function registers
c. stack pointers
d. program counters
ANSWER: (b) special function registers
42) What is the bit addressing range of addressable individual bits over the on-chip RAM?
a. 00H to FFH
b. 01H to 7FH
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c. 00H to 7FH
d. 80H to FFH
ANSWER: © 00H to 7FH
43) What is the divisional range of program memory for internal and external memory portions
respectively when enable access pin is held high (unity)?
a. 0000H – 0FFFH & 1000H – FFFFH
b. 0000H – 1000H & 0FFFH – FFFFH
c. 0001H – 0FFFH & 01FFH – FFFFH
d. None of the above
ANSWER: (a) 0000H – 0FFFH & 1000H – FFFFH
44) Consider the following statements. Which of them is/are correct in case of program execution
related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status of
EA pin is high (1)
b. External Program memory execution takes place from 0000H through 0FFFH only when the status of
EA pin is low (0)
c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held
low (0)
d. Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held high
(1)
a. A & C
b. B & D
c. A & B
d. Only A
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ANSWER: (b) B & D
45) How does the processor respond to an occurrence of the interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
ANSWER: (a) By Interrupt Service Subroutine
46) Which address/location in the program memory is supposed to get occupied when CPU jump
and execute instantaneously during the occurrence of an interrupt?
a. Scalar
b. Vector
c. Register
d. All of the above
ANSWER: (b) Vector
47) Which location specify the storage/loading of vector address during the interrupt generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
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ANSWER: (b) Program Counter
48) Match the following :
a. ISS —————————– 1. Monitors the status of interrupt pin
b. IER —————————– 2. Allows the termination of ISS
c. RETI ————————— 3. MCS-51 Interrupts Initialization
d. INTO ————————– 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
ANSWERc) A-1, B-3, C-2, D-4
49) What kind of triggering configuration of external interrupt intimate the signal to stay low until
the generation of subsequent interrupt?
a. Edge-Triggering
b. Level Triggering
c. Both a & b
d. None of the above
ANSWER: (b) Level Triggering
50) Which among the below mentioned reasons is/are responsible for the generation of Serial Port
Interrupt?
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a. Overflow of timer/counter 1
b. High to low transition on pin INT1
c. High to low transition on pin INT0
d. Setting of either TI or RI flag
a. A & B
b. Only B
c. C & D
d. Only D
ANSWER: (d) Only D
51) What is the counting rate of a machine cycle in correlation to the oscillator frequency for
timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
ANSWER: (b) 1 / 12
52) Which special function register play a vital role in the timer/counter mode selection process by
allocating the bits in it?
a. TMOD
b. TCON
c. SCON
d. PCON
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ANSWERa) TMOD
53) How many machine cycle/s is/are executed by the counters in 8051 in order to detect ‘1’ to ‘0’
transition at the external pin?
a. One
b. Two
c. Four
d. Eight
ANSWER: (b) Two
54) Which bit must be set in TCON register in order to start the ‘Timer 0’ while operating in ‘Mode
0’?
a. TR0
b. TF0
c. IT0
d. IE0
ANSWER: (a) TR0
55) Which among the following control/s the timer1 especially when it is configured as a timer in
mode’0′, where gate and TR1 bits are attributed to be ‘1” in TMOD register?
a. TR1
b. External input at (INT1)
c. TF1
d. All of the above
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ANSWER: (b) External input at (INT1)
56) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE
enhancing the program counter to jump to another vector location?
a. Mode 0
b. Mode 1
c. Mode 2
d. Mode 3
ANSWER: (b) Mode 1
57) Consider the below generated program segment for initializing Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0
SJMP $
Which among the below mentioned program segments represent the correct code?
a. MOV SP, # 54 H
MOV TCON ,# 0010 0000 C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, # 54H
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MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $
ANSWER: ©
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
58) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an
auto-reload mode (Mode 2) operation of the timer?
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a. 125 μs
b. 250 μs
c. 256 μs
d. 1200 μs
ANSWER: © 256 μs
59) Which among the below mentioned sequence of program instructions represent the correct
chronological order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B
2. MOV TL0, # 06H
3. MOV TH0, # 06H
4. SETB TR0
5. CPL p1.0
6. ORG 0000H
a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
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ANSWER: (b) 6, 1, 3, 2, 4, 5
60) Why is it not necessary to specify the baud rate to be equal to the number of bits per second?
a. Because each bit is preceded by a start bit & followed by one stop bit
b. Because each byte is preceded by a start byte & followed by one stop byte
c. Because each byte is preceded by a start bit & followed by one stop bit
d. Because each bit is preceded by a start byte &followed by one stop byte
ANSWER: © Because each byte is preceded by a start bit & followed by one stop bit
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MICROPROCESSOR
BCA
IV Sem
MULTIPLE CHOICE QUESTIONS
1) Which is the microprocessor comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
2) What is the store by register?
a. data
b. operands
c. memory
d. None of these
3) Accumulator based microprocessor example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
4) A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
5) There are primarily two types of register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
6) Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
7) BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
8) Which is used to store critical pieces of data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
9) The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
10) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a. 16
b. 32
c. 36
d. 64
12) Which is not the control bus signal:
a. READ
b. WRITE
c. RESET
d. None of these
13) PROM stands for:
a. Programmable read‐only memory
b. Programmable read write memory
c. Programmer read and write memory
d. None of these
14) EPROM stands for:
a. Erasable Programmable read‐only memory
b. Electrically Programmable read write memory
c. Electrically Programmable read‐only memory
d. None of these
15) Each memory location has:
a. Address
b. Contents
c. Both A and B
d. None of these
16) Which is the type of microcomputer memory:
a. Processor memory
b. Primary memory
c. Secondary memory
d. All of these
17) Secondary memory can store____:
a. Program store code
b. Compiler
c. Operating system
d. All of these
18) Secondary memory is also called____:
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
19) Customized ROMS are called:
a. Mask ROM
b. Flash ROM
c. EPROM
d. None of these
20) The RAM which is created using bipolar transistors is called:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. DDR RAM
21) Which type of RAM needs regular referred:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
22) Which RAM is created using MOS transistors:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
23) A microprocessor retries instructions from :
a. Control memory
b. Cache memory
c. Main memory
d. Virtual memory
24) The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
a. Address bus
b. System bus
c. Control bus
d. Data bus
25) The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
a. Read
b. Write
c. Both A and B
d. None of these
26) The CPU removes the ___ signal to complete the memory write operation:
a. Read
b. Write
c. Both A and B
d. None of these
27) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
28) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
29) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
30) Eight of the register are known as:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
31) The four index register can be used for:
a. Arithmetic operation
b. Multipulation operation
c. Subtraction operation
d. All of these
32) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
33) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
34) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
36) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
37) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
38) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
39) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
40) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
41) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
42) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
43) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
44) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
45) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
46) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
47) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
48) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
49) ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a. Data segment
b. Code segment
c. Stack segment
d. Extra segment
50) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
51) Which are the factor of cache memory:
a. Architecture of the microprocessor
b. Properties of the programs being executed
c. Size organization of the cache
d. All of these
52) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
53) Which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
54) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
55) Microprocessor reference that are available in the cache are called______:
a. Cache hits
b. Cache line
c. Cache memory
d. All of these
56) Microprocessor reference that are not available in the cache are called_________:
a. Cache hits
b. Cache line
c. Cache misses
d. Cache memory
57) Which causes the microprocessor to immediately terminate its present activity:
a. RESET signal
b. INTERUPT signal
c. Both
d. None of these
58) Which is responsible for all the outside world communication by the microprocessor:
a. BIU
b. PIU
c. TIU
d. LIU
59) INTR: it implies the__________ signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
60) Which of the following are the two main components of the CPU?
a. Control Unit and Registers
b. Registers and Main Memory
c. Control unit and ALU
d. ALU and bus
61) Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
a. Conductors
b. Buses
c. Connectors
d. Consecutives
62) The language that the computer can understand and execute is called
a. Machine language
b. Application software
c. System program
d. All of the above
63) Which of the following is used as a primary storage device?
a. Magnetic drum
b. PROM
c. Floppy disk
d. All of these
64) Which of the following memories needs refresh?
a. SRAM
b. DRAM
c. ROM
d. All of above
65) The memory which is programmed at the time it is manufactured
a. PROM
b. RAM
c. PROM
d. EPROM
66) Which of the following memory medium is not used as main memory system?
a. Magnetic core
b. Semiconductor
c. Magnetic tape
d. Both a and b
67) Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
68) One of the main feature that distinguish microprocessors from micro‐computers is
a. Words are usually larger in microprocessors
b. Words are shorter in microprocessors
c. Microprocessor does not contain I/O devices
d. Exactly the same as the machine cycle time
69) The first microprocessor built by the Intel Corporation was called
a. 8008
b. 8080
c. 4004
d. 8800
70) An integrated circuit is
a. A complicated circuit
b. An integrating device
c. Much costlier than a single transistor
d. Fabricated on a tiny silicon chip
71) Most important advantage of an IC is its
a. Easy replacement in case of circuit failure
b. Extremely high reliability
c. Reduced cost
d. Low powers consumption
72) Which of the following items are examples of storage devices?
a. Floppy / hard disks
b. CD‐ROMs
c. Tape devices
d. All of the above
73) The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
a. 8 bits
b. 12 bits
c. 16 bits
d. 32 bits
74) Which is the type of memory for information that does not change on your computer?
a. RAM
b. ROM
c. ERAM
d. RW / RAM
75) What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
a. Extended
b. Expanded
c. Base
d. Conventional
76) Before a disk can be used to store data. It must be…….
a. Formatted
b. Reformatted
c. Addressed
d. None of the above
77) Which company is the biggest player in the microprocessor industry?
a. Motorola
b. IBM
c. Intel
d. AMD
78) A typical personal computer used for business purposes would have… of RAM.
a. 4 KB
b. 16 K
c. 64 K
d. 256 K
78) The word length of a computer is measured in
a. Bytes
b. Millimeters
c. Meters
d. Bits
79) What are the three decisions making operations performed by the ALU of a computer?
a. Grater than
b. Less than
c. Equal to
d. All of the above
80) Which part of the computer is used for calculating and comparing?
a. Disk unit
b. Control unit
c. ALU
d. Modem
81) Can you tell what passes into and out from the computer via its ports?
a. Data
b. Bytes
c. Graphics
d. Pictures
82) What is the responsibility of the logical unit in the CPU of a computer?
a. To produce result
b. To compare numbers
c. To control flow of information
d. To do math’s works
83) The secondary storage devices can only store data but they cannot perform
a. Arithmetic Operation
b. Logic operation
c. Fetch operations
d. Either of the above
84) Which of the following memories allows simultaneous read and write operations?
a. ROM
b. RAM
c. EPROM
d. None of above
85) Which of the following memories has the shortest access times?
a. Cache memory
b. Magnetic bubble memory
c. Magnetic core memory
d. RAM
86) A 32 bit microprocessor has the word length equal to
a. 2 byte
b. 32 byte
c. 4 byte
d. 8 byte
87) An error in computer data is called
a. Chip
b. Bug
c. CPU
d. Storage device
88) The silicon chips used for data processing are called
a. RAM chips
b. ROM chips
c. Micro processors
d. PROM chips
89) The metal disks, which are permanently housed in, sealed and contamination free containers
are called
a. Hard disks
b. Floppy disk
c. Winchester disk
d. Flexible disk
90) A computer consists of
a. A central processing unit
b. A memory
c. Input and output unit
d. All of the above
91) The instructions for starting the computer are house on
a. Random access memory
b. CD‐Rom
c. Read only memory chip
d. All of above
92) The ALU of a computer normally contains a number of high speed storage element called
a. Semiconductor memory
b. Registers
c. Hard disks
d. Magnetic disk
93) The first digital computer built with IC chips was known as
a. IBM 7090
b. Apple – 1
c. IBM System / 360
d. VAX‐10
94) Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
95) Which of the following is used for manufacturing chips?
a. Control bus
b. Control unit
c. Parity unit
d. Semiconductor
96) To locate a data item for storage is
a. Field
b. Feed
c. Database
d. Fetch
97) A directly accessible appointment calendar is feature of a … resident package
a. CPU
b. Memory
c. Buffer
d. ALU
98) The term gigabyte refers to
a. 1024 bytes
b. 1024 kilobytes
c. 1024 megabytes
d. 1024 gigabyte
99) A/n …. Device is any device that provides information, which is sent to the CPU
a. Input
b. Output
c. CPU
d. Memory
100) Current SIMMs have either … or … connectors (pins)
a. 9 or 32
b. 30 or 70
c. 28 or 72
d. 30 or 72
101) Which is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
102) Which technology using the microprocessor is fabricated on a single chip:
a. POS
b. MOS
c. ALU
d. ABM
103) MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
104) In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
105) The register section is related to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
106) In Microprocessor one of the operands holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
107) Which register is a temporary storage location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
108) PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
109) IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
110) SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
111) The act of acquiring an instruction is referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
112) How many bit of instruction on our simple computer consist of one____:
a. 2‐bit
b. 6‐bit
c. 12‐bit
d. None of these
113) How many parts of single address computer instruction :
a. 1
b. 2
c. 3
d. 4
114) Single address computer instruction has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
115) LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
116) Which are the flags of status register:
a. Over flow flag
b. Carry flag
c. Half carry flag
d. Zero flag
e. Interrupt flag
f. Negative flag
g. All of these
117) The carry is operand by:
a. C
b. D
c. S
d. O
118) The sign is operand by:
a. S
b. D
c. C
d. O
119) The zero is operand by:
a. Z
b. D
c. S
d. O
120) The overflow is operand by:
a. O
b. D
c. S
d. C
121) _________ Stores the instruction currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
122) In which register instruction is decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
123) The status register is also called the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
124) The area of memory with addresses near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
125) The processor uses the stack to keep track of where the items are stored on it this by using
the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
126) Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
127) Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
128) SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
129) How many bit stored by status register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
130) The 16 bit register is separated into groups of 4 bit where each groups is called:
a. BCD
b. Nibble
c. Half byte
d. None of these
131) A nibble can be represented in the from of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
132) The left side of any binary number is called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
133) MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
134) _____ a subsystem that transfer data between computer components inside a computer
or between computer:
a. Chip
b. Register
c. Processor
d. Bus
135) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
136) Which bus carry addresses:
a. System bus
b. Address bus
c. Control bus
d. Data bus
137) A 16 bit address bus can generate___ addresses:
a. 32767
b. 25652
c. 65536
d. none of these
138) CPU can read & write data by using :
a. Control bus
b. Data bus
c. Address bus
d. None of these
139) Which bus transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a. Control bus
b. Data bus
c. Address bus
d. None of these
140) When memory read or I/O read are active data is to the processor :
a. Input
b. Output
c. Processor
d. None of these
141) When memory write or I/O read are active data is from the processor:
a. Input
b. Output
c. Processor
d. None of these
142) CS stands for:
a. Cable select
b. Chip select
c. Control select
d. Cable system
143) WE stands for:
a. Write enable
b. Wrote enable
c. Write envy
d. None of these
144) MAR stands for:
a. Memory address register
b. Memory address recode
c. Micro address register
d. None of these
145) MDR stands for:
a. Memory data register
b. Memory data recode
c. Micro data register
d. None of these
146) Which are the READ operation can in simple steps:
a. Address
b. Data
c. Control
d. All of these
147) DMA stands for:
a. Direct memory access
b. Direct memory allocation
c. Data memory access
d. Data memory allocation
148) The ____ place the data from a register onto the data bus:
a. CPU
b. ALU
c. Both A and B
d. None of these
149) The microcomputer system by using the ____device interface:
a. Input
b. Output
c. Both A and B
d. None of these
150) The standard I/O is also called:
a. Isolated I/O
b. Parallel I/O
c. both a and b
d. none of these
151) The external device is connected to a pin called the ______ pin on the processor chip.
a. Interrupt
b. Transfer
c. Both
d. None of these
152) Which interrupt has the highest priority?
a) INTR
b) TRAP
c) RST6.5
d) none of these
153) In 8085 name the 16 bit registers?
a) Stack pointer
b) Program counter
c) a & b
d) none of these
154) What are level Triggering interrupts?
a) INTR&TRAP
b) RST6.5&RST5.5
c) RST7.5&RST6.5
d) none of these
155) Which stack is used in 8085?
a) FIFO
b) LIFO
c) FILO
d) none of these
156) What is SIM?
a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask.
d) none of these
157) RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
d) none of these
158) In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR d) none of these
159) In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
160) BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
161) EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
162) Which are the part of architecture of 8086:
a. The bus interface unit
b. The execution unit
c. Both A and B
d. None of these
163) Which are the four categories of registers:
a. General‐ purpose register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
164) IP Stand for:
a. Instruction pointer
b. Instruction purpose
c. Instruction paints
d. None of these
165) CS Stand for:
a. Code segment
b. Coot segment
c. Cost segment
d. Counter segment
166) DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
167) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e. All of these
168) The acculatator is 16 bit wide and is called:
a. AX
b. AH
c. AL
d. DL
169) The upper 8 bit are called______:
a. BH
b. BL
c. AH
d. CH
170) The lower 8 bit are called_______:
a. AL
b. CL
c. BL
d. DL
171) IP stand for:
a. Industry pointer
b. Instruction pointer
c. Index pointer
d. None of these
172) Which has great important in modular programming:
a. Stack segment
b. Queue segment
c. Array segment
d. All of these
173) Which register containing the 8086/8088 flag:
a. Status register
b. Stack register
c. Flag register
d. Stand register
174) How many bits the instruction pointer is wide:
a. 16 bit
b. 32 bit
c. 64 bit
d. 128 bit
175) How many type of addressing in memory:
a. Logical address
b. Physical address
c. Both A and B
d. None of these
176) The size of each segment in 8086 is:
a. 64 kb
b. 24 kb
c. 50 kb
d. 16kb
177) The physical address of memory is :
a. 20 bit
b. 16 bit
c. 32 bit
d. 64 bit
178) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
179) The pin configuration of 8086 is available in the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
180) DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
181) PA stand for:
a. Project address
b. Physical address
c. Pin address
d. Pointer address
182) SBA stand for:
a. Segment bus address
b. Segment bit address
c. Segment base address
d. Segment byte address
183) EA stand for:
a. Effective address
b. Electrical address
c. Effect address
d. None of these
184) BP stand for:
a. Bit pointer
b. Base pointer
c. Bus pointer
d. Byte pointer
185) DI stand for:
a. Destination index
b. Defect index
c. Definition index
d. Delete index
186) SI stand for:
a. Stand index
b. Source index
c. Segment index
d. Simple index
187) DS stand for:
a. Default segment
b. Defect segment
c. Delete segment
d. Definition segment
188) ALE stand for:
a. Address latch enable
b. Address light enable
c. Address lower enable
d. Address last enable
189) AD stand for:
a. Address data
b. Address delete
c. Address date
d. Address deal
190) NMI stand for:
a. Non mask able interrupt
b. Non mistake interrupt
c. Both
d. None of these
191) PC stand for:
a. program counter
b. project counter
c. protect counter
d. planning counter
192) AH stand for:
a. Accumulator high
b. Address high
c. Appropriate high
d. Application high
193) AL stand for:
a. Accumulator low
b. Address low
c. Appropriate low
d. Application low
194) The offset of a particular segment varies from _________:
a. 000H to FFFH
b. 0000H to FFFFH
c. 00H to FFH
d. 00000H to FFFFFH
195) ________ is usually the first level of memory access by the microprocessor:
a. Cache memory
b. Data memory
c. Main memory
d. All of these
196) which is the small amount of high‐ speed memory used to work directly with the
microprocessor:
a. Cache
b. Case
c. Cost
d. Coos
197) The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a. Main memory
b. Case memory
c. Cache memory
d. All of these
198) How many type of cache memory:
a. 1
b. 2
c. 3
d. 4
199) Which is the type of cache memory:
a. Fully associative cache
b. Direct‐mapped cache
c. Set‐associative cache
d. All of these
200) ) Which memory is used to holds the address of the data stored in the cache :
a. Associative memory
b. Case memory
c. Ordinary memory
d. None of these
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
S. BTL
Objective Questions (MCQ /True or False / Fill up with Choices )
No.
8085 microprocessor has how many pins
A) 30
1 B) 39 L1
C) 40
D) 41
Which one of the following is not a vectored interrupt?
A) TRAP
L2
2 B) INTR
C) RST 7.5
D) RST 3
In 8085 microprocessor, the RST6 instruction transfer programme execution to following
location
A) 0030H L3
3
B) 0024H
C) 0048H
D) 0060H
HLT opcode means
A) Load data to accumulator
L2
4 B) Store result in memory
C) Load accumulator with contents of register
D) End of Program
In 8085 names of the 16 bit registers are
A) Stack pointer
L1
5 B) Program counter
C) Both A and B
D) None of these
What is SIM?
6 L2
A) Select interrupt
B) Sorting interrupt mask
Prepared By: R.Chitra AP/EEE Page 1 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) Set interrupt mask
D) None of these
A field programmable ROM is called
A) MROM
7 B) PROM L1
C) FROM
D) FPROM
The number of output pins in 8085 microprocessors are
A) 27
8 B) 40 L1
C) 21
D) 19
The program counter in a 8085 micro-processor is a 16-bit register, because
A) It counts 16 bit at a time
9 B) There are 16 address lines L2
C) It facilitates the user storing 16 bit data temporarily
D) It has to fetch two 8 bit data at a time
Output of the assembler in machine codes is referred to as
A) Object program
B) Source program
10 L2
C) Macro instruction
D) Symbolic addressing
Which of the following statements for intel 8085 is correct?
A) Program counter(PC) specifies the address of the instruction last executed
B) PC specifies the address of the instruction being executed
11 L1
C) PC specifies the address of the instruction to be executed
D) PC specifies the number of instructions executed so far
Which one of the following is not correct?
12 L1
A) Bus is a group of wires
Prepared By: R.Chitra AP/EEE Page 2 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
B) Bootstrap is a technique or device for loading first instruction
C) An instruction is a set of bits that defines a computer operation
D) An interrupt signal is required at the start of every program
The processor status word of 8085 microprocessor has five flags namely:
A) S, Z, AC, P, CY
13 B) S, OV, AC, P, CY L1
C) S, Z, OV, P, CY
D) S, Z, AC, P, OV
The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one
of the following?
A) Clock cycle
14 L2
B) Memory cycle
C) Machine cycle
D) Instruction cycle
Which is the microprocessor comprises:
A) Register section
15 B) One or more ALU L1
C) Control unit
D) All of these
What is the store by register?
A) Data
16 B) Operands L1
C) Memory
D) None of these
Accumulator based microprocessor example are:
A) Intel 8085
17 B) Motorola 6809 L2
C) A and B
D) None of these
A set of register which contain are:
18 L1
A) data
Prepared By: R.Chitra AP/EEE Page 3 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
B) Memory addresses
C) Result
D) All of these
There are primarily two types of register:
A. General purpose register
19 B. Dedicated register L3
C. A and B
D. None of these
BCD stands for:
A) Binary coded decimal
20 B) Binary coded decoded L2
C) Both a & b
D) none of these
Which is used to store critical pieces of data during subroutines and interrupts:
A) Stack
21 B) Queue L1
C) Accumulator
D) Data register
The data in the stack is called:
A) Pushing data
22 B) Pushed L3
C) Pulling
D) None of these
Which is not the control bus signal:
A) READ
23 B) WRITE L1
C) RESET
D) None of these
PROM stands for:
24 L2
A) Programmable read-only memory
B) Programmable read write memory
Prepared By: R.Chitra AP/EEE Page 4 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) Programmer read and write memory
D) None of these
Each memory location has:
A) Address
25 B) Contents L1
C) Both A and B
D) None of these
The RAM which is created using bipolar transistors is called:
A) Dynamic RAM
26 B) Static RAM L2
C) Permanent RAM
D) DDR RAM
EPROM stands for:
A) Erasable Programmable read-only memory
27 B) Electrically Programmable read write memory L3
C) Electrically Programmable read-only memory
D) None of these
The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
A) Read
28 B) Write L1
C) Both A and B
D) None of these
BIU STAND FOR:
A) Bus interface unit
29 B) Bess interface unit L3
C) A and B
D) None of these
The four index register can be used for:
30 A) Arithmetic operation L1
B) Multipulation operation
C) Subtraction operation
Prepared By: R.Chitra AP/EEE Page 5 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
D) All of these
The CPU removes the ___ signal to complete the memory write operation:
A) Read
31 B) Write L2
C) Both A and B
D) None of these
EU STAND FOR:
A) Execution unit
32 B) Execute unit L1
C) Exchange unit
D) None of these
Eight of the register are known as:
A) General- purpose register
33 B) Pointer or index registers L2
C) Segment registers
D) Other register
CS Stand for:
A) Code segment
34 B) Coot segment L3
C) Cost segment
D) Counter segment
In 8085 microprocessor system with memory mapped I/O, which of the following is true?
A) Devices have 8-bit address line
35 B) Devices are accessed using IN and OUT instructions L1
C) There can be maximum of 256 input devices and 256 output devices
D) Arithmetic and logic operations can be directly performed with the I/O data
Consider the following statements:
In 8085 microprocessor, data-bus and address bus are multiplexed in order to
Which of these statements is/are correct?
36 L1
A) Increase the speed of microprocessor.
B) Reduce the number of pins.
Prepared By: R.Chitra AP/EEE Page 6 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 01 Unit Name : 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) Connect more peripheral chips.
In intel 8085A microprocessor ALE signal is made high to
A) Enable the data bus to be used as low order address bus
37 B) To latch data D0-D7 from data bus L1
C) To disable data bus
D) To achieve all the functions listed above
DS Stand for:
A) Data segment
38 B) Direct segment L1
C) Declare segment
D) Divide segment
8085 microprocessor is an 8-bit microprocessor designed by?
A) IBM
39 B) Dell L2
C) Intel
D) VAX
Flag register is an 8-bit register having __________ 1-bit flip-flops.
A) 3
40 B) 4 L1
C) 5
D) 6.
What is true about Program counter?
A) It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
41 B) When an instruction is fetched from memory then it is stored in the program counter L2
C) It provides timing and control signal to the microprocessor
D) It is a 16-bit register used to store the memory address location of the next
instruction to be executed.
Prepared By: R.Chitra AP/EEE Page 7 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE/ EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
S.
Objective Questions (MCQ /True or False / Fill up with Choices ) BTL
No.
How many types of basic multiprocessor configurations?
A) 2
L1
1 B) 3
C) 4
D) 5
A _____________ is a specially designed circuit on microprocessor chip which can perform
the same task very quickly, which the microprocessor performs
A) Coprocessor configuration L2
2
B) Closely coupled configuration
C) Loosely coupled configuration
D) None of the above
The coprocessor and the processor is connected via?
A) TEST
3 B) QS0 L1
C) QS1
D) All of the above
It is a power supply signal, which requires +5V supply for the operation of the circuit.
A) VCA
4 B) VDD L2
C) VCC
D) INTA.
The _________ handles all the communication between the processor and the memory
A) numeric extension unit
5 B) Packed Unit L3
C) control unit
D) Binary Unit
In 8085 microprocessor system with memory mapped I/O, which of the following is true?
6 L2
A) Devices have 8-bit address line
B) Devices are accessed using IN and OUT instructions
Prepared By: R.Chitra AP/EEE Page 1 of 7
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) There can be maximum of 256 input devices and 256 output devices
D) Arithmetic and logic operations can be directly performed with the I/O data
An interrupt breaks the execution of instructions and diverts its execution to
A) Interrupt service routine
7 B) Counter word register L1
C) Execution unit
D) control unit
While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
A) multi-interrupt
8 L2
B) nested interrupt
C) interrupt within interrupt
D) nested interrupt and interrupt within interrupt
NMI stands for
A) nonmaskable interrupt
9 B) nonmultiple interrupt L1
C) nonmovable interrupt
D) none of the mentioned
If any interrupt request given to an input pin cannot be disabled by any means then the input
pin is called
A) maskable interrupt
10 L2
B) nonmaskable interrupt
C) maskable interrupt and nonmaskable interrupt
D) none of the mentioned
The INTR interrupt may be
A) maskable
11 L1
B) nonmaskable
C) maskable and nonmaskable
D) none of the mentioned
While CPU is executing a program, an interrupt exists then it
12 L2
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
A) follows the next instruction in the program
B) jumps to instruction in other registers
C) breaks the normal sequence of execution of instructions
D) stops executing the program
Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have
13 A) interrupt handling ability L2
B) interrupt processing ability
C) multiple interrupt processing ability
D) multiple interrupt executing ability
The Programmable interrupt controller is required to
A) handle one interrupt request
14 B) handle one or more interrupt requests at a time L1
C) handle one or more interrupt requests with a delay
D) handle no interrupt request
The INTR interrupt may be masked using the flag
A) direction flag
15 B) overflow flag L2
C) interrupt flag
D) sign flag
In 8085 microprocessor how many interrupts are maskable
A) Two
16 B) Three L1
C) Four
D) Five
Which stack is used in 8085 microprocessor
A) FIFO
17 B) FILO L1
C) LIFO
D) LILO
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
In this instruction of the 8085 microprocessor how many bytes are present
A) One or two
18 B) One , two or three L2
C) One only
D) Two or Three
Which one of the following addressing technique is not used in 8085 microprocessor
A) Register
19 B) Immediate L1
C) Register indirect
D) Relative
Which one of the following register of 8085 microprocessor is not a part of the programming
model
A) Instruction register
20 L1
B) Memory address register
C) Status register
D) Temporary data register
The program counter in 8085 microprocessor is a 16 bit register because
A) It counts 16 bits at a time
21 B) There are 16 address times L2
C) It facilitates the users storing 16 bit data temporarily
D) It has to fetch two 8 bit data at a time
A direct memory access (DMA) transfer replies
A) Direct transfer of data between memory and accumulator
B) Direct transfer of data between memory and I/O devices without the use of
22 microprocessor L1
C) Transfer of data exclusively within microprocessor registers
D) A fast transfer of data between microprocessor and I/O devices
Handshaking mode of data transfer is
23 A) Synchronous data transfer L1
B) asynchronous data transfer
C) interrupt driven data transfer
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
D) level mode of DMA data transfer
In a microprocessor the address of the new next instruction to be executed is stored in
A) Stack pointer
24 B) Address latch L2
C) Program counter
D) General purpose register
The instruction RET executes with the following series of machine cycle
A) Fetch, read, write
25 B) Fetch, write, write L2
C) Fetch, read, read
D) Fetch, read
Which one of the following statements is correct regarding the instruction CMP A
A) Compare accumulator with register A
B) Compare accumulator with memory
26 L1
C) Compare accumulator with register H
D) Instruction does not exist
The instruction JNC 16 – bit refers to jump to 16 – bit address if
A) Sign flag is set
27 B) Carry flag is reset L1
C) Zero flag is set
D) Parity flag is reset
Among the given instructions, the which affects the maximum number of flags is
A) RAL
B) POP PSW
28 L1
C) XRA A
D) DCR A
XCHG instruction of 8085 exchange the content of
29 L1
A) Top of stack with contents of register pair
B) BC and DE register pairs
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) HL and DE register pairs
D) None of the above
Direction flag is used with
A) String instructions
30 B) Stack instructions L2
C) Arithmetic instructions
D) Branch instructions
Following is a 16 bit register for 8085 microprocessor
A) Stack pointer
31 B) Accumulator L1
C) Register B
D) Register C
The register inform which holds the information about the nature of results of arithmetic of
logic operations is called as
A) Accumulator
32 L1
B) Condition code register
C) Flag register
D) Process status registers
When referring to instruction words a mnemonic is
A) A short abbreviation for the operand address
33 B) A short abbreviation for the operation to be performed L1
C) A short abbreviation for the data word stored at the operand address
D) Shorthand for machine language
A microprocessor retries instructions from :
A) Control memory
34 B) Cache memory L2
C) Main memory
D) Virtual memory
How many bits the instruction pointer is wide:
35 L1
A) 16 bit
B) 32 bit
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 02 Unit Name : Programming Of 8085 Processor Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) 64 bit
D) 128 bit
A machine language instructions format consists of
A) Operation code field.
36 B) Operation code field & operand field L1
C) Operand field
D) none of the mentioned
IP Stand for:
A) Instruction pointer
37 B) Instruction purpose L2
C) Instruction paints
D) None of these
The instruction MOVAX, 123H is an example of
A) register addressing mode
38 B) immediate addressing mode L1
C) based indexed addressing mode
D) direct addressing mode
Which of the following is true about Control and status signals?
A) These signals are used to identify the nature of operation.
39 B) There are 3 control signal and 3 status signals. L1
C) Three status signals are IO/M, S0 & S1.
D) All of the above
How many and what are the machine cycles needed foe execution of PUSH B?
A) 2, 1 Fetch and 1 Memory write
40 B) 3, 1 Fetch and 2 Memory write L2
C) 3, 1 Fetch , 1 Memory read and 1 Memory write
D) 3, 1 Fetch and 2 Memory read
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
S. BTL
Objective Questions (MCQ /True or False / Fill up with Choices )
No.
Which of the following is not an addressing mode of 8051?
A) register instructions
L1
1 B) register specific instructions
C) indexed addressing
D) None
The symbol, ‘address 16’ represents the 16-bit address which is used by the instructions to
specify the
A) destination address of CALL L2
2
B) source address of JUMP
C) destination address of call or jump
D) source address of call or jump
The storage of addresses that can be directly accessed is
A) external data RAM
L1
3 B) internal data ROM
C) internal data RAM and SFRS
D) external data ROM and SFRS
The address register for storing the 16-bit addresses can only be
A) stack pointer
4
L2
B) data pointer
C) instruction register
D) Accumulator
The address register for storing the 8-bit addresses can be
A) R0 of the selected bank of register
L1
5 B) R1 of the selected bank of register
C) Stack pointer
D) All of the mentioned
The instruction, ADD A, #100 performs
L3
6 A) 100(decimal) is added to contents of address register
B) 100(decimal) is subtracted from the accumulator
C) 100(decimal) is added to contents of an accumulator
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
D) None
In which of these addressing modes, a constant is specified in the instruction, after the
opcode byte?
A) register instructions L1
7
B) Register specific instructions
C) Direct addressing
D) immediate mode
The instruction, ADD A, R7 is an example of
A) register instructions
L1
8 B) Register specific instructions
C) Indexed addressing
D) none
The only memory which can be accessed using indexed addressing mode is
A) RAM
L2
9 B) ROM
C) Main memory
D) Program memory
The data address of look-up table is found by adding the contents of
A) accumulator with that of program counter
L1
10 B) accumulator with that of program counter or data pointer
C) data register with that of program counter or accumulator
D) data register with that of program counter or data pointer
8051 Microcontrollers are manufactured by which of the following companies?
A) Atmel
L2
11 B) Philips
C) Intel
D) All of the mentioned
AT89C2051 has RAM of:
L1
12
A) 128 bytes
B) 256 bytes
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) 64 bytes
D) 512 bytes
8051 series has how many 16 bit registers?
A) 2
L1
13 B) 3
C) 1
D) 0
When 8051 wakes up then 0x00 is loaded to which register?
A) PSW
L1
14 B) SP
C) PC
D) None of the mentioned
When the microcontroller executes some arithmetic operations, then the flag bits of which
register are affected?
A) PSW L2
15
B) SP
C) DPTR
D) PC
How are the status of the carry, auxiliary carry and parity flag affected if the write
instruction
MOV A,#9C
ADD A,#64H
L3
16
A) CY=0,AC=0,P=0
B) CY=1,AC=1,P=0
C) CY=0,AC=1,P=0
D) CY=1,AC=1,P=1
How are the bits of the register PSW affected if we select Bank2 of 8051?
A) PSW.5=0 and PSW.4=1
L2
17 B) PSW.2=0 and PSW.3=1
C) PSW.3=1 and PSW.4=1
D) PSW.3=0 and PSW.4=1
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
If we push data onto the stack then the stack pointer
A) increases with every push
L1
18 B) decreases with every push
C) increases & decreases with every push
D) none of the mentioned
On power up, the 8051 uses which RAM locations for register R0- R7
A) 00-2F
19
L1
B) 00-07
C) 00-7F
D) 00-0F
How many bytes of bit addressable memory is present in 8051 based microcontrollers?
A) 8 bytes
L2
20 B) 32 bytes
C) 16 bytes
D) 128 bytes
A microcontroller at-least should consist of:
A) RAM, ROM, I/O ports and timers
L1
21 B) CPU, RAM, I/O ports and timers
C) CPU, RAM, ROM, I/O ports and timers
D) CPU, ROM, I/O ports and timers
Unlike microprocessors, microcontrollers make use of batteries because they have:
A) high power dissipation
L1
22 B) low power consumption
C) low voltage consumption
D) low current consumption
Why microcontrollers are not called general purpose computers?
A) because they have built in RAM and ROM
23
L2
B) because they design to perform dedicated task
C) because they are cheap
D) because they consume low power
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
How many bytes of bit addressable memory is present in 8051 based microcontrollers?
A) 8 bytes
L1
24 B) 32 bytes
C) 16 bytes
D) 128 bytes
What are the two instruction set architecture (ISA) classification
A) SIDC & BIDC
25
L1
B) CISC & RISC
C) CISC & VISC
D) RISC & VISC
How many timers / counters 8051 16- bit microprocessor have
A) 1
L2
26 B) 2
C) 5
D) 8
Register that is used to holds the memory address of the next instruction to be executed is
A) Program Memory
L1
27 B) Program Counter
C) Control Unit
D) Instruction decoder
What do you mean by micro in microcontroller?
A) Distance between 2 IC’s
L2
28 B) Distance between 2 transistors
C) Size of a controller
D) Distance between 2 pins
What is the bit size of the 8051 microcontroller?
A) 8-bit
29
L1
B) 4-bit
C) 16-bit
D) 32-bit
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
Name the architecture and the instruction set for microcontroller?
A) Van- Neumann Architecture with CISC Instruction Set
L2
30 B) Harvard Architecture with CISC Instruction Set
C) Van- Neumann Architecture with RISC Instruction Set
D) Harvard Architecture with RISC Instruction Set
Number of I/O ports in the 8051 microcontroller?
A) 3 ports
31
L1
B) 4 ports
C) 5 ports
D) 4 ports with last port having 5 pins
Is ROM is used for storing data storage?
L2
32 A) True
B) False
SCON in serial port is used for which operation?
A) Transferring data
L1
33 B) Receiving data
C) Controlling
D) Controlling and transferring
Program counter stores what?
A) Address of before instruction
L3
34 B) Address of the next instruction
C) Data of the before execution to be executed
D) Data of the execution instruction
Auxiliary carry is set during which condition?
A) When carry is generated from D3 to D4
35
L1
B) When carry is generated from D7
C) When carry is generated from both D3 to D4 and D7
D) When carry is generated at either D3 to D4 or D7
The use of Address Latch Enable is to multiplex address and data memory.
L1
36
A) True
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NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 03 Unit Name : 8051 Micro Controller Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
B) False
Which pin provides a reset option in 8051?
A) Pin 1
L2
37 B) Pin 8
C) Pin 11
D) Pin 9
External Access is used to permit ____________
A) Peripherals
38
L1
B) Power supply
C) ALE
D) Memory interfacing
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
S.
Objective Questions (MCQ /True or False / Fill up with Choices ) BTL
No.
SPI device communicates in _________
A) Simplex
1 B) Half duplex L1
C) Full duplex
D) Both half and full duplex
Secure digital card application uses which protocol?
A) UART
2 B) SPI L2
C) I2C
D) USART
Do SPI have/has a single master?
3 A) True L1
B) False
How many logic signals are there in SPI?
A) 5 signals
4 B) 6 signals L3
C) 4 signals
D) 7 signals
Port C of 8255 can function independently as
A) input port
5 B) output port L2
C) either input or output ports
D) both input and output ports
The data bus buffer is controlled by
A) control word register
6 B) read/write control logic L3
C) data bus
D) none of the mentioned
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
SPI is described as Asynchronous serial interface.
7 A) True L1
B) False
Which of the following is an advantage of SPI?
A) No start and stop bits
8 B) Use 4 wires L2
C) Allows for single master
D) Error checking is not present
SMBUS stands for ___________
A) Serial Memory Bus
9 B) Serial Management Bus L3
C) System Management Bus
D) System Memory Bus
Programmable peripheral input-output port is another name for
A) serial input-output port
10 B) parallel input-output port L2
C) serial input port
D) parallel output port
All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
A) data bus control
11 L1
B) read logic control
C) control word register
D) none of the mentioned
The input provided by the microprocessor to the read/write control logic is
A) RESET
12 B) A1 L1
C) WR(ACTIVE LOW)
D) All of the mentioned
Which has a half duplex communication?
13 L1
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
A) Queued SPI
B) Micro wire
C) Micro wire/plus
D) Quad SPI
The device that receives or transmits data upon the execution of input or output instructions
by the microprocessor is
A) control word register
14 L1
B) read/write control logic
C) 3-state bidirectional buffer
D) none of the mentioned
The port th1at is used for the generation of handshake lines in mode 1 or mode 2 is
A) port A
15 B) port B L2
C) port C Lower
D) port C Upper
If A1=0, A0=1 then the input read cycle is performed from
A) port A to data bus
16 B) port B to data bus L1
C) port C to data bus
D) CWR to data bus
The function, ‘data bus tristated’ is performed when
A) CS(active low) = 1
B) CS(active low) = 0
17 L3
C) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
D) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low)
=1
The pin that clears the control word register of 8255 when enabled is
A) CLEAR
18 B) SET L1
C) RESET
D) CLK
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
Which of the following depends the number of bits that are transferred?
A) wait statement
19 B) ready statement L1
C) time
D) counter
What does SPI stand for?
A) serial parallel interface
20 B) serial peripheral interface L2
C) sequential peripheral interface
D) sequential port interface
In which register does the data is written in the master device?
A) index register
21 B) Accumulator L2
C) SPDR
D) status register
Which signal is used to select the slave in the serial peripheral interfacing?
A) slave select
22 B) master select L1
C) Interrupt
D) clock signal
How much time period is necessary for the slave to receive the interrupt and transfer the
data?
A) 4 clock time period
23 L2
B) 8 clock time period
C) 16 clock time period
D) 24 clock time period
How many pins does the 8255 PPI IC contains?
A) 24
24 B) 20 L3
C) 32
D) 40
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
Which of the following pins are responsible for handling the on the Read Write control
logic unit of the 8255 PPI?
A) CS'
25 L1
B) RD'
C) WR'
D) All of the above
In mode 2 of I/O mode, which of the following ports are capable of transferring the data in
both the directions?
A) Port A
26 L2
B) Port B
C) Port C
D) All of the above
The ______ is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O.
A) 8285A
27 L1
B) 8241A
C) 8255A
D) 8251A
How many ports 8255A has?
A) 2
28 B) 3 L3
C) 4
D) 5
Which port can be split into two parts?
A) PORT A
29 B) PORT B L1
C) PORT C
D) PORT D
How many bits of data can be transferred between the 8255 PPI and the interfaced device at
a time? or What is the size of internal bus of the 8255 PPI?
30 L2
A) 16 bits
B) 12 bits
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NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
C) 8 bits
D) None of the above
INTR, WR signal is an input/output signal pin?
A) both are output
31 B) both are input L1
C) one is input and the other is output
D) none of the mentioned
Which of the following uses N-MOS technology?
A) 8253
B) 8254
32 L3
C) 8255
D) 8256
8 input DAC has ________
A) 8 discrete voltage levels
33 B) 64 discrete voltage levels L1
C) 124 discrete voltage levels
D) 256 discrete voltage levels
8253/54 can be operated in _________ Modes?
A) 3
34 B) 4 L1
C) 5
D) 6
Which of the following statements are true about DAC0808?
A) parallel digital data to analog data conversion
35 B) it has current as an output L2
C) all of the mentioned
D) none of the mentioned
All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
36 L1
A) data bus control
Prepared By: R.Chitra AP/EEE Page 6 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 04 Unit Name : Peripheral Interfacing Date 30.09.2020
OBJECTIVE TYPE QUESTION BANK
B) read logic control
C) control word register
D) none of the mentioned
Prepared By: R.Chitra AP/EEE Page 7 of 7
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
S.
Objective Questions (MCQ /True or False / Fill up with Choices ) BTL
No.
What is the principle on which electromagnetic relays operate?
A) electromagnetic induction
1 B) motor control L1
C) Switching
D) none of the mentioned
Which of the following is not a type of stepper motor?
A) Variable Reluctance
2 B) Hybrid L2
C) Magnetic
D) Lead-Screw
To detect that in which column, the key is placed?
A) we can mask the bits and then check it
B) we can rotate the bits and then check that particular bit which is set or
3 L2
reset(according to the particular condition)
C) none of the mentioned
D) all of the mentioned
How many rows and columns are present in a 16*2 alphanumeric LCD?
A) rows=2, columns=32
4 B) rows=16, columns=2 L1
C) rows=16, columns=16
D) rows=2, columns=16
What are DPDT relays?
A) Single pole, single throw
5 B) Single pole, double throw L2
C) Double pole, double throw
D) None of the mentioned
Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is
being pressed?
6 L1
A) masking of bits
Prepared By: R.Chitra AP/EEE Page 1 of 6
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
B) ensuring that initially, all keys are open
C) checking that whether the key is actually pressed or not
D) all of the mentioned
What are optoisolators? L2
A) it is a driver
7 B) it is a thing isolated from the entire world
C) it is a device that can be used as an electromagnetic relay without a driver
D) none of the mentioned
How can we control the speed of a stepper motor? L1
A) by controlling its switching rate
8 B) by controlling its torque
C) by controlling its wave drive 4 step sequence
D) cannot be controlled
Which of the following can be a unit for torque? L3
A) kg/m2
9 B) ounce-inch
C) kg-m3
D) g/m
What is described by the following command? L2
KCODE0<<1
A) load KCODE0 with 0
10
B) rotate the contents of the KCODE0 register to the right
C) rotate the contents of the KCODE0 register to the left
D) none of the mentioned
If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of L1
what type?
A) External hardware interrupt
11
B) Timer interrupt
C) TI/RI interrupt
D) None of the mentioned
Prepared By: R.Chitra AP/EEE Page 2 of 6
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
To see if any key is pressed, all rows are grounded.
12 A) True L1
B) False
Which pin of the LCD is used for adjusting its contrast?
A) pin no 1
13 B) pin no 2 L2
C) pin no 3
D) pin no 4
In reading the columns of a matrix, if no key is pressed we should get all in binary notation
A) 0
14 B) 1 L3
C) F
D) 7
Which of the following is not a component of a stepper motor?
A) Windings
B) Rotor and Stator
15 L1
C) Commutator
D) Brush
E) Both C and D
What will happen if the two keys of the keyboard are pressed at a time?
A) both the keys will be displayed on the screen
B) the key which is being actually pressed(for more then 20microseconds) will be
16 L3
displayed
C) the key that is pressed first will be displayed
D) none of the mentioned
To identify that which key is being pressed, we need to:
A) ground all the pins of the port at a time
17 B) ground pins of the port one at a time L2
C) connect all the pins of the port to the main supply at a time
D) none of the mentioned
Prepared By: R.Chitra AP/EEE Page 3 of 6
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
Key press detection and Key identification are:
A) the same processes
18 B) two different works are done in Keyboard Interfacing L1
C) none of the mentioned
D) any of the mentioned
What is the difference between full-step and half-step?
A) In full-step two phases are on and in half-step only one phase is on.
19 B) More resonance is evident in half-step L2
C) More power required for full-step
D) Half-step offers better resolution
Why initially all keys are considered open before detecting the key pressed?
A) to make the task easy
20 B) to remove the errors caused by other pressing keys during detection L1
C) to remove the flow problems
D) none of the mentioned
Which of the following step/s is/are correct to perform reading operation from an LCD?
A) low to high pulse at E pin
21 B) R/W pin is set high L2
C) low to high pulse at E pin & R/W pin is set high
D) none of the mentioned
What criteria’s are necessary to consider when selecting a stepper motor?
A) Mechanical Motion.
22 B) Inertial Load L1
C) Speed Requirements
D) All of the above
Which command of an LCD is used to shift the entire display to the right?
A) 0x1C
23 B) 0x18 L1
C) 0x05
D) 0x07
Prepared By: R.Chitra AP/EEE Page 4 of 6
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
Which of the following is NOT an advantage of stepper motors?
A) Cost-efficient
24 B) Maintenance-free L1
C) No feedback
D) More complex circuitry
Which commands are used for addressing the off-chip data and associated codes
respectively by data pointer?
A) MOVX & MOVC
25 L2
B) MOVY & MOVB
C) MOVZ & MOVA
D) MOVC & MOVY
Which mode of timer 2 allow to hold the reload values with an assistance of RCAP2H &
RCAP2L register pair?
A) 8 bit auto-reload mode
26 L2
B) 16 bit auto reload mode
C) 8 bit capture mode
D) 16 bit capture mode
What is the required baud rate for an efficient operation of serial port devices in 8051
microcontroller?
A) 1200
26 L1
B) 2400
C) 4800
D) 9600
Which value of disc capacitors is preferred or recommended especially when the quartz
crystal is connected externally in an oscillator circuit of 8051?
L2
A) 10 pF
27
B) 20 pF
C) 30 pF
D) 40 pF
28 Why are the resonators not preferred for an oscillator circuit of 8051?
L1
A) Because they do not avail for 12 MHz higher order frequencies
Prepared By: R.Chitra AP/EEE Page 5 of 6
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY, THENI.
Course/Branch : BE / EEE Year / Semester : III / V Format
NAC/TLP-07a.13
No.
Subject Name :Microprocessors and
Subject Code :EE8551 Rev. No. 02
Microcontrollers
Unit No : 05 Unit Name : Micro Controller Programming & Date 30.09.2020
Applications
OBJECTIVE TYPE QUESTION BANK
B) Because they are unstable as compared to quartz crystals
C) Because cost reduction due to its utility is almost negligible in comparison to total
cost of microcontroller board
D) All of the above
The 8051 microcontroller is of ___pin package as a ______ processor.
A) 30, 1byte
29 B) 20, 1 byte L2
C) 40, 8 bit
D) 40, 8 byte
What is the constant activation rate of ALE that is optimized periodically in terms of an
oscillator frequency?
A) 1/8
30 B) 1/6 L1
C) 1/4
D) 1/2
Prepared By: R.Chitra AP/EEE Page 6 of 6
Correct
Sr.No. Question Option 1 Option 2 Option 3 Option 4
option
The physical quantity is converted to electrical signal
1 Transducer Transmitter Resistance Thermistor A
using a device called as _______________.
We need ______________ to convert voltage/ current
2 Transducer DAC Resistance ADC D
from transducers into digital numbers.
_______________ is defined as the time taken by the ADC
Resolution Conversion Transmissio Transfer
3 to convert voltage/ current into digital numbers B
Time Time n time Time
Vref
Only
Only (Reference
4 .__________ is/are used to calculate the step size. Vref(Referen Conversion D
Resolution Voltage) and
ce Voltage) Time
Resolution
For 8-bit ADC, if the Vref=3 Volts and input voltage
5 19.53 15.62 11.71 10 C
Vin=3.40 Volts, then the step size will be_________.
For 10-bit ADC, if the Vref=5 Volts and input voltage
6 4.88 1.25 2.5 4 A
Vin=4.40 Volts, the step size is_________.
For 8- bit ADC, we have Vref=5V. Calculate the output
7 if the input voltage Vin = 3V output produced will be 10011001B 10101010B 10111010 B 11010010 B A
_____
End of A/D
A/D D/A
In ADC once the Analog to Digital conversion is Conversion Interrupt
8 Interrupt Interrupt B
complete, ________ is set. Interrupt enable
flag (ADIF) Flag(DAIF)
Flag (EOCIF) (ADIE) Flag
End of A/D
A/D D/A
To use Analog to Digital conversion using interrupt Conversion interrupt
9 interrupt interrupt D
method, ____ flag must be set . interrupt(EO enable Flag
Flag (ADIF) Flag(DAIF)
CIF) (ADIE)
10 The resolution of 10 bit ADC is___ 562 625 1024 265 C
Number of SFRs associated with ADC operation of
11 2 3 4 5 D
PIC18 are_______
Current or
12 The output of DAC0808 is __________. Current Voltage Digital A
voltage
Light
13 LM34 and LM35 are ____________ sensors. Pressure Flow D
intensity Temperature
The LM35 temperature sensors provides
14 _____________mV for each degree celsius of 10 15 20 25 A
temperature.
The LM34 temperature sensors provides
15 10, Celsius 10,Fahrenhe 15,Celsius 20,Celsius B
_____________mV for each degree of _______temperature
it
In case of EEPROM, _____________register is used as
16 EEADR EEDATA EECON1 EECON2 A
pointer to EEPROM locations.
In case of EEPROM, _____________register is used to
17 EEADR EEDATA EECON1 EECON2 B
hold the data to be written in EEPROM.
In case of EEPROM, EEADR register is _______ bits
18 8 12 16 24 A
wide.
The onchip ADC of PIC18Fxx produces ___________ bit
19 4 10 16 24 B
output
ADC notifies the microcontroller analog input Vin Data
End of
20 conversion to digital output is complete by using Data ready Data Output conversion A
Conversion
______________Signal. Complete
Voltage
In PIC18’s ADC __________ register is used to select the A/D Control A/D Control Control
21 Selector A
Vref voltage. Register1 Register0 Register
Register
A/D Control
Register1 Clock
In A/D Conversion ___________ register(s) is used to set A/D Control A/D Control
22 and A/D Selector A
the conversion time Register1 Register0
Control Register
Register0
The number of discrete voltages (or current level) in
23 256 16 8 64 A
the output provided by the 8 bit DAC are________
The number of discrete voltages (or current level) in
24 1024 10 100 64 A
the output provided by the 10 bit DAC are________
What will be the value of output Current (Iout), In
25 case of DAC 0808, assume Iref=2mA and for the input 1.594 mA 1.501mA 1.45mA 1mA A
11001100(CCH) ?
The speed of semiconductor memory is in the range of Microsecond
26 picoseconds C
______ s milliseconds nanoseconds
SDO: (Serial
Data Out)
SDI: (Serial SDO: (Serial Chip
27 SPI devices uses _____ pins for data transfer and C
Data In) Data Out) Select(CE)
SDI: (Serial
Data In)
To Transfer/Receive the single byte through the SPI
28 SSPBUF SSPCON1 SSPSTAT SSPCON2 A
module ,byte is placed in ______ register
What will be the value of output Current (Iout), In
29 case of DAC 0808, assume Iref=3mA and for the input 1.594 mA 1.875mA 1.45mA 1mA B
10100000(A0H) ?
Analog channel selection bits of ADC are present in _____
30 ADCON3 ADCON2 ADCON1 ADCON0 D
register
Interrupt Interrupt
____ pin of the DS1306 RTC should be high during Chip SDI (Serial
31 Request Request(INT A
Read and Write Cycle Enable(CE) Data In)
(INT0) 1)
_____________locations of the RAM in the DS1306 are
32 0-6H 1-7H 20-75H 21-76H A
set aside for the clock and date.
Interrupt
Which pin is set high to select DS1306 RTC in SPI Chip SDI (Serial
33 Request SERMODE C
mode? Enable(CE) Data In)
(INT0)
34 The A/D of PIC18F is an ______ bit converter 10 8 12 16 A
LOW on HIGH ON
LOW on G0/ HIGH ON
Which of the following status bit indicate the ADON status ADON status
DOWN GO/DOWN
35 C
end-of-conversion in ADC? bit of bit ofstatus bit of status bit of
ADCON0 ADCON0ADCON0 ADCON0
ADRESL (A/D
Result Low
ADRESL(A/D ADRESH(A/D ADCON0((A/
In A/D of PIC18F after the A/D conversion is complete Byte) AND
36 Result Low Result High D Control C
the result is stored _____________ Register ADRESH (A/
Byte) Byte) Register)
D Result
High Byte)
What will be the value of output Current (Iout), In
37 case of DAC 0808, assume Iref=2mA and for the input Iout=1.5mA Iout=1.25mA Iout=1mA Iout=1.10mA C
1000000(80H) ?
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