2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, Kota

Kinabalu Malaysia

Comparative Study of Comparator and Encoder in a

4-bit Flash ADC using 0.18μm CMOS Technology
Ili Shairah Abdul Halim, Siti Lailatul Mohd Hassan, Nurul Dalila binti Mohd Akbar, A’zraa Afhzan Ab. Rahim
Faculty of Electrical Engineering
Universiti Teknologi MARA
Shah Alam, 40450, Selangor, Malaysia
e-mail: [email protected], [email protected], [email protected], [email protected]

Abstract— This paper describes a comparative study of circuit consists of 2n-1 comparators, a resistive ladder with 2n
comparator and encoder in 4-bit Flash Analog to Digital resistors that provides the reference voltages and a
Converter (ADC) for Pipeline ADC to obtain a high speed ADC. thermometer to binary code encoder as shown in Fig. 2. The
In this paper, the conventional comparator is replaced with an reference voltage for each comparator is one least significant
open loop comparator and the non-ROM type encoder is used as bit (LSB) greater than the reference voltage for the comparator
the alternative for the conventional encoder. It is implemented immediately below it [3].
using 0.18μm CMOS technology. Generally, the Silvaco
Electronic Design Automation (EDA) tools is used for drawing
the schematics, do the simulations and designing the layout of the
proposed Flash ADC. The simulation results include 1.8V analog
input range and 24.2662 mW of power dissipation at maximum
sampling frequency of 500MHz with the lowest propagation
delay time of 539.61ps.

Keywords-Flash ADC, XOR Encoder, Open Loop Comparator

I. INTRODUCTION
Data conversion circuit plays an important role in high-rate
data communications. ADC can be found in almost every
modern mixed-signal integrated circuit. A pipeline ADC is
designed to offer an attractive combination of high speed, high Figure 1. Block diagram of an N-bit Flash ADC
resolution, low power dissipation and small die size. In pipeline
ADC consists of Sample and Hold Circuit (SHC), the Flash B. Comparator
ADC, the Multiplying Digital to Analog Converter (MDAC) For a voltage comparator, it will produce output '1' when
and Digital Error Correction (DEC). The flash architecture is a the analog input voltage is greater than the reference voltage.
converter topology that allows fast data conversion, mainly due On the other hand, when the analog input voltage is less than
to its parallel structure. Since the demand on the speed for the reference voltage, the comparator will produce output '0'. In
digital processing keep increasing which requires higher speed Flash ADC, the 2n-1 comparators contribute the input for the
in analog interface blocks, many alternatives in redesigning the encoder in the form of thermometer code. Comparator is one of
comparator in flash architecture has been done. The Flash ADC the key blocks for high speed operation. When comparators
in [1] is only using 200 MS/s for its sampling rate. Hence, in sample the input signal in parallel, this leads to high power
this paper, in order to increase the speed, some modifications consumption and slower speed as the number of bit is
on the analog and digital part have to be done. For example, in increasing.
[2], a high speed differential clocked comparator circuit is used
where the comparator consists of a preamplifier and a latch 1) Conventional Comparator
followed by a dynamic latch that operates as an output sampler. The conventional comparator as shown in Fig. 3 consists
In this paper, the proposed Flash ADC design used an open of three stages which are an input preamplifier, a latch and an
loop comparator where it has a very minimal number of output buffer. The latch circuit is not suitable for a high
transistor and a XOR encoder to encode the thermometer code resolution. Thus, the preamplifier is needed. The output buffer
into binary code. is needed to amplify the signal coming from the latch and to
provide enough current for the load [4].
II. DESIGN OF FLASH ADC
A. Flash ADC 2) Proposed Comparator(Open Loop Comparator)
Flash ADC is ideal for applications requiring very large This comparator is an open loop comparator and consists
bandwidth; however they typically consume more power than of three stages which are input stage, push-pull inverter and
other ADC architectures. For an n-bit converter as in Fig. 1, the output stage as shown in Fig. 4. The advantage of this circuit

978-1-4673-3033-6/10/$26.00 ©2012 IEEE 35

 2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, Kota
Kinabalu Malaysia

is that the circuit consumes minimal number of transistor and 1) XOR Encoder
thus the circuit area is small [5]. As shown in Fig. 7, the logic function for the encoder is
reformulated to reduce wire crossings and delays in layout. In
Fig. 6, gray code is chosen as an intermediate code to
minimize the effect of the metastability and bubble errors.
XOR gates can be used to replace the AND/NAND gates due
to the special format of the thermometer code itself. For
example, ܶସ and തതതത
ܶଵଶ are proved as shown below:

ܶସ ȉ ܶതതതത തതതത
ଵଶ ൌ ܶସ ܶଵଶ (1)
ܶସ ۩ܶଵଶ ൌ ܶସ ܶଵଶ ൅ ܶഥସ ܶଵଶ
തതതത തതതത (2)

When ܶഥସ is 1, due to the special format of thermometer code,

ܶଵଶ is 0, which means ܶഥସ ܶଵଶ is always 0. The proof for other
gates is similar. Therefore, the encoder can be implemented
only with XOR gates, which improves the reliability of the
encoder. As shown in Fig. 7, extra delay cells are added to
match the delay difference among the signal paths [7].
Figure 2. 4-bit Flash ADC
2) Wallace Tree Encoder
Wallace Tree method can correct higher order bubbles.
The Wallace Tree method is originally used to implement high
speed multipliers in computer arithmetic units is the most
efficient. It has been used with the thermometer code in Flash
ADCs where the number of "1's" is counted (instead of the
0՞1 transition being determined. Due to the tree structure, the
number of cells is doubled and one stage is added for every 1
bit resolution increase. The Wallace Tree is consists of a tree
of full adders as shown in Fig. 8 [8].

Figure 3. Conventional comparator

Figure 6. Digital encoder

Figure 4. Proposed comparator

C. Digital Encoder
After the comparators produce the thermometer code, a
digital encoder is used to convert the thermometer code into
binary code. In this work, there are two types of digital
encoder has been compared, which are XOR encoder and
Wallace Tree encoder. These encoders will be compared based
on their performance in propagation delay time. The best
encoder will be chosen as the proposed encoder when it gives
the smallest propagation delay time.
Figure 7. The encoder implemented in XOR gates

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 2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, Kota
Kinabalu Malaysia

TABLE I. CONVENTIONAL COMPARATOR RESULTS WITH VARIOUS

FREQUENCY
Frequency Tplh (ns) Tphl (ns) Tavg (ns) Power
200MHz 0.23772 4.8949 2.56631 2.94574 mW
500MHz 0.13279 1.9921 1.06245 2.97749 mW

TABLE II. OPEN LOOP COMPARATOR RESULTS WITH VARIOUS

FREQUENCY

Frequency Tplh (ns) Tphl (ns) Tavg (ns) Power

200MHz 0.32272 4.9876 1.32758 2.71906 mW
500MHz 0.21351 0.6669 0.14010 2.76476 mW

Power dissipation in a Flash ADC happens only at the time

when the comparators are working, which is called the
sampling period. Nowadays the demand on the low cost and
low noise comparator is very high. Power dissipation is the
Figure 8. 4-bit of Wallace Tree encoder wasted power in the form of heat, voltage drop. The results of
the power dissipation of proposed and conventional
III. SIMULATION RESULTS AND DISCUSSIONS comparator are shown in table III. As stated in Eq. (3), power
dissipation is directly proportional to the bias current value.
The Flash ADC is designed in 0.18μm CMOS technology Hence, the power will decrease as the current decrease. A
with a 1.8 V supply. A bias current of 1mA is used for all gates minimal current is needed to drive the Flash ADC, therefore
in the comparator circuit.
the bias current should not be too small. It is shown that the
A. Comparator Result proposed comparator has a smaller power dissipation
In Fig. 4, a proposed comparator circuit is shown. The compared to the conventional comparator. Hence, in this
frequency of the analog signal input is varied in the way that paper, the proposed Flash ADC will choose 1mA for the bias
the minimal propagation time delay is obtained. For the current.
functionality purpose as shown in Fig. 9a, the reference
voltage, Vref is set to 0.9V and the supply voltage is 1.8V. As P = Vdd x Idd (3)
illustrated in Fig. 9b, if the input voltage is higher than 0.9V,
TABLE III. POWER DISSIPATION OF CONVENTIONAL AND PROPOSED
the output of comparator is high and vice versa. COMPARATOR WITH TWO DIFFERENT BIAS CURRENT
Conventional Proposed
Current 1 mA 5 mA 1 mA 5 mA
Power 2.97749 10.3251 2.76476 10.1062
dissipation mW mW mW mW

a)
B. Encoder Result
As the digital part, the speed of the encoder also plays an
important role in the Flash ADC. In this paper, two types of
encoder have been tested which are, XOR encoder and
b) Wallace Tree encoder. All the results of the propagation delay
Figure 9. Output of comparator time and the power dissipation have been summarized in table
IV and as the conclusion; the XOR encoder gives the smallest
Simulation results for the conventional and proposed power dissipation and the lowest propagation delay time (Tp).
comparator at several frequencies are summarized in table I Thus, XOR encoder is used as the proposed encoder in order
and II respectively. As shown in both table, power dissipation to contribute a higher speed in Flash ADC circuit.
of a comparator is increased proportional to the frequency.
Generally by increasing the frequency, the delay of the TABLE IV. COMPARISON BETWEEN 3 TYPES ENCODER
comparator will be decreased and thus the comparator will XOR Encoder Wallace Tree
have a higher speed. Encoder
Power 1.23248mW 1.47870mW
By comparing between the conventional and the proposed Tplh 1.694ns 2.492ns
comparator, it is proved that the proposed comparator which Tphl 49.556 ns 52.166ns
Tavg 25.625ns 27.329ns
has a smaller feature size is chosen as the component in the
Flash ADC because it results a smaller propagation delay time C. Comparison With Previous Work
and thus has a higher speed. Fig. 10a shows the analog input signal where the input
range is 1.8V. Fig. 10b, Fig. 10c, Fig. 10d and Fig. 10e show

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 2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, Kota
Kinabalu Malaysia

the outputs of the Flash ADC where it starts with the most and the present work. The comparison of the results is shown
significant bit (MSB), bit 3 and followed by the least in the table VI. As the conclusion, the proposed method can
significant bit (LSB), bit 0 respectively. Table V shows the increase up until 500MHz of sampling frequency in the
simulation results for 4-bit proposed Flash ADC. proposed Flash ADC in 1.8V power supply. For future
development, 90 nm technology can be apply to this design to
TABLE V. 500 MHZ 4-BIT PROPOSED FLASH ADC obtained a higher speed with a lower power.
Proposed Flash ADC
Technology 0.18 μm
Power Supply 1.8 V
Temperature 27 ÛC
Power Dissipation 24.2662 mW
Tphl 778.59 ps
Tplh 300.63 ps
Tp 539.61 ps

a)

b)

Figure 11. Layout of proposed 4-bit Flash ADC

c) ACKNOWLEDGMENT
The author would like to acknowledge with gratitude,
UiTM Research Management Institute and Faculty of
d) Electrical Engineering, UiTM for supporting this work under
Excellent Fund (Research Intensive Faculty) code 80/2012.
REFERENCES
e) [1] Sudakar S. Chauhan, S. Manabala, S.C. Bose, and R. Chandel, "A New
Approach To Design Low Power CMOS Flash A/D Converter",
Figure 10. Simulation results for the 4-bit proposed Flash ADC International Journal of VLSI design & Communication Systems
(VLSICS), Vol.2, No.2, June 2011, p.100.
TABLE VI. COMPARISON WITH PREVIOUS WORK [2] Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov, "A 0.35ȝm
Previous Work [1] Present Work CMOS Comparator Circuit For High-Speed ADC Applications" Circuits
Power Supply 3.3 V 1.8V and Systems, 2005. ISCAS 2005. IEEE International Symposium on,
Vol. 6, p. 6134-6137
Technology 0.35 μm 0.18 μm
Resolution 4-bit 4-bit [3] Pradeep Kumar, Amit Kolhe, "Design & Implementation of Low Power
Speed 200 MS/s 500 MS/s 3-bit Flash ADC in 0.18ȝm CMOS", International Journal of Soft
Power Dissipation 12.4 mW 24.2662 mW Computing and Engineering (IJSCE), ISSN: 2231-2307, Volume-1,
Issue-5, November 2011.
IV. LAYOUT OF THE FLASH ADC [4] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design,
Oxford University Press, Inc. 2002.
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It includes a resistive ladder with 16 resistors, 15 comparators And Simulation, New York, IEEE Press, 2008.
and a thermometer code to binary encoder. On the left side of [6] Meghana Kulkarni, V. Sridhar, G.H.Kulkarni, "The Quantized
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digital part. The area of the layout design is 182.575μm x International Journal of Computer Networks & Communications
(IJCNC), Vol.2, No.4, July 2010.
295.5053μm.
[7] Lianhong Wu, Fengyi Huang, Yang Gao, Yan Wang , Jia Cheng, "A 42
V. CONCLUSION mW 2 GS/s 4-bit flash ADC in 0.18-ȝm CMOS", 2009, International
Conference on Wireless Communication and Signal Processing, WCSP,
High speed architecture for a 4-bit Flash ADC is presented 2009, p. 1-5.
using 0.18μm CMOS Technology. The proposed Flash ADC [8] Paula Pereira, Jorge R. Fernandes, and Manuel M. Silva,"Wallace Tree
can achieve a higher speed compared to the previous work [1]. Encoding In Folding And Interpolation ADCs", IEEE International
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Author has compared the results between the previous work 509-I-512.

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