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DLD (Assignment 2)

The document contains the solutions to 4 questions regarding digital logic circuits. It includes Verilog and VHDL code for: 1) A circuit that outputs HIGH if the 4-bit input is >12 or <3. 2) A circuit with two switches that controls a lamp. 3) A 5-bit odd parity generator for a 4-bit input. 4) A 6-bit subtractor circuit that subtracts two 6-bit numbers.

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Hamna Sajjad
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73 views12 pages

DLD (Assignment 2)

The document contains the solutions to 4 questions regarding digital logic circuits. It includes Verilog and VHDL code for: 1) A circuit that outputs HIGH if the 4-bit input is >12 or <3. 2) A circuit with two switches that controls a lamp. 3) A 5-bit odd parity generator for a 4-bit input. 4) A 6-bit subtractor circuit that subtracts two 6-bit numbers.

Uploaded by

Hamna Sajjad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ASSIGNMENT 2

NAME: Hamna Sajjad

ROLL NO.: EL-19004

CLASS: SE-EL (section A)

SUBJECT: Digital Logic Circuit

COURSE CODE: TC-201


QUESTION: 01
Write the Verilog code for a circuit the produce a HIGH output only if the input, represented by
a 4-bit binary number, is greater than twelve or less than three. [CLO-02]

VERILOG CODE:
module NumberDetector (Sum, a, b, c, d)

output Sum;

input a, b, c, d;

assign Sum={(a&&b&&c&&d)||(a&&b&&c&&!d)||(a&&b&&!c&&d)||(!a&&!b&&c&&!d)
||(!a&&!b&&!c&&d)||(!a&&!b&&!c&&!d)}

end module
CIRCUIT:

a
b
c
d

Sum

SIMULATION:

d
Sum
QUESTION: 02
Write the Verilog code for logic circuit that meet the following requirements:

A battery-powered lamp in a room is to be operated from two switches, one at the back door
and one at the front door. The lamp is to be on if the front switch is on and the back switch is
off, or if the front switch is off and the back switch is on. The lamp is to be off if both switches
are off or if both switches are on. Let a HIGH output represent the on condition and a LOW
output represent the off condition. [CLO 2]

VERILOG CODE:
module Switch (X, A, B)

output X;

input A, B;

assign X = {(A&&!B)||(!A&&B)}

end module

CIRCUIT:

A
B X
SIMULATION:

B
X

QUESTION: 03
Parity bits are often used in digital communication for error detection and correction. The
simplest of these involve transmitting one additional bit with the data, a parity bit. In these
system the parity bit is attached to a group of transmitting bits to make the total number of 1s
in a group always even or always odd. An even parity bit makes number of 1s even and odd
parity bit makes the total number of 1s odd. Write the VHDL for parity generator that generates
a 5 bit odd parity generation for a 4 bit input number/group. [CLO 2]

VHDL CODE:
entity Parity_generator is
port(B1, B2, B3, B4: in bit;
P : out bit);
end Parity_generator;

architecture logic_circuit of Parity_generator is


begin
P <= (B1 or B2 or B3 or(not B4)) and (B1 or B2 or (not B3) or B4) and
(B1 or (not B2) or B3 or B4) and (B1 or (not B2) or (not B3) or (not B4)) and
((not B1) or B2 or B3 or B4) and ((not B1) or B2 or (not B3) or (not B4)) and
((not B1) or (not B2) or B3 or (not B4)) and ((not B1) or (not B2) or (not B3) or B4);
end logic_circuit;
CIRCUIT:

SIMULATION:
QUESTION: 04
Write the Verilog code for 6 bit subtractor i.e.
S(6bit) = A(6bit) – B(6bit)
Where,
A,B is a 6 bit signed number

VERILOG CODE:
(PART 01)

module FullAdder(S, Co, A, B, Ci);


output S, Co;
input A, B, Ci;
wire Abar, Bbar, Cibar, x1, x2, x3, x4, x5, x6, x7, x8;
not(Abar, A);
not(Bbar, B);
not(Cibar, Ci);
and(x1, Abar, Bbar, Ci);
and(x2, Abar, B, Cibar);
and(x3, A, Bbar, Cibar);
and(x4, A, B, Ci);
and(x5, Abar, B, Ci);
and(x6, A, Bbar, Ci);
and(x7, A, B, Cibar);
and(x8, A, B, Ci);
or(S, x1, x2, x3, x4);
or(Co, x5, x6, x7, x8);
end module
CIRCUIT:

SIMULATION:
VERILOG CODE:
(PART 02)

module AdderBit6(S, Co, A, B, Ci);

output [5:0]S;

output Co;

input [5:0]A, B;

input Ci;

wire [4:0]x;

FullAdder FA0(S[0], x[0], A[0], B[0], Ci);

FullAdder FA1(S[1], x[1], A[1], B[1], x[0]);

FullAdder FA2(S[2], x[2], A[2], B[2], x[1]);

FullAdder FA3(S[3], x[3], A[3], B[3], x[2]);

FullAdder FA4(S[4], x[4], A[4], B[4], x[3]);

FullAdder FA5(S[5], Co, A[5], B[5], x[4]);

end module

CIRCUIT:
SIMULATION:

VERILOG CODE:
(PART 03)

module Bit_6_Subtractor(S, Co, A, B, Ci);

output [5:0]S;

output Co;

input [5:0]A, B;

input Ci;

wire [5:0]X;

xor(X[0],B[0],Ci);

xor(X[1],B[1],Ci);

xor(X[2],B[2],Ci);

xor(X[3],B[3],Ci);

xor(X[4],B[4],Ci);

xor(X[5],B[5],Ci);

AdderBit6(S, Co, A, X, Ci);

end module
CIRCUIT:

SIMULATION:

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