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Topics To Prepare & Sample Questions

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32 views3 pages

Topics To Prepare & Sample Questions

Uploaded by

meghna v
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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TOPICS TO PREPARE

1. Digital Design
▪ Basic fundamentals, Flip-flop, Latches, Gates etc.
▪ Clocks, Generated Clocks, Clock Multiplication/ Division etc
▪ Timers, FIFO, LIFO, etc
▪ Counters, ADDERs etc.
▪ ECC, CRC
▪ TRUTH Table, FSM, K – Map

2. Computer Architecture
▪ Basic fundamentals, Branch Prediction, Processor Performance etc.
▪ Pipeline, parallelism etc.
▪ Instruction level/ Instruction set
▪ Caches/Cache types/ Cache Coherence/ Cache Management
▪ RISC/ CISC
▪ X86 architecture
▪ Translation Lookaside buffer, ALU
▪ Assembly language

3. C/ C++
▪ Basic fundamentals & Syntax
▪ Programming

4. Verilog
▪ Basic fundamentals & Syntax,
▪ Programming
▪ FSM

5. Analytical/Aptitude/Logical Skills

Note: This will provide insights to take up the test, but not limited to the topics
mentioned above.
Sample Questions
Note:
- These questions will only provide an insights and guidance for the test preparations.
- Please work on the concepts of these questions to crack the written test.

Verilog:

1. Draw table for Gray code and Binary code and explain how gray coding helps to
reduce power dissipation for fetching instructions from the main memory.

2. Design of the 11011 Sequence Detector. Its output goes to 1 when a target
sequence has been detected

Digital Design:

1. What is the difference between blocking and Non-blocking assignment ?

2. How do you design and verify a 16 entry 64-bit wide FIFO.

3. Design a FSM that implements the following functionality. State the assumptions
made, if any.
- Detect a sequence of “101101” in the serial input data. Set an output
signal when the sequence is detected and ignore any further input data. Keep the
output set till a clr input is asserted.
- The above logic must be enabled only when an enable input is asserted.
If the enable is deasserted midway through the sequence, the on-going sequence
must be aborted.

Logical:

1. Simplify the following expression using K-map


A’B’C’D’ + AB’C’D’ + A’BC’D + A’BCD + ABC’D + ABCD + A’B’CD’ + AB’CD’

2. Which number does not fit in the given series. What should this be replaced with
1 4 3 16 6 36 7 64 9 100

3. There is a building of 100 floors


- If an egg drops from the Nth floor or above it will break
- If it’s dropped from any floor below, it will not break
You’re given 2 eggs. Find the floor N where the egg does not break with least number of
tries.

4. Two trains of equal length are running on parallel lines in the same direction at
46km/hr and 36 km/hr. The faster train passes the slower train in 36 seconds.
Calculate the length of each train.
Computer Architecture:

1. Assume two address signals A[] and B[] each 32-bits wide. Design a logic circuit
whose output will be asserted when A and B have values within the same
64Kbyte address region. State any assumptions made.

2. What are various pipeline hazards in computer architecture? Elaborate with


examples

3. Find different register dependences that exist in the following instructions. In


each Instruction the first register is the destination and the others are sources.

Inst 1: Add R1,R2,R3


Inst 2: Mul R4,R1,R2
Inst 3: Add R4,R3,R5
Inst 4: Sub R3,R1,R4

C/C++ Programming:

1. Write a program to check whether the number is palindrome or not by not using
recursive function

2. Write a program to create a doubly linked list of integers. Write a function to


delete a given integer from that list.

3. Write a C/C++ program to input the number of terms needed for Fibonacci series
(0,1,1,2,3,5,8,13,21...) and print the required terms of the series.

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