TPS79601, TPS79618, TPS79625

TPS79628, TPS79630, TPS79633

www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A

LOW-DROPOUT LINEAR REGULATORS

FEATURES DESCRIPTION
• 1-A Low-Dropout Regulator With Enable The TPS796xx family of low-dropout (LDO)
• Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and low-power linear voltage regulators features high
Adjustable (1.2-V to 5.5-V) power supply rejection ratio (PSRR), ultralow-noise,
fast start-up, and excellent line and load transient
• High PSRR (53 dB at 10 kHz)
responses in small outline, 3 x 3 SON, SOT223-6,
• Ultralow-Noise (40 µVRMS, TPS79630) and 5-pin DDPAK packages. Each device in the
• Fast Start-Up Time (50 µs) family is stable with a small 1-µF ceramic capacitor
• Stable With a 1-µF Ceramic Capacitor on the output. The family uses an advanced, pro-
prietary BiCMOS fabrication process to yield ex-
• Excellent Load/Line Transient Response tremely low dropout voltages (e.g., 250 mV at 1 A).
• Very Low Dropout Voltage (250 mV at Full Each device achieves fast start-up times
Load, TPS79630) (approximately 50 µs with a 0.001-µF bypass capaci-
• 3 x 3 SON, 6-Pin SOT223-6, and tor) while consuming very low quiescent current
(265 µA typical). Moreover, when the device is placed
5-Pin DDPAK Packages
in standby mode, the supply current is reduced to
less than 1 µA. The TPS79630 exhibits approximately
APPLICATIONS 40 µVRMS of output voltage noise at 3.0-V output, with
• RF: VCOs, Receivers, ADCs a 0.1-µF bypass capacitor. Applications with analog
• Audio components that are noise sensitive, such as portable
• Bluetooth™, Wireless LAN RF electronics, benefit from the high PSRR, low
noise features, and the fast response time.
• Cellular and Cordless Telephones
• Handheld Organizers, PDAs
DCQ PACKAGE DRB PACKAGE TPS79630 TPS79630
SOT223-6 3 x 3 SON RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITY
(TOP VIEW) (TOP VIEW)
vs vs
EN 1 IN 1 8 EN FREQUENCY FREQUENCY
IN 2 IN 2 7 NC 80 0.7
6
GND 3 OUT 3 6 GND VIN = 4 V VIN = 5.5 V
Output Spectral Noise Density − µV/
Hz

GND 70 COUT = 10 µF 0.6 COUT = 2.2 µF

OUT 4 OUT 4 5 NR
IOUT = 1 mA CNR = 0.01 µF CNR = 0.1 µF
NR/FB 5 60
0.5
Ripple Rejection − dB

50
IOUT = 1 A 0.4
40
KTT (DDPAK) PACKAGE
0.3
(TOP VIEW) 30 IOUT = 1 mA
0.2
EN 1 20
IN 2 0.1
10
GND 3 IOUT = 1.5 A
OUT 0 0.0
4
NR/FB 1 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k
5
Frequency (Hz) Frequency (Hz)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

AVAILABLE OPTIONS (1)

TRANSPORT
PRODUCT VOLTAGE PACKAGE TJ SYMBOL PART NUMBER
MEDIA, QUANTITY
TPS79601DCQ Tube, 78
SOT223-6 PS79601
TPS79601DCQR Tape and Reel, 2500
TPS79601 1.2 to 5.5 V
TPS79601KTTT Reel, 50
DDPAK TPS79601
TPS79601KTTR Reel, 500
TPS79618DCQ Tube, 78
SOT223-6 PS79618
TPS79618DCQR Tape and Reel, 2500
TPS79618 1.8 V
TPS79618KTTT Reel, 50
DDPAK TPS79618
TPS79618KTTR Reel, 500
TPS79625DCQ Tube, 78
SOT223-6 PS79625
TPS79625DCQR Tape and Reel, 2500
TPS79625 2.5 V
TPS79625KTTT Reel, 50
DDPAK TPS79625
TPS79625KTTR Reel, 500
TPS79628DCQ Tube, 78
SOT223-6 PS79628
TPS79628DCQR Tape and Reel, 2500
-40°C to +125°C
TPS79628KTTT Reel, 50
DDPAK TPS79628
TPS79628KTTR Reel, 500
TPS79628 2.8 V
TPS79628DRB Tube, 78
TPS79628DRBR Tape and Reel, 2500
3 x 3 SON AMI
TPS79628DRBG4 Tube, 78
TPS79628DRBG4R Tape and Reel, 2500
TPS79630DCQ Tube, 78
SOT223-6 PS79630
TPS79630DCQR Tape and Reel, 2500
TPS79630 3V
TPS79630KTTT Reel, 50
DDPAK TPS79630
TPS79630KTTR Reel, 500
TPS79633DCQ Tube, 78
SOT223-6 PS79633
TPS79633DCQR Tape and Reel, 2500
TPS79633 3.3 V
TPS79633KTTT Reel, 50
DDPAK TPS79633
TPS79633KTTR Reel, 500

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.

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 TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
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SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating temperature range (unless otherwise noted) (1)
UNIT
VIN range -0.3 V to 6 V
VEN range -0.3 V to VIN + 0.3 V
VOUT range 6V
Peak output current Internally limited
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, TJ -40°C to 150°C
Storage temperature range, Tstg -65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE DISSIPATION RATINGS

PACKAGE BOARD RΘJC RΘJA
DDPAK High-K (1) 2 °C/W 23 °C/W
SOT223 Low-K (2) 15 °C/W 53 °C/W
3 x 3 SON 56.2 °C/W

(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.

3
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS
over recommended operating temperature range (TJ = -40 to 125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,
COUT = 10 µF, CNR = 0.01 µF (unless otherwise noted). Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage (1) 2.7 5.5 V
IOUT Continuous output current (1) 0 1 A
TPS79618 0 µA < IOUT < 1 A 2.8 V < VIN < 5.5 V 1.764 1.8 1.836 V
TPS79625 0 µA < IOUT < 1 A 3.5 V < VIN < 5.5 V 2.45 2.5 2.55
Output voltage TPS79628 0 µA < IOUT < 1 A 3.8 V < VIN < 5.5 V 2.744 2.8 2.856
V
TPS79630 0 µA < IOUT < 1 A 4 V < VIN < 5.5 V 2.94 3.0 3.06
TPS79633 0 µA < IOUT < 1 A 4.3 V < VIN < 5.5 V 3.234 3.3 3.366
Output voltage line regulation (∆VOUT%/VIN) (1) VOUT + 1 V < VIN ≤ 5.5 V 0.05 0.12 %/V
Load regulation (∆VOUT%/∆IOUT) 0 µA < IOUT < 1 A TJ = 25°C 5 mV
IOUT = 1 A 270 365
TPS79628
Dropout voltage (2) IOUT = 250 mA 67 90
mV
(VIN = VOUT (nom) - 0.1V) TPS79630 IOUT = 1 A 250 345
TPS79633 IOUT = 1 A 220 325
Output current limit VOUT = 0 V 2.4 4.2 A
Ground pin current 0 µA < IOUT < 1 A 265 385 µA
Shutdown current (3) VEN = 0 V, 2.7 V < VIN < 5.5 V 0.07 1 µA
FB pin current FB = 1.8 V 1 µA
f = 100 Hz IOUT = 10 mA 59
f = 100 Hz IOUT = 1 A 54
Power-supply ripple rejection TPS79630 dB
f = 10 Hz IOUT = 1 A 53
f = 100 Hz IOUT = 1 A 42
CNR = 0.001 µF 54
BW = 100 Hz to 100 kHz, CNR = 0.0047 µF 46
Output noise voltage (TPS79630) µVRMS
IOUT = 1 A CNR = 0.01 µF 41
CNR = 0.1 µF 40
CNR = 0.001 µF 50
Time, start-up (TPS79630) RL = 3 Ω, COUT = 1 µF CNR = 0.0047 µF 75 µs
CNR = 0.01 µF 110
EN pin current VEN = 0V -1 1 µA
High-level enable input voltage 2.7 V < VIN < 5.5 V 1.7 VIN V
Low-level enable input voltage 2.7 V < VIN < 5.5 V 0 0.7 V

(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.

(2) VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V.
(3) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.

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 TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION

IN OUT

UVLO Current
Sense
ILIM SHUTDOWN
R1
GND _ +
FB
EN UVLO
R2
Thermal
Shutdown
Quickstart External to
the Device
Bandgap
250 kΩ VREF
Reference
VIN
1.225 V

FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION

IN OUT

UVLO Current
Sense
GND SHUTDOWN
ILIM
R1
_ +
EN
UVLO

Thermal R2
Shutdown
Quickstart
R2 = 40k
Bandgap
Reference 250 kΩ VREF
VIN NR
1.225 V

Table 1. Terminal Functions

TERMINAL
DESCRIPTION
NAME ADJ FIXED
NR N/A 5 Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improves
power-supply rejection and reduces output noise.
EN 1 1 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
FB 5 N/A This terminal is the feedback input voltage for the adjustable device.
GND 3, Tab 3, Tab Regulator ground
IN 2 2 Unregulated input to the device.
OUT 4 4 Output of the regulator.

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TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

TPS79630 TPS79628 TPS79628

OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
3.05 2.795
4 350
VIN = 4 V VIN = 3.8 V VIN = 3.8 V
3.04
COUT = 10 µF COUT = 10 µF COUT = 10 µF
340
3.03 TJ = 25°C IOUT = 1 mA
3
2.790
3.02
330
3.01

IGND (µA)
3.00 2
2.785 320

VOUT (V)
VOUT (V)

IOUT = 1 A IOUT = 1 A
2.99
310
2.98
1
2.780 IOUT = 1 mA
2.97
300
2.96

2.95 0
2.775 290
0.0 0.2 0.4 0.6 0.8 1.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
IOUT (A) TJ (°C) TJ (°C)

Figure 1. Figure 2. Figure 3.

TPS79630 TPS79630 TPS79630

OUTPUT SPECTRAL NOISE DEN- OUTPUT SPECTRAL NOISE DEN- OUTPUT SPECTRAL NOISE DEN-
SITY SITY SITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
0.7 0.6 2.5
Output Spectral Noise Density − µV/
Hz

Output Spectral Noise Density − µV/
Hz

VIN = 5.5 V VIN = 5.5 V VIN = 5.5 V
Output Spectral Noise Density − µV/
Hz

0.6 COUT = 2.2 µF COUT = 10 µF COUT = 10 µF

0.5
CNR = 0.1 µF CNR = 0.1 µF 2.0 CNR = 0.01 µF IOUT = 1 A
0.5
0.4
1.5 CNR = 0.1 µF
0.4
IOUT = 1 mA
0.3
0.3 CNR = 0.0047 µF
1.0
IOUT = 1 mA
0.2
0.2 CNR = 0.001 µF
IOUT = 1 A 0.5
0.1 0.1
IOUT = 1.5 A
0.0 0.0 0.0
100 1k 10k 100k 100 1k 10k 100k 100 1k 10k 100k
Frequency (Hz) Frequency (Hz) Frequency (Hz)

Figure 4. Figure 5. Figure 6.

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 TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS (continued)

TPS79630
ROOT MEAN SQUARED OUTPUT TPS79628 TPS79630
NOISE DROPOUT VOLTAGE RIPPLE REJECTION
vs vs vs
BYPASS CAPACITANCE JUNCTION TEMPERATURE FREQUENCY
60 350 80
RMS − Root Mean Squared Output Noise − µVRMS

VIN = 2.7 V VIN = 4 V

300 COUT = 10 µF 70 COUT = 10 µF
50
IOUT = 1 A IOUT = 1 mA CNR = 0.01 µF
60
250

Ripple Rejection − dB
40
50 IOUT = 1 A

VDO (mV)
200
30 40
150
30
20
100
20
IOUT = 250 mA
10
COUT = 10 µF 50 10
BW = 100 Hz to 100 kHz
0 0 0
0.001 µF 0.0047 µF 0.01 µF 0.1 µF −40 −25 −10 5 20 35 50 65 80 95 110 125 1 10 100 1k 10k 100k 1M 10M
CNR (µF) TJ (°C) Frequency (Hz)

Figure 7. Figure 8. Figure 9.

TPS79630 TPS79630
RIPPLE REJECTION RIPPLE REJECTION
vs vs
FREQUENCY FREQUENCY START-UP TIME
80 80 3
VIN = 4 V VIN = 4 V 2.75 VIN = 4 V,
70 COUT = 10 µF 70 COUT = 2.2 µF COUT = 10 µF, CNR =
2.50 0.0047 µF
IOUT = 1 mA CNR = 0.1 µF IOUT = 1 mA CNR = 0.01 µF IOUT = 1.0 A
Ripple Rejection − dB

60 60 2.25
Ripple Rejection − dB

CNR = Enable
2
50 50 0.001 µF
IOUT = 1 A IOUT = 1 A 1.75
VOUT (V)

40 40 1.50 CNR =
1.25 0.01 µF
30 30
1
20 20 0.75
0.50
10 10
0.25
0 0 0
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600
Frequency (Hz) Frequency (Hz) t (ns)

Figure 10. Figure 11. Figure 12.

TPS79618 TPS79630 TPS79628

LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
5 6 2

4 5 1
IOUT (A)
VIN (V)

VIN (V)

3 4 0

2 IOUT = 1 A dv 1V 3 IOUT = 1 A dv 1V −1 VIN = 3.8 V di 1A

COUT = 10 µF COUT = 10 µF




COUT = 10 µF dt
s dt
s dt
s
40 CNR = 0.01 µF 40 CNR = 0.01 µF 150 CNR = 0.01 µF
∆VOUT (mV)

20 20 75
∆VOUT (mV)

∆VOUT (mV)

0 0 0

−20 −20 −75

−40 −40 −150

0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600 700 800 900 1000
t (µs) t (µs) t (µs)

Figure 13. Figure 14. Figure 15.

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TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS (continued)

TPS79630 TPS79601
DROPOUT VOLTAGE DROPOUT VOLTAGE
TPS79625 vs vs
POWER UP/POWER DOWN OUTPUT CURRENT INPUT VOLTAGE
4.0 350 300
VOUT = 2.5 V
3.5 RL = 10 Ω 300 250
CNR = 0.01 µF TJ = 125°C
3.0 TJ = 125°C
250
200
2.5
500 mV/Div

TJ = 25°C

VDO (mV)

VDO (mV)
200 TJ = 25°C
2.0 150
150
TJ = −40°C
1.5
100
VIN 100 TJ = −40°C
1.0
IOUT = 1 A
50
0.5
VOUT 50 COUT = 10 µF
CNR = 0.01 µF
0 0 0
0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 9001000 2.5 3.0 3.5 4.0 4.5 5.0
200 µs/Div IOUT (mA) VIN (V)

Figure 16. Figure 17. Figure 18.

TPS79630 TPS79630 TPS79630

TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE
(ESR) (ESR) (ESR)
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
100 100 100

ESR − Equivalent Series Resistance − Ω

ESR − Equivalent Series Resistance − Ω

ESR − Equivalent Series Resistance − Ω

COUT = 1 µF COUT = 2.2 µF COUT = 10.0 µF

Region of
Region of 10
10 10 Region of Instability
Instability
Instability

1
1 1
Region of Stability
Region of Stability Region of Stability
0.1
0.1 0.1

0.01
1 10 30 60 125 250 500 750 1000
0.01 0.01
IOUT (mA)
1 10 30 60 125 250 500 750 1000 1 10 30 60 125 250 500 750 1000
IOUT (mA) IOUT (mA)

Figure 19. Figure 20. Figure 21.

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TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

APPLICATION INFORMATION

The TPS796xx family of low-dropout (LDO) regulators For example, the TPS79630 exhibits 40 µVRMS of
has been optimized for use in noise-sensitive equip- output voltage noise using a 0.1-µF ceramic bypass
ment. The device features extremely low dropout capacitor and a 10-µF ceramic output capacitor. Note
voltages, high PSRR, ultralow output noise, low that the output starts up slower as the bypass
quiescent current (265 µA typically), and enable input capacitance increases due to the RC time constant at
to reduce supply currents to less than 1 µA when the the bypass pin that is created by the internal 250-kΩ
regulator is turned off. resistor and external capacitor.
A typical application circuit is shown in Figure 22.
Board Layout Recommendation to Improve
VIN VOUT
PSRR and Noise Performance
IN OUT
TPS796xx To improve ac measurements like PSRR, output
2.2µF 1 µF noise, and transient response, it is recommended that
EN GND NR
0.01µF the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
Figure 22. Typical Application Circuit ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
External Capacitor Requirements
Regulator Mounting
Although not required, it is good analog design
practice to place a 0.1-µF — 2.2-µF capacitor near The tab of the SOT223-6 package is electrically
the input of the regulator to counteract reactive input connected to ground. For best thermal performance,
sources. A 2.2-µF or larger ceramic input bypass the tab of the surface-mount version should be
capacitor, connected between IN and GND and soldered directly to a circuit-board copper area.
located close to the TPS796xx, is required for stability Increasing the copper area improves heat dissipation.
and improves transient response, noise rejection, and Solder pad footprint recommendations for the devices
ripple rejection. A higher-value input capacitor may be are presented in an application bulletin Solder Pad
necessary if large, fast-rise-time load transients are Recommendations for Surface-Mount Devices, litera-
anticipated and the device is located several inches ture number AB-132, available for download from the
from the power source. TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx
requires an output capacitor connected between OUT Programming the TPS79601 Adjustable LDO
and GND to stabilize the internal control loop. The Regulator
minimum recommended capacitance is 1 µF. Any The output voltage of the TPS79601 adjustable
1 µF or larger ceramic capacitor is suitable. regulator is programmed using an external resistor
The internal voltage reference is a key source of divider as shown in Figure 28. The output voltage is
noise in an LDO regulator. The TPS796xx has an NR calculated using Equation 1:
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
V V
O REF


1  R1
R2

(1)
internal resistor, in conjunction with an external by-
pass capacitor connected to the NR pin, creates a where:
low-pass filter to reduce the voltage reference noise • VREF = 1.2246 V typ (the internal reference
and, therefore, the noise at the regulator output. In voltage)
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum, Resistors R1 and R2 should be chosen for approxi-
because any leakage current creates an IR drop mately 40-µA divider current. Lower value resistors
across the internal resistor, thus creating an output can be used for improved noise performance, but the
error. Therefore, the bypass capacitor must have device wastes more power. Higher values should be
minimal leakage current. The bypass capacitor avoided, as leakage current at FB increases the
should be no more than 0.1-µF in order to ensure that output voltage error.
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.

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TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

The recommended design procedure is to choose Regulator Protection

R2 = 30.1 kΩ to set the divider current at 40 µA, C1 =
The TPS796xx PMOS-pass transistor has a built-in
15 pF for stability, and then calculate R1 using
back diode that conducts reverse current when the
Equation 2:
input voltage drops below the output voltage (e.g.,
R1  V
V
O 1
REF

R2
(2)
during power down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting might be appropriate.
In order to improve the stability of the adjustable
version, it is suggested that a small compensation The TPS796xx features internal current limiting and
capacitor be placed between OUT and FB. The thermal protection. During normal operation, the
approximate value of this capacitor can be calculated TPS796xx limits output current to approximately 2.8
as Equation 3: A. When current limiting engages, the output voltage
(3 x 10 –7) x (R1
R2) scales back linearly until the overcurrent condition
C1  ends. While current limiting is designed to prevent
(R1 x R2) (3) gross device failure, care should be taken not to
The suggested value of this capacitor for several exceed the power dissipation ratings of the package.
resistor ratios is shown in the table below (see If the temperature of the device exceeds approxi-
Figure 23). If this capacitor is not used (such as in a mately 165°C, thermal-protection circuitry shuts it
unity-gain configuration) then the minimum rec- down. Once the device has cooled down to below
ommended output capacitor is 2.2 µF instead of 1 µF. approximately 140°C, regulator operation resumes.

OUTPUT VOLTAGE
VIN IN OUT VOUT PROGRAMMING GUIDE
TPS79601
2.2 µF EN
R1 C1 OUTPUT
1 µF VOLTAGE R1 R2 C1
NR GND FB

0.01 µF R2 1.8 V 14.0 kΩ 30.1 kΩ 33 pF

3.6V 57.9 kΩ 30.1 kΩ 15 pF

Figure 23. TPS79601 Adjustable LDO Regulator Programming

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SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

THERMAL INFORMATION
temperature due to the regulator's power dissipation.
The amount of heat that an LDO linear regulator The temperature rise is computed by multiplying the
generates is directly proportional to the amount of maximum expected power dissipation by the sum of
power it dissipates during operation. All integrated
the thermal resistances between the junction and the
circuits have a maximum allowable junction tempera- case (RΘJC), the case to heatsink (RΘCS), and the
ture (TJmax) above which normal operation is not heatsink to ambient (RΘSA). Thermal resistances are
assured. A system designer must design the measures of how effectively an object dissipates
operating environment so that the operating junction heat. Typically, the larger the device, the more
temperature (TJ) does not exceed the maximum surface area available for power dissipation and the
junction temperature (TJmax). The two main environ- lower the object's thermal resistance.
mental variables that a designer can use to improve
thermal performance are air flow and external Figure 24 illustrates these thermal resistances for (a)
heatsinks. The purpose of this information is to aid a SOT223 package mounted in a JEDEC low-K
the designer in determining the proper operating board, and (b) a DDPAK package mounted on a
environment for a linear regulator that is operating at JEDEC high-K board.
a specific power level.
Equation 5 summarizes the computation:
In general, the maximum expected power (PD(max))
consumed by a linear regulator is computed as T
J
 T
PDmax x R
A

θJC

R
θCS

R
θSA

Equation 4: (5)
P max  V V 
IO(avg)  VI(avg) x I(Q) The RΘJC is specific to each regulator as determined
D I(avg) O(avg)
(4) by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
where: the type and size of heatsink. For example, black
• VI(avg) is the average input voltage. body radiator type heatsinks can have RΘCS values
• VO(avg) is the average output voltage. ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
• IO(avg) is the average output current. function of how the package is attached to the
• I(Q) is the quiescent current. heatsink. For example, if a thermal compound is used
For most TI LDO regulators, the quiescent current is to attach a heatsink to a SOT223 package, RΘCS of
insignificant compared to the average output current; 1°C/W is reasonable.
therefore, the term VI(avg) x I(Q) can be neglected. The
operating junction temperature is computed by adding
the ambient temperature (TA) and the increase in
A TJ

CIRCUIT BOARD COPPER AREA RθJC A

B
C
B TC
B
RθCS

A
C

RθSA
C
DDPAK Package
SOT223 Package (b)
TA
(a)

Figure 24. Thermal Resistances

11
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

Even if no external black body radiator type heatsink R max  (125
55)°C2.5 W  28°CW
θJA (9)
is attached to the package, the board on which the
regulator is mounted provides some heatsinking From Figure 25, DDPAK Thermal Resistance vs
through the pin solder connections. Some packages, Copper Heatsink Area, the ground plane needs to be
like the DDPAK and SOT223 packages, use a copper 1 cm2 for the part to dissipate 2.5 W. The operating
plane underneath the package or the circuit board's environment used in the computer model to construct
ground plane for additional heatsinking to improve Figure 25 consisted of a standard JEDEC High-K
their thermal performance. Computer-aided thermal board (2S2P) with a 1 oz. internal copper plane and
modeling can be used to compute very accurate ground plane. The package is soldered to a 2 oz.
approximations of an integrated circuit's thermal per- copper pad. The pad is tied through thermal vias to
formance in different operating environments (e.g., the 1 oz. ground plane. Figure 26 shows the side
different types of circuit boards, different types and view of the operating environment used in the com-
sizes of heatsinks, and different air flows, etc.). Using puter model.
these models, the three thermal resistances can be
combined into one thermal resistance between junc- 40
tion and ambient (RΘJA). This RΘJA is valid only for the No Air Flow
specific operating environment used in the computer

° C/W
model. 35

Rθ JA − Thermal Resistance −
Equation 5 simplifies into Equation 6: 150 LFM
T  T
PDmax x R
J A θJA (6) 30
Rearranging Equation 6 gives Equation 7:
T –T 250 LFM
R
J A
θJA P max
25
D (7)
Using Equation 6 and the computer model generated
curves shown in Figure 25 and Figure 28, a designer 20
can quickly compute the required heatsink thermal
resistance/board area for a given ambient tempera-
ture, power dissipation, and operating environment. 15
0.1 1 10 100
DDPAK Power Dissipation Copper Heatsink Area − cm2

The DDPAK package provides an effective means of Figure 25. DDPAK Thermal Resistance vs Copper
managing power dissipation in surface mount appli- Heatsink Area
cations. The DDPAK package dimensions are pro-
vided in the Mechanical Data section at the end of 2 oz. Copper Solder Pad
the data sheet. The addition of a copper plane with 25 Thermal Vias

directly underneath the DDPAK package enhances

the thermal performance of the package. 1 oz. Copper
Power Plane
To illustrate, the TPS72525 in a DDPAK package
was chosen. For this example, the average input
voltage is 5 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera- 1 oz. Copper
ture 55°C, the air flow is 150 LFM, and the operating Ground Plane

environment is the same as documented below.

Neglecting the quiescent current, the maximum aver- Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
age power is calculated as Equation 8:
P Dmax  (5
2.5) V x 1 A  2.5 W Figure 26. DDPAK Thermal Resistance
(8)
Substituting TJmax for TJ into Equation 6 gives From the data in Figure 27 and rearranging
Equation 9: Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed.

12
 TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
www.ti.com
SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004

5 180
TA = 55°C No Air Flow
160

° C/W
140
4 250 LFM

Rθ JA − Thermal Resistance −
120
PD Maximum (W)

150 LFM 100

3
80

60
No Air Flow
2
40

20

1 0
0.1 1 10 100 0.1 1 10
Copper Heatsink Area − cm2 PCB Copper Area − in2

Figure 27. Maximum Power Dissipation vs Copper Figure 28. SOT223 Thermal Resistance vs PCB
Heatsink Area Area

From the data in Figure 28 and rearranging

SOT223 Power Dissipation Equation 6, the maximum power dissipation for a
The SOT223 package provides an effective means of different ground plane area and a specific ambient
managing power dissipation in surface mount appli- temperature can be computed (see Figure 29).
cations. The SOT223 package dimensions are pro- 6
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane TA = 25°C
directly underneath the SOT223 package enhances 5
the thermal performance of the package.
To illustrate, the TPS72525 in a SOT223 package 4
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the 4 in2 PCB Area
PD Maximum (W)

average output current is 1 A, the ambient tempera- 3

ture 55°C, no air flow is present, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver- 0.5 in2 PCB Area
2
age power is calculated as Equation 10:
P Dmax  (3.3
2.5) V x 1 A  800 mW (10)
1
Substituting TJmax for TJ into Equation 6 gives
Equation 11:
0
R max  (125
55)°C800 mW  87.5°CW
θJA 0 25 50 75 100 125 150
(11) TA (°C)
From Figure 28, RΘJA vs PCB Copper Area, the
Figure 29. SOT223 Power Dissipation
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 28 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.

13
 PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2004

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPS79601DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79601DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79601KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79601KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79601KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR
TO-263
TPS79618DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79618DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79618KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79618KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79618KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR
TO-263
TPS79625DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79625DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79625KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79625KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79625KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR
TO-263
TPS79628DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79628DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79628KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79628KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79628KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR
TO-263
TPS79630DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79630DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79630KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79630KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79630KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR
TO-263
TPS79633DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR
TPS79633DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR
TPS79633KTT OBSOLETE DDPAK/ KTT 5 None Call TI Call TI
TO-263
TPS79633KTTR ACTIVE DDPAK/ KTT 5 500 None Call TI Level-3-240C-168 HR
TO-263
TPS79633KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2004

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TO-263
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.

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to Customer on an annual basis.

Addendum-Page 2
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