a Low Power 20 mW 2.3 V to 5.

5 V
Programmable Waveform Generator
AD9833
FEATURES GENERAL DESCRIPTION
Digitally Programmable Frequency and Phase The AD9833 is a low power programmable waveform generator
20 mW Power Consumption at 3 V capable of producing sine, triangular, and square wave outputs.
0 MHz to 12.5 MHz Output Frequency Range Waveform generation is required in various types of sensing,
28-Bit Resolution (0.1 Hz @ 25 MHz Ref Clock) actuation, and time domain reflectometry applications. The output
Sinusoidal/Triangular/Square Wave Outputs frequency and phase are software programmable, allowing easy
2.3 V to 5.5 V Power Supply tuning. No external components are needed. The frequency regis-
No External Components Required ters are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz
3-Wire SPI® Interface can be achieved. Similarly, with a 1 MHz clock rate, the AD9833
Extended Temperature Range: –40ⴗC to +105ⴗC can be tuned to 0.004 Hz resolution.
Power-Down Option The AD9833 is written to via a 3-wire serial interface. This serial
10-Lead MSOP Package interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
APPLICATIONS with a power supply from 2.3 V to 5.5 V.
Frequency Stimulus/Waveform Generation The AD9833 has a power-down function (SLEEP). This allows
Liquid and Gas Flow Measurement sections of the device that are not being used to be powered down,
Sensory Applications—Proximity, Motion, and Defect thus minimizing the current consumption of the part, e.g., the DAC
Detection can be powered down when a clock output is being generated.
Line Loss/Attenuation
The AD9833 is available in a 10-lead MSOP package.
Test and Medical Equipment
Sweep/Clock Generators
TDR

FUNCTIONAL BLOCK DIAGRAM

AGND DGND VDD CAP/2.5V

ON-BOARD
MCLK REGULATOR REFERENCE
AVDD/ FULL-SCALE
DVDD COMP
CONTROL
2.5V

FREQ0 REG 12
PHASE SIN
ACCUMULATOR ⌺ MUX 10-BIT DAC
MUX ROM
(28-BIT)
FREQ1 REG
MSB

PHASE0 REG
PHASE1 REG MUX
DIVIDE VOUT
MUX
BY 2
CONTROL REGISTER
R
200⍀
SERIAL INTERFACE
AND
CONTROL LOGIC AD9833

FSYNC SCLK SDATA

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
 (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 k⍀ for
AD9833–SPECIFICATIONS* VOUT, unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate 25 MSPS
VOUT Max 0.65 V
VOUT Min 38 mV
VOUT TC 200 ppm/∞C
DC Accuracy
Integral Nonlinearity ± 1.0 LSB
Differential Nonlinearity ± 0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio 55 60 dB fMCLK = 25 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion –66 –56 dBc fMCLK = 25 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist) –60 dBc fMCLK = 25 MHz, fOUT = fMCLK/50
Narrow Band (± 200 kHz) –78 dBc fMCLK = 25 MHz, fOUT = fMCLK/50
Clock Feedthrough –60 dBc
Wake-Up Time 1 ms
LOGIC INPUTS
VINH, Input High Voltage 1.7 V 2.3 V to 2.7 V Power Supply
2.0 V 2.7 V to 3.6 V Power Supply
2.8 V 4.5 V to 5.5 V Power Supply
VINL, Input Low Voltage 0.5 V 2.3 V to 2.7 V Power Supply
0.7 V 2.7 V to 3.6 V Power Supply
0.8 V 4.5 V to 5.5 V Power Supply
IINH/IINL, Input Current 10 mA
CIN, Input Capacitance 3 pF
POWER SUPPLIES fMCLK = 25 MHz, fOUT = fMCLK/4096
VDD 2.3 5.5 V
IDD 4.5 5.5 mA IDD Code Dependent. See TPC 2.
Low Power Sleep Mode 0.5 mA DAC Powered Down,
MCLK Running
*Operating temperature range is as follows: B Version: –40∞C to +105∞C; typical specifications are at 25∞C.
Specifications subject to change without notice.

100nF
VDD
10nF

CAP/2.5V COMP

REGULATOR 12
SIN VOUT
10-BIT DAC
ROM
20pF
AD9833

Figure 1. Test Circuit Used to Test Specifications

–2– REV. A
 AD9833
TIMING CHARACTERISTICS* (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.)
Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 40 ns min MCLK Period
t2 16 ns min MCLK High Duration
t3 16 ns min MCLK Low Duration
t4 25 ns min SCLK Period
t5 10 ns min SCLK High Duration
t6 10 ns min SCLK Low Duration
t7 5 ns min FSYNC to SCLK Falling Edge Setup Time
t8 min 10 ns min FSYNC to SCLK Hold Time
t8 max t4 – 5 ns max
t9 5 ns min Data Setup Time
t10 3 ns min Data Hold Time
t11 5 ns min SCLK High to FSYNC Falling Edge Setup Time
*Guaranteed by design, not production tested.
Specifications subject to change without notice.

t1
MCLK
t2
t3

Figure 2. Master Clock

t11 t5 t4
SCLK
t7 t6 t8
FSYNC

t10
t9
SDATA D15 D14 D2 D1 D0 D15 D14

Figure 3. Serial Timing

REV. A –3–
AD9833
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V MSOP Package
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206∞C/W
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44∞C/W
CAP/2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300∞C
Digital I/O Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220∞C
Analog I/O Voltage to AGND . . . . . . –0.3 V to VDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause perma-
Operating Temperature Range nent damage to the device. This is a stress rating only; functional operation of the
Industrial (B Version) . . . . . . . . . . . . . . . –40∞C to +105∞C device at these or any other conditions above those listed in the operational
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150∞C

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD9833BRM –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DJB
EVAL-AD9833EB Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD9833
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.

–4– REV. A
 AD9833
PIN CONFIGURATION

COMP 1 10 VOUT

VDD 2 AD9833 9 AGND

CAP/2.5V 3 TOP VIEW 8 FSYNC

DGND 4 (Not to Scale) 7 SCLK

MCLK 5 6 SDATA

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Function

Power Supply
2 VDD Positive Power Supply for the Analog and the Digital Interface Sections. The
on-board 2.5 V regulator is also supplied from VDD. VDD can have a value
from 2.3 V to 5.5 V. A 0.1 mF and a 10 mF decoupling capacitor should be
connected between VDD and AGND.
3 CAP/2.5 V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated
from VDD using an on-board regulator (when VDD exceeds 2.7 V). The
regulator requires a decoupling capacitor of typically 100 nF, which is connected
from CAP/2.5 V to DGND. If VDD is equal to or less than 2.7 V, CAP/2.5 V
should be tied directly to VDD.
4 DGND Digital Ground.
9 AGND Analog Ground.
Analog Signal and Reference
1 COMP A DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
10 VOUT Voltage Output. The analog and digital output from the AD9833 is available at
this pin. An external load resistor is not required because the device has a
200 W resistor on board.
Digital Interface and Control
5 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction
of the frequency of MCLK. The output frequency accuracy and phase noise
are determined by this clock.
6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
7 SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.
8 FSYNC Active Low Control Input. This is the frame synchronization signal for the input
data. When FSYNC is taken low, the internal logic is informed that a new word is
being loaded into the device.

REV. A –5–
AD9833–Typical Performance Characteristics
5.5 5.5 –60
T A = 25ⴗC TA = 25ⴗC AVDD = 3V
5V TA = 25ⴗC
–65
5.0 5.0
5V
–70
4.5 4.5

IDD (mA)
I DD (mA)

3V

SFDR (dBc)
–75
3V
4.0 4.0
SFDR dB MCLK/7 SFDR dB MCLK/50
–80

3.5 3.5
–85

3.0 –90
3.0
0 5 10 15 20 25 1 10 100 1k 10k 100k 1M 0 5 10 15 20 25
MCLK (MHz) fOUT (Hz) MCLK FREQUENCY (MHz)

TPC 1. Typical Current Consumption TPC 2. Typical IDD vs. fOUT for TPC 3. Narrow-Band SFDR
vs. MCLK Frequency fMCLK = 25 MHz vs. MCLK Frequency

–40 0
–40
VDD = 3V VDD = 3V
TA = 25ⴗC
TA = 25ⴗC –10 TA = 25ⴗC
VDD = 3V
–45 –45
–20 fOUT = MCLK/4096

–50 –30
–50
SFDR (dBc)

SFDR (dB)

MCLK 10MHz

SNR (dB)
–40
SFDR dB MCLK/7 MCLK 18MHz
–55 –55
–50 MCLK 1MHz

–60 –60
SFDR dB MCLK/50 –60
–70
–65 –65
–80
MCLK 25MHz
–70 –90
5 7 9 11 13 15 17 19 21 23 25 0.001 0.01 0.1 1 10 100 –70
1.0 5.0 10 12.5 25
MCLK FREQUENCY (MHz) fOUT/f MCLK
MCLK FREQUENCY (MHz)

TPC 4. Wideband SFDR vs. TPC 5. Wideband SFDR vs. TPC 6. SNR vs. MCLK Frequency
MCLK Frequency fOUT/fMCLK for Various MCLK
Frequencies

1000 1.250
950
1.225 UPPER RANGE
900
2.3V
WAKE-UP TIME (␮s)

850
1.200
800
VREFOUT (V)

750
5.5V 1.175
700
LOWER RANGE
650 1.150

600
1.125
550

500 1.100
–40 25 105 –40 25 105
TEMPERATURE (ⴗC) TEMPERATURE (ⴗC)

TPC 7. Wake-Up Time vs. TPC 8. VREFOUT vs. Temperature

Temperature

–6– REV. A
 AD9833
0 0 0

–10 –10 –10

–20 –20 –20

–30 –30 –30

–40 –40 –40

dB

dB

dB
–50 –50 –50

–60 –60 –60

–70 –70 –70

–80 –80 –80

–90 –90 –90

–100 –100 –100
0 100k 0 5M 0 5M
RWB 100 VWB 30 ST 100 SEC RWB 1K VWB 300 ST 50 SEC RWB 1K VWB 300 ST 50 SEC
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TPC 9. fMCLK = 10 MHz, TPC 10. fMCLK = 10 MHz, TPC 11. fMCLK = 10 MHz,
fOUT = 2.4 kHz, Frequency fOUT = 1.43 MHz = fMCLK/7, fOUT = 3.33 MHz = fMCLK/3,
Word = 000FBA9 Frequency Word = 2492492 Frequency Word = 5555555

0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40 –40 –40
dB

dB

dB
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
0 100k 0 1M 0 12.5M
RWB 100 VWB 30 ST 100 SEC RWB 300 VWB 100 ST 100 SEC RWB 1K VWB 300 ST 100 SEC
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TPC 12. fMCLK = 25 MHz, TPC 13. fMCLK = 25 MHz, TPC 14. fMCLK = 25 MHz,
fOUT = 6 kHz, Frequency fOUT = 60 kHz, Frequency fOUT = 600 kHz, Frequency
Word = 000FBA9 Word = 009D495 Word = 0624DD3

0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40 –40 –40
dB
dB

dB

–50 –50 –50

–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
0 12.5M 0 12.5M 0 12.5M
RWB 1K VWB 300 ST 100 SEC RWB 1K VWB 300 ST 100 SEC RWB 1K VWB 300 ST 100 SEC
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TPC 15. fMCLK = 25 MHz, TPC 16. fMCLK = 25 MHz, TPC 17. fMCLK = 25 MHz,
fOUT = 2.4 MHz, Frequency fOUT = 3.857 MHz = fMCLK/7, fOUT = 8.333 MHz = fMCLK/3,
Word = 189374D Frequency Word = 2492492 Frequency Word = 5555555

REV. A –7–
AD9833
TERMINOLOGY THEORY OF OPERATION
Integral Nonlinearity Sine waves are typically thought of in terms of their magnitude
This is the maximum deviation of any code from a straight line form a(t) = sin(t). However, these are nonlinear and not easy
passing through the endpoints of the transfer function. The end- to generate except through piecewise construction. On the other
points of the transfer function are zero scale, a point 0.5 LSB hand, the angular information is linear in nature. That is, the
below the first code transition (000 . . . 00 to 000 . . . 01), phase angle rotates through a fixed angle for each unit of time.
and full scale, a point 0.5 LSB above the last code transition The angular rate depends on the frequency of the signal by the
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. traditional rate of  = 2f.
Differential Nonlinearity MAGNITUDE
This is the difference between the measured and ideal 1 LSB +1
change between two adjacent codes in the DAC. A specified differ-
ential nonlinearity of ± 1 LSB maximum ensures monotonicity. 0
6␲
2␲ 4␲
Output Compliance
The output compliance refers to the maximum voltage that can be –1
generated at the output of the DAC to meet the specifications.
When voltages greater than that specified for the output compli- 2␲ PHASE 4␲ 6␲
2p
ance are generated, the AD9833 may not meet the specifications
listed in the data sheet.
0
Spurious-Free Dynamic Range
Along with the frequency of interest, harmonics of the fundamental Figure 4. Sine Wave
frequency and images of these frequencies are present at the output Knowing that the phase of a sine wave is linear and given a
of a DDS device. The spurious-free dynamic range (SFDR) refers reference interval (clock period), the phase rotation for that
to the largest spur or harmonic present in the band of interest. period can be determined.
The wideband SFDR gives the magnitude of the largest harmonic
DPhase = wDt
or spur relative to the magnitude of the fundamental frequency
in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the Solving for 
attenuation of the largest spur or harmonic in a bandwidth of
w = DPhase / Dt = 2pf
± 200 kHz about the fundamental frequency.
Solving for f and substituting the reference clock frequency for
the reference period (1/ f MCLK = Dt )
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the rms value of the fundamental. For the AD9833, f = DPhase ¥ f MCLK / 2p
THD is defined as
The AD9833 builds the output based on this simple equation. A
2 2 2 2 2
V + V3 + V4 + V5 + V6 simple DDS chip can implement this equation with three major
THD = 20 log 2 subcircuits: numerically controlled oscillator + phase modulator,
V1
SIN ROM, and digital-to-analog converter.
where V1 is the rms amplitude of the fundamental and V2, V3, Each of these subcircuits is discussed in the following section.
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics. CIRCUIT DESCRIPTION
Signal-to-Noise Ratio (SNR) The AD9833 is a fully integrated direct digital synthesis (DDS)
SNR is the ratio of the rms value of the measured output signal chip. The chip requires one reference clock, one low precision
to the rms sum of all other spectral components below the Nyquist resistor, and decoupling capacitors to provide digitally created
frequency. The value for SNR is expressed in decibels. sine waves up to 12.5 MHz. In addition to the generation of this
Clock Feedthrough RF signal, the chip is fully capable of a broad range of simple
There will be feedthrough from the MCLK input to the analog and complex modulation schemes. These modulation schemes
output. Clock feedthrough refers to the magnitude of the MCLK are fully implemented in the digital domain, allowing accurate
signal relative to the fundamental frequency in the AD9833’s and simple realization of complex modulation algorithms
output spectrum. using DSP techniques.
The internal circuitry of the AD9833 consists of the following
main sections: a numerically controlled oscillator (NCO),
frequency and phase modulators, SIN ROM, a digital-to-analog
converter, and a regulator.

–8– REV. A
 AD9833
Numerically Controlled Oscillator Plus Phase Modulator Regulator
This consists of two frequency select registers, a phase accumu- VDD provides the power supply required for the analog section
lator, two phase offset registers, and a phase offset adder. The and the digital section of the AD9833. This supply can have a
main component of the NCO is a 28-bit phase accumulator. value of 2.3 V to 5.5 V.
Continuous time signals have a phase range of 0 to 2. Outside The internal digital section of the AD9833 is operated at 2.5 V.
this range of numbers, the sinusoid functions repeat themselves An on-board regulator steps down the voltage applied at VDD
in a periodic manner. The digital implementation is no different. to 2.5 V. When the applied voltage at the VDD pin of the AD9833
The accumulator simply scales the range of phase numbers into is equal to or less than 2.7 V, the CAP/2.5 V and VDD pins
a multibit digital word. The phase accumulator in the AD9833 is should be tied together, thus bypassing the on-board regulator.
implemented with 28 bits. Therefore, in the AD9833, 2 = 228.
Likewise, the Phase term is scaled into this range of numbers FUNCTIONAL DESCRIPTION
0 < Phase < 228 – 1. With these substitutions, the previous Serial Interface
equation becomes The AD9833 has a standard 3-wire serial interface that is com-
f = Phase ¥ f MCLK / 2 28 patible with SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
where 0 < Phase < 228 – 1.
Data is loaded into the device as a 16-bit word under the control
The input to the phase accumulator can be selected either from of a serial clock input, SCLK. The timing diagram for this opera-
the FREQ0 register or FREQ1 register, and is controlled by tion is given in Figure 3.
the FSELECT bit. NCOs inherently generate continuous phase
The FSYNC input is a level triggered input that acts as a frame
signals, thus avoiding any output discontinuity when switching
synchronization and chip enable. Data can be transferred into
between frequencies.
the device only when FSYNC is low. To start the serial data
Following the NCO, a phase offset can be added to perform phase transfer, FSYNC should be taken low, observing the minimum
modulation using the 12-bit phase registers. The contents of FSYNC to SCLK falling edge setup time, t7. After FSYNC goes
one of these phase registers is added to the most significant bits low, serial data will be shifted into the device’s input shift register
of the NCO. The AD9833 has two phase registers; their resolu- on the falling edges of SCLK for 16 clock pulses. FSYNC may
tion is 2/4096. be taken high after the 16th falling edge of SCLK, observing
SIN ROM the minimum SCLK falling edge to FSYNC rising edge time, t8.
To make the output from the NCO useful, it must be converted Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
from phase information into a sinusoidal value. Since phase infor- pulses and then brought high at the end of the data transfer. In
mation maps directly into amplitude, the SIN ROM uses the digital this way, a continuous stream of 16-bit words can be loaded while
phase information as an address to a look-up table and converts FSYNC is held low, FSYNC only going high after the 16th SCLK
the phase information into amplitude. Although the NCO contains falling edge of the last word loaded.
a 28-bit phase accumulator, the output of the NCO is truncated The SCLK can be continuous, or alternatively the SCLK can
to 12 bits. Using the full resolution of the phase accumulator is idle high or low between write operations but must be high
impractical and unnecessary, as this would require a look-up when FSYNC goes low (t11).
table of 228 entries. It is necessary only to have sufficient phase
Powering Up the AD9833
resolution such that the errors due to truncation are smaller than
The flow chart in Figure 7 shows the operating routine for the
the resolution of the 10-bit DAC. This requires that the SIN ROM
AD9833. When the AD9833 is powered up, the part should be
have two bits of phase resolution more than the 10-bit DAC.
reset. This will reset appropriate internal registers to zero to pro-
The SIN ROM is enabled using the MODE bit (D1) in the vide an analog output of midscale. To avoid spurious DAC outputs
control register. This is explained further in Table XI. while the AD9833 is being initialized, the RESET bit should be
Digital-to-Analog Converter set to 1 until the part is ready to begin generating an output.
The AD9833 includes a high impedance current source 10-bit RESET does not reset the phase, frequency, or control registers.
DAC. The DAC receives the digital words from the SIN ROM These registers will contain invalid data, and therefore should be
and converts them into the corresponding analog voltages. set to a known value by the user. The RESET bit should then
be set to 0 to begin generating an output. The data will appear
The DAC is configured for single-ended operation. An external on the DAC output eight MCLK cycles after RESET is set to 0.
load resistor is not required since the device has a 200 W resis-
tor on board. The DAC generates an output voltage of typically Latency
0.6 V p-p. Associated with each asynchronous write operation in the AD9833
is a latency. If a selected frequency/phase register is loaded with
a new word, there is a delay of seven to eight MCLK cycles before
the analog output will change. (There is an uncertainty of one
MCLK cycle, as it depends on the position of the MCLK rising
edge when the data is loaded into the destination register.)

REV. A –9–
AD9833
Control Register To inform the AD9833 that the contents of the control register
The AD9833 contains a 16-bit control register that sets up the will be altered, D15 and D14 must be set to 0 as shown below.
AD9833 as the user wants to operate it. All control bits, except
MODE, are sampled on the internal negative edge of MCLK. Table I. Control Register
Table II describes the individual bits of the control register. D15 D14 D13 D0
The different functions and the various output options from
the AD9833 are described in more detail in the section 0 0 CONTROL BITS
following Table II.
SLEEP12
SLEEP1
AD9833

SIN
ROM 0 (LOW POWER)
RESET PHASE 10-BIT DAC
MUX
ACCUMULATOR
1
(28-BIT)

MODE + OPBITEN
1 DIGITAL
MUX OUTPUT VOUT
DIVIDE 0 (ENABLE)
BY 2
DIV2
OPBITEN

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 B28 HLB FSELECT PSELECT 0 RESET SLEEP1 SLEEP12 OPBITEN 0 DIV2 0 MODE 0

Figure 5. Function of Control Bits

Table II. Description of Bits in the Control Register

Bit Name Function

D13 B28 Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word, and the next write will contain the 14 MSBs. The first two bits of
each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same
for both of the consecutive writes. Refer to Table IV for the appropriate addresses. The write to the frequency
register occurs after both words have been loaded, so the register never holds an intermediate value. An example
of a complete 28-bit write is shown in Table V.
When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and
the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent
of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate
frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the
14 MSBs or 14 LSBs.
D12 HLB This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring
the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction
with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs
or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and
LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11 FSELECT The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.
D10 PSELECT The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of
the phase accumulator.
D9 Reserved This bit should be set to 0.
D8 RESET RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale.
RESET = 0 disables RESET. This function is explained further in Table IX.
D7 SLEEP1 When SLEEP1 = 1, the internal MCLK clock is disabled, the DAC output will remain at its present value as
the NCO is no longer accumulating.
When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table X.

–10– REV. A
 AD9833
Table II. Description of Bits in the Control Register (continued)
Bit Name Function
D6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of
the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table X.
D5 OPBITEN The function of this bit, in association with D1 (MODE), is to control what is output at the VOUT pin. This is
explained further in Table XI.
When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or
MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The bit DIV2
controls whether it is the MSB or MSB/2 that is output.
When OPBITEN = 0, the DAC is connected to VOUT. The MODE bit determines whether it is a sinusoidal
or a ramp output that is available.
D4 Reserved This bit must be set to 0.
D3 DIV2 DIV2 is used in association with D5 (OPBITEN). This is explained further in Table XI.
When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin.
When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
D2 Reserved This bit must be set to 0.
D1 MODE This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at
the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit
OPBITEN = 1. This is explained further in Table XI.
When MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC.
When MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, which
results in a sinusoidal signal at the output.
D0 Reserved This bit must be set to 0.

Frequency and Phase Registers The analog output from the AD9833 is
The AD9833 contains two frequency registers and two phase
f MCLK /228 ¥ FREQREG
registers, which are described in Table III.
where FREQREG is the value loaded into the selected frequency
Table III. Frequency/Phase Registers register. This signal will be phase shifted by
2 p/ 4096 ¥ PHASEREG
Register Size Description
FREQ0 28 Bits Frequency Register 0. When the FSELECT where PHASEREG is the value contained in the selected
bit = 0, this register defines the output fre- phase register. Consideration must be given to the relationship of
quency as a fraction of the MCLK frequency. the selected output frequency and the reference clock frequency
to avoid unwanted output anomalies.
FREQ1 28 Bits Frequency Register 1. When the FSELECT
bit = 1, this register defines the output fre- The flow chart in Figure 9 shows the routine for writing to the
quency as a fraction of the MCLK frequency. frequency and phase registers of the AD9833.

PHASE0 12 Bits Phase Offset Register 0. When the PSELECT Writing to a Frequency Register
bit = 0, the contents of this register are added When writing to a frequency register, Bits D15 and D14 give
to the output of the phase accumulator. the address of the frequency register.
PHASE1 12 Bits Phase Offset Register 1. When the PSELECT Table IV. Frequency Register Bits
bit = 1, the contents of this register are added
to the output of the phase accumulator. D15 D14 D13 D0
0 1 MSB 14 FREQ0 REG Bits LSB
1 0 MSB 14 FREQ1 REG Bits LSB

REV. A –11–
AD9833
If the user wants to change the entire contents of a frequency regis- RESET Function
ter, two consecutive writes to the same address must be performed The RESET function resets appropriate internal registers to 0
since the frequency registers are 28 bits wide. The first write will to provide an analog output of midscale. RESET does not reset
contain the 14 LSBs, while the second write will contain the 14 MSBs. the phase, frequency, or control registers. When the AD9833 is
For this mode of operation, the control bit B28 (D13) should powered up, the part should be reset. To reset the AD9833, set
be set to 1. An example of a 28-bit write is shown in Table V. the RESET bit to 1. To take the part out of reset, set the bit to 0.
A signal will appear at the DAC to output eight MCLK cycles
Table V. Writing 00FC00 to FREQ0 REG after RESET is set to 0.
SDATA Input Result of Input Word Table IX. Applying RESET
0010 0000 0000 0000 Control Word Write (D15, D14 = 00),
RESET Bit Result
B28 (D13) = 1, HLB (D12) = X
0100 0000 0000 0000 FREQ0 REG Write (D15, D14 = 01), 0 No Reset Applied
14 LSBs = 0000 1 Internal Registers Reset
0100 0000 0011 1111 FREQ0 REG Write (D15, D14 = 01),
14 MSBs = 003F SLEEP Function
Sections of the AD9833 that are not in use can be powered
In some applications, the user does not need to alter all 28 bits down to minimize power consumption. This is done using the
of the frequency register. With coarse tuning, only the 14 MSBs SLEEP function. The parts of the chip that can be powered
are altered, while with fine tuning, only the 14 LSBs are altered. down are the internal clock and the DAC. The bits required for
By setting the control bit B28 (D13) to 0, the 28-bit frequency the SLEEP function are outlined in Table X.
register operates as two, 14-bit registers, one containing the
14 MSBs and the other containing the 14 LSBs. This means that Table X. Applying the SLEEP Function
the 14 MSBs of the frequency word can be altered independent
of the 14 LSBs, and vice versa. Bit HLB (D12) in the control SLEEP1 Bit SLEEP12 Bit Result
register identifies which 14 bits are being altered. Examples of 0 0 No Power-Down
this are shown in Tables VI and VII. 0 1 DAC Powered Down
1 0 Internal Clock Disabled
Table VI. Writing 3FFF to the 14 LSBs of FREQ1 REG 1 1 Both the DAC Powered Down
and the Internal Clock Disabled
SDATA Input Result of Input Word
0000 0000 0000 0000 Control Word Write (D15, D14 = 00), DAC Powered Down
B28 (D13) = 0; HLB (D12) = 0, This is useful when the AD9833 is used to output the MSB of
i.e. LSBs the DAC data only. In this case, the DAC is not required so it
1011 1111 1111 1111 FREQ1 REG Write (D15, D14 = 10), can be powered down to reduce power consumption.
14 LSBs = 3FFF Internal Clock Disabled
When the internal clock of the AD9833 is disabled, the DAC
Table VII. Writing 00FF to the 14 MSBs of FREQ0 REG output will remain at its present value as the NCO is no longer
accumulating. New frequency, phase, and control words can be
SDATA Input Result of Input Word written to the part when the SLEEP1 control bit is active. The
synchronizing clock is still active, which means that the selected
0001 0000 0000 0000 Control Word Write (D15, D14 = 00),
frequency and phase registers can also be changed using the
B28 (D13) = 0, HLB (D12) = 1,
control bits. Setting the SLEEP1 bit to 0 enables the MCLK.
i.e., MSBs
Any changes made to the registers while SLEEP1 was active will
0100 0000 1111 1111 FREQ0 REG Write (D15, D14 = 01),
be seen at the output after a certain latency.
14 MSBs = 00FF
VOUT Pin
Writing to a Phase Register The AD9833 offers a variety of outputs from the chip, all of which
When writing to a phase register, Bits D15 and D14 are set to 11. are available from the VOUT pin. The choice of outputs are the
Bit D13 identifies which phase register is being loaded. MSB of the DAC data, a sinusoidal output, or a triangle output.
The OPBITEN (D5) and MODE (D1) bits in the control
Table VIII. Phase Register Bits
register are used to decide which output is available from the
D15 D14 D13 D12 D11 D0 AD9833. This is explained further below and also in Table XI.

1 1 0 X MSB 12 PHASE0 Bits LSB MSB of the DAC Data

1 1 1 X MSB 12 PHASE1 Bits LSB The MSB of the DAC data can be output from the AD9833. By
setting the OPBITEN (D5) control bit to 1, the MSB of the DAC
data is available at the VOUT pin. This is useful as a coarse
clock source. This square wave can also be divided by two before
being output. The DIV2 (D3) bit in the control register controls
the frequency of this output from the VOUT pin.

–12– REV. A
 AD9833
Sinusoidal Output The AD9833 is also suitable for signal generator applications.
The SIN ROM is used to convert the phase information from Because the MSB of the DAC data is available at the VOUT
the frequency and phase registers into amplitude information pin, the device can be used to generate a square wave.
that results in a sinusoidal signal at the output. To have a With its low current consumption, the part is suitable for appli-
sinusoidal output from the VOUT pin, set the MODE (D1) bit to 0 cations in which it can be used as a local oscillator.
and the OPBITEN (D5) bit to 0.
Triangle Output GROUNDING AND LAYOUT
The SIN ROM can be bypassed so that the truncated digital output The printed circuit board that houses the AD9833 should be
from the NCO is sent to the DAC. In this case, the output is no designed so that the analog and digital sections are separated
longer sinusoidal. The DAC will produce a 10-bit linear trian- and confined to certain areas of the board. This facilitates the
gular function. To have a triangle output from the VOUT pin, use of ground planes that can be separated easily. A minimum
set the MODE (D1) bit = 1. etch technique is generally best for ground planes since it gives
Note that the SLEEP12 bit must be 0 (i.e., the DAC is enabled) the best shielding. Digital and analog ground planes should be
when using this pin. joined in one place only. If the AD9833 is the only device requiring
an AGND to DGND connection, then the ground planes should
Table XI. Various Outputs from VOUT be connected at the AGND and DGND pins of the AD9833. If
the AD9833 is in a system where multiple devices require AGND
OPBITEN Bit MODE Bit DIV2 Bit VOUT Pin to DGND connections, the connection should be made at one
point only, a star ground point that should be established as
0 0 X Sinusoid
close as possible to the AD9833.
0 1 X Triangle
1 0 0 DAC Data MSB/2 Avoid running digital lines under the device as these will couple
1 0 1 DAC Data MSB noise onto the die. The analog ground plane should be allowed to
1 1 X Reserved run under the AD9833 to avoid noise coupling. The power supply
lines to the AD9833 should use as large a track as possible to
provide low impedance paths and reduce the effects of glitches
VOUT MAX
on the power supply line. Fast switching signals, such as clocks,
should be shielded with digital ground to avoid radiating noise
VOUT MIN
to other sections of the board. Avoid crossover of digital and
2␲ 4␲ 6␲ analog signals. Traces on opposite sides of the board should run
at right angles to each other. This will reduce the effects of
Figure 6. Triangle Output feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
APPLICATIONS this technique, the component side of the board is dedicated to
Because of the various output options available from the part, the ground planes, while signals are placed on the other side.
AD9833 can be configured to suit a wide variety of applications.
Good decoupling is important. The AD9833 should have supply
One of the areas where the AD9833 is suitable is in modulation bypassing of 0.1 µF ceramic capacitors in parallel with 10 µF
applications. The part can be used to perform simple modu- tantalum capacitors. To achieve the best from the decoupling
lation, such as FSK. More complex modulation schemes, such as capacitors, they should be placed as close as possible to the
GMSK and QPSK, can also be implemented using the AD9833. device, ideally right up against the device.
In an FSK application, the two frequency registers of the AD9833 Proper operation of the comparator requires good layout strategy.
are loaded with different values. One frequency will represent The strategy must minimize through proper layout of the PCB
the space frequency, while the other will represent the mark the parasitic capacitance between VIN and the SIGN BIT OUT
frequency. Using the FSELECT bit in the control register of the pin by adding isolation using a ground plane. For example, in a
AD9833, the user can modulate the carrier frequency between 4-layer board, the CIN signal could be connected to the top layer
the two values. and the SIGN BIT OUT connected to the bottom layer, so that
The AD9833 has two phase registers; this enables the part to isolation is provided by the power and ground planes between.
perform PSK. With phase shift keying, the carrier frequency
is phase shifted, the phase being altered by an amount that is
related to the bit stream being input to the modulator.

REV. A –13–
AD9833
DATA WRITE
SEE FIGURE 9

SELECT DATA
SOURCES

WAIT 8/9 MCLK INITIALIZATION

CYCLES SEE FIGURE 8 BELOW

DAC OUTPUT

VOUT = VREF ⴛ 18 ⴛ RLOAD/R SET ⴛ (1 + (SIN(2␲(FREQREG ⴛ fMCLK ⴛ t /228 + PHASEREG/212))))

YES YES
CHANGE PHASE? CHANGE
PSELECT?

NO NO

YES CHANGE YES CHANGE PHASE

CHANGE FREQUENCY?
FSELECT? REGISTER?

NO NO YES

YES CHANGE FREQUENCY CHANGE DAC OUTPUT

REGISTER? FROM SIN TO RAMP?
YES
NO

YES CHANGE OUTPUT TO

CONTROL REGISTER
WRITE A DIGITAL SIGNAL?
(SEE TABLE XI)
NO

Figure 7. Flow Chart for AD9833 Initialization and Operation

INITIALIZATION

APPLY RESET

(CONTROL REGISTER WRITE)

RESET = 1

WRITE TO FREQUENCY AND PHASE REGISTERS

FREQ0 REG = FOUT0 / f MCLK ⴛ 228
FREQ1 REG = FOUT1 / f MCLK ⴛ 228
PHASE0 AND PHASE1 REG = (PHASESHIFT ⴛ 212) / 2␲

(SEE FIGURE 9)

SET RESET = 0
SELECT FREQUENCY REGISTERS
SELECT PHASE REGISTERS

(CONTROL REGISTER WRITE)

RESET BIT = 0
FSELECT = SELECTED FREQUENCY REGISTER
PSELECT = SELECTED PHASE REGISTER

Figure 8. Initialization

–14– REV. A
 AD9833
DATA WRITE

WRITE A FULL 28-BIT WORD NO WRITE 14 MSBs OR LSBs NO

TO A FREQUENCY REGISTER? WRITE TO PHASE
TO A FREQUENCY REGISTER? REGISTER?

YES YES
YES

(CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE)

B28 (D13) = 0
B28 (D13) = 1 HLB (D12) = 0/1
(16-BIT WRITE)
D15, D14 = 11
D13 = 0/1 (CHOOSE THE
WRITE A 16-BIT WORD
WRITE TWO CONSECUTIVE PHASE REGISTER)
16-BIT WORDS D12 = X
(SEE TABLES VI AND VII
D11 ... D0 = PHASE DATA
FOR EXAMPLES)
(SEE TABLE V FOR EXAMPLE)

WRITE 14MSBs OR LSBs WRITE TO ANOTHER

WRITE ANOTHER FULL TO A
28-BIT WORD TO A PHASE REGISTER? YES
FREQUENCY REGISTER? YES
YES FREQUENCY REGISTER?
NO NO
NO

Figure 9. Data Writes

INTERFACING TO MICROPROCESSORS ADSP-2101/

ADSP-2103* AD9833*
The AD9833 has a standard serial interface that allows the part to
interface directly with several microprocessors. The device uses
an external serial clock to write the data/control information TFS FSYNC
into the device. The serial clock can have a frequency of 40 MHz DT SDATA
maximum. The serial clock can be continuous, or it can idle high SCLK SCLK
or low between write operations. When data/control information
is being written to the AD9833, FSYNC is taken low and is held
low while the 16 bits of data are being written into the AD9833. *ADDITIONAL PINS OMITTED FOR CLARITY
The FSYNC signal frames the 16 bits of information being loaded
into the AD9833. Figure 10. ADSP-2101/ADSP-2103 to AD9833 Interface
AD9833 to ADSP-21xx Interface AD9833 to 68HC11/68L11 Interface
Figure 10 shows the serial interface between the AD9833 and Figure 11 shows the serial interface between the AD9833 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in the 68HC11/68L11 microcontroller. The microcontroller is
the SPORT transmit alternate framing mode (TFSW = 1). The configured as the master by setting bit MSTR in the SPCR to 1.
ADSP-21xx is programmed through the SPORT control register This provides a serial clock on SCK while the MOSI output drives
and should be configured as follows: the serial data line SDATA. Since the microcontroller does not
have a dedicated frame sync pin, the FSYNC signal is derived from
• Internal clock operation (ISCLK = 1)
a port line (PC7). The setup conditions for correct operation of
• Active low framing (INVTFS = 1) the interface are as follows:
• 16-bit word length (SLEN = 15) • SCK idles high between write operations (CPOL = 0)
• Internal frame sync signal (ITFS = 1) • Data is valid on the SCK falling edge (CPHA = 1)
• Generate a frame sync for each write (TFSR = 1) When data is being transmitted to the AD9833, the FSYNC line is
Transmission is initiated by writing a word to the Tx register taken low (PC7). Serial data from the 68HC11/68L11 is transmit-
after the SPORT has been enabled. The data is clocked out on ted in 8-bit bytes with only eight falling clock edges occurring in
each rising edge of the serial clock and clocked into the AD9833 the transmit cycle. Data is transmitted MSB first. In order to load
on the SCLK falling edge. data into the AD9833, PC7 is held low after the first 8 bits are
transferred, and a second serial write operation is performed to
the AD9833. Only after the second 8 bits have been transferred
should FSYNC be taken high again.

REV. A –15–
AD9833
68HC11/68L11* DSP56002*
AD9833* AD9833*

PC7 FSYNC SC2 FSYNC

MOSI SDATA STD SDATA

SCK SCLK SCK SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY

Figure 11. 68HC11/68L11 to AD9833 Interface Figure 13. DSP56002 to AD9833 Interface
AD9833 to 80C51/80L51 Interface
Figure 12 shows the serial interface between the AD9833 and the AD9833 EVALUATION BOARD
80C51/80L51 microcontroller. The microcontroller is operated The AD9833 Evaluation Board allows designers to evaluate the
in mode 0 so that TxD of the 80C51/80L51 drives SCLK of the high performance AD9833 DDS modulator with a minimum
AD9833, while RxD drives the serial data line SDATA. The of effort.
FSYNC signal is again derived from a bit programmable pin on To prove that this device will meet the user’s waveform synthesis
the port (P3.3 being used in the diagram). When data is to be trans- requirements, the user requires only a power supply, an IBM®
mitted to the AD9833, P3.3 is taken low. The 80C51/80L51 compatible PC, and a spectrum analyzer along with the evalua-
transmits data in 8-bit bytes, thus only eight falling SCLK edges tion board.
occur in each cycle. To load the remaining 8 bits to the AD9833, The DDS evaluation kit includes a populated, tested AD9833
P3.3 is held low after the first 8 bits have been transmitted, and a printed circuit board. The evaluation board interfaces to the
second write operation is initiated to transmit the second byte of parallel port of an IBM compatible PC. Software is available
data. P3.3 is taken high following the completion of the second with the evaluation board that allows the user to easily program
write operation. SCLK should idle high between the two write the AD9833. A schematic of the evaluation board is shown in
operations. The 80C51/80L51 outputs the serial data in a format Figure 14. The software will run on any IBM compatible PC
that has the LSB first. The AD9833 accepts the MSB first that has Microsoft Windows® 95, Windows 98, Windows ME,
(the 4 MSBs being the control information, the next 4 bits being or Windows 2000 NT® installed.
the address, while the 8 LSBs contain the data when writing to a
destination register). Therefore, the transmit routine of the Using the AD9833 Evaluation Board
80C51/80L51 must take this into account and rearrange the bits The AD9833 evaluation kit is a test system designed to simplify
so that the MSB is output first. the evaluation of the AD9833. An application note is also avail-
able with the evaluation board and gives full information on
80C51/80L51*
operating the evaluation board.
AD9833*
Prototyping Area
An area is available on the evaluation board for the user to add
P3.3 FSYNC additional circuits to the evaluation test set. Users may want to
RxD SDATA build custom analog filters for the output or add buffers and
TxD SCLK operational amplifiers to be used in the final application.
XO vs. External Clock
The AD9833 can operate with master clocks up to 25 MHz.
*ADDITIONAL PINS OMITTED FOR CLARITY
A 25 MHz oscillator is included on the evaluation board. How-
Figure 12. 80C51/80L51 to AD9833 Interface ever, this oscillator can be removed and, if required, an external
CMOS clock connected to the part.
AD9833 to DSP56002 Interface
Figure 13 shows the interface between the AD9833 and the Power Supply
DSP56002. The DSP56002 is configured for normal mode Power to the AD9833 evaluation board must be provided exter-
asynchronous operation with a gated internal clock (SYN = 0, nally through pin connections. The power leads should be twisted
GCK = 1, SCKD = 1). The frame sync pin is generated internally to reduce ground loops.
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal will frame the 16 bits (FSL = 0).
The frame sync signal is available on pin SC2, but it needs to be
inverted before being applied to the AD9833. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.

–16– REV. A
 AD9833
1
2
SCLK
3 SDATA C11
10␮F VDD
4
FSYNC C2
5 DVDD 0.1␮F
6 J2 J3
DVDD VDD
7 C6 C1 LK1
8 0.1␮F DVDD 0.1␮F C8 C7 C9 C10
9 3 2 10␮F 0.1␮F 0.1␮F 10␮F
10 C6
0.1␮F CAP VDD
11 J1 1
12 2 18 7 SCLK
SCLK VDD
13
4 16 6 SDATA C3
14 SDATA
0.01␮F
15 6 1
14 8 COMP
FSYNC FSYNC
16
17
18 U1
19 U2 AD9833
20
21 MCLK LK2 VOUT
5 10
22 MCLK VOUT
23 R1 DVDD C4
50⍀
24
25 DVDD
C5
26 0.1␮F DGND AGND
27 U3 4 9
28 OUT
29 DGND
30
31
32
33
34
35
36

Figure 14. Evaluation Board Layout

Integrated Circuits
U1 AD9833BRU
U2 74HCT244
U3 OSC XTAL 25 MHz
Capacitors
C1, C2 100 nF Ceramic Capacitor 0805
C3 10 nF Ceramic Capacitor
C4 Option for Extra Decoupling Capacitor
C5, C6, C7, C9 100 nF Ceramic Capacitor
C8, C10, C11 10 mF Tantalum Capacitor
Resistor
R1 50 W Resistor
Links
LK1, LK2 2-Pin Sil Header
Sockets
MCLK VOUT Subminiature BNC Connector
Connectors
J1 36-Pin Edge Connector
J2, J3 PCB Mounting Terminal Block

REV. A –17–
AD9833
OUTLINE DIMENSIONS

10-Lead Mini Small Outline Package [MSOP]

(RM-10)
Dimensions shown in millimeters

3.00 BSC

10 6

3.00 BSC 4.90 BSC

1 5

PIN 1
0.50 BSC
0.95
0.85 1.10 MAX
0.75 0.23
0.08 0.80
0.15 0.27 8ⴗ
SEATING 0.40
0 0.17 PLANE 0ⴗ

COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA

–18– REV. A
 AD9833
Revision History
Location Page
6/03—Data Sheet changed from REV. 0 to REV. A.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

REV. A –19–
–20–
C02704–0–6/03(A)