APPLICATION NOTE

Theory and Application of

Sampling Phase Detector

The phase lock of a Voltage Controlled Oscillator (VCO) for VHF, UHF The error signal output of the sampling phase detector Vbeat =
and microwave frequencies is very important in communications Em sin∅ is the differential phase error between the VCO and the
and radar application. It combines the far-out phase noise of fun- crystal oscillator. The loop amplifier amplifies the error signal to
damental oscillators, especially in the microwave frequency range the VCO and corrects the VCO to be in phase with the crystal
(100 kHz away from carrier frequency and beyond), the excellent oscillator. At the same time, the loop amplifier acts as a low pass
long-term stability, and the close-in phase noise of a crystal oscil- filter and filters away the crystal frequency.
lator (from carrier frequency to 100 kHz away). This method of phase lock will achieve the lowest phase noise
A voltage-controlled oscillator can be phase locked by possible beside the theoretical degradation of 20 log N, where
two methods: N is the multiplication factor between the crystal oscillator and
1. Digital phase lock: This is usually achieved by using a fre- the VCO. The other circuits that will generate additional noise
quency divider to divide the higher frequency of the VCO to the are the driver amplifier, sampling phase detector, and the loop
same frequency of the crystal reference. A digital phase amplifier. They may all contribute to further degradation in phase
detector is then used to acquire the phase lock. The advantage noise (typically 1 dB if the crystal oscillator has a noise floor
of this method is that it is self-acquiring and can operate at of -155 dBc/Hz or 3 dB if the crystal oscillator noise floor is
very low frequencies. It is widely used at low frequencies from -160 dBc/Hz).
1 MHz up to 3 GHz. However, this method also has two disad-
vantages. First, the noise floor of the divider will limit its phase
noise; and second, at microwave frequencies it will not be Circuit Description and Operation of the
economical. Sampling Phase Detector
2. Analog phase lock: This is achieved by using an SRD as a The sampling phase detector is shown in figure 2.
comb generator to create a comb of reference frequencies to 3
the frequency of the VCO. The phase detecting is accomplished
by using a mixer to detect the phase differences between the C1
reference and the VCO. The Skyworks sampling phase detector 2

is designed to perform the analog phase lock in a simple and D2

more economical way. D1 4

The sampling phase detector used in phase lock of a VCO oper- D3

ating by the theory of principles of feedback control systems is 1
shown in Figure 1. C2

VC(t) = E1 sin(wct + 0t) VVCO(t) = E2 sin(wvcot + 0 VCO) 5

Kφ K VCO
Figure 2.
Sampling
Crystal
Phase VCO
Oscillator
Detector

F(s)
Vbeat(t) = Em sinφ
Loop
Amplifier

Figure 1.

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APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

The sampling phase detector consists of three main parts inte- 3. Series pair Schottky diodes: The series pair Schottky diodes in
grated to form a module. The integrated part has the advantage the sampling phase detector are used to detect the errors
of minimized size and improved performance, as it eliminates the between the microwave VCO frequency and the crystal refer-
circuit self-resonance, especially at higher frequencies (13 GHz ence. The Schottky diodes are turned on and off by the gated
and above). The following is the description and function of the capacitor. When turned on, a sample of microwave frequency
three parts: is compared with the switch frequency. An error frequency pro-
1. SRD: The SRD takes an input crystal frequency and generates portional to the differences will be generated as an error signal
a sharp narrow pulse (in the time domain) or combs (in the output or beat note. This error signal will be processed through
frequency domain). The period of the pulse is the same as that the loop amplifier for phase lock (refer to figure 1). The crucial
of the input crystal frequency. The operating range of the sam- parameter on the Schottky diodes is the balance between the
pling phase detector is heavily dependent on the narrow pulse series pair, especially over temperature. Also, the drive level of
generated by the SRD or the transition time of the SRD. The the microwave signal sometimes requires medium or high-
SRD also needs to recover before the next cycle of the crystal level Schottky diodes instead of the normal low-level diodes.
frequency. This is defined by the carrier lifetime of the SRD. The drive level should be proportional to the diodes used. Any
Thus, for a selected input crystal frequency and output phase underdrive results in temperature and unit-to-unit variation.
locked VCO frequency, a special SRD is selected in the partic- Excessive overdrive will result in increased noise floor.
ular sampling phase detector. There are two ways to optimize Therefore, the diodes should be selected based on the opera-
the SRD: tion parameter design for them. Skyworks has a variety of
sampling phase detectors for all applications.
a) For narrow-band operation, the SRD is selected to opti-
mize at the first peak of sin X/X wave form, which
generates the maximum beat note at a specific frequency. Characterization and Evaluation of Sampling
b) For broadband operation, the SRD is selected to 70% of the Phase Detector
first null of the sin X/X wave form, which generates a broad There are two circuits widely used to evaluate and characterize
band of combs of virtually equal amplitude. This is more the performance of the sampling phase detector. Figure 3a and
suitable for wide bandwidth operation, as it generates equal 3b show the single-end and double-end configuration of the test
beat note over a wide frequency range. circuit. These circuits can also be used in real application for
2. Capacitors: The capacitors in the sampling phase detector phase locked VCO.
act as a switch. The switch turns on/off by the pulse gener- To evaluate the sampling phase detector, certain precautions
ated by the SRD. Therefore, these capacitors should be a have to be taken to ensure that the data are varied and repeat-
single layer microwave capacitor that has very low ESR and able. The following is the sequence of setup and test equipment
high self-resonating frequency well above the operating fre- required for the test.
quency of the sampling phase detector. The value of the
capacitor is typically inversely proportional to the operating
frequency. Thus, the higher the operating frequency, the Test Equipment
smaller the value of the capacitor. The capacitor controls the
1. Stable signal source: Crystal oscillators or signal generators. If
efficiency of the transfer of energy or signal from VHF (crystal
a signal generator is selected, a synthesized signal generator
or multiple frequency) to microwave frequency (VCO). As the
is preferred.
capacitor turned “ON,” it quickly charged up to its peak RF
level, and when turned “OFF,” it quickly fully discharged its 2. Power amplifier: Frequency range of 10–500 MHz. Capable of
energy. A more efficient transfer of energy results in lower 15 dB min. gain and a linear power output of 25 dBm min.
phase noise. 3. Sweep microwave signal generator: Should cover the
microwave frequency range to be tested. Power output up to
5 dBm min.
4. Oscilloscope: A dual channel 400 MHz oscilloscope will be
adequate for this test.

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 APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

10 TO 1 TURN RATIO
STEP DOWN TRANSFORMER
470 K

10–100 pF 100 C1
T1 3
2
MICROWAVE INPUT
D2 10 pF
D1
4
D3 50

1 5 IF BUFFERED
100 C2
10–100 pF OUTPUT IF OUTPUT
470 K 1000 pF

Figure 3a. Test Circuit for Sampling Phase Detector

3 TO 1 TURN RATIO
STEP DOWN TRANSFORMER
470 K
BUFFERED
L1 IF OUTPUT
T1 C1
2 3
MICROWAVE INPUT

REFERENCE INPUT D2 10 pF
D1
100 MHz SINE WAVE
+17 to +20 dBm 4 IF OUTPUT
D3 50

1 5
L2 C2
BUFFERED
470 K IF OUTPUT

Figure 3b. Test Circuit for Sampling Phase Detector

Test Setup operational amplifier is used as a low pass filter and it also
1. Set up the reference signal, typically 100 MHz @ 17 dBm or lowers the impedance of the Sampling Phase Detector output.
16 VPP, across the primary of the transformer. The reference As a result, the measured beat note will be consistent and will
signal should have minimum harmonic contents. not be loaded down by the capacitance of the scope probe.
The frequency set for the microwave source is the frequency
2. Between the secondary of the transformer and the sampling we set to test. The power level of the microwave signal is typi-
phase detector is a matching network, which isolates the cally set to 0 dBm.
transformer from the sampling phase detector. The matching
network also acts as a termination and tune circuit (Figure 3a) Once all the test conditions are set, the beat note can be mea-
or as a short at reference frequency and an open circuit at sured at the output using the oscilloscope. The input reference
microwave frequency. The transformer should have an ampli- signal level and the microwave signal levels are adjusted to mea-
tude balance of 0.5 dB and a phase balance of 2 degrees at sure the 1 dB compression point of the sampling phase detector.
the operating frequency of 100 MHz. The data can be taken across the entire operating bandwidth.
Temperature data can be taken in the same manner. From these
3. The microwave signal input is terminated by a thin-film, high- data, one can select the proper reference frequency and drive
frequency, 5O Ω terminating resistor. The coupling input level, as well as the proper microwave frequency and power
capacitor acts as a high pass filter, which allows the level, which will ensure that their system requirements are met.
microwave frequency to pass through, but blocks the lower
reference frequency. The beat note output is connecting to the
operational amplifier, which is wired as a unity gain buffer. The

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APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

Implementation and Optimization of Sampling Test Circuit and Data on the Sampling Phase
Phase Detector Detector
To achieve the best phase noise, the implementation and optimiza-
tion of the sampling phase detector requires the proper selection of 100 Ω 10 kΩ
the components and circuits. The following are circuit guidelines Reference 47 pF
placed in descending order according to their importance. Frequency
Input
1. The crystal oscillator should have a minimum phase noise of 10–500 MHz 22 pF
VCO
CL Input
3 dB better than the system specification from 10 Hz to
100 kHz away from the carrier. SRD

2. The VCO or DRO should have a minimum phase noise of CL RFC IF

3 dB worse than the specification at 100 kHz away from the Output
Input
carrier and 6 dB better at 1 MHz away from the carrier. At Transformer 100 Ω
5 and 10 MHz away from the carrier, the phase noise should 100 Ω
be minimum 3 dB better than the system. 47 pF 39 pF
10 kΩ
3. The noise loop bandwidth should be set at 250–300 kHz, using
a second order loop. This will give enough correction to correct
the VCO or DRO phase noise to the crystal reference, and at Input transformer: 10:1 step down impedance ratio.
the same time, suppress the phase noise of the VCO or DRO at
1 MHz. Suggested Circuit

4. The VCO or DRO should have good tuning linearity. The linear
tuning range should be a minimum of twice the range of tem- 1000
perature drift and long-term drift. The linear tuning range Ref. Frequency: 100 MHz
defines as the maximum variation of voltage tuning sensitivity 800 Ref Input Power: 17 dBm
Best Note Voltage (mV)

by ±10%. This will guarantee a stable loop with minimum VCO Power: 0 dBm
bandwidth change in temperature. 600
5. The loop amplifier is also a critical part of the system. A
proper operational amplifier should be selected for this func- 400
tion. The operational amplifier should have low noise, low DC
offset and low DC offset drift. The bandwidth of the opera- 200
tional amplifier should be between 1–8 MHz. The noise of
2.5 nV/root square Hz is sufficient for most applications. At 0
this level, the operational amplifier is still reasonably priced 0 2 4 6 8 10 12 14 16 18 20 22
at about $1.50 each in 1K quantities. For the extremely low VCO Frequency (GHz)
noise of 0.8 nV/root square Hz, the operational amplifier
SPD1101-111
becomes very expensive at approximately $8.00 each.
Typical Performance

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 APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

0.110 (2.794 mm) Application of the Sampling

4 Phase Detector
The most widely used application of the sampling phase detector
3
0.090 (2.286 mm) 5 is for phase locking a Dielectric Resonator Oscillator (DRO). The
phase-locked DRO is mainly used in the wireless industry, com-
2 1
munication systems and RADAR as a stable LO. In all these
systems, low cost simplicity, reliability, and good performance are
0.015 Epoxy 0.040 required. Here, we discuss the application of the sampling phase
(0.381 mm) (1.016 mm)
Ceramic detector used in the function of a phase-locked DRO.
To design a good phase-locked DRO the first requirement is to
(2.743 mm)
(0.051 mm)

(0.941 mm)

(1.829 mm)
0.108
define the performance of all the components as follows:
0.002

0.039

0.072

1. Crystal oscillator: To ensure the best performance, a 100 MHz

0.088 (2.235 mm) 3rd overtone SC-cut crystal is selected to design a crystal
0.073 (1.854 mm)
0.053 (1.346 mm) oscillator, which can achieve a noise floor of -0.170 dBc/Hz.
The cost of the crystal is high, approximately $20.00 each in
0.017 (0.432 mm)
0.002 (0.051 mm)
50K quantities. The alternative is to use an AT-cut crystal,
0.000
which costs approximately $4.00 each in 50K quantities.
0.000
0.017 (0.432 mm)
0.037 (0.940 mm)

0.073 (1.854 mm)

0.093 (2.362 mm)

However, the trade-off is 3 dB degrading in phase noise and

some increase in the long-term aging rate.
2. DRO: The DRO performance is very important. The DRO should
have a buffer amplifier to isolate the load pulling and also to
achieve an output power of 19 dBm, which is adequate for
-111 Package Outline most applications as LO. The free running phase noise of the
DRO at 100 KHz away from carrier should be -116 dBc/Hz min-
imum over temperature in the operating range (9–13 GHz). The
2 3 operating range is defined as the linear tuning range of the
DRO, which should be twice the temperature drift of the DRO
4 over its operating temperature range. The linear tuning range is
1 5 defined as the tuning range over which the tuning sensitivity of
the DRO varies less than 10%.
Schematic Diagram
3. Sampling phase detector: The sampling phase detector
SPD1102-111 will suit for this design.
4. Loop amplifier: For low cost, an Analog Device OP113 will be
adequate for the design.
5. Low noise power supply: A low noise power supply is very
important for the performance of the phase-locked DRO. In the
system, it is preferable to have local, on-board, low noise reg-
ulators to supply the voltage source to the individual circuits.
This will also isolate the interference from outside and mini-
mize the voltage variation created by current variation and
power wire length variation.

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APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

In this design, the sampling phase detector circuit we selected is POSITIVE FEEDBACK
SWEEPING CIRCUIT
shown in Figure 3b. This was selected because most systems do
not have negative voltage available. This allows us to use a single
REF.
supply and make everything simple and universally adaptable to V = BIAS V/2
BIAS V
most systems. The crystal oscillator will be amplified and drive
the primary of the transformer with a power level of 16 V peak-
to-peak. The DRO/Amp. output is passed through a 16 dB C26
0.1 µF TO V TUNE
directional coupler. This results in a 2 dBm microwave signal to IF INPUT
the sampling phase detector. This will generate a beat note of 0.2

400 mV peak-to-peak output. The loop amplifier used is a

second-order loop (Figure 4a), and the phase noise loop band-
width was set at 300 kHz.
A wide loop bandwidth will be less susceptible to microphonics.
This is very important in the wireless industry, as the unit is nor-
mally mounted outside and is subject to such environmental LOOP FILTER
effects as wind, rain and hail. In this configuration, we can
achieve a system phase noise of -80 dBc/Hz at 100 Hz; Figure 4b. Third-Order Loop
-104 dBc/Hz at 1 kHz; -114 dBc/Hz at 10 kHz; -124 dBc/Hz at
100 kHz; -136 dBc/Hz at 1 MHz; -155 dBc/Hz at 5 MHz. The POSITIVE FEEDBACK
SWEEPING CIRCUIT
system noise floor limits the phase noise measurement at 5 MHz
on the HP Phase Noise Measurement System. If further suppres- REF.
sion of noise is required, a higher order of loop amplifier design V = BIAS V/2
BIAS V
can be selected as shown in Figures 4b through 4d.
The simplicity of the sampling phase detector used in the phase- C26
locked DRO allows us to fabricate the complete circuit including IF INPUT
0.1 µF TO V TUNE
the reference crystal oscillator all on one small PC board. The 0.2
integration of the high-frequency components into one single
package allows us to eliminate wire-bonding, and as a result,
create a complete system which can be automated using surface
mount technology.

POSITIVE FEEDBACK
SWEEPING CIRCUIT LOOP FILTER

REF. Figure 4c. Fourth-Order Loop

V = BIAS V/2
BIAS V
POSITIVE FEEDBACK
SWEEPING CIRCUIT
C26
0.1 µF TO V TUNE
IF INPUT REF.
V = BIAS V/2
0.2 BIAS V

C26
0.1 µF TO V TUNE
IF INPUT
0.2

LOOP FILTER

Figure 4a. Second-Order Loop

LOOP FILTER

Figure 4d. Fifth-Order Loop

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 APPLICATION NOTE • THEORY AND APPLICATION OF SAMPLING PHASE DETECTOR

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