Coolsic™ Mosfet 650 V M1 Trench Power Device: An - 1907 - Pl52 - 1911 - 144109

AN_1907_PL52_1911_144109
CoolSiC™ MOSFET 650 V M1 trench power device

Infineon’s first 650 V silicon carbide MOSFET for industrial applications
About this document

Scope and purpose
Due to the worldwide increase in power consumption it is necessary to design power supplies that offer the
highest possible efficiency during standard operating conditions. This application note will first give an
overview covering the technological parameters of Infineon’s first 650 V SiC trench MOSFET. Second, it will
provide benchmarking results based on characterization data, and in target applications against competitors.
Finally, it will provide design guidelines for implementing SiC in the target applications.
Intended audience
SMPS designers, technology developers.
Please read the Important Notice and Warnings at the end of this document
www.infineon.com page 1 of 37 2020-01-16
Table of contents
Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 2
1 Introduction .......................................................................................................................... 3
2 Overview of CoolSiC™ M1 SiC trench power device ..................................................................... 4
2.1 Positioning ............................................................................................................................................... 4
2.2 Target applications ................................................................................................................................. 5
2.3 Focus topologies ..................................................................................................................................... 6
2.3.1 CCM totem pole PFC (or representative for any hard-switching bridge configuration).................. 7
2.3.2 LLC (or representative for any resonant switching bridge configuration) ....................................... 8
3 Technology parameters ......................................................................................................... 10
3.1 RDS(on) junction over-temperature ......................................................................................................... 10
3.2 Qrr – reverse recovery charge ................................................................................................................ 11
3.3 V(BR)DSS – drain-source breakdown voltage ............................................................................................ 12
3.4 Transfer characteristics ........................................................................................................................ 13
3.5 Coss – output capacitance ...................................................................................................................... 14
3.6 Eoss – energy stored in output capacitance/Qoss – charge in the output capacitance ......................... 16
3.7 VSD (VF) – forward voltage of the body diode......................................................................................... 18
3.8 QG – gate charge .................................................................................................................................... 19
4 Design guidelines .................................................................................................................. 21
4.1 Gate driving ........................................................................................................................................... 21
4.2 Negative gate-source voltage ............................................................................................................... 21
4.3 Kelvin source configuration .................................................................................................................. 24
5 Benchmarking in target applications ....................................................................................... 26
5.1 Switching energies (Eon and Eoff)............................................................................................................ 26
5.2 3.3 kW CCM totem pole PFC .................................................................................................................. 29
5.3 3 kW LLC converter ................................................................................................................................ 32
6 Summary ............................................................................................................................. 35
Revision history............................................................................................................................. 36
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Introduction
1 Introduction
The CoolSiC™ MOSFET 650 V M1 trench power device is Infineon’s first generation of SiC trench MOSFETs. It is
designed to address the needs of power supplies in the range from several hundred watts to tens of kilowatts,
including server and telecom SMPS, solar inverters and EV charging. These applications, considering the overall
Total Cost of Ownership (TCO), benefit from power semiconductors and topology that serves high switching
frequencies, enabling fast switching under hard-switching conditions and providing low conduction losses as
well as a small output and reverse recovery charge (Qrr).
This technology enables highly efficient topologies such as the full-bridge totem pole PFC, which is by nature a
bridgeless topology and therefore boosts efficiency in all load points. It can achieve peak efficiency of more
than 99 percent. This high PFC efficiency is the minimum needed in order to achieve an overall system
efficiency of more than 98 percent.
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Overview of CoolSiC™ M1 SiC trench power device
2 Overview of CoolSiC™ M1 SiC trench power device

2.1 Positioning
Due to the CoolSiCTM M1 technology parameters, which will be explained later, nearly every
application/topology can benefit from it in terms of increased efficiency. Nevertheless, due to the body diode
behavior and the linear output capacitance the main focus is the hard-switching topologies, which have a hard
commutation on a conducting body diode in every switching cycle, e.g. in a CCM totem pole PFC, and resonant
topologies like an LLC converter.
Infineon Technologies is offering Si-, SiC- and GaN-based power products. This gives customers the chance to
cover the whole power transmission line from AC to DC and vice versa. Next it is necessary to explain the
positioning of these three technologies.
Figure 1 Positioning of Infineon technologies for HV power switches
As can be seen in the positioning diagram in Figure 1, Si power transistors will remain the mainstream
technology in the next few years, covering a wide range of possible applications with adequate power and
frequency possibilities. SiC, on the other hand, complements Si in many applications but also enables new
solutions and topologies for higher-power and robust applications. GaN is able to achieve the highest efficiency
and by nature has the best Figure-of-Merit (FOM) for achieving the highest switching frequency.
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Infineon recommends the different technologies as follows:
CoolMOSTM:
 Maintaining cost/performance benefit across a wide range of applications
 High efficiency (up to 97 percent) for certain power density limitations
 Easy design-in
 PFC topologies and resonant topologies covering switching frequency from 45 kHz to 300 kHz
 Short evaluation times and plenty of experience using silicon in PSU
CoolGaNTM:
 Top efficiency and density: best FOM efficiency x power density
 Best for maintaining high efficiency while increasing frequency
 Totem pole PFC and any hard and resonant switching topology operating at higher frequencies
 Daughter card/SMD optimized design approach
CoolSiCTM:
 High efficiency and density: applications where high power is combined with high-temperature operating
conditions
 Totem pole PFC and any hard and resonant switching topology
 Robustness
There is a clear overlap between the three technologies, and the selection of the right technology is heavily
dependent on the application requirements, as all three technologies have a specific value proposition in the
600 V/650 V segment.
The next section of this chapter will explain the target applications and the target topologies that can benefit
from SiC.
2.2 Target applications

With SiC MOSFETs it is possible to easily achieve the high efficiency necessary for customers in order to reduce
the overall power consumption, which is dramatically increased by server, telecom and EV charging
applications.
Now the question arises: why should CoolSiCTM be used in the applications mentioned? This is answered in the
next section.
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Figure 2 Target applications for CoolSiCTM
In all of these applications SiC gives a high value proposition if a topology uses the internal body diode for short
usage or for body diode operation in switching frequency of more than 8 kHz.
One of these topologies is the Continuous Conduction Mode (CCM) totem pole PFC, which is a bridgeless
topology and by nature suitable for bi-directional operation, including highest possible efficiency compared to
nearly all available PFC topologies.
2.3 Focus topologies

Standard server and telecom applications consist of two stages: first the AC-DC conversion, and second a DC-
DC conversion as represented in the following image, based on a full-bridge CCM totem pole PFC and an LLC
converter.
Figure 3 Example SMPS
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2.3.1 CCM totem pole PFC (or representative for any hard-switching bridge
configuration)
The principle of operation of the CCM totem pole PFC is simplified and divided into four phases over one AC
cycle – two phases for the positive and two for the negative cycle of the input voltage.
Positive AC-line cycle:
The low-ohmic superjunction (SJ) MOSFET (SJ2) is continuously conducting. During the magnetizing phase the
SiC MOSFET (SiC2) is turned on and operates as in a standard PFC, which is necessary in order to magnetize the
PFC choke. After SiC2 is turned off, the body diode of SiC1 is conducting and finally actively turning on SiC1, and
the demagnetizing phase starts. During this time SiC1 acts as a synchronous boost. At exactly the same time as
the synchronous boost turns off, there is a short period in which the body diode of SiC1 is conducting again and
SiC2 is actively turned on, which leads to a hard commutation on the conducting body diode. This means this
hard commutation is present in every switching cycle on one of the SiC MOSFETs, and therefore the switching
energy and the losses increase during this turn-on based on the Qrr and the Qoss.
Figure 4 Operating principle of positive AC-line cycle
Negative AC-line cycle:
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The negative AC-line cycle operation is exactly the same as the inverted positive AC-line cycle. In this case the
low-ohmic SJ MOSFET (SJ1) is continuously conducting. During the magnetizing phase the SiC MOSFET (SiC1) is
turned on and operates as in a standard PFC, which is necessary in order to magnetize the PFC choke. After
SiC1 is turned off, the body diode of SiC2 is conducting and finally actively turning on SiC2, and the
demagnetizing phase starts. During this time SiC2 acts as a synchronous boost. As can be seen in this topology,
the already mentioned lowest possible Qrr and Qoss are required, as during every switching cycle there is a hard
commutation on the conducting body diode.
Figure 5 Operating principle of negative AC-line cycle
For this reason the SiC MOSFET and its related technology parameters are the optimum choice to easily achieve
99 percent efficiency.
2.3.2 LLC (or representative for any resonant switching bridge configuration)
Due to the low Qrr and Qoss CoolSiCTM can give the system on the one hand an increased system reliability in
abnormal operating conditions, and fast changes in switching frequency due to e.g. load jumps, and on the
other hand higher efficiency and the possibility to boost the switching frequency due to easily achievable full
Zero Voltage Switching (ZVS) under any load condition and/or reduction of the resonant current in order to
achieve full ZVS operation.
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The next chapter describes the CoolSiCTM technology parameters compared to the most well-known
technology, CFD7, before looking at the results in the application testing.
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Technology parameters
3 Technology parameters
This chapter will describe the most important technology parameters and give general recommendations for
using CoolSiCTM.
3.1 RDS(on) junction over-temperature

One of the most important benefits of CoolSiCTM describes the thermal characteristics of the on-state
resistance. In all device datasheets the typical RDS(on) is represented at 25°C junction temperature. Usually the
devices operate at higher junction temperatures, so it is also necessary to know the RDS(on) at higher
temperatures, for example at 100°C.
The junction temperature can be seen on the X-axis, and on the Y-axis the normalized RDS(on) is visible. The gray
line correlates to the CoolMOSTM and the blue line to the CoolSiCTM devices. It is shown that at 25°C the RDS(on) is
the same for CoolMOSTM and CoolSiCTM. This 25°C value is represented in the datasheets and in the naming
convention.
Figure 6 Normalized RDS(on) over-temperature comparison between CoolMOSTM and CoolSiCTM
The multiplication factor from 25°C to 100°C to the RDS(on) is 1.67 for CoolMOSTM and 1.13 for CoolSiCTM. This
means that in order to have the same conduction losses (𝑃𝑐𝑜𝑛𝑑 = 𝐼 2 ∙ 𝑅𝐷𝑆(𝑜𝑛) (𝑇𝐽 )) of CoolMOSTM and CoolSiCTM
it is possible to design-in a higher RDS(on) for CoolSiCTM. Ideally there is the potential for CoolSiCTM 84 mΩ to have
the same conduction losses as a 57 mΩ CoolMOSTM at 100°C. Beside of the same conduction losses, CoolSiCTM
also enables lower switching losses and lower cost.
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3.2 Qrr – reverse recovery charge

As already anticipated, the reverse recovery charge (Qrr) is one of the most important parameters for any
resonant topology, or any topology that has a continuous hard commutation on a conducting body diode. Such
a topology is the already explained CCM totem pole PFC. The Qrr is the charge that needs to be removed from
the body diode after it is conducting. In the diagram the Qrr is shown as the area below the 0 A line.
Figure 7 Simplified explanation for Qrr measurement
CoolMOSTM has already found ways to improve or reduce the Qrr of the body diode, which came out as a fast
diode device like the CFD or CFD7. Nevertheless, this charge is still too much in order to achieve high efficiency
values in the CCM totem pole PFC, but now the CoolSiCTM can be used. CoolSiCTM has 10 times lower charge than
the best fast diode SJ MOSFET available on the market.
Figure 8 Qrr comparison between CoolMOSTM, CoolMOSTM fast diode and CoolSiCTM
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It is only because of this behavior that CoolSiCTM is able to achieve more than 99 percent peak efficiency in the
PFC stage.
3.3 V(BR)DSS – drain-source breakdown voltage

In general the behavior of the breakdown voltage from CoolSiCTM and CoolMOSTM is equal; the main difference is
that CoolSiCTM has a lower slope, as can be seen in Figure 9, in which the X-axis corresponds to the junction
temperature and the Y-axis represents the breakdown. One very important difference is that at lower
temperatures the breakdown voltage is higher than compared to CoolMOSTM, which is beneficial for customers
for outdoor applications or applications that start up at lower temperatures. CoolSiCTM has a rated breakdown
voltage of 650 V at 25°C for the whole portfolio.
Figure 9 V(BR)DSS comparison between CoolMOSTM and CoolSiCTM
It is never recommended to apply voltages above the rated breakdown voltage even during switching
transients and abnormal operation conditions.
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3.4 Transfer characteristics

This technology parameter is very important as it describes how much current can be transferred via the
channel and the dependency on the gate-source voltage.
Figure 10 Transfer characteristics comparison between CoolMOSTM and CoolSiCTM at VDS = 20 V;

TJ = 25°C (upper) and TJ = 150°C (lower)
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In these two graphs the X-axis describes the gate-source voltage and the Y-axis the transferable drain current.
The straight gray line represents the CoolMOSTM and the straight blue line the CoolSiCTM device. The dashed
lines always represent the different RDS(on) classes of CoolSiCTM. The additional lines are included in all
technology parameters due to the RDS(on) over-temperature behavior. The upper graph shows the transfer
characteristics at 25°C and the lower graph shows them at 150°C.
As can be seen, the transfer characteristics here also follow the same basic principles. Nevertheless, CoolSiCTM
shows up to 20 V gate-source voltage with no saturation, unlike CoolMOSTM, which saturates at around 10 V. It is
also clear to see why for CoolSiCTM the 18 V driving voltage is recommended in order to enable driving the
current required by the application. This does not mean that CoolSiCTM cannot be driven with lower gate-source
voltage – it absolutely can – but customers need to consider which drain current they need in their application
and not operate it in linear mode.
Another very important benefit of CoolSiCTM is again visible due to the RDS(on) over-temperature behavior; the
transfer characteristics show nearly no impact at 150°C. This means that at 25°C ideally CoolMOSTM can transfer
higher currents, but the higher the temperature gets the worse is the behavior of CoolMOSTM in comparison to
CoolSiCTM.
3.5 Coss – output capacitance

The output capacitance for both technologies as it is a very important indicator with respect to switching speed
and EMI behavior. In this graph it is visualized that CoolMOSTM CFD7 offers much lower output capacitance than
CoolSiCTM with the same typical RDS(on) at 25°C above 50 V drain-source voltage.
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Figure 11 Typical Coss of CoolMOSTM and CoolSiCTM
This indicates that CoolMOSTM has the capability to offer lower Eoss, which is the energy stored in the output
capacitance that needs to be dissipated during a non-zero-voltage turn-on, allowing for higher switching speed
and lower switching losses. However, lower output capacitance at higher voltages may lead to a higher
sensitivity of PCB behavior and design parasitics, including drain-source voltage overshoots during turn-off,
resulting in higher RG usage for CoolMOSTM. At voltages below 50 V drain-source voltage, CoolSiCTM offers lower
capacitances than CoolMOSTM, therefore representing a much more linear output capacitance behavior. A
higher output capacitance at higher voltages does not directly mean there is no benefit from this capacitance.
The benefit of a higher Coss at higher voltages is directly interlinked with the “ease of use” in target applications
and a direct indicator for the switching losses. In Figure 12 a comparison in the same 3 kW LLC converter during
start-up is shown. The marked waveform is the drain-source voltage peak. It can be clearly seen that due to the
higher output capacitance the CoolSiCTM does not need to be manually slowed down via the external gate
resistor in order to stay within de-rating guidelines of 80 percent VDS,max.
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Figure 12 VDS overshoot during start-up in 3 kW LLC converter
Typically, customers are used to 80 percent de-rating on the drain source voltage, which means that the
maximum allowed drain-source voltage peak is 80 percent of the rated blocking voltage in the datasheets. In
order to have this de-rating guideline applied it is necessary to manually slow down the switching speed of the
CoolMOSTM with an external turn-on gate resistor of 47 Ω. Meanwhile, on the right-hand side the external gate
resistor for CoolSiCTM is adjusted to 0 Ω while still having more than 80 percent de-rating. This external gate
resistor has a big impact on the switching losses during turn-off, especially if the turn-off current is increased.
As result CoolSiCTM offers much greater ease-of-use with respect to voltage peaks.
Based on the Coss the next two parameters can be directly derived from this parameter.
3.6 Eoss – energy stored in output capacitance/Qoss – charge in the output

capacitance
The Eoss is derived by:
400 𝑉
𝐸𝑜𝑠𝑠 = ∫ 𝐶𝑜𝑠𝑠 ∙ 𝑉 𝑑𝑉
0
and the Qoss by:

400 𝑉
dV
𝑄𝑜𝑠𝑠 = ∫ 𝐶𝑜𝑠𝑠 ∙ d𝑡
dt
0
The following diagram illustrates the Eoss in µJ on the Y-axis and the related drain-source voltage on the X-axis.
Due to the higher output capacitance at voltages above 50 V also the related the energy stored in the output
capacitance which needs to be dissipated during a non-zero-voltage turn-on is 400 V higher than the CoolMOSTM
counterpart compared to the same typical RDS(on). This leads to the assumption that the hard-switching turn-on
losses at 400 V bulk voltage are around 1.5 times higher than CoolMOSTM. Despite this fact, the Eoss is much
smaller than the real turn-on losses in a CCM totem pole PFC, as this also depends on the Qoss and the Qrr of the
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devices. It can also be seen that using the RDS(on) over-temperature benefit from CoolSiCTM and comparing the
72 mΩ against the CoolMOSTM counterpart the Eoss drawback is once again on the same level.
Figure 13 Eoss comparison between CoolMOSTM and CoolSiCTM
As already anticipated, CoolSiCTM can be used in the high-efficiency CCM totem pole PFC, while CoolMOSTM
cannot. This technology parameter is one key parameter which makes this possible. During hard commutation
on a conducting body diode the Qoss also needs to be discharged accordingly, leading to additional losses. In
this case the CoolSiCTM offers around 75 percent lower Qoss at 400 V.
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Figure 14 Qoss comparison between CoolMOSTM and CoolSiCTM
This difference arises from the linear output capacitance of CoolSiCTM. Especially in the region of less than 50 V
drain-source voltage the CoolMOSTM has one or two orders of magnitude higher Coss, resulting in a big step of
the Qoss. The Qoss is also related in resonant topologies that define the current and time, which is necessary in
order to achieve full ZVS operation. As the charge is described by current multiplied by time designers can
reduce either the necessary recirculating current or the time resulting on one side on the reduced losses, and
on the other side there is the possibility to increase switching frequency.
There is one drawback for CoolSiCTM related to the lower Qoss and the body diode, which will be described in the
following section.
3.7 VSD (VF) – forward voltage of the body diode

As already visible in the Qrr analysis, the body diode of CoolSiCTM shows ruggedness never seen before in any
silicon counterpart. Nevertheless, the forward voltage is around four times higher than the body diode of a
CoolMOSTM.
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Table 1 Forward voltage comparison between IMZA65R048M1H and IPW60R070CFD7

Parameter CoolSiCTM CoolMOSTM
VF,typical at IF = 15 A and 25°C 3.6 V 1V
This leads to the fact, that if customers intend to use the CoolSiCTM in a plug-and-play scenario without
adapting or reducing the body diode conduction time, the body diode conduction losses will be around four
times higher at the same diode current. This can impact the light load efficiency in an LLC converter depending
on the output power up to 0.5 percent, which will be described in the benchmark section of this application
note. A very important point is also that in order to achieve the highest possible peak efficiency in a CCM totem
pole PFC, it is necessary to boost via the channel and not the body diode.
3.8 QG – gate charge

The final technology parameter is the gate charge. The gate charge is an indicator of how quickly a device can
be turned on and off. Furthermore, it describes the charge needed in order to fully activate the device, resulting
in an indicator for switching losses.
The diagram shows the gate charge on the X-axis and the gate-source voltage on the Y-axis. In this comparison
it can be seen that the CoolSiCTM has around 50 percent lower gate charge in order to turn on the device with
the same typical RDS(on).
Figure 15 QG comparison between CoolMOSTM and CoolSiCTM
CoolMOSTM has a clear plateau visible, which is the so-called Miller plateau derived from the Miller capacitance,
also known as gate-drain capacitance CGD. CoolSiCTM does not show a plateau like CoolMOSTM, which is the so-
called Drain Induced Barrier Lowering (DIBL) where the electric field from the drain of the chip starts to act on
the channel by depleting it. In the DIBL VGS(th) decreases with increasing drain-source voltage.
CGS is still being charged during this Miller plateau. With the opening channel, e.g. decreasing VDS, more and
more charges in the channel have to be controlled by the gate, so they contribute to charging the CGS. In long-
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channel devices such as the CoolMOSTM the plateau is flat, because all charges in the channel are independent
of the VDS; for example, they are always completely controlled by the gate electrode. So once the channel is
open, the gate electrode must provide charges for CGD (which is changing because of the drift zone filling with
mobile carriers), but not for CGS, hence the plateau.
Now that the technology differences are known, the following section will focus on some application-related
guidelines and also some application benchmarks.
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Design guidelines
4 Design guidelines
The first guideline will describe the positive and negative aspects related to the gate driving.
4.1 Gate driving

One of the benefits of this Wide Bandgap (WBG) technology is the possibility of using standard gate drivers like
CoolMOSTM, as it is operating is the same way. Nevertheless, customers should consider one very important
factor: Infineon recommends a driving voltage from 0 V to 18 V.
In general, customers should not use negative gate driving – this will be explained later in this document. The
18 V gate driving can be very beneficial to the customer, as there is the chance to reduce the RDS(on) by around 18
percent if not using 15 V. CoolSiCTM can also be driven at lower voltages like CoolMOSTM; nevertheless, the RDS(on)
will have a negative effect when operating in this condition.
Figure 16 RDS(on) dependency on VGS
This diagram clearly describes the RDS(on) dependency of the gate voltage. On the Y-axis the RDS(on) is represented
in absolute values. On the X-axis the junction temperature is visible. Comparing the RDS(on) with the 15 V gate-
source voltage, the red line and the 18 V gate-source voltage, and the light blue line at 60°C, it is possible to see
that the RDS(on) changes from 34 mΩ to 28 mΩ, which can have a big impact, especially under full-load condition.
4.2 Negative gate-source voltage

Now to explain the negative gate-source voltage. Negative gate-source voltage can have two root causes. First
of all, the inductive-driven gate-source voltage oscillation during turn-off, which is mainly driven by turning off
at high di/dt, which generates a voltage drop over the source inductance inside the gate-drive loop.
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Design guidelines
Figure 17 Root causes of negative VGS
The second root cause is the capacitive-driven negative gate-source voltage, which is coupled via the CGD of the
MOSFET by having high dv/dt transients from the second switch in a half-bridge configuration. For both of
these root causes, there are ways to improve or reduce the effect on the gate, but before starting to explain the
solution the impact needs to be clarified.
Negative gate-source voltages below -2 V can influence the threshold voltage and the resulting RDS(on) over the
lifetime, depending on operation frequency, duration and amplitude of the negative voltage. The 650 V
CoolSiCTM was performing a long-term test in the target application with the following test parameters.
Figure 18 Test parameters to see the impact of negative VGS in the CCM totem pole PFC
After applying these test parameters, characterization of the devices used and using a calculation model we
observed a threshold voltage increase by 600 mV, which results in an RDS(on) increase of 8 percent after 15 years.
This additional RDS(on) after 15 years of life is implemented in the maximum RDS(on) rating in the final datasheets.
For more information about this phenomenon please refer to application note AN2018-09.
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Design guidelines
As the root causes and the effect are described, the solutions to these challenges also need to be discussed. The
capacitive-driven negative gate-source voltage was seen as the greatest challenge, as it has the highest impact
on the drift. One solution for both root causes is to manually reduce the di/dt and dv/dt, but this would result in
increased switching losses and therefore reduced efficiency, so this solution will not be described further.
The use of a diode clamp can be the solution for both the capacitive- and inductive-driven root cause, and is
the recommended solution. In these two waveforms the gate-source voltage is shown, and it is possible to
directly see that there is no VGS lower than -2 V and therefore no VGS(th) drift. It is very important that the diode is
located close to the power device.
Figure 19 Impact of diode clamp
For the inductive-driven root cause the source impedance in the gate-drive loop can be reduced by splitting the
common source to a power source and driver source concept, which is represented in the two simplified
circuits. In these conditions there is now high di/dt, as shown by the gate during turn-off and therefore not
under-voltage peak. Figure 20 describes the simplified circuits for a standard source connection, the Kelvin
source connection and the diode gate clamp. Therefore, in order to reduce unwanted re-turn-on the driver
needs to be placed as close as possible to the power device.
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Design guidelines
Figure 20 Diode clamp recommendation for standard and Kelvin source connection
Please be aware also that the parasitic gate inductance can have an impact on the negative VGS. The Kelvin
source configuration applies an additional benefit, which is described next.
4.3 Kelvin source configuration

Infineon Technologies has been offering products with Kelvin source connection for years, as Infineon really
wants to achieve the best efficiency and performance in customer applications. Figure 21 shows the impact of
the Kelvin source with respect to the switching losses Eon and Eoff on the Y-axis over the drain current on the X-
axis. Especially in a totem pole configuration, the Eon values are the point of interest.
Figure 21 Comparison of switching energies of standard and Kelvin source configuration
In a 3.3 kW totem pole PFC at a 90-degree phase angle, the turn-off current reaches around 25 A to 30 A. As can
be seen, the Eon losses of this device are heavily dependent on the drain current. The higher the current, the
greater the benefit for the designer with respect to switching losses. With the conditions mentioned there are
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Design guidelines
up to three times lower switching losses. Assuming an average 13 A at 3.3 kW over the AC cycle and 65 kHz
switching frequency this results in 3.9 W, which must additionally be dissipated over one MOSFET only due to
switching losses.
As the overall CoolSiCTM technology is very similar to CoolMOSTM with respect to usage, all other restrictions are
valid for both technologies and are therefore not described further in this document.
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Benchmarking in target applications
5 Benchmarking in target applications

As already anticipated this application note will first start to show Eon and Eoff measurements of CoolSiCTM for
the different RDS(on) classes. It is always very important to mention the Eon and Eoff values, which are heavily
dependent on the measurement set-up due to parasitic inductances, coupling capacitors, gate-drive loop,
operating conditions and more. Therefore, these values are not implemented in CoolSiCTM datasheets, as the
values probably do not represent the behavior in end customer designs.
5.1 Switching energies (Eon and Eoff)

The represented data is measured in the following set-up:
Figure 22 Test set-up for Eon and Eoff measurements (double-pulse set-up)
As can be seen, the Eon values include the losses related to the hard commutation on a conducting body diode,
which represents the standard operation in a CCM totem pole PFC. For further information related to the
measurement set-up please see application note AN2017-44.
With this test set-up it is possible to test IGBT and CoolSiCTM up to 900 V bulk voltage, and it is also suitable for
400 V bulk voltage and the assessment of switching losses of the 650 V CoolSiCTM.
The results represented will show the 27 mΩ, 48 mΩ and 72 mΩ typical RDS(on), launched in February 2020.
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Figure 23 Typical switching energies for IMZA65R027M1H
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5.2 3.3 kW CCM totem pole PFC

The CCM totem pole PFC is the highest-efficiency bridgeless topology, achieving efficiency higher than 99
percent peak. 99 percent efficiency is necessary to achieve system efficiency of an SMPS of above 98 percent.
This power supply is a 3.3 kW server power supply, a full Infineon solution using the IMZA6R048M1H as boost
stage including 600 V CoolMOSTM C7 17 mΩ devices as grid rectifier, Infineon 18 V auxiliary bias supply, XMC1404
and more. The input voltage is from 176 V AC to 360 V AC, fully capable of 3.3 kW output power at 400 V output
voltage and a switching frequency of 65 kHz. This board can also be equipped with the newest static switch
from Infineon technologies, the 600 V CoolMOSTM S7.
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Figure 26 3.3 kW CCM totem pole PFC
Figure 27 shows the absolute efficiency over the output power at 230 V AC input voltage and 25°C ambient
temperature, which was possible to achieve with the IMZA65R048M1H. The gray line corresponds to the
IMZA65R048M1H, which has more than 99 percent from 20 percent to 50 percent of load. Even with the
IMZA65R072M1H it is possible to achieve 99 percent peak efficiency and full capability to deliver the output
power down to 176 V AC. Also the IMZA65R107M1H is able to come close to 99 percent peak efficiency and can
operate up to 3.3 kW at 230 V AC; nevertheless, by decreasing the input voltage the output power also needs to
be reduced due to thermal management. If the customer is willing to reduce the output power at lower input
voltages it can lower costs significantly.
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Figure 27 Efficiency comparison between CoolMOSTM and CoolSiCTM
The best calculated efficiency which can be achieved in a dual-boost PFC by CoolMOSTM is represented as a
green line with a peak efficiency of 98.85 percent; nevertheless, this might result in an increased Bill of Materials
(BOM) cost due to the use of a synchronous grid, additional magnetics and space restrictions. It would be
possible to further improve the efficiency using CoolMOSTM in a TCM totem pole PFC; this would result in much
higher driving and controlling complexity, and once again a higher part count.
All restrictions on VGS and 80 percent de-rating on VDS are applicable for CoolSiCTM, and the best measurement
results in this design are obtained by the following external gate resistor selection.
Table 2 Used RG,ext values for the 3.3 kW CCM totem pole PFC
Device RG,ext [Ω]
IMZA65R048M1H 6.4
IMZA65R072M1H 10
IMZA65R107M1H 15
In order to operate the IMZA65R107M1H at lower input voltages and benefit from lower costs in a CCM totem
pole PFC it is necessary to reduce the output power based on the decreased input voltage. According to this
measurement the mold compound temperature was kept constant at 80°C at 25°C ambient.
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Figure 28 Power de-rating need for low Vin for IMZA65R107M1H
In order to verify that the junction temperature is not exceeding the limit in the datasheet at 60°C ambient the
assumption based on simulations is taken that the junction in this system has around 20°C higher temperature
than the mold compound. Under these conditions there is still enough safety margin. It can be clearly seen that
it is possible to have full output power down to 220 V AC. Further increasing the input voltage leads to an
output power de-rating down to 2.5 kW at 176 V AC input voltage.
5.3 3 kW LLC converter

Due to the described technology parameters CoolSiCTM is also a very good fit for resonant topologies like the
LLC converter. The body diode behavior can improve the system stability under certain operating conditions in
which a hard commutation can occur.
This test board is based on telecom requirements with an input voltage of 380 V DC and an output power of
3 kW at 54 V output voltage. For the measurements only one rail of the dual phase was chosen in order to see
the differences on the primary-side MOSFETs while not depending on the synchronous rectification on the
secondary stage.
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Figure 29 Relative efficiency comparison with optimized body diode conduction time
This set-up was introduced with CoolMOSTM, and so the measurements can only show a comparison with
maximum 14 V gate driving.
The diode conduction times of silicon carbide devices have been measured. From this, the diode losses have
been calculated and implemented in the efficiency curves in order to get an estimation of the resulting
efficiency in case optimized dead-times were used. This calculation has not been done for CoolMOSTM devices,
since diode conduction time ‒ due to non-optimal dead-times ‒ is an almost-negligible contribution to the
overall efficiency. With these considerations, CoolSiCTM can have around 0.5 percent higher efficiency,
especially at light load.
The diode conduction time is very important. The following efficiency comparison shows the impact of
CoolSiCTM forward voltage and an un-optimized dead-time setting. All devices present in this comparison have
ZVS. The board has a minimum dead-time of 200 ns, so a full optimization per device is not possible.
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Figure 30 Relative efficiency comparison with 200 ns body diode conduction time
This leads to long diode conduction times, which will in turn lead to lower efficiency. Therefore, customers
need to take special care of the dead-time changes and be aware that plug-and-play is generally not
recommended in any resonant topology.
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Summary
6 Summary
In summary:
CoolMOSTM:
 Cost-effective solution for SMPS up to 97 percent system efficiency
 Easy to use
 Most granular portfolio
 Proven quality
CoolSiCTM:
 Cost-effective solution for SMPS greater than or equal to 97 percent system efficiency
 Easy to use, with recommended driving voltage of 18 V turn-on and 0 V turn-off
 Indicated for high-power applications
 Most suitable in any application where hard commutation on a conducting body diode is present or might
occur
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Revision history
Revision history
Document Date of release Description of changes
version
Release of final version
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2020-01-16
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Edition 2020-01-16 The information contained in this application note is For further information on the product, technology,
given as a hint for the implementation of the product delivery terms and conditions and prices please
Published by only and shall in no event be regarded as a contact your nearest Infineon Technologies office
description or warranty of a certain functionality, (www.infineon.com).
Infineon Technologies AG condition or quality of the product. Before
81726 Munich, Germany implementation of the product, the recipient of this
application note must verify any function and other WARNINGS
technical information given herein in the real Due to technical requirements products may contain
© 2020 Infineon Technologies AG. application. Infineon Technologies hereby disclaims dangerous substances. For information on the types
any and all warranties and liabilities of any kind in question please contact your nearest Infineon
All Rights Reserved. (including without limitation warranties of non- Technologies office.
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AN_1907_PL52_1911_144109 intended application and the completeness of the
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respect to such application.

Coolsic™ Mosfet 650 V M1 Trench Power Device: An - 1907 - Pl52 - 1911 - 144109

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CoolSiC™ MOSFET 650 V M1 trench power device

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2 Overview of CoolSiC™ M1 SiC trench power device

Figure 1 Positioning of Infineon technologies for HV power switches

Infineon recommends the different technologies as follows:

2.2 Target applications

Figure 2 Target applications for CoolSiCTM

2.3 Focus topologies

Figure 3 Example SMPS

Figure 4 Operating principle of positive AC-line cycle

Negative AC-line cycle:

Figure 5 Operating principle of negative AC-line cycle

3.1 RDS(on) junction over-temperature

Figure 6 Normalized RDS(on) over-temperature comparison between CoolMOSTM and CoolSiCTM

3.2 Qrr – reverse recovery charge

Figure 7 Simplified explanation for Qrr measurement

3.3 V(BR)DSS – drain-source breakdown voltage

Figure 9 V(BR)DSS comparison between CoolMOSTM and CoolSiCTM

3.4 Transfer characteristics

Figure 10 Transfer characteristics comparison between CoolMOSTM and CoolSiCTM at VDS = 20 V;

3.5 Coss – output capacitance

Figure 11 Typical Coss of CoolMOSTM and CoolSiCTM

Figure 12 VDS overshoot during start-up in 3 kW LLC converter

3.6 Eoss – energy stored in output capacitance/Qoss – charge in the output

and the Qoss by:

Figure 13 Eoss comparison between CoolMOSTM and CoolSiCTM

Figure 14 Qoss comparison between CoolMOSTM and CoolSiCTM

3.7 VSD (VF) – forward voltage of the body diode

Table 1 Forward voltage comparison between IMZA65R048M1H and IPW60R070CFD7

3.8 QG – gate charge

Figure 15 QG comparison between CoolMOSTM and CoolSiCTM

4.1 Gate driving

Figure 16 RDS(on) dependency on VGS

4.2 Negative gate-source voltage

Figure 17 Root causes of negative VGS

Figure 19 Impact of diode clamp

4.3 Kelvin source configuration

Figure 21 Comparison of switching energies of standard and Kelvin source configuration

5 Benchmarking in target applications

5.1 Switching energies (Eon and Eoff)

Figure 23 Typical switching energies for IMZA65R027M1H

Figure 24 Typical switching energies for IMZA65R048M1H

Figure 25 Typical switching energies for IMZA65R072M1H

5.2 3.3 kW CCM totem pole PFC

Figure 26 3.3 kW CCM totem pole PFC

Figure 27 Efficiency comparison between CoolMOSTM and CoolSiCTM

Figure 28 Power de-rating need for low Vin for IMZA65R107M1H

5.3 3 kW LLC converter

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