Zilog Z80-CPU ‘Technical Manual Price: $7.50Copyright © 1976 by Zilog. All sights reserved, No part of this publication may he reproduced, stored in a retrieval sysiem, or transmitted, ia any form or by any means, electronic, mnechanical, photocopying, recording, or otherwise, ‘without the prior written pennission of Zilog Zilog assumes no responsibility for the use of any circuitry other then circuitry embodied in a Zilog product. No other circuit patent licenses are implied,TABLE OF CONTENTS Chapter 10 2.0 3.0 40 50 60 70 80 9.0 10.0 11.0 Introduction Z-80 CPU Architecure 2... Z-80 CPUPin Description... - CPUTiming, ee Z-80 CPU InstructionSet 2. ee Flags Summary of OP Codes and Execution Times .. Interrupt Response... bee Hardware Implementation Examples... 2... Fe Software Implementation Examples ©. 2... 0s bee Bleotrical Specifications... ee ee Page . 39 43 - 55 $9 6831.0 INTRODUCTION The term “microcomputer” has been used to describe virtually every. type of small computing device designed within the last few years, Tis term has been applied to everything from simple “microprogram- med” controllers constructed out of TTL MSI up to low end minicomputers with a portion ofthe CPU. constructed out of TTL LSI “bit slices.” However, the major impact ofthe LSI technology within the last few years has been with MOS LSI. With this technology, it is possible to fabricate complete and very power- ful computer systems with only afew MOS LSI components. ‘The Zilog Z-80 family of components isa significant advancement in the state-of-the art of micro: computers. These components can be configured with any type of standard semiconductor memory to generate computer systems with an extremely wide range of capabilities. For example, as few as two LS} circuits and three standard TTL MSI packages can be combined to form a simple controller. With additional ‘memory and I/O devices a computer can be constructed with capabilities that only a minicomputer could previously deliver. This wide range of computational power allows standard modules to be constructed by a user that can satisfy the requirements of an extremely wide range of applications, ‘The major reason for MOS LSI domination of the microcomputer market is the low cost of these few LSI components. For example, MOS LSI microcomputers have already replaced TTL logic in such applications as terminal controllers, peripheral device controllers, traffic signal controllers, point of sale terminals, intelligent terminals and test systems. In fact the MOS LSI microcomputer is finding its way into almost every product that now uses electronics and it is even replacing many mechanical systems such as weight scales and automobile controls. ‘The MOS LSI microcomputer market is already well established and new products using them are being developed at an extraordinary rate. The Zilog Z-80 component set has been designed to fit into this market through the following factors: 1. The Z.80 is fully software compatible with the popular 8080A CPU offered from several sources, Existing designs can be easily converted to include the Z-80 as a superior alternative. 2. The Z-80 component set is superior in both software and hardware capabilities to any other micro- computer system on the market, These capabilities provide the user with significantly lower hardware and software development costs while aso allowing him to offer additional features in his system, 3. A complete product line including full software support with strong emphasis on high level languages and a disk-based development system with advanced realtime debug capabilities is offered to enable the user to easily develop new products Microcomputer systems are extremely simple to construct using Z-80 components. Any such system consists of three parts: 1, CPU (Central Processing Unit) 2. Memory 3, Interface Circuits to peripheral devices ‘The CPU is the heart of the system, Its function is to obtain instructions from the memory and perform, the desired operations, The memory is used to contain instructions and in most cases data that is to be processed. For example, a typical instruction sequence may be to read data from a specific peripheral device, store it ina location in memory, check the parity and write it out to another peripheral device. Note that the Zilog component set includes the CPU and various general purpose 1/0 device controllers, while @ wide range of memory devices may be used from any source, Thus, all required components can be connected together ina very simple manner with virtually no other external logic. The users effort then becomes primarily one of software development, That is the user can concentrate on describing his prob: Jem and translating it into a series of instructions that can be loaded into the microcomputer memory. Zilog is dedicated to making this step of software generation as simple as possible, A good example of this is our assembly language in which a simple mnemonic is used to represent every instruction that the CPU can perform. This language is self documenting in such a way that from the mnemonic the user can understand exactly what the instruction is doing without constantly checking back to a complex cross listing.2.0 Z-80 CPU ARCHITECTURE A block diagram of the intemal architecture of the Z-80 CPU is shown in figure 2.0-1. The diagram shows all of the major elements in the CPU and it should be referred to throughout the following description, ttt Loe avon TP rBheams 2-80 CPU BLOCK DIAGRAM FIGURE 2.0-1 2.1. CPU REGISTERS The 2-80 CPU contains 208 bits of R/W memory that are accessible to the programmer. Figure 2.02 illustrates how this memory is configured into eighteen 8-bit registers and four 16-bit registers. All Z-80 registers are implemented using static RAM. The registers include two sets of six general purpose registers that may be used individually as 8-bit registers or in pairs as 16-bit registers, There are also two sets of. accumulator and flag registers Special Purpose Registers 1, Program Counter (PC), The program counter holds the 16-bit address of the current instruction being fetched from memory. The PC is automatically incremented after its contents have been transferred to the address lines, When a program jump occurs the new value is automatically placed in the PC, overriding the incrementer. 2. Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of a stack located ‘anywhere in external system RAM memory, The external stack memory is organized as & last-in first: ut (LIFO) file. Data can be pushed onto the stack from specific CPU registers or popped off of the stack into specific CPU registers through the execution of PUSH and POP instructions. The data popped from the stack is always the last data pushed onto it. The stack allows simple implementation ‘of multiple level interrupts, unlimited subroutine nesting and simplification of many types of data———— meaisvens intent | — wewonr vecron’” | ferns INDEX REGISTER Rinwose STACK POINTER SP 2-80 CPU REGISTER CONFIGURATION FIGURE 2.0-2 3. Two Index Registers (IX & IY). The two independent index registers hold a 16-bit base address that is used in indexed addressing modes. In this mode, an index register is used as a base to point to a region in memory from which data is to be stored or retrieved. An additional byte is included in indexed insteuetions to specify a displacement from this base. This displacement is specified as a two's complement signed integer. This mode of addressing greatly simplifies many types of programs, especially where tables of data are used. 4. Interrupt Page Address Register (1). The Z-80 CPU can be operated in a mode where an indirect call, to any memory location can be achieved in response to an interrupt. The I Register is used for this purpose to store the high order 8-bits of the indirect address while the interrupting device provides the lower &-bits of the address, This feature allows interrupt routines to be dynamically located anywhere in memory with absolute minimal access time to the routine. 5. Memory Refresh Register (R). The Z-80 CPU contains a memory refresh counter to enable dynamic memories to be used with the same ease as static memories. This 7-bit register is automatically incre- ‘mented after each instruction fetch, The data in the refresh counter is sent out on the lower portion of the address bus along with a zeftesh control signal while the CPU is decoding and executing the fetched instruction. This mode of refresh is totally transparent to the programmer and does not slow down the CPU operation, The programmer can load the R register for testing purposes, but this register is normally not used by the programmer. Accumulator and Flag Registers ‘The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers. The accumu: lator holds the results of 8-bit arithmetic of logical operations while the flag register indicates specific conditions for 8 or 16-bit operations, such as indicating whether or not the result of an operation is equal to zer0, The programmer selects the accumulator and flag pair that he wishes to work with with e single ‘exchange instruction so that he may easily work with either pair,General Purpose Registers Thete are two matched sets of general purpose registers, each set containing six 8-bit registers that may be used individually as 8:bit registers or as I G-bit register pairs by the programmer, One set is called BC, DE and HL while the complementary set is called BC’, DE and HL". AL any one time the programmer can select either set of registers to work with through a single exchange command for the entire set. In systems where fast interrupt response is required. one set of general purpose registers and an accumulator) flag register may be reserved fir handling this very fast routine. Only a simple exchange commands need be executed fo go between the routines. This greatly reduces interrupt service time by eliminating the require ‘ment for saving and retrieving register contents in the external stack during interrupt or subroutine process ing. These general purpose registers are used for a wide range of applications by the programmer. They also simplify programming, especially in ROM based systems whee little external read/write memory is available, 2.2 ARITHMETIC & LOGIC UNIT (ALU) ‘The 8-bit arithmetic end logical instructions of the CPU are executed in the ALU. Internally the ALU communicates with the registers and the external data bus on the internat data bus. The type of functions performed by the ALU include: Add Left or right shifts or rotates (arithmetic and logical) Subtract Increment Logical AND Decrement Logical OR Set bit Logical Exclusive OR Reset bit Compare Test bit 2.3. INSTRUCTION REGISTER AND CPU CONTROL As each instruction is fetched from memory, itis placed in the instruction register and decoded. The control sections performs this function and then generates and supplies all of the control signals necessary to read or write data from or to the registers, control the ALU and provide all required external control signals,@ 3.0 2-80 CPU PIN DESCRIPTION ‘The Z-80 CPU is packaged in an industry standard 40 pin Dual In-Line Package, The I/O pins are shown in figure 3.0-1 and the function of each is described below. Lice saree Les ts Ag (BUS. [a ay ee A Z80crU fact 4 mm —2al Pee a td se SSnnoe = . ao Reso Pay 10 Ps [am % 2.80 PIN CONFIGURATION FIGURE 3.01 AgAis Tristate output, active high, Ag-Ays constitute a 16bit adress bus. The ig dares bs provides the ade fo memory (up to 64K bytes) data exchanges and for I/O device data exchanges. UO addressing uses the 8 lower addres bits to allow the user to directly select up to 256 input or 256 output ors. Ap isthe least significant addres bit During refresh time, the lower Tits contain a valid refresh adress. DgD. Tristate input/output, active high. Dy constitute an 8bit bidirectional a data bus. The data bus is used for dats exchanges with memory and 10 % Output, active low. MF indicates that the current machine eye i the OP code fetch cycle ofan instruction execution, Note that during execution of Z-byte opcodes, Ml is generated as each op code byte is fetched. These ‘wo byte op-codes always begin with CBH, DDH, EDH or FDH. Mi also ‘ecurs with TORQ to indicate an interrupt acknowledge cycle. (Machine Cycle one) WREQ Tristate output, active low. The memory request signal indicates that the oe (Memory Request) address bus holds a valid address for a memory read ot memory write operation.TORO (Input/Output Request) RD (Memory Read) WR (Memory Write) RFSH (Refresh) HALT (Halt state) WAIT (Wait) iNT (Interrupt Request) Nat (Non Maskable Interrupt) ‘Tristate output, active low. The TORO signal indicates thatthe lower half of the address bus holds valid 1/0 address fora 1/0 tead or write operation. An TORQ signals also generated with an MI signal when an interrupt is being acknowledged to indicate that an interrupt response vector can be placed on the data bus Interrupt Acknowledge operations occur during My time while YO operations never occur during My time, Tristate output, active low. RD indicates thatthe CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should se thissgnal fo gte data onto the CPU data bus. Tri-state output, active low. WR indicates that the CPU data bus holds valid data to be stored in the addressed memory or I/O device, Output, active low. RFSH indicates that the lower 7 bits of the address bus contain a refresh address for dynamic memories and the current MREQ signal should be used to do a refresh read to all dynamic memories. Output, active low. HALT indicates that the CPU has executed 2 HALT soft- ‘ware instruction and is awaiting either a non maskable or a maskable inter- rupt (with the mask enabled) before operation can resume. While halted, the CPU executes NOP’s to maintain memory reftesh activity. Input, active low. WATT indicates to the Z-80 CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter wait states for as long as this signal is active. This signal allows memory or I/O devices of any speed to be synchronized to the CPU. Input, active low. The Interrupt Request signal is generated by I/O devices. A request will be honored at the end of the current instruction if the internal software controlled interrupt enable flip-flop (IFF) is enabled and if the 'BUSRO signal is not active. When the CPU accepts the interrupt, an acknowl edge signal (TORQ during Mj time) is sent out at the beginning of the next instruction cycle. The CPU can respond to an interrupt in three different modes that are described in detail in section 5.4 (CPU Control Instructions. Input, negative edge triggered. The non maskable interrupt request line has a higher priority than INT and is always recognized at the end of the current_ instruction, independent of the status of the interrupt enable flipflop. NMI automatically forces the Z-80 CPU to restart to location 0066}. The program ‘counter is automatically saved in the external stack so that the user can return to the program that was interrupted. Note that continuous WAIT cycles can prevent the current instruction from ending, and that a BUSRO will override NMI.RESET BUSRO (Bus Request) BUSAK (Bus Acknowledge) Input, active low, RESET forces the program counter to zero and initializes, the CPU. The CPU initialization includes: 1) Disable the interrupt enable flip-flop 2) Set Register I 3) Set Register R= 004, 4) Set Interrupt Mode 0 During reset time, the address bus and data bus go to a high impedance state and all control output signals go to the inactive state Input, active low. The bus request signal is used to request the CPU address bus, data bus and tri-state output control signals to go to @high impedance state so that other devices can control these buses. When BUSRO is activated, the CPU will set these buses to a high impedance state as soon as the current CPU machine cycle is terminated Output, active low. Bus acknowledge is used to indicate to the requesting device that the CPU address bus, data bus and tristate control bus signals have been set to their high impedance state and the external device can now control these signals, Single phase TIL level clock which requires only # 330 ohm pull-up resistor 10 +5 volts to meet all clock requirements,4.0 CPU TIMING ‘The Z-80 CPU executes instructions by stepping through a very precise set of a few basic operations. ‘These include: Memory read or write YO device read or write Interrupt acknowledge All instructions are merely a series of these basic operations. Each of these basic operations can take from three to six clock periods to complete or they can be lengthened to synchronize the CPU to the speed of | extemal devices. The basic clock periods are referred to as T cycles and the basic operations are referred to a8 M (for machine) cycles. Figure 4.0.0 illustrates how a typical instruction will be merely a series of specific M and T cycles. Notice that this instruction consists of three machine cycles (M1, M2 and M3). The first machine cycle of any instruction is a fetch cycle which is four, five or six T cycles long (unless length ened by the wait signal which will be fully described in the next section), The fetch cycle (MI) is used to fetch the OP code of the next instruction to be executed. Subsequent machine cycles move data between the CPU and memory or I/O devices and they may have anywhere-from three to five T cycles (again they ‘may be lengthened by wait states to synchronize the external devices to the CPU). The following para- ‘graphs describe the timing which occurs within any of the basic machiste cycles, In section 10, the exact, timing for each instruction is specified, we co (or cade Ftc! (emery Read) | Memory Wt) BASIC CPU TIMING EXAMPLE FIGURE 4.0-0 Al CPU timing can be broken down into a few very simple timing diagrams as shown in figure 4.0-1 ‘through 4.0-7, These diagrams show the following basic operations with and without wait states (wait states are added to synchronize the CPU to slow memory or I/O devices). 4.0-1. Instruction OP code fetch (MI cycle) 40-2. Memory data read or write cycles 403. YO read or write cycles 4.04, Bus Request/ Acknowledge Cycle 40-5, Interrupt Request/ Acknowledge Cycle 40.6. Non maskable Interrupt Request/Acknowledge Cycle 40-7, Exit from a HALT instruction nINSTRUCTION FETCH Figure 4.0-1 shows the timing during en M1 cycle (OP code fetch). Notice that the PC is placed on the address bus atthe beginning of the MI cycle. One half clock time later the MREEQ signal goes ative. At this time the address to the memory has had time to stabilize so that the falling edge of MREO can be used directly asa chip enable clock to dyramie memories, The RD line also goes active to indicate thatthe ‘memory read data should be enabled onto the CPU data bus. The CPU samples the data from the memory on the data bus with the rising edge of the lock of state T3 and this same edge i wsed by the CPU to turn off the RD and MRO signals. Thus the data has already been sampled by the CPU before the RD signal becomes inactive. Clock state T3 and 7 of a fetch cycle are used to refresh dynamic memories. (The CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time). During T3 and T4 the lower 7 bits ofthe address bus contain a memory refesh address and the RFSHT signal becomes active to indicate that areitesh read of all dynamic memories should be accomplished. Notice that a RD signal is not generated during reftesh time to prevent data from different memory segments from being gated onto the data bus, The MREQ sina during rettesh time shouldbe used to perform a ettesh ead of all memory elements, The refresh signal can not be used by itself since the refresh address only guaran- teed to be stable during MREQ time. n 8 8 ‘ nl 6 Or TT. sovas TEREST INSTRUCTION OP CODE FETCH FIGURE 4.0-1 Figure 4,0-1A illustrates how the fetch cycle is delayed if the memory activates the WAIT line. Dur- ing T2 and every subsequent Tw, the CPU samples the WAIT line with the falling edge of ©. Ifthe WAIT line is active at this time, another wait state will be entered during the following cycle. Using this technique the read cycle can be lengthened to match the access time of any type of memory device.—— TTI ie AO ~ ANS Lt re =| CE FReSH ADDR. @ ans oe. » TT i INSTRUCTION OP CODE FETCH WITH WAIT STATES FIGURE 4.0-18 MEMORY READ OR WRITE Figure 4.0-2 illustrates the timing of memory read or write cycles other than an OP code fetch (MI cycle). These cycles are generally three clock periods long unless wait states are requested by the memory via the WATT signal. The MREQ signal and the RD signal are used the same as in the fetch cycle. In the ease of a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be used directly as chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that it can be used directly as a R/W pulse to virtually any type of semiconductor memory Furthermore the WR signal goes inactive one half T state before the address and data bus contents ave ‘changed so that the overlap requirements for victually any type of semiconductor memory type will be met. be } tency ea ye we many yee ———e} 6 TTT. 1 19-015 yore Zo ‘anes 1 F 1 IT wm Lites MEMORY READ OR WRITE CYCLES FIGURE 4.02Figure 4.0-2A illustrates how a WAIT request signal will lengthen any memory read or write opera- tion, This operation is identical to that previously described for a fetch cycle, Notice in this figure that a separate read and a separate write cycle are shown in the same figure although read and write cycles can, never occur simultaneously. 2 1 Lr 1 1 vo-axe “OL ORY RGR x mea 7. | S 7 4 J \esao Bees = — Jes am 1 oaranus TROT ra co | I I MEMORY READ OR WRITE CYCLES WITH WAIT STATES FIGURE 40-24, INPUT OR OUTPUT CYCLES Figure 4.0: illustrates an 1/0 read or /O write operation, Notice that during I/O operations a single wait state is automatically inserted. The reason for this is that during I/O operations, the time from when the TORQ signal goes active until the CPU must sample the WATT line is very short and without this extra state sufficient time does not exist for an 1/0 port to decode its address and activate the WAIT line if a wait is required, Also, without this wait state it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state time the WAIT request signal is sampled. During a read 1/O operation, the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read. For 1/0 write operations, the WR line is used asa clock to the I/O port, again with sufficient overlap timing automatically provided so that the rising edge may be used as a data clock. Figure 4.0-3A illustrates how additional wait states may be added with the WAIT line. The operation {s identical to that previously described. BUS REQUEST/ACKNOWLEDGE CYCLE Figure 40-4 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSRO signal is sampled by the CPU with the rising edge of the last clock period of any machine cycle. Ifthe BUS signal i active, the CPU will set its address, data and tri-state control signals to the high impedance state with the rising edge of the next clock pulse. At that time any external device can control the buses to transfer data between memory and I/O devices. (This is generally known as Direct Memory Access [DMA] using eycle stealing). The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external controller can maintain control of the bus for as many clock cycles a is desire. Note, however, that if very long DMA eycles ae used, and dynamic memories are being used, the external controller must also perform the refresh function, This situation only occurs if very lage blocks of data are transferred under DMA control Also note that during a bus request cycle, the CPU cannot be interrupted by either a NMI or an INT signal. e ®. ae er er rk vor IT FORT ADORESS ‘RG 1 { ——_S oT LY ase wm TL ee ai barxwus or ieee INPUT OR OUTPUT CYCLES FIGURE 4.0.3 aa 1 laa evete INPUT OR OUTPUT CYCLES WITH WAIT STATES. FIGURE 4.038a ° L cs = La au 1 See eee cece noma —— o~o7 + zs BUS REQUEST/ACKNOWLEDGE CYCLE FIGURE 40-4 INTERRUPT REQUEST/ACKNOWLEDGE CYCLE Figure 4.0.5 illustrates the ming associated with an interrupt cycle. The interrupt signal (INT) is ‘sampled by the CPU with the rising edge of the last clock at the end of any instruction. The signal will not be accepted ifthe internal CPU software controtled interrupt enable flip-flop is not set or if the BUSRO signal is active, When the signal is accepted a special MI cycle is generated. During this special M1 cycle the TORQ signal becomes active (instead of the normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. Notice that two wait states are automatically added to this cycle. These states are added so that a ripple priority interrupt scheme can be easily implemented. The two wait states allow sufficient time for the ripple signals to stabilize and identify which 1/O device must insert the response vector. Refer to section 8.0 for details on how the interrupt response veetor is utilized by the CPU. Lae M oe a pom ats Yt ¥ Trae w 1 eS L ORS 1 r INTERRUPT REQUEST/ACKNOWLEDGE CYCLE FIGURE 4.05Figure 4.0.54 illustrates how additional wait states can be added to the interrupt response cycle Again the operation is identical to that previously described, INTERRUPT REQUEST/ACKNOWLEDGE WITH WAIT STATES FIGURE 4.050, NON MASKABLE INTERRUPT RESPONSE Figure 4.0-6 illustrates the request/acknowledge cycle for the non maskable interrupt. This signal is sampled at the same time as the interrupt line, but this line has priority over the normal interrupt and it can not be disdbled under software conteol. Its usual function is to provide immediate response to important signals such as an impending power failure. The CPU response to a non maskable interrupt is similar to a rhormal memory read operation. The only difference being that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location 006644. The service routine for the non maskable interrupt must begin at this location if this interrupt is used HALT EXIT ‘Whenever a software halt instruction is executed the CPU begins executing NOP's until an interrupt is received (either a non maskable or a maskable interrupt while the intercupt flip flop is enabled). The two interrupt lines are sampled with the rising clock edge during each T4 state as shown in figure 4.0.7, Ifa non ‘maskable interrupt has been received ora maskable interrupt has been received and the interrupt enable Mip-lop is set, then the halt state will be exited on the next rising clock edge. The following cycle will then be an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If oth are ‘received at this time, then the non maskable one will be acknowledged since it has highest priority. The purpose of executing NOP instructions while in the halt stae isto keep the memory refresh signals active, Each eyele in the halt state is a normal M1 (fetch) eycle except that the data received from the memory is, ignored and a NOP instruction is forced internally to the CPU, The halt acknowledge signal is aetive during this time to indicate that the processor isin the halt stateLat eye bpp * 1 1 1 1 Ly \ 0 A38 I = L arm a 1 f REG 1 iol f "5 a l RH : —S NON MASKABLE INTERRUPT REQUEST OPERATION FIGURE 40-6 tsreceiveo HALT EXIT FIGURE 4075.0 Z-80 CPU INSTRUCTION SET The Z:80 CPU can execute 158 different instruction types including all 78 of the 8080 CPU ‘The instructions can be broken down into the following major groups: © Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (set, reset test) Jump, Call and Retuen Inpuy/Output © Basic CPU Control 5.1 INTRODUCTION TO INSTRUCTION TYPES The load instructions move data internally between CPU registers or between CPU registers and exter nal memory. All of these instructions must specify a source location from which the data is ta he moved and 2 destination location, The source location isnot altered by a load instruction, Examples of load group instructions include moves between any of the general purpose registers sch as move the data to Registes B from Register C. This group also includes load immediate to any CPU register ar t0-any external memory location, Other types of load instructions allow transfer between CPU registers and ‘memory leations, The exchange instructions can trade the contents of two registers, A unique set of block transfer instructions is provided in,the Z-80. With a single instruction a block of memory of any size can he moved to any other location in memory. This st of block moves {Sextremely valuable when lage strings of data must be processed. The Z-80 block search instructicns are also valuable for this type of processing, With a single instruction, a block of extemal memery of any desired length can be searched for any 8:bit character. Once the characteris found the instruction automatically terminates. Both the block transfer and the block search instructions can be interrupted, uring their execution so as to not occupy the CPU for long periods of time. ‘The arithmetic and logical instructions operate on data stored in the accumulator and other general purpose CPU registers or external memory locations. The results of the operations are placed in the accumulator and the appropriate flags are set according to the result of the operation, Ava example of an arithmetic operation is adding the accumulator to the contents of an external memory location. The results of the addition ate placed in the accumulator. This group also includes 1é-bit addition and subtraction between 16-bit CPU registers, The bit manipulation instructions allow any bit in the accumulator, any general purpose register or any external memory location tobe set, rest or tested with a single insttuction. For example, {he most significant bit of register 1 can be reset. This group is especially useful in control applications and for controlling software flags in general purpose programming, The jump, call and return instructions are used to transfer between various locations in the user's Program. This group uses several different techniques for obtaining the new program counter address from specific external memory locations, A unique type of jump isthe restart instruction, ‘This instruction actually contains the new address as a part of the 8-bit OP code. This is possible since only 8 separate addresses located in page zero ofthe external memory may be specified. Program jumps may alo be achieved by loading register HL, IX or IY directly into the PC, thus allowing the jump addvess to bea complex furction of the routine being executed.‘The inputjoutput group of instructions in the Z-80 allow for a wide range of transfers between, external memory locations or the general purpose CPU registers, and the extemal I/O devices. In each case, the port number is provided on the lower 8 bits of the address bus during any If transaction. One instruction allows this port number to be specified by the second byte of the instsuction ‘while other Z-80 instructions allow it to be specified as the content of the C register. One major ad ‘vantage of using the C register as a pointer to the I/O device is that it allows different 1/0 ports to share common software driver routines, This is not possible when the address is part of the OP code if the routines are stored in ROM. Another feature of these input instructions is that they set the flag register automatically so that additional operations are not required to determine the state of the input data (for example its parity). The Z-80 CPU includes single instructions that can move blocks of data (up to 256 bytes) automatically to or from any I/O port ditectly to any memory location, {In conjunction with the dual set of general purpose registers, these instructions provide for fest VO block transter rates, The value of this I/O instruction set is demonstrated by the fact that the 7-80 CPU can provide all required floppy disk formatting (i... the CPU provides the preamble, address, {data and enables the CRC codes) on double density floppy disk drives on an interrupt driven basis Finally, he basic CPU control instructions allow various options and modes, This group includes nstructions such as setting or resetting the interrupt enable flip flop or setting the mode of interrupt response, 5.2 ADDRESSING MODES Most of the Z-80 instructions operate on data stored in internal CPU registers, external memory cor in the YO ports, Addcessing refers to how the address of this data is generated in each instyuetion ‘This section gives a brief summary of the types of addressing used in the 7-80 while subsequent sections detail the type of addressing available for euch insteuetion group. Immediate, In this mode of addressing the byte following the OP code in memory contains the actual operand, OP Code] Pome or 2 bytes Operand 4. bg Excmples of this type of instruction would be to load the accumulator with a constant, where the constant is the byte immediately following the OP code. Immediate Extended. This mode is metely an extension of immediate addressing in that the two bytes following the OP codesare the operand. ‘OP code ] one or bytes Operand | low order Operand | high order Examples of this (ype of instruction would be to load the HL register pair (16-bit registed with Io bits (2 bytes) of data, 20Modified Page Zero Addressing. The Z-80 has a special single byte call instruction to any of 8 locations in page zero of memory, This insttuction (which is referted to as a restart) sets the PC to an effective address in page zero. The value of this instruction is that it allows a single byte to specify a complete 16bit address where commonly called subroutines are located, thus saving memory space. ‘OP Code ] one byte Eifective address is (bs by b3 000), Relative Addressing. Relative addressing uses one byte of data following the OP code to speci displacement from the existing program to which a program jump can occur, This displacement is 4 signed two's complement number that is added to the address of the OP code of the following instruction, OP Code | | Jump relative (one byte OP code) Operand | f° bit two's complement displacement added to. Address (A#2) The value of relative addressing is that it allows jumps to nearby locations while only requiring two bytes of memory space. For most programs, relative jumps ere by far the most prevalent type of jjunip due to the proximity of related program segments. Thus, these instructions can significantly Feduce memory space requirements. The signed displacement can range between +127 and -128 from A+ 2. Thisallows for a total displacement of +129 10 -126 from the jump relative OP code address Another major advantage is that it allows for relocatable code, Extended Addr Extended Addressing provides for two bytes (16 bits) of address to be included Inthe instruction, This data can be an addzess to which a program can jump or it can be an address is located, where an oper OP Code Sore or wo bytes Low Order Address or Low onder operand High Order Address or high order operand Extended addressing is required for & program 10 jump from any location in memory to aay other Location, or load and store data in any memory location, When extended addressing is used to specily the source or destination address of an operand, the notation (nn) will be used to indicate thecontent of memory at nn, where nn isthe L6-bit address specified in the insteuction. This means that the two bytes of address nn are used as a pointer to a memory location. The use of the parentheses always means that the value enclosed within them is used as a pointer to a memory location, For example, (1200) refers to the contents of memory at location 1200, Indexed Addressing. In this type of dressing, the byte of data following the OP code contains a displacement which is added to one of the two index registers (the OP code specifies which index fegister i used) 10 form a pointes to memory. The contents of the index register are not altered by this operation, OP Code two byte OP code OP Code Displacement | Operand added to index register to form a pointer to memory 27 , ae, ‘An example of an indexed instruction would be to load the conteris of the memory location (Index Register + Displacement ) into the accumulator. The displacement is a signed two's complement umber, Indexed addressing greatly simplifies programs using tables of data since the index register ‘can point to the start of any table, Two index registers are provided since very often operations require two or more tables, Indexed addressing also allows for relocatable code. ‘The two index registers in the Z-80 are referred to as IX and IY. To indicate indexed addressing the notation: (X44) or (1Y¥#8) is used, Here d is the displacement specified after the OP code, The parentheses indicate that this value is used as a pointer to external memory. Register Addressing. Many of the Z-80 OP codes contain bits of information that specify which CPU register isto be used for an operation. An example of register addressing would be to load the data in register B into register C. Implied Addressing. __ Implied addressing refers to operations where the OP code automatically implies one o more CPU registers as containing the operands, An example i the set of arithmetic ‘operations where the accumulator is always implied to be the destination of the results. Register Indirect Addressing, This type of addressing specifies a 16-bit CPU register pair (such as HL) to be used asa pointer to any location in memory. This type of instruction is very powerful and it is used in a wide range of applications. (OP Code ] Sone or two bytes ‘An example of this type of instruction would be to load the accumulator with the data in the memory location pointed to by the HL register contents, Indexed addressing is actually a form of register indirect. ‘addressing except that a displacement is added with indexed addressing Register indirect addressing allows for very powerful but simple to implement memory accesses. The block move and search commands in the Z-80 are extensions of this type of addressing where automatic register incrementing, decrementing and comparing has been added, The notation for indicating register indirect addressing is to put parentheses around the name of the register that is to be used as the pointer. For example, the symbol (aL) specifies that the contents of the HL register are to be used as a pointer to a memory location, Often register indirect addressing is used to specify 16-bit operands. In this case, the register contents point to the lower order portion of the operand while the register contents are automatically incremented to obtain the upper portion of the operand, Bit Addressing. The Z-80 contains a large number of bit set, reset and test instructions. These instructions allow any memory location or CPU register to be specified for a bit operation through one of three previous addressing modes (register register indirect and indexed) while three bits in the OP code specify which of the eight bits is to be manipulated. ADDRESSING MODE COMBINATIONS ‘Many instructions include more than one operand (such as arithmetic instructions or loads). In these cases, (wo types of addressing may be employed. For example, load can use immediate addressing to specify the source and register indirect or indexed addressing to specify the destination, 25.3. INSTRUCTION OP CODES This section describes each of the Z-80 instructions and provides tables isting the OP codes for every Instruction. In each of these tables the OP codes in bold type are identical to those offered in the 8080A ‘CPU, Also shown is the assembly language mnemonic that is used for each instruction. All instruction OP codes are listed in hexadecimal notation. Single byte OP codes require two hex characters while double byte OP codes require four hex characters. The conversion from hex to binary is repeated here for Hex Binary Decimal Hex Binary Decimal ° 0000 0 8 1000 8 1 0001 1 9 loot 9 2) el 0010) 2 A = 1010 = 10 3 ool 3 Bo= WH = WL 4 100 4 c = 100 = 12 5s = 10 5 D = no = 13 6 = ono 6 ee 0 a) 7 = ol = 7 Foe oul = 4s 2.80 instruction mnemonics consist of an OP code and zero, one or two operands. Instructions in which the operand is implied have no operand. Instructions which have only one logical operand or those in which one operand is invariant (such as the Logical OR instruction) are represented by a one operand ‘mnemonic, Instructions which may have two varying operands are represented by two operand mnemonics. LOAD AND EXCHANGE ‘Table 5.3-1 defines the OP code for all ofthe 8-bit load instructions implemented in the Z-80 CPU. Also shown in this table is the type of addressing used for each instruction. The source of the data is found. ‘on the top horizontal row while the destination is specified by the left hand column, For example, load register C from register B uses the OP code 48H. In all of the tables the OP code is specified in hexadecimal notation and the 48H (=0100 1000 binary) code is fetched by the CPU from the external memory during MI time, decoded and then the register transfer is automatically performed by the CPU. ‘The assembly language mnemonic for this entire group is LD, followed by the destination followed by the source (LD DEST. SOURCE). Note that several combinations of addressing modes are possible. For ‘example, the source may use register addressing and the destination may be register indirect; such as load the memory location pointed to by register HL with the contents of register D. The OP code for this ‘operation would be 72. The mnemonic for this load instruction would be as follows LD (HL), D ‘The parentheses around the HL means that the contents of HL are used as @ pointer to a memory location. In all 2-80 load instruction mnemonics the destination is always listed first, with the source following, The 2-80 assembly language has been defined for ease of programming, Every instruction is self documenting and programs written in Z-80 language are easy to maintain, Note in table 5,3-1 that some load OP codes that are available in the Z-80 use two bytes. This is an efficient method of memory utilization since 8, 16, 24 or 32 bit instructions are implemented in the Z-80. ‘Thus often utilized instructions such as arithmetic or logical operations are only 8:bits which results in better memory utilization than is achieved with fixed instruction sizes such as 16-its All load instructions using indexed addressing for either the source or destination location actually use three bytes of memory with the third byte being the displacement d. For example a load register E with the operand pointed to by IX with an offset of +8 would be written LDE,(IX +8) 2BThe instruction sequence for this in memory would be: Addres A [DD] OP Code ati [SF A+2[ 08] Displacement operand ‘The two extended addressing instructions are also three byte instructions. For example the instruetion to Joad the accumulator with the operand in memory location 6F32H would be written: LD A, (6F 3241) and its instruction sequence would be Address A [3A] OP Code +1 [32 | low order address +2 6F | high order address Notice that the low order portion of the address is always the frst operand, ‘The load immediate insteuctions for the general purpose 8-it registers are two-byte instructions. The instruction load register H with the value 36H would be written: LDH, 368 and its sequence would be: Address A [26] OP Code Att [36 | Operand Loading a memory location using indexed addressing for the destination and immediate addressing for the source requires four bytes. For example: LD (IX - 15), 21H would appear as: Address A [DD] ati [36 displacement (15 in AY 2] FI | ipned two's complement) A+3] 21] operand to load OP Code Notice that with any indexed addressing the displacement always follows directly after the OP code. Table 5.3-2 specifies the 16-bit losd operations. This table is very similar to the previous one. Notice that the extended addressing capability covers al register pais Also notice that register indirect operations specifying the stack pointer are the PUSH and POP instructions. The mnemonic for these instructions is SPUSHI” and “POP.” These differ from other 16-bit loads in that the stack pointer is automatically decre: ‘mented end incremented as each byte is pushed onto or popped from the stack respectively. For example the instewetion: 4PUSIAF is a single byte instruction with the OP code of FSH. When this instruction is executed the following sequence is generated: Decrement SP LD (SP) A Deorement SP LD (SP) F Thos the exter sack now per flows 8%) [Te fe top orstack sna + [sl sls Pelsd? |? ETS i ale FlF] ie : Fs 7] exrmanen | fo z = wer e FISTPLTPLPLE | = CI 8 BIT LOAD GROUP ene TABLES.3~1‘The POP instruction isthe exact reverse of a PUSH. Notice that all PUSH and POP instructions utilize a 16-bit operand and the high order byte is always pushed first and popped last. That isa PUSH BC is PUSH B then C PUSH DE. is PUSH D then E PUSHHL is PUSHH then L POP HL isPOP Lthen ‘The instruction using extended immediate addressing for the source obviously requires 2 bytes of data following the OP code. For example: LD DE, 06591 will be: Address A [11] OP Code Atl [59] Low order operand to register E A+2 [06 | High order operand to register D Inall extended immediate or extended addressing modes, the low order byte always appears fist after the OP code ‘Table 5.3.3 lists the 16-bit exchange instructions implemented in the Z-80. OP code OSH allows the programmer to switch between the two pairs of accumulator fla registers while D9H allows the pro: ‘grammer to switch between the duplicate set of six general purpose registers. These OP codes are only one byte in length to absolutely minimize the time necessary to perform the exchange so that the duplicate banks can be used to effect very fast interrupt response times, BLOCK TRANSFER AND SEARCH ‘Table 5.3-4 lists the extremely powerful block transfer instructions. All of these instructions operate with three registers. HL points to the source location. DE points to the destination location. BC is a byte counter. After the programmer has initialized these three registers, any of these four instructions may be used. The LDI (Load and Increment) instruction moves one byte from the location pointed to by HL to the location pointed to by DE. Register pairs HL and DE are then automaticaly incremented and are ready to point to the following locations, The byte counter (tegister pair BC) is also decremented at this time. This instruc- tion is valuable when blocks of data must be moved but other types of processing are required between each, move, The LDIR (Load, increment and repeat) instruction is an extension of the LDI instruction. The same load and increment operation is repeated until the byte counter reaches the count of zero. Thus, this single instruction can move any block of data from one location to any other. Note that since 16-bit registers are used, the size of the block can be up to 64K bytes (1K = 1024) Jong and it can be moved from any location in memory to any other location. Furthermore the blocks can. be overlapping since there ate absolutely no constraints on the data that is used in the three register pais. ‘The LDD and LDDR instructions are very similar to the LDI and LDIR. The only difference is that register pairs HL and DE are decremented after every move so that a block transfer starts from the highest address of the designated block rather than the lowest. 26source wlelelmlelalwl= | ale pestination | 7 i z . alee ct = * R | oo a Pie 5b} BP |e run glace | on Le oo | NOTE: ctr tet ie moar _ 188IT Loan cRouP “PUSHY AND “POP” TABLES? TaRTES ADORE AF [ecopane| wu | x v _ baru 0° [ = REG. | (sr) = po | fp EXCHANGES “CAND ERX’ TABLE S32 aco | tor tora eee) mo | nec Be, be Be co | tim — Leng oeb——imuy Ee 50 | eM & OE Bee Bo Repeat ent BC= 0 estimation [RES | (08) co [4007 — Load (OE) (HL) ne /Dectce BE, Bec Be be [eile BE bec 8c mapmrentac~0 | fe HL BLOCK TRANSFER GROUP TABLE 5.3-4 ‘Table 5.3-5 specifies the OP codes for the four block search instructions. The first, CPI (compare and increment) compares the data in the accumulator, with the contents of the memory location pointed to by. register HL. The result of the compare is stored in one of the flag bits (see section 6.0 for a detailed exph nation of the flag operations) and the HL register pair is then incremented and the byte counter (register pair BC) is decremented, ‘The instruction CPIR is merely an extension of the CPI instruction in which the compare is repeated until either a match is found or the byte counter (register pair BC) becomes zero, Thus, this single instruc tion can search the entire memory for any 8-bit character, The CPD (Compare and Decrement) and CPDR (Compare, Decrement and Repeat) ate similar instructions, their only difference being that they decrement HL after every compare so that they search the memory in the opposite direction. (The search is started at the highest location in the memory block), It should be emphasized again that these block transfer and compare instructions are extremely powerful in string manipulation applications. ARITHMETIC AND LOGICAL ‘Table 5.3-6 lists all of the 8-bit arithmetic operations that can be performed with the accumulator, also listed are the increment (INC) and decrement (DEC) instructions. In all of these instructions, except INC and DEC, the specified 8-bit operation is performed between the data in the accumulator and the source data specified in the table. The result of the operation is placed in the accumulator with the excep. tion of compare (CP) that leaves the accumulator unaffected. All of these operations affect the flag register as result of the specified operation. (Section 6.0 provides all of the details on how the flags are affected by any instruction type). INC and DEC instructions specify a register or a memory location as both source and destination of the result. When the source operand is addressed using the index registers the displacement must follow directly, With immediate addressing the actual operand will follow directly. For example the instruction: AND O7H would appear as Address A [6] OP Code avi[o7 | Operand 8toeation worn wo eo |e. 81 | reper untl 6 or find match S| ooecnvase fo | wow onmase 89 | Rene on 868 find mach eciebvts counter BLOCK SEARCH GROUP TABLE 53-5 ‘Assuming that the accumulator contained the value F3H the result of 03H would be placed in the accumulator: ‘Ace before operation 1111 0011 = F3H Operand 0000 0111 = O7H. Result to Ace (0000 0011 = 034 ‘The Add instruction (ADD) performs a binary add between the data in the source location and the data in the accumulator. The subtract (SUB) does a binary subtraction. When the add with carry is specified (ADC) or the subtract with carry (SBC), then the carry flag is also added or subtracted respectively, The ‘lags and decimal adjust instruction (DAA) in the Z-80 (fully described in section 6.0) allow arithmetic ‘operations for ‘multiprecision packed BCD numbers ‘ultiprecision signed or unsigned binary numbers ‘multiprecision two's complement signed numbers Other instructions in this group are logical and (AND), logical or (OR), exclusive or (XUK) and compare (CP). ‘There are five general purpose arithmetic instructions that operate on the accumulator or carry flag. ‘These five are listed in table 5.37. The decimal adjust instruction can adjust for subtraction as well as add= ition, thus making BCD arithmetic operations simple, Note that to allow for this operation the fag N is used, ‘This fag is set if the ast arithmetic operation was a subtract. The negate accumulator (NEG) instruction forms the two's complement of the number in the accumulator. Finally notice that a reset carry instruction is not included in the Z-80 since this operation can be easily achieved through other instructions such as & logical AND of the accumulator with itself Table 5.38 lists all of the 16-bit arithmetic operations between 16-bit registers. There are five groups of instructions including add with carry and subtract with carry. ADC and SBC affect all of the flags These ‘two groups simplify address calculation operations or other 1Gbit arithmetic operations. 2»source w]e fe fo fe fu [a fom fecafra] ais |e | | : =| wie le |e le | jm jo [os oS | =) | cmzcarmv | or [mf me fm foe fw | om fm |e [2 | oe mo fm | mf ar | me | ow] | om fae [2 |S | wow | we | me wolu [2 [2 | = ‘oR’ a | oo we [ee [as [be as | |e ie cowane [mr | pe} | a | wo | ac | wo [oe jor joe | re wonewenr [se | of oe [uta f ala im [8 [2 t oo fe ccm | [al wlw|wolal| mlm |» | 88IT ARITHMETIC AND Logic TABLES3-6 owns Ataraes oan |? conioneaner | at wy a, ne © - g open Gary Fi 6 | set cay i. 86F = GENERAL PURPOSE AF OPERATIONS TABLE 827 x0sounce sc | ve | mw | se | x | wv nw |e | |» | oo c= Ge i|tne) en & | % " f f 0 ‘|e |e & B DESTINATION jpwinncanny ano | wm | eo | eo | £0 | eo SePrtaas noe we | se | a | oe wuaurracanny ano | wu | > | eo | €0 | eo Serrines sec elafle|2 wenewenr we’ ws | @ [a | | 0 | Fo oeenewent vee [ee | w | am | m | 00 | #0 16 BIT ARITHMETIC TABLE 5:3-8 ROTATE AND SHIFT A major capability of the Z-80 is its ability to rotate or shift data in the accumulator, any general pur- pose register, or any memory Jocation. All of the rotate and shift OP codes are shown in table 5.3.9. Also included in the 2-80 are arithmetic and logical shift operations. These operations are useful in an extremely wide range of applications including integer multiplication and division. Two BCD digit rotate instructions (RRD and RLD) allow a digit in the accumulator to be rotated with the two digits in a memory location pointed to by register pair HL. (See figure S.3-9). These instructions allow for efficient BCD arithmetic, BIT MANIPULATION The ability to set, reset and test individual bits ina register or memory location is needed in almost every program, These bits may be flags ina general purpose software routine, indications of external con- trol conditions or data packed into memory locations to make memory utilization more efficient. ‘The 2-60 has the ability to set, reset or test any bit in the accumulator, any general purpose register ‘or any memory location with a single instruction, Table 5.3-10 lists the 240 instructions that are available for this purpose. Register addressing can specify the accumulator or any general purpose register on which the operation isto be performed. Register indirect and indexed addressing are available to operate on external memory locations. Bit test operations set the zero flag (Z)if the tested bit is a zero. (Refer to section 6.0 for further explanation of flag operation), JUMP, CALL AND RETURN Figure 5.311 lists all of the jump, call and return instructions implemented in the Z-80 CPU, A jump is branch in a program where the program counter is loaded with the 16-bit value as specified by one of the three available addressing modes (Immediate Extended, Relative or Register Indirect), Notice that the jump ‘group has several different conditions that can be specified to be met before the jump will be made, If these conditions are not met, the program merely continues with the next sequential instruction. The conditions are all dependent on the data in the flag register. (Refer to section 6.0 for details on the flag register). The immediate extended addressing is used to jump to any location in the memory. This im struction requires three bytes (two to specify the l6bit address) with the low order address byte first followed by the high order address byte. 31TPP PT i (] =o Eee Ge oS etal eee TH che] Geeta = ew Flelstelelele see we) See x am (= [el[als[s(2 [eels] Fle SS nae ~le(sis[e[sle| ste au ro Te fefels{sfe{ sls 2 we im fet | ROTATES AND SHIFTS TABLE 5.3-9 For example an unconditional Jump to memory location 3£32H woutd be: Address A [C3] OP Code +1 [32 | Low order address A+2[3E | High order address ‘The relative jump instruction uses only (wo bytes, the second byte is a signed two's complement dis- placement form the existing PC. This displacement can be in the range of +129 to -126 and is measured From the address of the instruction OP code. ‘Throe types of register indirect jumps ace also included. These instructions are implemented by loading the register pair HL or one of the index registers IX or IY dizectly into the PC. This capability allows for program jumps to be a function of previous calculations. ‘A call isa special form of a jump where the address of the byte following the call instruction is pushed onto the stack before the jump is made, A return instruction is the reverse ofa call because the ata on the top of the stack is popped directly into the PC to form a jump address, The call and return instructions allow for simple subroutine and interrupt handling. Two special return instructions have been jncluded in the 2-80 family of components. The turn from interrupt instruction (RET) and the return from non maskable interrupt (RETN) ate treated in the CPU as an unconditional return identical to the OP ‘code COH. The difference is that (RETI) can be used at the end of an interrupt routine and all Z-80 peripheral chips will ecognize the execution of this instruction for proper control of nested priority interrupt handling. ‘This instruction coupled with the Z-80 peripheral devices implementation simplifies the normal return from nested interrupt, Without this feature the Following soltware sequence would be necessary to inform the interrupting device that the interrupt routine is completed: 32 &ma] $s 3 2 S 2 3 2 3 Zz g 3 a TABLE 53-10 33Disable Interrupt prevent interrupt before routine is exited, LDAn — notify peripheral that service OUT HA routine is complete Enable Interrupt Return ‘This seven byte sequence can be replaced with the two byte RETI instruction in the Z-80, This is important since interrupt service time often must be minimized. To facilitate program loop control the instruction DINZ ¢ can be used advantageously. This two byte, ‘elative jump instruction decrements the B register and the jump occurs if the B register has not been decre- ‘mented to 2e10, The relative displacement is expressed as @ signed two’s complement number. A simple ex: ample of its use might be: Adaies Instruction Comments NNtI B7 {set Brepster to count of 7 N+210N+9 (Perform a sequence Gtiucion) stoop to be performed 7 ties NHIQNEH —DINZ 10 ‘Ho jump from N12 10N#2 N+i2 (Next Instruction) conorrion a@falapal|r @ pop | oa some ene, Jom |e fe fe fe fa |e . ext. me [ate fate a auwe sn’ [retanive|rc% | 19 | 2a | a | 2 | 20 mele ea| oe] oe ~ See SES Sere” are i RETURN fnecisren | sri | eo | oe | oo | cx | co | es | co | fe | Fo a Ene erenvo seerion Soran devalue JUMP, CALL and RETURN GROUP TABLE 53-11 4e Table 5.3-12 lists the eight OP codes for the restart instruction, This instruction is a single byte call to any of the eight addresses listed. The simple mnemonic for these eight calls is also shown. The value of this in- struction is that frequently used routines can be called with this instruction to minimize memory usage o 000, | or | nero” owe, | ex | sre § fom) OF | casrae t | 5 [tm | OF | onsrae 8 B | oozn,| © | stax 5 0028] €F | rast a0" 020, | | asta woe, | FF | -asrse RESTART GROUP TABLE 53-12, INPUT/OUTPUT ‘The Z-80 has an extensive set of Input and Output instructions as shown in table 5.3-13 and table 5.3-14. The addressing of the input or output device can be either absolute or register indirect, using the C register. Notice that in the register indirect addressing mode data can be transferred between the I/O devices, and any of the internal registers. In addition eight block transfer instructions have been implemented. These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to ‘the memory source (output commands) or destination (input commands) while register B is used as a byte counter. Register C holds the address of the port for which the input or output command is desired. Since register B is eight bits in length, the 1/0 block transfer command handles up to 256 bytes. In the instructions IN A, n and OUT n, A the 1/0 device address n appeats in the lower half of the add: ress bus (Ag-A) while the accumulator content is transfereed in the upper half of the address bus. In all reg- ister indirect input output instructions, including block I/O transfers the evintent of register C is transferred to the lower half of the address bus (device address) while the content of register B is transferred to the upper half of the address bus, 35