.AMD FP6 Motherboard Design Guide

AMD Confidential—Advance Information
FP6
Processor Motherboard Design
Guide
www.teknisi-indonesia.com
Publication # 56178 Revision: 1.03

Issue Date: January 2020
Advanced Micro Devices

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56178 Rev. 1.03 January 2020 FP6 Processor Motherboard Design Guide
Contents
List of Figures .....................................................................................................................................9
List of Tables .................................................................................................................................... 13
List of Abbreviations ....................................................................................................................... 16
Revision History.................................................................................................................................... 17
1 Introduction........................................................................................................................................20
1.1 Compatibility......................................................................................................................................................... 20
1.2 General Power Supply Guidelines......................................................................................................................... 21
1.3 Pinout Assignment................................................................................................................................................. 21
1.4 Package Information.............................................................................................................................................. 21
1.5 Reference Documents............................................................................................................................................ 21
2 System Overview................................................................................................................................24
2.1 Memory Overview................................................................................................................................................. 24
2.1.1 Memory Topology.................................................................................................................................. 25
2.1.2 Valid Memory Configurations................................................................................................................25
2.2 Display Overview.................................................................................................................................................. 25
2.3 Power Management Overview...............................................................................................................................26
3 PCB Planning..................................................................................................................................... 27
3.1 Stackups................................................................................................................................................................. 27
3.1.1 Six-Layer Stackup...................................................................................................................................27
3.1.2 Ten-Layer Stackup..................................................................................................................................27
3.1.3 Twelve-Layer Stackup............................................................................................................................ 28
3.2 Impedance.............................................................................................................................................................. 29
3.3 Trace Length Matching..........................................................................................................................................29
3.4 DDR Trace Routing Regions................................................................................................................................. 30
3.5 Crosstalk................................................................................................................................................................ 33
3.6 Routing of Differential Signals..............................................................................................................................34
3.7 Reference Planes....................................................................................................................................................35
3.7.1 Reference Plane—Microstrip..................................................................................................................35
3.7.2 Reference Plane—Stripline.....................................................................................................................35
3.8 Changing Reference Planes................................................................................................................................... 38
3.8.1 Stitching Vias..........................................................................................................................................39
3.8.2 Stitching Capacitors................................................................................................................................ 43
3.9 Point-to-point Routing........................................................................................................................................... 46
3.10 Non-Functional Pads on Vias and Connectors.................................................................................................... 46
3.11 Via Stubs..............................................................................................................................................................46
4 Clock Design Guidelines....................................................................................................................47

4.1 Differential Clock Design Guidelines....................................................................................................................47
4.1.1 General Differential Clock Schematic and Layout Requirements..........................................................47
4.1.2 Layer Assignments—Differential Clocks...............................................................................................47
4.1.3 Layout Guidelines—Differential Clocks................................................................................................ 48
4.2 Single-Ended Clock Design Guidelines.................................................................................................................49
Contents 3
FP6 Processor Motherboard Design Guide 56178 Rev. 1.03 January 2020
4.2.1 RTCCLK Real Time Clock (RTC) and Battery Interface...................................................................... 49

4.2.2 General Single-Ended Clock Layout Requirements............................................................................... 50
4.2.3 Layer Assignments—Single-Ended Clocks............................................................................................50
4.2.4 Layout Guidelines—Single-Ended Clocks............................................................................................. 50
5 Memory Design Guidelines............................................................................................................... 53

5.1 Memory Interface...................................................................................................................................................53
5.1.1 Signal Descriptions................................................................................................................................. 53
5.1.2 Memory Signals and Connections.......................................................................................................... 55
5.1.3 Memory Layer/Signal Assignments....................................................................................................... 60
5.1.4 Memory Length Matching...................................................................................................................... 62
5.2 UDIMM Memory Design Guidelines....................................................................................................................63
5.2.1 UDIMM Design Topology..................................................................................................................... 63
5.2.2 UDIMM Placement.................................................................................................................................64
5.2.3 UDIMM Layout Guidelines....................................................................................................................65
5.3 SO-DIMM Memory Design Guidelines................................................................................................................ 75
5.3.1 SO-DIMM Design Topology..................................................................................................................75
5.3.2 SO-DIMM Placement............................................................................................................................. 75
5.3.3 SO-DIMM Layout Guidelines—One DDR4 SO-DIMM ...................................................................... 78
5.4 DDR4 DRAM Down Memory Design Guidelines................................................................................................89
5.4.1 DDR4 DRAM Down Population Order..................................................................................................89
5.4.2 DDR4 DRAM Down Decoupling...........................................................................................................92
5.4.3 DRAM Down Layout Procedure............................................................................................................ 92
5.5 LPDDR4x DRAM Down Memory Design Guidelines....................................................................................... 113
5.5.1 LPDDR4x DRAM Down Layer Assignments......................................................................................113
5.5.2 LPDDR4x DRAM Down Placement.................................................................................................... 113
5.5.3 LPDDR4x DRAM Down Layout Guidelines....................................................................................... 115
6 PCIe® Link Design Guidelines....................................................................................................... 126
6.1 PCIe® Technology Overview.............................................................................................................................. 126
6.1.1 PCIe® Link Signals...............................................................................................................................126
6.1.2 PCIe® and SATA to M.2 Connector Routing.......................................................................................129
6.2 Layer Assignments—PCIe®................................................................................................................................ 131
6.3 PCIe® AC-Coupling Capacitors.......................................................................................................................... 131
6.4 Routing Guidelines for PCIe® Interface..............................................................................................................133
6.4.1 Layout Guidelines—PCIe® Interface to Onboard Devices.................................................................. 133
6.4.2 Layout Guidelines—PCIe® Interface to Connector............................................................................. 134
6.5 Length Matching—PCIe®................................................................................................................................... 136
6.6 Length Limits—PCIe® ....................................................................................................................................... 137
7 Display Interface Design Guidelines.............................................................................................. 138

7.1 DisplayPort Interface........................................................................................................................................... 138
7.1.1 StereoSync............................................................................................................................................ 140
7.2 DisplayPort Configurations................................................................................................................................. 140
7.2.1 DisplayPort Connectors (No DVI or HDMI™ Support).......................................................................142
7.2.2 Embedded DisplayPort Panel—eDP.....................................................................................................142
7.2.3 DisplayPort Plus Plus (DP++) Connector.............................................................................................145
7.2.4 DisplayPort to DVI Connector..............................................................................................................147
7.2.5 DisplayPort to HDMI™ Connector.......................................................................................................149
7.2.6 DisplayPort to LVDS and VGA Translator.......................................................................................... 153
7.3 Layer Assignments—DisplayPort....................................................................................................................... 155
7.4 DisplayPort AC-Coupling Capacitors..................................................................................................................156
7.5 Routing Guidelines for DisplayPort.....................................................................................................................158
4 Contents
7.5.1 Layout Guidelines—DisplayPort ML to DP or eDP Connectors......................................................... 158

7.5.2 Layout Guidelines—DisplayPort AUX Channel to DP or eDP Connectors........................................ 159
7.5.3 Layout Guidelines—DisplayPort ML to DP++ Connector.................................................................. 160
7.5.4 Layout Guidelines—DisplayPort AUX Channel to DP++ Connector................................................. 162
7.5.5 Layout Guidelines—DisplayPort ML to DVI or HDMI™ Connector..................................................163
7.5.6 Layout Guidelines—DisplayPort AUX Channel to DVI or HDMI™ Connector.................................164
7.5.7 Layout Guidelines—DisplayPort ML to Translator............................................................................. 165
7.5.8 Layout Guidelines—DisplayPort AUX Channel to Translator............................................................ 167
7.5.9 Layout Guidelines—DisplayPort Hot Plug Detect to Connector......................................................... 168
7.6 Length Limits—DisplayPort................................................................................................................................168
8 USB Interface Design Guidelines................................................................................................... 170

8.1 USB Interface Signals..........................................................................................................................................170
8.1.1 USB Controller to Port Mapping.......................................................................................................... 170
8.1.2 Layout Requirements for I/O Connectors Using Metal Shielding........................................................172
8.1.3 USB Micro-AB Connector Implementation Requirements..................................................................172
8.1.4 USB 3.2 Connector Voids.....................................................................................................................174
8.1.5 USB 2.0 Interface..................................................................................................................................180
8.1.6 USB 3.2 Interface..................................................................................................................................182
9 DisplayPort Alternate Mode/USB to USB-C® Connector Design Guidelines............................187

9.1 DisplayPort/USB AC-Coupling Capacitors and ESD Device Placement........................................................... 188
9.2 DisplayPort DP Alt Mode/USB-C® Layout Guidelines......................................................................................190
10 SATA Interface Design Guidelines...............................................................................................198

10.1 SATA Technology Overview............................................................................................................................ 198
10.1.1 SATA Miscellaneous Signals............................................................................................................. 198
10.1.2 SATA AC-Coupled Bus..................................................................................................................... 199
10.1.3 SATA Interface...................................................................................................................................200
11 Audio Interface Design Guidelines...............................................................................................203

11.1 HD Audio Interface Signals...............................................................................................................................203
11.2 I2S Bus Audio Interface Signals........................................................................................................................205
11.3 Wake on Voice (WoV) Interface Signals.......................................................................................................... 207
12 Secure Biometric Camera Solution.............................................................................................. 209

12.1 Secure Biometrics Introduction......................................................................................................................... 209
12.2 Secure Biometrics Overview............................................................................................................................. 209
12.3 Secure Biometrics Camera Solution Requirements...........................................................................................209
12.3.1 Secure Biometrics Camera Solution Overall Requirements...............................................................209
12.3.2 Secure Biometrics Camera Requirements.......................................................................................... 209
12.3.3 Secure Biometrics Platform Hardware Requirements........................................................................ 209
12.3.4 Secure Biometrics System Level Requirements................................................................................. 210
13 ACPI Interface Design Guidelines............................................................................................... 211

13.1 Modern Standby Introduction............................................................................................................................ 211
13.1.1 Modern Standby Overview................................................................................................................. 211
13.1.2 Modern Standby Power State Design ................................................................................................ 211
13.1.3 Modern Standby References............................................................................................................... 212
13.2 Modern Standby Platform Hardware ................................................................................................................ 213
13.2.1 Modern Standby Power Rails............................................................................................................. 213
Contents 5
13.2.2 Modern Standby Power/Reset Design PCIe® Devices.......................................................................213

13.2.3 Modern Standby Sleep Control Signal............................................................................................... 214
13.2.4 Modern Standby Wake Signals - General...........................................................................................215
13.2.5 Modern Standby Hardware-Reduced ACPI Design........................................................................... 215
13.2.6 Modern Standby - AC_PRES signal...................................................................................................215
13.3 Modern Standby Platform Components.............................................................................................................215
13.3.1 Modern Standby Component Selection.............................................................................................. 215
13.3.2 Modern Standby Storage Devices.......................................................................................................215
13.3.3 General Information for Modern Standby Wake Sources/Wake Events............................................ 216
13.4 Modern Standby Wake Sources/Wake Events.................................................................................................. 216
13.4.1 General Information for Modern Standby Wake Sources/Wake Events............................................ 216
13.4.2 Modern Standby Wake Devices/Event List........................................................................................216
13.4.3 Modern Standby Power Rail Assignment – Wake Sources................................................................219
13.4.4 Modern Standby Wake Signal Input to SoC.......................................................................................219
13.5 Modern Standby Wake on Voice.......................................................................................................................220
13.5.1 Modern Standby Wake on Voice Overview....................................................................................... 220
13.5.2 Modern Standby Wake on Voice System Overview.......................................................................... 220
13.6 ACPI Modern Standby and Legacy System Schematic and Routing Design Guidelines................................. 222
14 Miscellaneous Signals Design Guidelines.................................................................................... 226

Miscellaneous Signals Design Guidelines................................................................................................................. 226
14.1 Strapping Options ............................................................................................................................................. 235
14.2 Voltage Regulator Signals................................................................................................................................. 236
14.2.1 Routing of Voltage Feedback Signals.................................................................................................237
14.3 DDR4 VREF......................................................................................................................................................238
14.4 Global Signals....................................................................................................................................................239
14.4.1 Edge Rates and Signal Quality........................................................................................................... 239
14.4.2 PWR_GOOD...................................................................................................................................... 239
14.4.3 PWROK.............................................................................................................................................. 239
14.4.4 RESET_L............................................................................................................................................240
14.5 Headers.............................................................................................................................................................. 240
14.5.1 Header Placement............................................................................................................................... 240
14.5.2 HDT+ Header......................................................................................................................................240
14.5.3 HDT Over USBC................................................................................................................................241
14.5.4 BP Probing Header............................................................................................................................. 241
14.6 Validation Related Signals.................................................................................................................................242
14.6.1 Voltage Margining.............................................................................................................................. 242
14.7 System Control Signals—Power, Reset, and Warm Reset Headers..................................................................243
14.8 Test Points..........................................................................................................................................................244
14.9 Voltage Translation (Level Shifting)................................................................................................................. 245
14.10 SMBus Interface.............................................................................................................................................. 248
14.11 Sensor Fusion Hub (SFH)................................................................................................................................249
14.12 LPC Bus Interface............................................................................................................................................251
14.13 LPC Clock Interface........................................................................................................................................ 252
14.14 Serial Peripheral Interface (SPI)...................................................................................................................... 254
14.14.1 SPI ROM Sharing............................................................................................................................. 255
14.15 Enhanced Serial Peripheral Interface (eSPI)....................................................................................................256
14.16 Thermal Management Signals......................................................................................................................... 259
14.16.1 THERMTRIP_L............................................................................................................................... 259
14.16.2 PROCHOT_L................................................................................................................................... 259
14.16.3 SIC, SID and ALERT_L...................................................................................................................260
14.17 General Purpose I/O.........................................................................................................................................260
15 Power Distribution Network Design Guidelines......................................................................... 261
6 Contents
15.1 Power Distribution Network Design Guidelines............................................................................................... 261

15.2 High-Frequency Design Considerations............................................................................................................ 261
15.2.1 Capacitor Selection............................................................................................................................. 261
15.2.2 Capacitor Placement........................................................................................................................... 262
15.2.3 Capacitor Orientation..........................................................................................................................262
15.2.4 Capacitor Interconnect........................................................................................................................ 263
15.2.5 Guideline Adherence.......................................................................................................................... 266
15.2.6 Component Substitution..................................................................................................................... 267
15.2.7 Routing and Decoupling..................................................................................................................... 267
15.3 Power Generation and Distribution Guidelines................................................................................................. 267
15.3.1 VDDP Power Delivery and Decoupling............................................................................................. 269
15.3.2 VDDP_S5 Power Delivery and Decoupling.......................................................................................269
15.3.3 VDD_18 Power Delivery and Decoupling......................................................................................... 269
15.3.4 VDD_18_S5 Power Delivery and Decoupling................................................................................... 269
15.3.5 VDDIO_VPH Power Delivery and Decoupling................................................................................. 269
15.3.6 VDDIO_MEM_S3 Power Delivery and Decoupling......................................................................... 269
15.3.7 VDDCR_SOC Power Delivery and Decoupling................................................................................ 270
15.3.8 VDDSPD Power................................................................................................................................. 270
15.3.9 Decoupling Capacitors for Processor Power...................................................................................... 271
16 EMI and ESD Design Guidelines................................................................................................. 272

16.1 Decoupling, Bypass, Stitching, and Filtering Capacitors.................................................................................. 272
16.1.1 Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)...............................................272
16.1.2 High-Frequency Bypass and Stitching Capacitors............................................................................. 272
16.1.3 DDR VDDIO_MEM_S3 to VSS Stitching Capacitor Requirements.................................................272
16.1.4 Voltage Filtering Requirements..........................................................................................................273
16.2 Clocks and EMI................................................................................................................................................. 273
16.2.1 Spread-Spectrum Clocking (SSC)...................................................................................................... 273
16.2.2 Display SSC........................................................................................................................................ 273
16.2.3 Unused Clock Outputs........................................................................................................................ 273
16.2.4 Clock Generators................................................................................................................................ 273
16.2.5 Clock Signal Termination................................................................................................................... 275
16.3 I/O Signal Partitioning and Separation.............................................................................................................. 275
16.3.1 I/O Filtering........................................................................................................................................ 275
16.3.2 Heatsink Grounding............................................................................................................................ 276
16.3.3 Fan Cabling.........................................................................................................................................276
16.4 Motherboard Grounding.................................................................................................................................... 276
16.4.1 Motherboard-to-Chassis Grounding................................................................................................... 276
16.5 Power and Ground Fill Vias.............................................................................................................................. 277
16.6 Electrostatic Discharge (ESD)........................................................................................................................... 277
16.6.1 ESD Component Placement................................................................................................................280
17 Low EMI Noise for System Radio Integration Design Guidelines............................................ 282
17.1 Most Commonly Integrated Radio Bands..........................................................................................................282
17.2 Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)..............................................................282
17.3 Key Radio Bands............................................................................................................................................... 282
17.4 Principal Harmonic Signal Threats to Radio Integration...................................................................................283
17.5 General Rules to Optimize Differential-Mode Radio Performance.................................................................. 285
17.6 Common-Mode Ground Disturbances...............................................................................................................285
17.7 Design Rules for Optimal Radio Performance.................................................................................................. 286
18 Power Optimization Design Guidelines....................................................................................... 288

18.1 Peripheral Selection and Optimization.............................................................................................................. 288
Contents 7
18.1.1 Device Implementation—USB........................................................................................................... 288

18.1.2 Selective Suspend............................................................................................................................... 288
18.1.3 Device Implementation—PCIe® Interface......................................................................................... 289
18.1.4 Device Implementation—Discrete Graphics ..................................................................................... 289
18.1.5 Device Implementation—SATA........................................................................................................ 290
18.1.6 Device Implementation—HD Audio.................................................................................................. 290
18.1.7 Device Implementation—Network Device.........................................................................................290
18.1.8 Device Implementation—TPM 2.0.....................................................................................................290
18.1.9 Device Implementation—Memory..................................................................................................... 290
18.1.10 Device Implementation—LCD Panel............................................................................................... 290
18.2 BIOS and Drivers...............................................................................................................................................290
18.2.1 BIOS Implementation......................................................................................................................... 290
18.2.2 Graphics Driver Implementation........................................................................................................ 291
19 Power Regulator Design Guidelines.............................................................................................292

19.1 Power Regulation Overview.............................................................................................................................. 292
19.2 Power Delivery—Good Design Practice........................................................................................................... 292
19.3 Power Conversion—Hierarchy..........................................................................................................................292
19.3.1 Stage 1 Regulator—Main Power Supply............................................................................................295
19.4 Switching Regulator Design Considerations..................................................................................................... 299
19.4.1 Switching Regulator Topologies.........................................................................................................299
19.4.2 Switching Regulator Types.................................................................................................................300
19.4.3 Component Selection.......................................................................................................................... 302
19.5 Power Distribution from the Regulator..............................................................................................................305
19.5.1 Power Status Indicator........................................................................................................................ 308
Appendix A GRAPHICS CONNECTOR PINOUTS...................................................................... 309
Connector Pinouts......................................................................................................................................................309
Appendix B HEIGHT-RESTRICTION DRAWINGS.................................................................... 312

Height-Restriction Drawings for FP6 Motherboards.................................................................................................312
Glossary ...........................................................................................................................................315
8 Contents
List of Figures
Figure 1. Block Diagram—FP6 Processor-Based System.......................................................................................................24
Figure 2. Six-Layer Stackup.................................................................................................................................................... 27
Figure 3. Ten-Layer Stackup................................................................................................................................................... 27
Figure 4. Twelve-Layer Stackup..............................................................................................................................................28
Figure 5. DDR Routing Regions..............................................................................................................................................30
Figure 6. End Region - Through-hole UDIMMs .................................................................................................................... 31
Figure 7. End Region - SMT Device with Tee Vias................................................................................................................32
Figure 8. End Region - SMT Device and No Tees.................................................................................................................. 33
Figure 9. Serpentine (Self) Spacing......................................................................................................................................... 33
Figure 10. Routing Differential Signals Around Vias............................................................................................................. 34
Figure 11. Differential Traces and Spacing............................................................................................................................. 34
Figure 12. Microstrip Topology...............................................................................................................................................35
Figure 13. Stripline Topology..................................................................................................................................................36
Figure 14. Single-Ended Signal Crossing a Weak Side Plane Split........................................................................................ 36
Figure 15. Differential Signal Crossing a Weak Side Plane Split........................................................................................... 37
Figure 16. Stitching Via Placement for Multiple Differential Pairs........................................................................................ 39
Figure 17. Stitching Via Placement for Single-Ended Traces................................................................................................. 39
Figure 18. Stitching Via Placement for Differential Pairs.......................................................................................................40
Figure 19. Preferred Optimized 6 Layer PCB Differential Signal Vias with 4 VSS Vias...................................................... 41
Figure 20. Acceptable Optimized 6 Layer PCB Differential Signal Vias with 2 VSS Vias................................................... 42
Figure 21. Acceptable Optimized 6 Layer PCB Differential Signal Vias with 2 VSS Vias................................................... 42
Figure 22. High-Speed AC-Coupling Capacitor VSS/Reference Plane Void......................................................................... 43
Figure 23. Trace Crossing Reference Plane Split—Same Layer.............................................................................................43
Figure 24. Trace Crossing Reference Plane Split—Different Layer....................................................................................... 44
Figure 25. Via Stubs................................................................................................................................................................ 46
Figure 26. Differential Clock Signal Assignment for Six-Layer Board.................................................................................. 47
Figure 27. Differential Clock Routing Model..........................................................................................................................48
Figure 28. RTC with Battery Backup Interface Routing Model..............................................................................................49
Figure 29. Single-Ended Clock Signal Assignment for Six-Layer Board............................................................................... 50
Figure 30. Single-Ended Clock Routing Model...................................................................................................................... 51
Figure 31. DIMM Memory Signal Assignment—Eight-Layer Board.....................................................................................60
Figure 32. DRAM Down Memory Signal Assignment—Ten-Layer Board............................................................................61
Figure 33. DRAM Down Memory Signal Assignment—Twelve-Layer Board......................................................................62
Figure 34. UDIMM Placement—Two UDIMMs.................................................................................................................... 64
Figure 35. CLK Routing Model (DDR4 UDIMMs)................................................................................................................66
Figure 36. ADD/CMD/CTL Routing Model (DDR4 UDIMMs)............................................................................................ 67
Figure 37. DQS Routing Model (DDR4 UDIMMs)................................................................................................................69
Figure 38. Data/DM Routing Model (DDR4 UDIMMs).........................................................................................................71
Figure 39. Miscellaneous Routing Model (DDR4 UDIMMs).................................................................................................73
Figure 40. SO-DIMM Placement —Two SO-DIMMs............................................................................................................ 75
Figure 41. SO-DIMM Placement —Two SO-DIMMs (Side-by-Side)................................................................................... 76
Figure 42. CLK Routing Model (DDR4 SO-DIMMs)............................................................................................................ 79
Figure 43. ADD/CMD/CTL Routing Model (DDR4 SO-DIMMs).........................................................................................81
Figure 44. DQS Routing Model (DDR4 SO-DIMMs) ........................................................................................................... 83
Figure 45. Data/DM Routing Model (DDR4 SO-DIMMs) .................................................................................................... 85
Figure 46. Miscellaneous Routing Model (DDR4 SO-DIMMs)............................................................................................. 87
Figure 47. U-Turn Routing for ADD/CMD/CTL/CLK—x8...................................................................................................89
Figure 48. DRAM Placement—Single-Rank x8 SDP DRAMs or Dual-Rank x8 DDP DRAMs........................................... 89
Figure 49. DRAM Placement—Dual-Rank x8 SDP DRAMs................................................................................................. 90
Figure 50. Single Row Fly-By Routing for ADD/CMD/CTL/CLK— x16.............................................................................90
Figure 51. DRAM Placement— Single-Rank x16 SDP DRAMs or Dual-Rank x16 DDP DRAMs ..................................... 91
List of Figures 9
Figure 52. DRAM Placement—Dual-Rank x16 SDP DRAMs............................................................................................... 91

Figure 53. CLK Routing Model (DDR4 x8 DRAM Down)....................................................................................................94
Figure 54. ADD/CMD/CTL Routing Model (DDR4 x8 DRAM Down)................................................................................ 96
Figure 55. DQS Routing Model (DDR4 X8 DRAM Down)................................................................................................... 98
Figure 56. Data/DM Routing Model (DDR4 x8 DRAM Down)...........................................................................................100
Figure 57. Miscellaneous Routing Model (DDR4 x8 DRAM Down)...................................................................................102
Figure 58. CLK Routing Model (DDR4 x16 DRAM Down)................................................................................................104
Figure 59. ADD/CMD/CTL Routing Model (DDR4 x16 DRAM Down)............................................................................ 106
Figure 60. DQS Routing Model (DDR4 x16 DRAM Down)................................................................................................108
Figure 61. Data/DM Routing Model x16 DRAM Down)......................................................................................................110
Figure 62. Miscellaneous Routing Model (DDR4 x16 DRAM Down).................................................................................111
Figure 63. Memory Signal Assignment LPDDR4x x32—Ten-Layer Board ....................................................................... 113
Figure 64. LPDDR4x x32 DRAM Down Routing for ADD/CMD/CTL/CLK..................................................................... 114
Figure 65. LPDDR4x x32 DRAM Down Placement.............................................................................................................114
Figure 66. CLK Routing Model (LPDDR4x x32 DRAM Down)......................................................................................... 117
Figure 67. ADD/CMD/CTL Routing Model (LPDDR4x x32 DRAM Down)......................................................................119
Figure 68. DQS Routing Model (LPDDR4x x32 DRAM Down)......................................................................................... 121
Figure 69. Data/DM Routing Model (LPDDR4x x32 DRAM Down).................................................................................. 123
Figure 70. Block Diagram—PCI Express® Interface to Connector...................................................................................... 127
Figure 71. Block Diagram—PCI Express® Interface to Onboard Device............................................................................ 128
Figure 72. Block Diagram—PCI Express® and SATA to M.2 Connector (PCIe SSDs Supported—SATA SSDs Not
Supported).................................................................................................................................................. 129
Figure 73. Block Diagram—PCI Express® and SATA to M.2 Connector (PCIe SSDs or SATA SSDs Supported)...........130
Figure 74. PCIe® Signal Assignment for a Six-Layer Board................................................................................................ 131
Figure 75. PCIe® Signal Assignment for an Eight-Layer Board...........................................................................................131
Figure 76. PCIe® AC-Coupling Capacitor Placement...........................................................................................................132
Figure 77. PCIe® Interface Routing Model to PCIe Onboard Device...................................................................................133
Figure 78. PCIe® Interface Routing Model to PCIe Connector............................................................................................ 134
Figure 79. PCIe® Length Matching.......................................................................................................................................136
Figure 80. Schematic Diagram—StereoSync Interface......................................................................................................... 140
Figure 81. Schematic Diagram—DisplayPort to DisplayPort Connector (DP Only)............................................................142
Figure 82. Schematic Diagram—DisplayPort to eDP Panel................................................................................................. 142
Figure 83. Schematic Diagram—DisplayPort to DisplayPort Plus Plus (DP++) Connector................................................ 145
Figure 84. Schematic Diagram—AUX Conversion Block and HPD Level Shifter.............................................................. 146
Figure 85. Schematic Diagram—Single-Link DVI Interface................................................................................................ 147
Figure 86. Schematic Diagram—HDMI™ Interface............................................................................................................. 149
Figure 87. Schematic Diagram—HDMI™ 2.0 to Retimer/Redriver to Connector................................................................152
Figure 88. DisplayPort to LVDS Translator Block Diagram................................................................................................ 153
Figure 89. Schematic Diagram—DisplayPort, Translator and LCD (LVDS)....................................................................... 153
Figure 90. Schematic Diagram—DisplayPort, Translator and VGA.................................................................................... 155
Figure 91. DP Signal Assignment for a 6-Layer Board.........................................................................................................156
Figure 92. DP Signal Assignment for an 8-Layer Board.......................................................................................................156
Figure 93. DisplayPort AC-Coupling Capacitor Placement.................................................................................................. 157
Figure 94. DP Routing Model (MainLink to DP or eDP Connector)....................................................................................158
Figure 95. DP Routing Model (AUX to DP or eDP Connector)........................................................................................... 159
Figure 96. DP Routing Model (MainLink to DP++ Connector)............................................................................................160
Figure 97. DP Routing Model (AUX to DP++ Connector)................................................................................................... 162
Figure 98. DP Routing Model (MainLink to DVI or HDMI™ Connector)...........................................................................163
Figure 99. DP Routing Model (AUX to DVI or HDMI™ Connector).................................................................................. 164
Figure 100. DP Routing Model (MainLink to Translator).................................................................................................... 165
Figure 101. DP Routing Model (AUX to Translator)............................................................................................................167
Figure 102. DP HPD Routing Model to Connector...............................................................................................................168
Figure 103. FP6 Processor USB Controller to Port Mapping—No USB-C® Connector .....................................................170
Figure 104. USB 2.0/SS HUB Tier Mismatch—xHCI Specification Violation....................................................................172
Figure 105. USB Power Switch for Micro-AB Receptacles..................................................................................................172
Figure 106. Example 1 USB Micro-B VSS/Reference Plane Void.......................................................................................174
10 List of Figures
Figure 107. Example 2 USB Micro-B VSS/Reference Plane Void.......................................................................................174

Figure 108. Example 1 SMT Component Pad VSS/Reference Plane Void.......................................................................... 175
Figure 109. Example 2 SMT Component Pad VSS/Reference Plane Void.......................................................................... 175
Figure 110. Example USB-A Connector VSS/Reference Plane Void...................................................................................176
Figure 111. Example 1 USB-C® Connector VSS/Reference Plane Void............................................................................. 177
Figure 112. Example 2 USB-C® Connector VSS/Reference Plane Void............................................................................. 177
Figure 113. Example 1 USB ESD Device VSS/Reference Plane Void.................................................................................178
Figure 114. Example 2 USB ESD Device VSS/Reference Plane Void.................................................................................178
Figure 115. Example 1 USB Differential Signal Pair Void and VSS Vias .......................................................................... 179
Figure 116. Example 2 USB Differential Signal Pair Void...................................................................................................179
Figure 117. USB 2.0 Interface—Schematic and Routing Model.......................................................................................... 180
Figure 118. USB 3.2 Interface—Schematic and Routing Model.......................................................................................... 182
Figure 119. USB 3.2 Interface with Retimer/Redriver—Schematic and Routing Model..................................................... 182
Figure 120. USB 3.2 AC-Coupling Capacitor Placement..................................................................................................... 184
Figure 121. FP6 Processor—DP Alt Mode/USB Controller to Port Mapping—USB-C® Connector.................................. 187
Figure 122. DisplayPort/USB AC-Coupling Capacitor and ESD Device Placement........................................................... 188
Figure 123. Schematic Diagram—DisplayPort/USB to USB-C® Connector....................................................................... 190
Figure 124. Schematic Diagram—DisplayPort/USB with Retimer/Redriver to USB-C® Connector.................................. 190
Figure 125. SATA AC-Coupling Capacitor Placement.........................................................................................................199
Figure 126. SATA Mobile Routing Model............................................................................................................................201
Figure 127. HD Audio Interface—Schematic and Routing Mode........................................................................................ 203
Figure 128. I2S Bus Interface—Schematic and Routing Mode............................................................................................ 205
Figure 129. WoV Interface—Schematic and Routing Mode.................................................................................................207
Figure 130. Secure Biometrics Camera Solution — Block Diagram.................................................................................... 209
Figure 131. System Power Rail Summary.............................................................................................................................213
Figure 132. System Power-Up/Reset Sequence.....................................................................................................................214
Figure 133. Modern Standby Wake on Voice/ Keyword Spotting System System Block Diagram.....................................220
Figure 134. Modern Standby ACPI Interface Routing Model...............................................................................................222
Figure 135. Legacy ACPI Interface Routing Model (No Modern Standby support)............................................................ 224
Figure 136. Routing Diagram for Voltage Sense Signals......................................................................................................237
Figure 137. VREF Circuit: VREFCA (DIMM).....................................................................................................................238
Figure 138. Schematic Diagram—Multi-Drop Net............................................................................................................... 239
Figure 139. Margin Tool Connector—VREF on DIMMs..................................................................................................... 242
Figure 140. Margin Tool Connector...................................................................................................................................... 243
Figure 141. Power Button and Reset Headers....................................................................................................................... 243
Figure 142. Power and Reset Button Schematic....................................................................................................................244
Figure 143. Variable Spacing Differential Probe.................................................................................................................. 244
Figure 144. Voltage Thresholds for 3.3 V and 1.5 V............................................................................................................ 245
Figure 145. Voltage Translation Circuit Example for Single-Ended Signals........................................................................247
Figure 146. Voltage Translation Circuit for SB-TSI............................................................................................................. 247
Figure 147. SMBus Interface Routing Model........................................................................................................................249
Figure 148. SFH Routing Model........................................................................................................................................... 249
Figure 149. LPC Interface Routing Model............................................................................................................................ 251
Figure 150. LPC Clock Interface Routing Model..................................................................................................................252
Figure 151. SPI Routing Model............................................................................................................................................. 254
Figure 152. Multiple SPI Device Routing Model..................................................................................................................255
Figure 153. SPI ROM Sharing Routing Model..................................................................................................................... 255
Figure 154. eSPI Single Master-Single Slave with eSPI_RESET_L Master to Slave Routing Model................................. 257
Figure 155. LPC eSPI Data Mux........................................................................................................................................... 258
Figure 156. Example PROCHOT_L Schematic.................................................................................................................... 259
Figure 157. Schematic Diagram for AMD Validation Environment Header........................................................................ 260
Figure 158. Capacitor Aspect Ratio—Standard, Transposed, and Multi-Terminal.............................................................. 262
Figure 159. Alignment of VDD and VSS Vias to Minimize Mutual Inductance..................................................................262
Figure 160. Decoupling Interconnection Comparison...........................................................................................................263
Figure 161. Length-to-Width Ratio of Decoupling Interconnection..................................................................................... 264
Figure 162. Copper Pour—Mini-Plane Decoupling Interconnection.................................................................................... 265
List of Figures 11
Figure 163. Power Connections for Processor and Dual-Plane Supply.................................................................................267

Figure 164. Trace Routing over a Plane................................................................................................................................ 274
Figure 165. Top Layer VSS Copper Fill Beneath Clock Generator...................................................................................... 274
Figure 166. PCB Standard and Edge Mounting Holes.......................................................................................................... 276
Figure 167. Block Diagram—System ESD Examples.......................................................................................................... 278
Figure 168. Schematic Diagram—ESD Device Connecting to Signals and VSS................................................................. 279
Figure 169. Typical Board Layout—ESD Device Connecting to Signals and VSS............................................................. 279
Figure 170. Schematic Diagram—ESD Device Connecting to Signal, VSS, and VCC....................................................... 279
Figure 171. Typical Board Layout—ESD Device Connecting to Signal, VSS, and VCC....................................................280
Figure 172. Placement of an Integrated ESD-Protection Device.......................................................................................... 280
Figure 173. Power Conversion Block Diagram (Simplified)................................................................................................ 292
Figure 174. Efficiency Versus Stages of Regulation............................................................................................................. 293
Figure 175. Power Delivery Efficiency for Various Power Supply Solutions...................................................................... 294
Figure 176. Power Efficiency Curves....................................................................................................................................295
Figure 177. Ideal Power.........................................................................................................................................................296
Figure 178. Voltage-Current Phase Relationships.................................................................................................................297
Figure 179. PFC Phase Adjustment in Inductive Systems.................................................................................................... 297
Figure 180. PFC Phase Adjustment in Capacitive Systems.................................................................................................. 298
Figure 181. Example Buck Regulator Simplified Schematic Diagram................................................................................. 300
Figure 182. Continuous Mode Inductor Current....................................................................................................................301
Figure 183. Copper Pour—Necked Down Example..............................................................................................................305
Figure 184. Copper Pour—Bad Via Placement Example......................................................................................................306
Figure 185. Copper Pour—Good Via Placement Example................................................................................................... 307
Figure 186. Power and Ground Via Placement..................................................................................................................... 307
Figure 187. FP6 Processor SDLE Component Keepout Height-Restrictions Sheet 1 of 2................................................... 312
Figure 188. FP6 Processor SDLE Component Keepout Height-Restrictions Sheet 2 of 2................................................... 313
12 List of Figures
List of Tables
Table 1. Feature Compatibility................................................................................................................................................ 20
Table 2. Reference Documents................................................................................................................................................ 21
Table 3. Recommended Socketed-Memory Configurations per Channel............................................................................... 25
Table 4. Valid DRAM-Down Configurations per Channel..................................................................................................... 25
Table 5. Supported Display Interfaces.....................................................................................................................................25
Table 6. Computing Trace-Length Matching Example........................................................................................................... 30
Table 7. Asymmetric Stripline dB Isolation on Weak-Side Plane with Moat......................................................................... 38
Table 8. Stitching Vias—between Two Reference Planes...................................................................................................... 40
Table 9. Stitching Capacitors—between Two Reference Planes.............................................................................................45
Table 10. Routing Rules for Differential Clocks..................................................................................................................... 48
Table 11. Routing Rules for Single-Ended Clocks..................................................................................................................51
Table 12. DDR4 Signal Descriptions.......................................................................................................................................53
Table 13. LPDDR4x Signal Descriptions................................................................................................................................54
Table 14. Signals and Connections for One DDR4 SO-DIMM on Channel A or Channel B.................................................55
Table 15. Signals and Connections for One DDR4 UDIMM .................................................................................................56
Table 16. Signals and Connections for DDR4 DRAM Down ................................................................................................ 57
Table 17. Signals and Connections for LPDDR4x DRAM Down —LPDDR4x x32............................................................. 59
Table 18. Routing Topology for One DDR4 UDIMM per Channel .......................................................................................63
Table 19. Routing Rules for CLK (DDR4 UDIMMs).............................................................................................................66
Table 20. Routing Rules for ADD/CMD/CTL (DDR4 UDIMMs)......................................................................................... 67
Table 21. Routing Rules for DQS (DDR4 UDIMMs).............................................................................................................69
Table 22. Routing Rules for Data/DM (DDR4 UDIMMs)......................................................................................................71
Table 23. Component Table—DDR4 Miscellaneous Termination......................................................................................... 73
Table 24. Routing Rules for Miscellaneous (DDR4 UDIMMs)..............................................................................................73
Table 25. Routing Topology for One DDR4 SO-DIMM on Channel A or Channel B...........................................................75
Table 26. Routing Rules for CLK (One DDR4 SO-DIMM per Channel)...............................................................................79
Table 27. Routing Rules for ADD/CMD/CTL (One DDR4 SO-DIMM per Channel)........................................................... 81
Table 28. Routing Rules for DQS (One DDR4 SO-DIMM per Channel)...............................................................................83
Table 29. Routing Rules for Data/DM (One DDR4 SO-DIMM per Channel)........................................................................85
Table 30. Component Table—DDR4 Miscellaneous Termination......................................................................................... 87
Table 31. Routing Rules for Miscellaneous (One DDR4 SO-DIMM )................................................................................... 87
Table 32. DDR4 DRAM Down Per-Channel Decoupling Capacitors.................................................................................... 92
Table 33. Component Table—DDR4 x8 CLK Termination................................................................................................... 94
Table 34. Routing Rules for CLK (DDR4 x8 DRAM Down).................................................................................................94
Table 35. Component Table—DDR4 x8 ADD/CMD/CTL Termination................................................................................96
Table 36. Routing Rules for ADD/CMD/CTL (DDR4 x8 DRAM Down)............................................................................. 96
Table 37. Routing Rules for DQS (DDR4 X8 DRAM Down)................................................................................................ 98
Table 38. Routing Rules for Data/DM (DDR4 x8 DRAM Down)........................................................................................100
Table 39. Routing Rules for Miscellaneous (DDR4 x8 DRAM Down)................................................................................102
Table 40. Component Table—DDR4 x16 CLK Termination............................................................................................... 104
Table 41. Routing Rules for CLK (DDR4 x16 DRAM Down).............................................................................................104
Table 42. Component Table—DDR4 x16 ADD/CMD/CTL Termination............................................................................106
Table 43. Routing Rules for ADD/CMD/CTL (DDR4 x16 DRAM Down)......................................................................... 106
Table 44. Routing Rules for DQS (DDR4 x16 DRAM Down).............................................................................................108
Table 45. Routing Rules for Data/DM (DDR4 x16 DRAM Down)......................................................................................110
Table 46. Routing Rules for Miscellaneous (DDR4 x16 DRAM Down)..............................................................................111
Table 47. LPDDR4x DRAM Down Decoupling Capacitors.................................................................................................115
Table 48. Routing Rules for CLK (LPDDR4x x32 DRAM Down)...................................................................................... 117
Table 49. Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM Down)...................................................................119
Table 50. Component Table—LPDDR4x DQS Termination................................................................................................121
Table 51. Routing Rules for DQS (LPDDR4x x32 DRAM Down)...................................................................................... 121
List of Tables 13
Table 52. Routing Rules for Data/DM (LPDDR4x x32 DRAM Down)............................................................................... 123
Table 53. Routing Rules for Miscellaneous (LPDDR4x x32 DRAM Down)....................................................................... 125
Table 54. Possible Port/Lane Usages for GFX PCIe Controller............................................................................................126
Table 55. Possible Port/Lane Usages for GPP PCIe Controller............................................................................................ 127
Table 56. Component Table—PCIe® Interface to Connector or Onboard Device............................................................... 128
Table 57. Recommended AC-Coupling Component Placement........................................................................................... 132
Table 58. Routing Rules for PCIe® Interface to Onboard Device.........................................................................................133
Table 59. Routing Rules for PCIe® Interface to PCIe Connector......................................................................................... 135
Table 60. PCIe® Routing Lengths vs. Topology .................................................................................................................. 137
Table 61. Display Feature Compatibility...............................................................................................................................138
Table 62. DisplayPort MainLink (ML), Auxiliary (AUX), and Hot Plug Detect HPD) Signals.......................................... 138
Table 63. DisplayPort Signal Descriptions............................................................................................................................139
Table 64. Component Table—StereoSync Interface............................................................................................................. 140
Table 65. DisplayPort Configurations................................................................................................................................... 141
Table 66. Component Table—DisplayPort to DP and eDP Connectors............................................................................... 143
Table 67. DisplayPort Signals to eDP Panel..........................................................................................................................143
Table 68. Component Table—DisplayPort to DP++ Connector........................................................................................... 145
Table 69. Component Table—DP++ AUX Conversion Block............................................................................................. 146
Table 70. DisplayPort Signals to DP or DP++ Connector.....................................................................................................147
Table 71. Component Table—DisplayPort to Single-Link DVI Connector..........................................................................148
Table 72. Connections for DisplayPort to Single-Link DVI Interface.................................................................................. 149
Table 73. Component Table—Display Interface to HDMI™ Connector.............................................................................. 150
Table 74. Connections for DisplayPort to HDMI™ Interface............................................................................................... 151
Table 75. Component Table—Display Interface to HDMI™ 2.0 Retimer/Redriver to Connector....................................... 152
Table 76. Component Table—DisplayPort, Translator and LCD (LVDS)........................................................................... 154
Table 77. Component Table—DisplayPort to Translator and VGA Interface...................................................................... 155
Table 78. Recommended AC-Coupling Component Placement........................................................................................... 157
Table 79. Routing Rules for DP (MainLink to DP or eDP Connector).................................................................................158
Table 80. Routing Rules for DP (AUX to DP or eDP Connector)........................................................................................ 159
Table 81. Routing Rules for DP (MainLink to DP++ Connector).........................................................................................161
Table 82. Routing Rules for DP (AUX to DP++ Connector)................................................................................................ 162
Table 83. Routing Rules for DP (MainLink to DVI or HDMI™ Connector)........................................................................163
Table 84. Routing Rules for DP (AUX to DVI or HDMI™ Connector)............................................................................... 165
Table 85. Routing Rules for DP (MainLink to Translator)................................................................................................... 166
Table 86. Routing Rules for DP (AUX to Translator)...........................................................................................................167
Table 87. Routing Rules for DP HPD to Connector..............................................................................................................168
Table 88. Display Interface Maximum Trace Length vs. Topology......................................................................................168
Table 89. FP6 Platform—USB Signal to USB Port Mapping............................................................................................... 170
Table 90. Routing Rules for USB 2.0 Interface.....................................................................................................................180
Table 91. Recommended AC-Coupling Capacitor Placement.............................................................................................. 184
Table 92. Component Table—USB 3.2 Interface..................................................................................................................185
Table 93. Routing Rules for USB 3.2 Interface.....................................................................................................................186
Table 94. FP6 Platform—DP Alt Mode/USB Signal to Port Mapping................................................................................. 188
Table 95. Recommended AC-Coupling Capacitor and ESD Device Placement...................................................................189
Table 96. Component Table—DisplayPort/USB to USB-C® Connector..............................................................................192
Table 97. DisplayPort/USB Signals to USB-C® Connector..................................................................................................192
Table 98. Routing Rules for DP Alt Mode/USB to USB-C® Connector.............................................................................. 194
Table 99. Component Table—SATA Interface TX and RX Signals.....................................................................................199
Table 100. Recommended AC-Coupling Capacitor Placement............................................................................................ 199
Table 101. Routing Rules for SATA Interface...................................................................................................................... 200
Table 102. Routing Rules for HD Audio Interface................................................................................................................203
Table 103. Component Table—I2S Bus Audio Interface......................................................................................................205
Table 104. Routing Rules for I2S Bus Audio Interface.........................................................................................................205
Table 105. Routing Rules for WoV Interface........................................................................................................................207
Table 106. Acronyms and Terminologies..............................................................................................................................211
Table 107. Modern Standby References................................................................................................................................212
14 List of Tables
Table 108. Modern Standby Wake Source/Events................................................................................................................ 216

Table 109. Modern Standby Platform Component I/O and GPIO Assignment.................................................................... 219
Table 110. Routing Rules for Mobile ACPI Interface...........................................................................................................224
Table 111. Miscellaneous Signals Quick Reference..............................................................................................................226
Table 112. Routing Rules for Miscellaneous Signals............................................................................................................235
Table 113. Strapping Options................................................................................................................................................ 236
Table 114. Voltage Regulator Signals................................................................................................................................... 237
Table 115. Header Part Numbers...........................................................................................................................................240
Table 116. HDT+ Header Pinout........................................................................................................................................... 240
Table 117. BP Probing Signals.............................................................................................................................................. 241
Table 118. Routing Requirements for VREF +Force and −Force Signals............................................................................ 242
Table 119. Voltage Translator Recommended Component Values.......................................................................................248
Table 120. Routing Rules for SMBus Interface.....................................................................................................................249
Table 121. Component Table—SFH Termination.................................................................................................................250
Table 122. Routing Rules for SFH........................................................................................................................................ 250
Table 123. Routing Rules for LPC Interface......................................................................................................................... 251
Table 124. Clock to LPC Device Connections...................................................................................................................... 252
Table 125. Routing Rules for LPC Clock Interface...............................................................................................................252
Table 126. Routing Rules for SPI.......................................................................................................................................... 254
Table 127. Routing Rules for Multiple SPI Devices............................................................................................................. 255
Table 128. eSPI Features of FP6 Processor........................................................................................................................... 256
Table 129. eSPI Signal Descriptions..................................................................................................................................... 256
Table 130. Routing Rules for eSPI Bus................................................................................................................................. 257
Table 131. Attributes of PDN Components...........................................................................................................................261
Table 132. Decoupling Capacitors for Processor Power....................................................................................................... 271
Table 133. Spread-Spectrum Settings for Display Mode...................................................................................................... 273
Table 134. Electrical Specifications for TVS Devices.......................................................................................................... 278
Table 135. Key Embedded Radio Bands............................................................................................................................... 282
Table 136. Principal System Harmonics Coinciding with Key Radio Bands........................................................................283
Table 137. Differential-Mode and Common-Mode Factors Affecting Radio Compliance...................................................285
Table 138. Information for Radio Performance Optimization...............................................................................................286
Table 139. Internal USB Device Usage Models....................................................................................................................288
Table 140. Pinout of Mini DisplayPort Connector................................................................................................................ 309
Table 141. Pinout of Mini DisplayPort Connector................................................................................................................ 309
Table 142. Pinout of HDMI™ Connector.............................................................................................................................. 310
List of Tables 15
List of Abbreviations
APU accelerated processing unit PCI peripheral component interconnect
CRC cyclic redundancy check PCIe peripheral component interconnect
DIMM dual in-line memory module express
DRAM dynamic random-access memory RTC realtime clock
GPP general purpose port SG switchable graphics
GPU graphics processing unit SSD solid-state disk
LP low power USB universal serial bus
LVX low-voltage translator
16 List of Abbreviations
Revision History
Date Revision Description
January 2020 1.03 General: Added AMD Family 19h Models 50h-5Fh FP6 Type 2 processor to the design guide.
• Chapter 5: Added MA_PAROUT and MA_ALERT_L to the Signals and Connections for DDR4
DRAM Down table. Changed EVENT_L to ALERT_L in the Routing Rules for Miscellaneous (DDR4
x8 DRAM Down) table, Miscellaneous Routing Model (DDR4 x8 DRAM Down) figure, Routing
Rules for Miscellaneous (DDR4 x16 DRAM Down) table, and Miscellaneous Routing Model (DDR4
x16 DRAM Down) figure.
• Chapter 14: Updated SPI_HOLD_L/ESPI_DAT3 and SPI_WP_L/ESPI_DAT2 in the ESPI/SPI ROM
Signals section in the Miscellaneous Signals Quick Reference table.
December 2019 1.02 • Chapter 5: Changed "TBD" for the Maximum trace length to DRAM (L1 + L2 + L7) to 63.5 mm in the
Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM Down) table.
®
• Chapter 6: Updated the PCIe Link Signals section.
• Chapter 7: Changed the TBD for eDP HBR3 to N/A in the Display Interface Maximum Trace Length
vs. Topology table.
• Chapter 11: Added text to remind developer to check the DMIC datasheet to get the left and right
channel connection to the FP6 processor connected correctly. Updated the Routing Rules for WoV
Interface table.
• Chapter 14: Updated PCIE_RST0_L/EGPIO26 and PCIE_RST1_L/EGPIO27 in the Global Signals
section in the Miscellaneous Signals Quick Reference table. Added a 22 pF cap to SPI_TPM_CS_L/
AGPIO29 in the SPI TPM Signals section in the Miscellaneous Signals Quick Reference table. Updated
VDDIO_VPH in the Voltage Regulator Signals table.
• Chapter 15: Updated the VDDIO_VPH Power Delivery and Decoupling section.
October 2019 1.01 • Chapter 9: Changed the differential pair length matching specification for USB3.2 from 0.75 ps to 0.50
ps in the Routing Rules for DP Alt Mode/USB to USB-C® Connector table to be consistent with
DP_TXP/N requirements in Routing Rules for DP Tables.
• Chapter 14: Updated ESPI_ALERT_L in the LPC Signals and ESPI/SPI ROM Signals Connection
section in the Miscellaneous table. Updated SPI_ROM_REQ/EGPIO67 in the ESPI/SPI ROM Signals
Connection section in the Miscellaneous table.
September 2019 1.00 • Removed device specific references for ESD devices throughout document.
• Chapter 5: Added DDR Mode select to the DDR4 Signal Descriptions table and the LPDDR4x Signal
Descriptions table. Added DRx16 to the DDR4 DRAM Down Per-Channel Decoupling Capacitors
table. Added VDDQ -VSS for LPDDR4 to the LPDDR4x DRAM Down Decoupling Capacitors table.
Updated the specification for L4 trace length in the Routing Rules for CLK (DDR4 x16 DRAM Down)
table. Updated Length Matching in the Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM
Down) table. Added LPDDR4 to the Component Table—LPDDR4x DQS Termination table.
• Chapter 6: Added Allowable Link Combination tables in the PCIe® Link Signals section. Added Phy
information to the PCIe® and SATA to M.2 Connector Routing section.
• Chapter 7: Added voids under pads to reduce pad capacitance.
• Chapter 14: Changed the pullup resistor value from 300 ohms to 4.7 kohms for PWROK and RESET_L
in the Miscellaneous Signals Quick Reference table.Updated Termination Voltage for I2C Bus Signals
and added notes about dual-source voltages in the Miscellaneous Signals Quick Reference table. Added
information the DIMM SPD can only be connected to SMBUS0 in the SMBus Interface section. Added
note in the THERMTRIP_L section that the system must return to G3 after a THERMTRIP_L
condition.
Revision History 17
August 2019 0.82 • Chapter 1: Removed SDIO from the Feature Compatibility table. Updated the AVL document PID and
Title in the Reference Documents table.
• Chapter 5: Updated the LPDDR4x DRAM Down Decoupling Capacitors table. Updated the Reference
Plane in the Signals and Connections for LPDDR4x DRAM Down —LPDDR4x x32 table. Updated the
LPDDR4x x32 DRAM Down Routing Rules for Trace length from Tee to DRAM pin (L7) in the
LPDDR4x DRAM Down Layout Guidelines section. Updated the RTT value to 453 ohms in the
Component Table—LPDDR4x DQS Termination table.
• Chapter 7: Removed capacitor C3 from the Schematic Diagram—AUX Conversion Block and HPD
Level Shifter figure and the Component Table—DP++ AUX Conversion Block table.
• Chapter 9: Added note about USB-C programming model change for FP6. Added RESET_L to the
USB-PD controller in the FP6 Processor—DP Alt Mode/USB Controller to Port Mapping—USB-C
Connector figure, the Schematic Diagram—DisplayPort/USB to USB-C Connector figure, and the
Schematic Diagram—DisplayPort/USB with Retimer/Redriver to USB-C Connector figure.
• Chapter 10: Added information about DEVSLP in the SATA Miscellaneous Signals section.
• Chapter 13: Updated the PID and Title of the AVL in the Modern Standby Component Selection
section. Updated the Power Domain for PCIe SSD in the Modern Standby Platform Component I/O and
GPIO Assignment table.
• Chapter 14: Updated SPI_CLK Connection in the Miscellaneous Signals Quick Reference table.
Updated SPI_DI/ESPI_DATA Termination in the Miscellaneous Signals Quick Reference table. Added
SPI_CLK isolation using FET in the SPI ROM Sharing section. Updated the SPI ROM Sharing Routing
Model figure to show the isolation FET on SPI_CLK. Updated the eSPI Single Master-Single Slave
with eSPI_RESET_L Master to Slave Routing Model figure to add pullup resistor on ESPI_ALERT_L.
Added note that SPI_CLK needs isolation FET if ROM is shared in the Enhanced Serial Peripheral
Interface (eSPI) section.
June 2019
0.81
• Chapter 15: Updated the Decoupling Capacitors for Processor Power table.
• Changed from USB3.2 Gen1(5Gpbs) to USB 3.2 G1 (5Gbps) and from USB 3.2 Gen2 to "USB 3.2 G2
(10Gbps) throughout document. Removed CSI Chapter 13 as it is no longer supported.
• Chapter 3: Added 10-layer stackup figure. Added section for removal of non-functional pads.
• Chapter 5: Updated the layers required to breakout DDR. Changed the layers required to support
LPDDR4x from 6 to 10. Updated bullets in the Layout Sequence for DRAM Down and LPDDR4x x32
DRAM Down section. Changed Length Matching from 1.80 ps to .90 ps, deleted Minimum trace length
requirement, and changed Maximum trace length requirement from TBD to 50.8 mm in the Routing
Rules for CLK (LPDDR4x x32 DRAM Down) table. Changed Length Matching requirement from +/-
23 ps to +0 / -20 ps in the Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM Down) table.
Added Breakout Region 1 and Breakout Region 2 requirement and deleted Minimum trace length
requirement in the Routing Rules for DQS (LPDDR4x x32 DRAM Down) table. Added Breakout
Region 1 and Breakout Region 2 requirement, deleted Minimum trace length requirement, and changed
Maximum trace length requirement from TBD to 50.8 mm in the Routing Rules for DQS and Data/DM
(LPDDR4x x32 DRAM Down)
• Chapter 7: Updated Bus Channel SL specification from 5H to 4H in the Routing Rules for DP to
(MainLink to DP or eDP Connector), Routing Rules for DP to (MainLink to DP++ Connector), Routing
Rules for DP to (MainLink to DVI or HDMI Connector), and Routing Rules for DP to (MainLink to
Translator) tables. Updated the Display Interface Maximum Trace Length vs. Topology table.
• Chapter 9: Changed from 152.4 mm to uS 152.4 mm and SL 139.7 mm in the Length Limits for Table
96.
• Added (new) Chapter 12: Secure Biometric Camera Solution.
• Chapter 14: Updated Termination field for SPI_DI signal. Added 27 pF capacitor requirement for
SVT0/SVC0/SVD0.
18 Revision History
April 2019 0.80 USB3.1 was changed to USB3.2 throughout document. Transfer rate was added to USB3.2 Gen1 and USB
3.2 Gen2 for clarification throughout document.
• Chapter 1: Added PID# 56490 to Reference Documents Table.

• Chapter 4: Added bullet for VSS plane stitching vias to Layout Guidelines—Differential Clocks
section. Updated X48M_X1 and X48M_X2, and X32K_X1 and X32K_X2 text in the Single-Ended
Clock Design Guidelines section. Updated the reference plane(s) for Single-Ended Clocks in the Layout
Guidelines—Single-Ended Clocks section. Added a row to Routing Rules for Single-Ended Clocks
table for Stitching Vias specification.
• Chapter 5: Updated LPDDR4x DRAM Down Layout Guidelines section.
• Chapter 6: Added GFX signals to PCIe® Routing Lengths vs. Topology Table for Onboard Device row.
Changed from 0.75ps to 0.50ps in the Routing Rules for PCIe® Interface to Onboard Device table and
the Routing Rules for PCIe Interface to PCIe Connector Table.
• Chapter 7: Increased DP MainLink SL Trace Spacing in the Bus Channel from 4H to 5H. Updated the
Display Interface Maximum Trace Length vs. Topology table. Changed from 0.75ps to 0.50ps in the
Routing Rules for DP (MainLink to DP or eDP Connector) Table and the Routing Rules for DP (AUX
to DP or eDP Connector) Table.
• Chapter 8: Added Example USB-A Connector VSS/Reference Plane Void figure to USB 3.2 Connector
Voids section. Updated specifications for Length Limits and Trace Spacing in the Routing Rules for
USB 3.2 Interface Table.
• Chapter 9: Updated FP6 Processor—DP Alt Mode/USB Controller to Port Mapping—USB-C
Connector Figure: Changed to DP2_AUXP/N to USB-C Port 0 and DP3_AUXP/N to USB-C Port 4.
• Chapter 11: Updated the routing topology in Wake on Voice (WoV) Interface Signals.
• Chapter 13: Updated specifications, or footnotes, or added signals: PWROK, RESET_L,
SYS_RESET_L, PCIE_RST0_L, I2C3_SDA, I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA,
LPC_PME_L, LPC_RST_L, ESPI_ALERT_L, ESPI_RESET_L, SPI_CLK2, SPI_CS2_L, SPI_CS3_L,
ESPI1_DATA[3:0], and SPI_TPM_CS_L in Miscellaneous Signals Quick Reference Table. Added
GPIO gate recommendation to Mobile ACPI Interface Routing Model (Legacy - No Modern Standby
support) figure.
• Chapter 14: Updated the Decoupling Capacitors for Processor Power table.
December 2018 0.50 Early Design Guidance Pending Full Electrical Simulation.
November 2018 0.10 Preliminary release.
Revision History 19
1 Introduction
The AMD FP6 processor combines the central processing unit (CPU) with the graphics processing unit (GPU)
and the fusion controller hub (FCH) in a single-chip AMD Accelerated Processing Unit (APU) package. AMD
FP6 processor-based systems include the memory interface, PCIe® interface, digital display interface (DDI),
power delivery, system I/O interface, clock generator, and miscellaneous test signals that connect to the
processor. This document describes the rules, recommendations, and guidelines for designing FP6 processor-
based systems.
AMD has no responsibility for any errors, expenses, or damages directly or indirectly caused by deviations from
the design guidelines. Any deviation is taken at the sole risk and liability of the designer.
1.1 Compatibility
Table 1 outlines the different feature sets of FP6 processors.
Table 1. Feature Compatibility

Processor Features FP6 Processor
FP6 Type 1 FP6 Type 2
Family/Model Numbers Family 17h, Models 60h-6Fh Family 19h, Models 50h-5Fh
On-chip Graphics Four Display Controllers
Four Display Interfaces
Memory Two 64b DDR4 Channels
or
Four 32b LPDDR4x Channels
DDR EVENT_L Yes
SVI2 Interface(s) 1
Voltage Planes VDDCR

(CPU/GPU, SOC) VDDCR_SOC
SB-TSI Yes
®
PCIe P_GFX x8 (supports up to Gen 3)
P_GPP x12
Four P_GPP lanes are multiplexed with other signals (supports up to Gen 3)
Universal Serial Bus (USB) Ports Four USB3.2 G2 (10Gbps) (Two with USB-C DP alt mode support)
Eight USB2.0 (Four are shared with USB3.2 ports)
Serial Advanced Technology Attachment Yes

(SATA)
Secure Digital I/O (SDIO) No
HDA/Soundwire/Inter-IC Sound (I2S) Yes
Inter-Integrated Circuit (I2C) Yes
Universal Video Decoder (UVD) Yes
20 Introduction
Table 1. Feature Compatibility (continued)

Processor Features FP6 Processor
FP6 Type 1 FP6 Type 2
System Management Bus (SMBus) Yes
Low Pin Count/Serial Peripheral Interface (LPC/ Yes

SPI)
Enhanced Serial Peripheral Interface (eSPI) Yes
Universal Asynchronous Receiver/Transmitter Yes

(UART)
Voltage Regulation—Compatible voltage regulator devices conform to the AMD Serial VID Interface 2.0
(SVI2) Specification.
Thermal Monitoring and Control—This processor uses SB-TSI for thermal monitoring and control. For
specific information about thermal monitoring and control, refer to the Processor Programming Reference (PPR)
for AMD Family 17h, Models 60h-6Fh Processors (NDA) and the Preliminary Processor Programming
Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA).
1.2 General Power Supply Guidelines

For an overview of the power supplies required for the processor and of the power supply relationships during
power-up, power-down, and entry and exit of any power management state, refer to the Electrical Data Sheet for
AMD Family 17h Models 60h-6Fh Processors and the Electrical Data Sheet for AMD Family 19h Models
50h-5Fh Processors.
1.3 Pinout Assignment www.teknisi-indonesia.com

The FP6 processor pin assignments are documented in the FP6 Processor Functional Data Sheet.
1.4 Package Information

For package information, refer to the FP6 Processor Functional Data Sheet.
1.5 Reference Documents

Table 2 provides a list of related documents for additional information.
Table 2. Reference Documents

Short Name PID Title
BIOS and Software
PPR 56569 Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA)
PPR 55922 Processor Programming Reference (PPR) for AMD Family 17h, Models 60h-6Fh Processors (NDA)
Data Sheets
EDS 56805 Electrical Data Sheet for AMD Family 19h Models 50h-5Fh Processors
EDS 56417 Electrical Data Sheet for AMD Family 17h Models 60h-6Fh Processors
FDS 56177 FP6 Processor Functional Data Sheet
RG 56809 Revision Guide for AMD Family 19h Models 50h-5Fh Processors (NDA)
Introduction 21
Table 2. Reference Documents (continued)

RG 56503 Revision Guide for AMD Family 17h Models 60h-6Fh Processors (NDA)
ESPI 56812 AMD Family 19h Models 50h-5Fh Engineering Sample Processor Information (NDA)
ESPI 56482 AMD Family 17h Models 60h-6Fh Engineering Sample Processor Information (NDA)
Debug
HDT N/A Hardware Debug Tool—Hardware and software that interfaces to the JTAG and DB Ports to gain control of internal
functions of the processor
HDT OUDG 56342 HDT Over USBC Design Guide
Platform
MBDG 56178 FP6 Processor Motherboard Design Guide - (NDA) (this document)
SCL 56179 FP6 Processor Motherboard Schematic Checklist - (NDA)
LCL 56180 FP6 Processor Motherboard Layout Checklist - (NDA)
FG 56485 FP6 Processor Platform Code-Named “Celadon" Functionality Guide
UG 56486 FP6 Processor Platform Code-Named “Celadon" User Guide
FG 56487 FP6 Processor Platform Code-Named “Majolica" Functionality Guide
UG 56488 FP6 Processor Platform Code-Named “Majolica" User Guide
PPOG 56465 AMD Family 17h Models 60h-6Fh FP6 Platform Performance and Power Optimization Guide (PPOG) (NDA)
MSBIG 56358
Modern Standby BIOS Implementation Guide
SC-AVL 56641 AMD Approved Vendor List (AVL) System Components for AMD Family 17h Models 60-6Fh Processors (NDA)
SFHDG 56467 AMD FP6 SFH Design Guide
SFHBIG 56559 Sensor Fusion Hub (SFH) BIOS Implementation Guide
SBFBIG 56560 SecureBIO Function BIOS Implementation Guide
Power and Thermal
SVI2_TAN 55711 SVI2 Current Telemetry Hardware Requirement and Calibration Application Note
TDG 56483 Thermal Design Guide for FP6 Processors (NDA)
SSITGT 56494 Smart Shift Implementation Thermal Guideline and Tool (NDA)
FT-UG 56484 Flotherm Thermal Model of FP6 Processor User's Guide
PTDS 56466 AMD Family 17h Models 60h-6Fh Processor Power and Thermal Data Sheet
SDLE2UG 47498 Static and Dynamic Load Emulator 2 (SDLE2) User Guide (NDA)
Roadmaps
IRM 56328 FP6 Infrastructure Roadmap
Specifications
DGFS 48530 AMD Platform Switchable Graphics and Dual Graphics Design Guidance and Functional Specification
– 47713 ANX9834: Ultra Low Power Receiver with VGA and LVDS Output
SVI2 48022 AMD Serial VID Interface 2.0 (SVI2) Specification
22 Introduction
Table 2. Reference Documents (continued)

– 51788 Muxless Switchable Graphics Technology PX5.5 Functional Specification
Validation
SVM 50657 AMD System Validation Manual (SVM)
Introduction 23
2 System Overview
The FP6 processor has many different system configuration options.
Figure 1 shows a block diagram example of a typical FP6 processor-based system.
x1 PCIe
GFX
x1 (x8)
PCIe®
x8 GFX
x1
APU (2 Channels)
DDR4 SO-DIMMs
x1 (iGPU)
Connector DDR DDR4 UDIMMs
x1 DDR4 DRAM Down
x1
LPDDR4x
x1
x1
Display 0 DP0
AUX R Amp L
Display 1 DP1
AUX
CODEC
HDA/
USB-C® Display 2 DP2 Soundwire/
Connector AUX
I2S
using USB 3.2 Head
Mic
internal or G2 (10Gbps) phone
MUX on USB Port 0
DP2/USB Connector USB2
Port 0 Port 0 ACP
WOV Mic
Mic
USB-C DP3
Display 3
Connector AUX
USB 3.2
using G2 (10Gbps)
USB 3.2
internal or G2 (10Gbps) Port 1 USB
MUX on USB Port 4 Connector
USB2
DP3/USB Connector
USB2 Port 1
Port 4 Port 4
USB 3.2
G2 (10Gbps)
Port 5 USB
PCIe GPP
GPP0 Connector
USB2
x1 Port 5
GPP1
x1
GPP2/SATA0 USB
x1 USB2
Port 2 Connector
GPP3/SATA1
x1
USB2 USB
GPP4
x1 Port 3 Connector
Up to
PCIe Devices GPP5 12 GPP
x1 USB2 USB
M.2 WiFi
GPP6 Port 6 Connector
DT x1 Connector Up to
x1
M.2 SSD (4 Lanes) 4 SATA
GPP7 USB2 USB
SATA (4 Lanes)
x1 Port 7 Connector
GPP8/SATA2
x1
LPC/
GPP9/SATA3 LPC/
x1 SPI/
eSPI Embedded
eSPI Controller
GPP10
x1 LPC/SPI/eSPI
SPI
GPP11
x1
UART Devices UART

SPI Device(s)
SPI/ ROM
SFI I2C Sensor Devices I2C SFH eSPI TPM
FP
General I2C/SMBus Devices Four I2C
GPS Two are
NFC SMBus
Touch Panel capable
SVI2 Capable
JTAG SVI2
HDT+ VRM
Debug
Figure 1. Block Diagram—FP6 Processor-Based System
2.1 Memory Overview

FP6 processors support different memory configurations. See Table 1 for a list of FP6 processor features.
24 System Overview
• The FP6 processor can contain up to two 64-bit DDR4 SDRAM memory controllers depending on the OPN.
The maximum capacity depending on OPN is either two SO-DIMMs or two UDIMMs, one on Channel A
and one on Channel B.
2.1.1 Memory Topology
Each DDR channel is routed on the same layer for the Breakout and the Bus Channel portions of the DDR nets
including the Pin Field of the DIMMs. The FP6 package density requires one of the DDR channels to be routed
microstrip. For SO-DIMM designs, the final portion of the net must be on an outer layer of the PCB to connect
to the SMT SO-DIMM socket.
To potentially achieve higher performance when routing DDR traces, AMD recommends waiting until the Bus
Channel region spacing requirements are met before increasing trace width to meet the Bus Channel impedance
requirements.
2.1.2 Valid Memory Configurations

The FP6 processor supports multiple memory configurations. Table 3 shows the recommended socketed-
memory configurations. See the Memory Design Guidelines Chapter for more information on memory signal
descriptions and connections.
Table 3. Recommended Socketed-Memory Configurations per Channel

Memory Type Board Layers Number of DIMM Sockets Number of DIMMs DIMM
per Channel Populated
DDR4 SO-DIMMs or 1 1 SR/DR

6
UDIMMs
Note: SR indicates a single-rank DIMM; DR indicates a dual-rank DIMM.
Table 4 shows the valid DRAM-down configurations.
Table 4. Valid DRAM-Down Configurations per Channel
Memory Type Board Layers DRAM Type Number of DRAMS Rank 0 DRAM Rank 1 DRAM
Quantity Quantity
x8 8 8 –
12
x8 16 8 8
DDR4 DRAM Down x16 4 4 -
6, 8, 10 x16 Dual-Die Package 4 41, 2 -
(DDP)
LPDDR4x DRAM x32 2 21 -

6, 8, 10
Down
Note: 1. Both Rank 0 and Rank 1 are contained in same package for DDP.
2. AMD does not support 3D/stacked DDR4 DRAMs.
2.2 Display Overview

The FP6 processor has both DisplayPort and PCIe GFX interfaces. These interfaces can support various display
interfaces as indicated in Table 5.
System Overview 25
Table 5. Supported Display Interfaces

Processor Display Interfaces Supported
Interface
DisplayPort DP
DP++
eDP
DVI1
HDMI
™ 1
LVDS (through DP to LVDS translator)
VGA (through DP to VGA translator)
Muxed DP2 and For USB-C with DP Alt mode

®
USB-C
Muxed DP3 and For USB-C with DP Alt mode

USB-C
®
PCIe (P_GFX) dGPU
Note: 1. DDC and HPD level translation is required. See DisplayPort to DVI Connector and DisplayPort to HDMI Connector for details.
Sometimes the pin-out of a device and the placement on the board makes it difficult to route signals without
crossing connections. Because of this, PCIe allows a reversal of the physical lane ordering between the host
device (APU) and the target device (dGPU). The requirements are that the lanes are still sequentially ordered but
can be logically reversed; for example, on a x4 P_GFX APU lane 3 connects to dGPU lane 0, APU lane 2
connects to dGPU lane 1, APU lane 1 connects to dGPU lane 2, and APU lane 0 connects to dGPU lane 3.
2.3 Power Management Overview

There are many factors involved with minimizing power consumption and optimizing performance of a system.
Refer to the Power Optimization Design Guidelines, Power Regulator Design Guidelines, and the AMD Family
17h Models 60h-6Fh FP6 Platform Performance and Power Optimization Guide (PPOG) (NDA) for details
required to maximize the performance of a FP6 processor-based system.
26 System Overview
3 PCB Planning
PCB planning encompasses planning motherboard stackups and determining optimal routing methods.
3.1 Stackups
The stackups are driven by mechanical restrictions and routing requirements of high-speed buses such as DDR
memory.
3.1.1 Six-Layer Stackup

Typical notebook system stackups have six layers.
Figure 2 shows a typical six-layer stackup.
Layer
# Layer Material Weight Height (mm) DDR I/O DP
Type
Solder Mask 0.025
Plating 1.0 Oz 0.036
1 Cu 0.5 Oz 0.018 Signal Channel-B Tx/Rx Tx/Aux
Dielectric 0.068
2 Cu 1.0 Oz 0.036 Plane VDDIO_MEM_S3 and VSS VSS VSS
0.076
3 Cu 0.5 Oz 0.018 Signal Channel-A VSS VSS
Dielectric 0.532
4 Cu 0.5 Oz 0.018 Signal Channel-A VSS VSS
0.076
5 Cu 1.0 Oz 0.036 Plane VDDIO_MEM_S3 and VSS VSS VSS
Dielectric 0.068
6 Cu 0.5 Oz 0.018 Signal Channel-B Tx/Rx Tx/Aux
Solder Mask 0.025
Total 1.016
Figure 2. Six-Layer Stackup
3.1.2 Ten-Layer Stackup

Typical system stackups with DRAM down have ten layers.
DRAM Down: Each DDR channel is routed on an internal (stripline) layer from the processor Breakout and Bus
Channel until reaching the DRAM connection area (end route). DRAM connections are made on outer layers.
Reference plane for DRAM down is VSS.
Figure 3 shows a typical ten-layer stackup.
PCB Planning 27
Thickness Ref
Vias Layer Type Material mm [mils] (1) Dk (2) Plane
DIELECTRIC SOLDERMASK 0.0127 [0.50] 3.00
L1 CONDUCTOR 1/2 OZ COPPER + PLATE 0.0460 [1.81] L2
DIELECTRIC 1080 PREPREG 0.0686 [2.70] 3.70
L2 PLANE 1/2 OZ COPPER 0.0152 [0.60]
DIELECTRIC CORE 1080 0.0762 [3.00] 3.80
L3 CONDUCTOR 1/2 OZ COPPER 0.0152 [0.60] L2 & L4
DIELECTRIC PREPREG 0.2978 [11.72] 3.90
L4 PLANE 1/2 OZ COPPER 0.0152 [0.60]
DIELECTRIC CORE 1080 0.0762 [3.00] 3.80
L6 PLANE 1/2 OZ COPPER 0.0152 [0.60]
DIELECTRIC CORE 1080 0.0762 [3.00] 3.80
L7 PLANE 1/2 OZ COPPER 0.0152 [0.60]
DIELECTRIC CORE 1080 0.0762 [3.00] 3.80
L9 PLANE 1/2 OZ COPPER 0.0152 [0.60]
DIELECTRIC 1080 PREPREG 0.0686 [2.70] 3.70
L10 CONDUCTOR 1/2 OZ COPPER + PLATE 0.0460 [1.81] L9
DIELECTRIC SOLDERMASK 0.0127 [0.50] 3.00
Thickness Over Copper (4) 1.5491 [60.99]
Thickness Over Soldermask (4) 1.5745 [61.99]
Figure 3. Ten-Layer Stackup
Note: 1. Dielectrics with target thickness under 0.15 mm (6 mils) must be approved for changes ≥ .005 mm
(0.2 mils).
2. Report DK variances used for impedance calculation of greater than +/-0.3.
3. Approval required if an increase of target line width is needed to meet impedance.
4. PCB thickness tolerance is +/- 10% and is measured at gold plated fingers if present and over solder
mask if gold fingers are not present.
3.1.3 Twelve-Layer Stackup

Typical notebook system stackups with DRAM down have twelve layers.
Each DDR channel is routed on an internal (stripline) layer from the processor Breakout and Bus Channel until
reaching the DRAM connection area (end route). DRAM connections are made on outer layers. Reference plane
for DRAM down is VSS.
Figure 4 shows a typical twelve-layer stackup.
28 PCB Planning
Height Layer
# Layer Material DDR I/O DP
(mm) Type
Solder Mask 0.025
1 Cu 0.5 Oz 0.018 Signal End Route Tx/Rx Tx/Aux
Dielectric 0.076
2 Cu 1.0 Oz 0.036 Plane VSS VSS VSS
Dielectric 0.076
3 Cu 0.5 Oz 0.018 Signal CH-B Data
Dielectric 0.221
Dielectric 0.076
5 Cu 0.5 Oz 0.018 Signal Ch-A or Ch-B Address
Dielectric 0.221
6 Cu 1.0 Oz 0.036 Plane VDDIO_MEM_S3
Dielectric 0.076
7 Cu 1.0 Oz 0.036 Plane VREF VSS VSS
Dielectric 0.221
8 Cu 0.5 Oz 0.018 Signal Ch-A or Ch-B Address
Dielectric 0.076
Dielectric 0.221
10 Cu 0.5 Oz 0.018 Signal CH-A Data Tx/Rx Tx/Aux
Dielectric 0.076
Dielectric 0.076
12 Cu 0.5 Oz 0.018 Signal End Route Tx/Rx Tx/Aux
Solder Mask 0.025
Total 1.858
Figure 4. Twelve-Layer Stackup
3.2 Impedance
In a high-speed signaling environment, signal trace impedances must be controlled in order to maintain good
signal quality across the motherboard. Signal trace impedance is a function of the following factors.
• Motherboard stackup
• Dielectric constant of the PCB substrate
• Signal trace width
• Signal trace thickness
The reliance of signal trace impedance on these factors demonstrates the importance of following the
recommended stackup and routing rules outlined in this document.
The processor routing guidelines were developed with the aid of signal-integrity simulations. These simulations
assume controlled-impedance motherboards with a dielectric constant between 3.6 and 4.4 @ 1 GHz. Any epoxy
resins, including those employing halogen-free technology are acceptable, provided the recommended dielectric
constant is met.
3.3 Trace Length Matching

The motherboard layout guidelines provided in this document define length-matching criterion for PCB traces.
The length-matching guidelines were derived using a default trace propagation delay (Pd) of 150 ps per inch for
microstrip (µS) traces or 180 ps per inch for stripline (SL) traces.
Pd varies depending on the motherboard stackup. Compute the actual Pd for µS and, if applicable, SL traces.
Use the actual Pd to convert routed lengths to effective lengths. Always use effective lengths when verifying
compliance to AMD length-matching guidelines.
PCB Planning 29
Table 6 shows an example of effective-length matching being calculated for two traces. The length-matching
guideline in this example is ≤ 15 ps. Based on a Pd of 150 ps per inch, 15 ps equates to 100 mils.
In this example, the Pd of the motherboard does not match the default Pd, so the effective length must be
calculated. The L2 trace segments are routed as SL, so the propagation delay for an SL trace must be used. The
L1 and L3 propagation delays also are calculated using the customer µS Pd. Although the total routed trace
lengths appear to meet the 15-ps specification (100 mils), the effective-length mismatch fails after accounting for
the varying Pd of the µS and SL traces.
Table 6. Computing Trace-Length Matching Example

Length Matching: ≤ 15 ps (100 mils)
Trace Segments L1 L2 L3 Total Difference Result
Trace type µS SL µS
Pd (ps per inch) 149 181 149
Trace A (mils) 1,510 3,000 2,010 6,520 60 mils PASS

Trace B (mils) 1,500 3,200 1,880 6,580 (physical length only)
Trace A Pd 1,500 3,620 1,997 7,117 102 mils FAIL

Trace B Pd 1,490 3,861 1,867 7,218 (effective length)
In summary, board designers must consider their motherboard-specific Pd and their use of combined µS and SL
trace segments to accurately compute effective lengths when performing length matching. False passes may
result if variance from the default motherboard Pd is not considered.
3.4 DDR Trace Routing Regions
The DDR layout guidelines divide routing specifications into three sections: Breakout, Bus Channel, and End
Region (DIMM Field or DRAM Via/Pin Field).
The following trace-routing scenarios exist dependent upon the type of system memory used:
• Through-hole UDIMMs
• SMT SO-DIMMs, UDIMMs
• SMT DRAMs
These scenarios cause the definition of the End Region to vary. The Breakout and Bus Channel definitions are
identical for all scenarios. Although a single-ended trace is represented in the subsequent figures, the same
principles apply to differential traces.
Figure 5 illustrates how the Breakout and Bus Channel are determined for all scenarios. The regions are defined
for each trace, as it is routed from point to point. The regions are not geographical locations on the motherboard.
The regions are allocated as the routed trace meets the minimum trace length required for that region.
30 PCB Planning
DDR ROUTING REGIONS

Breakout Bus Channel End Region
Processor
500-mils
routed length Implementation
Specific
Drawing is not to scale
Figure 5. DDR Routing Regions
Breakout
The Breakout region is closest to the processor and is assigned the first 500 mils of routed trace, beginning at the
processor pin. In some routing scenarios such as traces to a strapping resistor, the trace may not be 500 mils
long. However, the Breakout routing rules still apply. The Breakout always exists even if the minimum trace
length is not met.
The Breakout region is a space-constrained area where routing traces is more difficult. Therefore, narrower trace
widths resulting in higher impedances and narrower trace spacing are allowed compared to the Bus Channel.
When routing traces in the Breakout region, it is more important to utilize available space to maximize trace
spacing than to increase trace width to match the lower Bus Channel impedance. Increasing trace spacing
minimizes coupling across traces and improves overall signal quality, more so than widening traces to meet the
Bus Channel impedance.
If adequate space exists in the Breakout region, a trace can break out in less than 500 mils. Implement the Bus
Channel impedance and trace spacing rules for the remainder of the Breakout region in this scenario.
Bus Channel
The Bus Channel is assigned the balance of the routed trace that does not reside in the Breakout or End Region.
End Region — Through-hole UDIMMs
Figure 6 illustrates how the End Region (DIMM Field) is defined for a through-hole UDIMM implementation.
As illustrated below, the End Region is defined by a box drawn within 100 mils of the UDIMM outer row of
pins. All trace segments routed within this box are designated as being in the End Region. The End Region
applies to all routed layers.
Similar to the Breakout region, the End Region is also a space-constrained area. Give priority to maximizing
trace spacing over increasing trace width.
PCB Planning 31
DDR ROUTING REGIONS – THROUGH-HOLE DIMMs
End Region
Breakout Bus Channel All routing layers
Processor DIMM DIMM
500-mils
routed length
100 mils
Breakout is defined on
a signal-by-signal basis Box around
outermost row of
pins
100 mils
Figure 6. End Region - Through-hole UDIMMs
End Region — SMT SO-DIMMs or DRAMs with Tee Vias

Figure 7 illustrates how the End Region is defined for SMT SO-DIMM (DIMM Field) or onboard SMT DRAM
(DRAM Via/Pin Field) implementations that contain tee vias in the routing topology. The first tee via
encountered along the trace from the processor designates the beginning of the End Region. All trace segments
beyond this tee via, routed to any or all devices on any layer, are designated to be in the End Region.
Similar to the Breakout, the End Region is also a space-constrained area. Give priority to maximizing trace
spacing over increasing trace width.
DDR ROUTING REGIONS – SMT WITH TEE VIAS

End Region
Breakout Bus Channel Begins at 1st Tee Via
Processor
500-mils
routed length SMT SMT
Device Device
All trace segments

beyond the 1st Tee Via
are in the End Region
Figure 7. End Region - SMT Device with Tee Vias
End Region — SMT SO-DIMMs or DRAMs without Tee Vias
32 PCB Planning
Figure 8 illustrates how the End Region is defined for SMT SO-DIMM (DIMM Field) or onboard SMT DRAM
(DRAM Via/Pin Field) implementations that do not contain tee vias in the routing topology. The End Region is
depicted as the area within the red dotted line. This boundary line essentially defines a fence placed around the
concentration of layer-change vias within 100 mils of the vias. If a signal changes layers within this boundary,
the resulting trace segment is designated as being in the End Region. This µS trace segment must reside on the
same outer routing layer as the SMT device. This µS trace segment is referred to as the End Route in the DDR
Routing Rules tables. Stripline trace segments occurring before the final layer-change via, although routed
through the End Region boundary, are designated as Bus Channel trace segments.
DDR ROUTING REGIONS – SMT POINT TO POINT (No Tees)

End Region
Exists only on same layer as DIMM
Breakout Bus Channel
Processor
500-mils SMT SMT
routed length DIMM DIMM
End Region boundary line
encircles DIMM signal vias.
Figure 8. End Region - SMT Device and No Tees
3.5 Crosstalk
Follow these recommendations to reduce crosstalk on the motherboard.
• Do not allow high-speed signals to cross reference-plane splits.
• Reference critical signals to ground planes.
• Do not cut ground planes unless it is absolutely necessary.
• Reduce the length of signals that are routed in parallel.
• Provide analog signals with guard shields or guard rings.
• Keep analog signals away from digital signals.
• When performing neighbor spacing calculations, ignore GND pours on the same layer as the signal.
During the board layout phase, spacing violations can contribute to crosstalk and other signal integrity concerns.
Follow the rules for serpentine (self-) spacing in order to minimize signal quality concerns. Figure 9 shows an
example of trace spacing and serpentine spacing.
PCB Planning 33
Serpentine
Spacing
Trace Spacing
Differential Spacing
Figure 9. Serpentine (Self) Spacing
3.6 Routing of Differential Signals

Figure 10 illustrates the recommended routing method for differential signals. In the example in Figure 10, sense
signals are used to show differential signal routing around vias. The first two routing methods illustrated
maintain the same length for the signal pair; these are acceptable routing methods for differential signals. In the
third method illustrated, one path is much longer than the complement; this is an unacceptable routing method
for differential signals.
SIGNAL_P
SIGNAL_N
Figure 10. Routing Differential Signals Around Vias
Both traces of the differential pair must be routed such that both signals are exposed to similar noise
environments (Common-Mode Noise). Figure 11 illustrates acceptable and unacceptable spacing of differential
signals to other signals and noise sources. Item (d) fails due to excessive spacing within the pair; item (e) fails
for insufficient space to other nets; and item (f) fails because the routing is too close to an inductor.
When routing high-speed differential signals, traces must have sufficient spacing to avoid broadside coupling.
34 PCB Planning
Differential
Traces Differential Traces
(a) (b) (c)
H L H VIA L
Acceptable
Differential
Differential Traces Traces
(d) (e) (f)

L H H L
Not Acceptable
Figure 11. Differential Traces and Spacing
3.7 Reference Planes

Reference planes serve as the return path for high-speed signal currents. The reference plane upon which return
currents flow depends on the routing topology chosen. The typical signal-routing topologies for high-speed
signals are microstrip and stripline.
3.7.1 Reference Plane—Microstrip
Microstrip routing topology consists of transmission lines on one side of a dielectric substrate and a reference
plane on the opposite side. The reference plane forms the layer adjacent to the routing layer. Figure 12 shows a
typical microstrip structure.
t
h
w = width of trace
h = distance between signal trace and reference plane
t = thickness of trace
Figure 12. Microstrip Topology
In microstrip structures, the return path for a signal lies directly beneath the signal on the adjacent reference
plane; therefore, it is important for the reference plane to be solid, in other words, without splits, in order to
greatly reduce problems with signal integrity, timing, and EMI radiated emissions.
3.7.2 Reference Plane—Stripline

Stripline routing topology consists of transmission lines located between two reference planes, with a dielectric
material completely surrounding the traces. Figure 13 shows a typical stripline structure.
PCB Planning 35
h2
t
h1
w = width of trace
h1 = distance between signal trace and lower reference plane
h2 = distance between signal trace and upper reference plane
t = thickness of trace
Figure 13. Stripline Topology
In stripline structures, both reference planes form the return path for a signal. The return path lies directly
beneath the signal on the lower reference plane and directly above the signal on the upper reference plane. The
amount of return current flowing on each reference plane is determined by the distance from each plane to the
signal layer.
In a symmetrical stripline h1 = h2. The return current is shared equally between the two planes, in other words,
half of the return current flows on one plane, and the other half flows on the other plane.
In an asymmetrical stripline h1 < h2. A higher percentage of the return current flows on the reference plane
closer to the signal layer (h1) than on the plane that is farther away (h2). The signal layer has strong coupling to
the reference plane that is closer to it, and it has weak coupling to the reference plane that is farther away.
3.7.2.1 Reference Plane Splits

It is important for both reference planes of a stripline route to be solid, in other words, without splits, in order to
greatly reduce the risk of signal integrity, timing, or EMI issues.
When splits in the weak-side plane of an asymmetric stripline are unavoidable, and signals cross those splits, it is
important for the weak-side plane to be at a minimum distance away from the signal layer to reduce the risk of
EMI issues. The minimum separation between the weak-side plane and the signal layer depends on the type of
signal crossing the plane split, for example, single-ended high-speed signals or differential high-speed signals. A
single-ended high-speed signal crossing a plane split as shown in Figure 14 can produce radiated-emission
(EMI) failures 20 dB above the Class B limit.
36 PCB Planning
Split in Weak Side Plane
h2
h1
Figure 14. Single-Ended Signal Crossing a Weak Side Plane Split
Differential high-speed signals crossing a plane split as shown in Figure 15 can produce EMI failures 14 dB over
the B limit; therefore, when high-speed signals cross plane splits in the weak-side plane of an asymmetric
stripline, it is critical that the separation between the signal layer and the weak-side plane provide an isolation of
at least 20 dB for single-ended high-speed signals and 14 dB for differential high-speed signals.
Split in Weak Side Plane
h2
h1
Figure 15. Differential Signal Crossing a Weak Side Plane Split
PCB Planning 37
As indicated in Table 7 the recommended minimum distance between the split, weak-side plane and the signal
layer of an asymmetric stripline, to ensure compliance with Class B radiated-emission limits is:
• h2 = 3.0 x h1 for single-ended high-speed signals
• h2 = 2.0 x h1 for differential high-speed signals
Where:
• h1 = distance between signal layer and strong-side (closer) plane
• h2 = distance between signal layer and weak-side (farther) plane
Table 7. Asymmetric Stripline dB Isolation on Weak-Side Plane with Moat
Single-ended
1 Differential Signals
Asymmetric Stripline - Split Returns Reference Signals
EMC Risk vs. SS/WS Coupling with Plane Moat
Common and Differential
Common Mode Risk Only 3
Mode Risk 2
EMC Compliance CLASS B EMC Compliance CLASS B

h1 h2
Levels Levels
Undesired
Strong Weak Desired Plane Xtalk dB isolation
Side Side SS Moat Lay out Considerations per Risk Zone
on WS plane
(SS) (WS) Coupling WS Coupling h1 3/ h2 3
1 1 50% 50% 1.000 0.000 dB
1 1.2 65% 35% 0.694 -3.167 dB
High Risk
1 1.4 74% 26% 0.510 -5.845 dB
1 1.6 80% 20% 0.391 -8.165 dB
High Risk
1 1.8 85% 15% 0.309 -10.211 dB
1 2 88% 13% 0.250 -12.041 dB Medium Risk
1 2.2 90% 10% 0.207 -13.697 dB
1 2.4 91% 9% 0.174 -15.208 dB Greater than 14 dB isolation
1 2.6 93% 7% 0.148 -16.599 dB
1 2.8 94% 6% 0.128 -17.886 dB
1 3 94% 6% 0.111 -19.085 dB Medium Risk
1 3.2 95% 5% 0.098 -20.206 dB Low Risk / Safe
1 3.4 96% 4% 0.087 -21.259 dB Greater than 20 dB isolation
1 3.6 96% 4% 0.077 -22.252 dB
1 3.8 97% 3% 0.069 -23.191 dB
1 4 97% 3% 0.063 -24.082 dB
1 4.2 97% 3% 0.057 -24.930 dB Low Risk / Safe
1 4.4 97% 3% 0.052 -25.738 dB
1 4.6 98% 2% 0.047 -26.510 dB
1 4.8 98% 2% 0.043 -27.250 dB
1 5 98% 2% 0.040 -27.959 dB
Normalized to h1 = 1.0
Notes: 1. Single-ended signal breach over moat can exceed CLASS B emissions > 20 dB over limit.
2. Assumes common-mode (CM) emissions of transceivers are 6 dB below the differential-mode (DM) (single-ended) emissions.
3. Assumes differential trace moat breaches include stitching capacitor across moat breach.
3.8 Changing Reference Planes

There are two cases where a signal may change reference planes: crossing a plane split or changing signal layers.
If either of these are unavoidable, techniques must be used to minimize the negative impact caused by changing
reference planes. Crossing plane splits for high speed differential signals is allowed as long as the crossing is
38 PCB Planning
orthogonal to the split (straight across if possible). Minimize the width or gap of the split to minimize
impedance discontinuity.
3.8.1 Stitching Vias

A stitching via connects two reference planes of the same potential and is placed close to a signal layer-change
via. A stitching via provides a short signal return-current path. DIMM connector power and ground vias are not
stitching vias. Measure placement specifications from the center of each via.
• Stitching vias must be placed within the specified distance to the layer-change via for optimal performance.
• Stitching vias are permitted only where indicated in each checklist section.
• Minimum of one stitching via is used when a differential pair changes layers, but two vias are preferred. For
example, clock.
• One stitching via is used when an individual single-ended signal changes layers. For example, a single-ended
clock.
• One stitching via is used for up to three single-ended signals changing layers. For example, an address bus.
Place stitching vias among the signal vias when signal traces change layers in order to provide a return path
between the two reference planes. Place the stitching vias as shown in the following figures: Figure 16, Figure
17, Figure 18, and Table 8.
Stitching
Differential Pair routed on Via
Top Microstrip
GND 1
Signal
Side View
Vias
PWR 1
GND 2
Differential Pair routed on

Bottom Microstrip
Stitching Signal
Vias
Top View
Vias
r1
Top Microstrip reference to GND 1 Bottom Microstrip reference to GND 2
Figure 16. Stitching Via Placement for Multiple Differential Pairs
Figure 17 shows the recommended stitching via placement for single-ended nets.
PCB Planning 39
Single-Ended Traces
r1
r1
r2 r1
One Single-Ended Clock Multiple Single-Ended Multiple Single-Ended

Trace Non-Clock Traces Clock Traces
1:1 3:1 1:1
Figure 17. Stitching Via Placement for Single-Ended Traces
Figure 18 shows the recommended stitching via placement for differential pairs.
Differential Pairs
r1
r1
One Pair
Multiple Pairs
(1 x Diff Pairs)
(N x Diff Pairs)
(2 Vias)
(N + 1 Vias)
Figure 18. Stitching Via Placement for Differential Pairs
Table 8 shows the design specifications for via stitching between two reference planes.
Table 8. Stitching Vias—between Two Reference Planes

Signal Type1 Signal to Via Ratio Distance From Via Comment
SE Clock 1 net : 1 via r1 ≤ 1.27 mm Single or multiple clock traces
40 PCB Planning
Table 8. Stitching Vias—between Two Reference Planes (continued)

Signal Type1 Signal to Via Ratio Distance From Via Comment
SE Non Clock 1 net : 1 via r1 ≤ 1.27 mm Single trace
SE Non Clock 3 nets : 1 via r2 ≤ 1.905 mm Multiple traces
Differential Pair2 1 pair : 1 via r1 ≤ 1.27 mm Single Differential Pair
Differential Pair N pairs : N + 1 vias r1 ≤ 1.27 mm Multiple N Differential Pairs
Note: 1. SE is Single Ended

2. One via per differential pair is required but two vias are preferred
3.8.1.1 High-Speed Differential Signal Pair Voids, VSS Vias, and AC-Coupling Capacitor Voids
VSS vias for high-speed differential signal pairs are required for ≥ 8Gb/s and recommended for < 8Gb/s. Figure
19 shows an example of a preferred high-speed differential signal pair with 4 VSS vias that improves signal
integrity. The VSS vias for high-speed differential signal pairs help reduce common-mode noise. The distance
from the GND to signal vias must remain symmetrical.
1.0 mm Plating Wall

Signal Vias
Finished Hole
Void
2.1 mm
0.8 mm
GND Vias Drill Hole
Pad Size
0.9 mm
Figure 19. Preferred Optimized 6 Layer PCB Differential Signal Vias with 4 VSS Vias
• Place the 4 Ground Vias Symmetrically.

• Finished Drill Hole Size 0.3 mm, Pad Size (Diameter) 0.5 mm
• Remove all unconnected internal layer pads beneath the void.
PCB Planning 41
Figure 20 shows an example of an acceptable high-speed differential signal pair with 2 VSS vias that improves
signal integrity. The VSS vias for high-speed differential signal pairs help reduce common-mode noise. The
distance from the GND to signal vias must remain symmetrical.
Plating Wall
Signal Vias
Finished Hole
Void
2.1 mm
0.8 mm
GND Vias Drill Hole
Pad Size
0.9 mm
Figure 20. Acceptable Optimized 6 Layer PCB Differential Signal Vias with 2 VSS Vias
• Place the 2 Ground Vias Symmetrically

Figure 21 shows another example of an acceptable high-speed differential signal pair with 2 VSS vias that
improves signal integrity. The VSS vias for high-speed differential signal pairs help reduce common-mode
noise. The distance from the GND to signal vias must remain symmetrical.
Plating Wall
Signal Vias
Finished Hole
Void
2.1 mm
0.8 mm
GND Vias Drill Hole
Pad Size
0.9 mm
Figure 21. Acceptable Optimized 6 Layer PCB Differential Signal Vias with 2 VSS Vias
• Place the 2 Ground Vias Symmetrically
42 PCB Planning
High-speed AC-coupling capacitor voids are required for ≥ 8Gb/s and recommended for < 8Gb/s. Figure 22
shows an example of a high-speed AC-coupling capacitor VSS/Reference plane void that improves signal
integrity. The void is directly beneath the signal pins on the nearest/adjacent reference plane.
2.2 mm
Signal
Pads
2 mm
0.8 mm
0.5 mm
GND Vias Void

0.6 mm
Figure 22. High-Speed AC-Coupling Capacitor VSS/Reference Plane Void
Note: GND Via location is flexible, but cannot be placed in the void area.
3.8.2 Stitching Capacitors

A stitching capacitor connects two reference planes of different potential. Stitching capacitors are used to
provide a short return path when the normal return path is broken. Signals that cross reference-plane splits
require stitching capacitors, as do signals that change layers resulting in a reference plane of a different potential.
Placement specifications are measured from the center of a layer-change via(s) or a reference-plane-split
crossing to the closest edge of a stitching capacitor footprint pad.
• Place the stitching capacitor within the specified distance to the layer-change via for optimal performance.
• Stitching capacitors are only permitted where indicated in each checklist section.
• One stitching capacitor is used when an individual differential pair changes layers. For example, clock.
• One stitching capacitor is used for up to four differential pairs changing layers. Place the stitching capacitor
in the center of the four differential pairs.
• One stitching capacitor is used when an individual single-ended signal changes layers. For example, a single-
ended clock.
• One stitching capacitor is used for up to three single-ended signals changing layers. For example, an address
bus.
3.8.2.1 Changing Reference Planes—Same Layer

Use a 0.1-µF or 0.01-µF stitching capacitor with an 0402 or smaller body size when a signal crosses a reference-
plane split on the same layer. Place a stitching capacitor no more than 0.508 mm (20 mils) from where the trace
crosses the reference-plane split as shown in Figure 23.
PCB Planning 43
Stitching
Capacitor
Side View
Stitching Top View

Capacitor
r1
Reference Plane 1 Reference Plane 2
Figure 23. Trace Crossing Reference Plane Split—Same Layer
In cases where signals may reference only one of a number of reference planes, the allowable reference planes
are stated as "VSS ^ VDDIO," meaning the plane is either VSS or VDDIO exclusively. The signal may not
change reference planes.
In cases where signals may reference more than one plane, the allowable reference planes are stated as "VSS or
VDDIO," meaning the planes are either VSS or VDDIO. The signal may change reference planes, provided that
reference-plane split crossing and stitching capacitor rules are followed.
3.8.2.2 Changing Reference Planes—Different Layers

When a signal net changes reference planes due to a layer change use a 0.1-µF or 0.01-µF stitching capacitor
with an 0402 or smaller body size. Place the stitching capacitor as close as possible to the reference-plane split
crossing, as shown in Figure 24.
44 PCB Planning
Stitching Capacitor Vias to Reference Plane

Example Trace
Plane 1
Side View
Plane 2
SE Clock
SE Clock
SE Non-CLK
SE Non-CLK
r1
SE Non-CLK
Differential Pair
Top View
Reference to Plane 1 Reference to Plane 2
Figure 24. Trace Crossing Reference Plane Split—Different Layer
Table 9 shows the design specifications for capacitor stitching between two reference planes.
Table 9. Stitching Capacitors—between Two Reference Planes

Signal Type1 Signal to Capacitor Ratio2 Distance From Capacitor Comment
SE Clock 1 net : 1 capacitor r1 ≤ 1.27 mm Single or multiple clock traces
SE Non Clock 1 net : 1 capacitor r1 ≤ 1.27 mm Single trace
SE Non Clock 3 nets: 1 capacitor r1 ≤ 1.905 mm Multiple traces
Differential Pair 1 pair : 1 capacitor r1 ≤ 1.27 mm Single Differential Pair
Differential Pair 4 pairs : 1 capacitor r1 ≤ 1.905 mm Multiple Differential Pairs
Note: 1. SE is Single Ended

2. Layer change or crossing a reference-plane split
PCB Planning 45
3.9 Point-to-point Routing

Point-to-point routing routes traces directly from the source pin to the destination pin without encountering any
other logic. Layer changes, pull-up, and pull-down terminators may be used and the routing is still considered to
be point to point.
3.10 Non-Functional Pads on Vias and Connectors

Remove all non-functional pads from vias and connectors on the PCB.
3.11 Via Stubs

When changing layers, some high-speed signals prohibit the use of vias with excessively long stubs because long
stubs contribute to crosstalk and reduce signal quality. In general, it is good practice to avoid routing scenarios
that yield long stubs. In some cases this may be unavoidable, such as when routing DDR traces on -layer board.
Figure 25 shows examples of layer changes and the resulting via stubs.
Preferred Acceptable
Top Microstrip Top Microstrip
No Stubs Short Stub
Lower Stripline
Stitching Bottom Microstrip Stitching

Via Via
Acceptable Avoid
Top Microstrip
Upper Stripline Upper Stripline

Short Stubs
Long Stub
Lower Stripline
Stitching No Stitching
Via Vias Needed
Figure 25. Via Stubs
46 PCB Planning
4 Clock Design Guidelines

The FP6 APU features an integrated clock generator designed to meet the needs of a fully featured system.
The following sections contain specific schematic and board layout rules for the APU integrated clock generator
and input clock requirements.
4.1 Differential Clock Design Guidelines

The FP6 APU has the following pairs of differential clock pins:
• GPP_CLK[6:0]P/N (output)
GPP_CLK[6:0]P/N outputs are controlled by CLK_REQ[6:0]_L. Refer to the Processor Programming Reference
(PPR) for AMD Family 17h, Models 60h-6Fh Processors (NDA) and the Preliminary Processor Programming
Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA) for details.
The GPP clocks are designated for PCIe devices which can include an onboard PCIe® graphics device.
4.1.1 General Differential Clock Schematic and Layout Requirements

Use the following schematic design rules for an integrated clock-generator design.
Route the processor clock as follows:
• Always reference a VSS plane (preferred) or a power plane (not including the 12.7 mm for processor
Breakout).
• Layer changes and crossing plane splits are discouraged. If changing layers or crossing plane splits is
unavoidable, follow the recommendations outlined in Reference Planes.
4.1.2 Layer Assignments—Differential Clocks
The differential clock layer assignments are shown in Figure 26 .
OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER DIFF_CLK DIFF_CLK OTHER
VSS OTHER POWER VSS
VSS OTHER POWER VSS
Figure 26. Differential Clock Signal Assignment for Six-Layer Board
Clock Design Guidelines 47

4.1.3 Layout Guidelines—Differential Clocks

No onboard termination is required for the differential clocks. The target Bus Channel impedance for differential
clock allows for 10% variance, which includes manufacturing tolerances. The differential signal pair uses point-
to-point routing and references a VSS plane (preferred) or a power plane.
GPP_CLK[6:0]P/N:
• Connect to a PCIe connector or onboard device REFCLK input pair with an optional 0-Ω source series
termination resistor on each net, if supported.
• Place termination within 25.4 mm of the pin.
• One VSS plane stitching via for each clock via pair.
• Leave unconnected if not used.
Figure 27 shows the routing model for differential clocks.
BREAK PIN
BUS CHANNEL
Processor OUT FIELD dGPU
12.7 mm
GPP_CLK[6:0]P IN0_H PCIe® Slot/Device

GPP_CLK[6:0]N IN0_L
GPP_CLK[6:0]P IN[6:0]_H
GPP_CLK[6:0]N IN[6:0]_L
Internal Clock
Generator
Figure 27. Differential Clock Routing Model
Differential clocks use the layout and length-matching routing rules in Table 10.
Table 10. Routing Rules for Differential Clocks
Signals Rule Description Specification
Device Spacing Placement of stitching vias relative to signal vias ≤ 1.27 mm
Placement of stitching capacitor relative to signal vias ≤ 1.27 mm
Differential vias (within pair) are placed center to center ≤ 1.27 mm
GPP_CLK[6:0]P Separation of layer-change vias on same signal ≥ 12.7 mm

GPP_CLK[6:0]N Plane Edge Trace spacing from reference-plane edge ≥ 5H
Length Maximum difference between true and complement traces in a differential 0.75 ps
Matching pair
Length Limits Minimum trace length 25.4 mm
Maximum trace length 304.8 mm
Table 10. Routing Rules for Differential Clocks (continued)

Bus Channel
Signals Rule Breakout Pin Field
µS SL
Max Layer Changes 4
ZOD ≥ 0.1/0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%

GPP_CLK[6:0]P
GPP_CLK[6:0]N Trace Spacing ≥ 0.1 mm ≥ 5H ≥ 4H ≥ 3H
Self Spacing Not Permitted ≥ 5H Not Permitted

(serpentine)

4.2 Single-Ended Clock Design Guidelines

This section provides specific termination, routing, and layout rules for single-ended clocks. The following
single-ended clock signals are either inputs to the processor, or are single-ended clock outputs generated by the
processor.
• X48M_OSC
Connect this clock to devices that require a single-ended OSC input with a 22Ω, 5% series termination
resistor. This single-ended clock output is 48 MHz. The clock drive strength is configurable to either 4 mA or
8 mA. The default setting is 8 mA. For a single load configuration the recommended drive strength is 4 mA.
Refer to the Processor Programming Reference (PPR) for AMD Family 17h, Models 60h-6Fh Processors
(NDA) and the Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 50h,
Revision A0 Processors (NDA) for programming register selectable parameters. Connect to devices that
require a free-running non-spread 48-MHz clock.
• X48M_X1 and X48M_X2:
These clock inputs are designated for the APU integrated clock generator. Connect to a 48-MHz fundamental
XTAL (± 10 PPM recommended) with a capacitor (typically 22 pF) to GND as required by XTAL and 1
-MΩ , 5% resistor from X48M_X1 to X48M_X2. Overtone XTALs are not supported. This is the reference
clock for the internal clock generator. Accuracy of the system time depends on the XTAL PPM and load
capacitors selected. System time is a function of the HPET counter which uses 48 MHz as the clock source.
Adjust the XTAL PPM and load capacitor values to meet the intended system time accuracy requirements.
AMD reference designs are validated with a 22-pF capacitor.
• RTCCLK
This clock output is designated for a device requiring an RTC clock.
• X32K_X1 and X32K_X2:
These clock inputs are designated for the processor integrated realtime clock. Connect a 32.768 kHz (±
20 PPM recommended) XTAL with a capacitor value of 15 pF, regardless of XTAL ESR, to VSS on each
signal and a 20-MΩ, 5% resistor across X32K_X1 and X32K_X2. The ESR for the XTAL should be between
10 kΩ to 65 kΩ. The maximum ESR can be no more than 65 kΩ. The capacitor value must be tuned to the
PCB layout, must meet the allowable load capacitance range as defined by the XTAL manufacturer, and must
be tested to satisfy the RTC accuracy requirements of the platform. AMD reference designs are validated
with a 15-pF capacitor.
4.2.1 RTCCLK Real Time Clock (RTC) and Battery Interface

The APU contains an integrated realtime clock (RTC) with battery backup. External RTC is not supported. This
clock output is designated for a device requiring an RTC clock. Figure 28, Figure 30, and Table 11 show the
schematic and layout guidelines for the RTC with battery-backup interface signals.

32K_X1 L1
Processor 32.768-kHz
Crystal
32K_X2 L1
External Device
RTCCLK
(optional)
+3.3V_LDO
JUMPER = 1:2 Normal Either
JUMPER = 2:3 Clear CMOS Install if VDDBT_RTC_G
is connected to Coin Battery
VDDBT_RTC_G
3 2 1 BT1
Jumper 3.3V ALW

or
Install if VDDBT_RTC_G
is connected to S5 power
Figure 28. RTC with Battery Backup Interface Routing Model
4.2.2 General Single-Ended Clock Layout Requirements

Route the processor clocks according to these guidelines.
• Always reference a VSS plane (preferred) or a power plane (not including the 12.7 mm for processor
Breakout). www.teknisi-indonesia.com
• Layer changes and crossing plane splits are discouraged. If changing layers or crossing plane splits is
unavoidable, follow the recommendations outlined in Reference Planes.
4.2.3 Layer Assignments—Single-Ended Clocks

The following six-layer board stackup is defined for APU single-ended clocks. The layer assignments for the
following clocks are defined in Figure 29.
OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER SE_CLK SE_CLK OTHER
VSS OTHER POWER VSS
VSS OTHER POWER VSS
Figure 29. Single-Ended Clock Signal Assignment for Six-Layer Board
4.2.4 Layout Guidelines—Single-Ended Clocks

The target Bus Channel impedance for clock allows for 10% variance, which includes manufacturing tolerances.
Each clock signal pair is routed point to point and references a VSS plane (preferred) or a power plane.

Figure 30 shows the routing model for single-ended clocks.
BREAK PIN
BUS CHANNEL
Processor OUT FIELD
12.7 mm
X48M_OSC IN0
RS External Device
X48M_X1
48-MHz XTAL
X48M_X2
X32K_X1
32.768-kHz XTAL
X32K_X2
RTCCLK IN0 RTC Device
Figure 30. Single-Ended Clock Routing Model
Single-ended clocks use the layout and routing rules in Table 11.
Table 11. Routing Rules for Single-Ended Clocks

Device Spacing Placement of stitching vias relative to signal vias ≤ 1.27 mm
Placement of stitching vias relative to reference plane changes - place one stitching
via for every 3 single-ended clock signals within:
≤ 1.905 mm
Placement of stitching capacitor relative to signal vias ≤ 1.27 mm
Differential vias (within pair) are placed center to center ≤ 1.27 mm
Separation of layer-change vias on same signal ≥ 12.7 mm
Plane Edge Trace spacing from reference-plane edge ≥ 5H
Length Limits RTCCLK ≥ 25.4 mm

Minimum trace length:
X48M_OSC
X32K_X1
RTCCLK ≤ 404.6 mm
X32K_X2
X48M_X1 Maximum trace length:
X48M_X2
RTCCLK X48M_OSC ≥ 0 mm
X32K_X1/X2
X48M_X1/X2
Minimum trace length:
X48M_OSC ≤ 254 mm
Maximum trace length:
X32K_X1/X2 ≤ 38.1 mm
X48M_X1/X2
Maximum trace length:
LRS: Maximum trace length from APU pin to series resistor. ≤ 25.4 mm

Table 11. Routing Rules for Single-Ended Clocks (continued)

Signals Rule Bus Channel
Breakout Pin Field
µS SL
Max Layer Changes 4
ZO ≥ 0.1 mm 50Ω ± 10% 50Ω ± 10%

48M_OSC
X32K_X1 Trace Spacing ≥ 0.1 mm ≥ 7H ≥ 6H ≥ 4H
X32K_X2
Trace Spacing ≥ 5H ≥ 4H
X48M_X1
X48M_X2 (Between X1 and X2)
RTCCLK
(serpentine)

5 Memory Design Guidelines

This section provides general design guidelines for the memory subsystem and components.
5.1 Memory Interface

The memory bus interface is made up of the following signal groups:
• Clock group
• Address/Command/Control group
• Data group
• Miscellaneous group
See the sections that follow for memory package-specific and implementation-specific information and design
considerations.
5.1.1 Signal Descriptions

Table 12 shows the DDR4 signal groups and the channel-specific miscellaneous signals in Channel A. Channel
B has identical signals to Channel A (substituting B for A in each signal name) In addition to the channel-
specific signals, other miscellaneous signals are defined for reference.
Table 12. DDR4 Signal Descriptions

Signal Group Processor Signal Name Description Processor Pin Type
Data MA_DATA[63:0] Memory Data Bidirectional
MA_DQS_H[7:0]
MA_DQS_L[7:0]
Data Strobe true
Data Strobe complement
Bidirectional
MA_DM[7:0] Data Mask Bidirectional
Clocks MA_CLK_H[1:0] Differential Clock true Output
MA_CLK_L[1:0] Differential Clock complement
Address MA_ADD[12:0] Memory Address Output
MA_ADD13_BANK2 Memory Address / Bank Address
MA_BANK[1:0] Bank Address Output
MA_BG[1:0] Bank Group Output
Command MA_ACT_L Activation Command Output
MA_RAS_L_ADD[16] Multi-function Command/Address: Output

Row Address Strobe or Address 16,
depending on the state of the
Activation command signal.
MA_CAS_L_ADD[15] Multi-function Command/Address: Output

Column Address Strobe or Address
15, depending on the state of the
Memory Design Guidelines 53

Table 12. DDR4 Signal Descriptions (continued)

Command MA_WE_L_ADD[14] Multi-function Command/Address: Output

Write Enable or Address 14,
depending on the state of the
Control MA_CKE[1:0] Clock Enable Output
MA_ODT[1:0] DRAM On-Die Termination Output
MA_CS_L[1:0] Chip Select Output
Miscellaneous MA_EVENT_L Memory Thermal Event Input
MA_RESET_L Memory Reset Output
MA_ALERT_L Multi-function : CRC error flag and Input/Output

Command and Address parity error.
MA_PAROUT Command and Address Parity Output

Output: DDR4 Supports Even Parity
check in DRAMs with MR setting.
Other M_DDR4 DDR4 Mode Select: Input

M_LPDDR4 Connect M_DDR4 to
See Table 113 for a list of FP6 VDDIO_MEM_S3
processor straps. and
www.teknisi-indonesia.com M_LPDDR4 to VSS

to select DDR4 mode.
FP6 processors support LPDDR4x. Table 13 shows the LPDDR4x signal groups and the channel-specific
miscellaneous signals in Channel A. Channel B has identical signals to Channel A (substituting "MB" for "MA"
in each signal name). In addition to the channel-specific signals, other miscellaneous signals are defined for
reference.
Table 13. LPDDR4x Signal Descriptions

Data MAA_DATA[31:0] Memory Data Channel A Bidirectional

subchannel a
MAB_DATA[31:0] Memory Data Channel A

subchannel b
MAA_DQS_H[3:0] Data Strobe True Channel A Bidirectional

MAA_DQS_L[3:0] subchannel a
Data Strobe Complement Channel
A subchannel a
MAB_DQS_H[3:0] Data Strobe True Channel A Bidirectional

MAB_DQS_L[3:0] subchannel b
Data Strobe Complement Channel
A subchannel b
MAA_DM[3:0] Data Mask Channel A subchannel a Output

Table 13. LPDDR4x Signal Descriptions (continued)

Data MAB_DM[3:0] Data Mask Channel A subchannel b Output
Clocks MAA_CKT Differential Clock True Channel A Output

MAA_CKC subchannel a
Differential Clock Complement
Channel A subchannel a
MAB_CKT Differential Clock True Channel A Output

MAB_CKC subchannel b
Differential Clock Complement
Channel A subchannel b
Address MAA_CA[5:0] Memory Address Channel A Output

subchannel a
MAB_CA[5:0] Memory Address Channel A

subchannel b
Control MAA_CKE[1:0] Clock Enable Channel A Output

subchannel a
MAB_CKE[1:0] Clock Enable Channel A

subchannel b
MAA_CS_L[1:0] Chip Select Channel A subchannel a Output
MAB_CS_L[1:0] Chip Select Channel A subchannel b
Miscellaneous MA_EVENT_L Memory Thermal Event Channel A Input
MA_RESET_L Memory Reset Channel A Output
Other MA_TEST Test for LPDDR Channel A Analog
Other M_LPDDR4 LPDDR4 Mode Select: Input

M_DDR4 Connect M_LPDDR4 to
See Table 113 for a list of FP6 VDDIO_MEM_S3
processor straps. and
M_DDR4 to VSS
to select LPDDR4 mode.
5.1.2 Memory Signals and Connections

The following sections cover the connections between the processor and memory subsystem.
5.1.2.1 DIMM Signals and Connections

Table 14 shows the pin connections between the processor and the DDR4 SO-DIMM and intended reference
plane(s) for each net for a one DDR4 SO-DIMM per channel memory configuration. For a one DDR4 SO-
DIMM per Channel configuration the connections for Channel B are identical to Channel A (changing out the
"MA" in the Processor Pin Name with "MB").
Connect M_DDR4 to VDDIO_MEM_S3 and M_LPDDR4 to VSS to select DDR4 mode. See Table 113 for a
list of FP6 processor straps.

Table 14. Signals and Connections for One DDR4 SO-DIMM on Channel A or Channel B
Processor Pin Name Pin Definition Reference Plane SO-DIMM0
MA_CLK_H/L[1] DRAM Clock VDDIO_MEM_S3 CK1/CK1#
MA_ADD[12:0] Memory Address VDDIO_MEM_S3 A[12:0]
MA_ADD13_BANK2 Memory Address / VDDIO_MEM_S3 A13/BA2

Bank Address
MA_BANK[1:0] Bank Address VDDIO_MEM_S3 BA[1:0]
MA_BG[1:0] Bank Group VDDIO_MEM_S3 BG[1:0]
MA_ACT_L Activation Command VDDIO_MEM_S3 ACT#
MA_RAS_L_ADD[16] Row Address Strobe/Address 16 VDDIO_MEM_S3 RAS#/A16
MA_CAS_L_ADD[15] Column Address Strobe/Address 15 VDDIO_MEM_S3 CAS#/A15
MA_WE_L_ADD[14] Write Enable/Address 14 VDDIO_MEM_S3 WE#/A14
MA_CS_L[0] Chip Select VDDIO_MEM_S3 S0#
MA_CS_L[1] Chip Select VDDIO_MEM_S3 S1#
MA_ODT[0] On-Die Termination VDDIO_MEM_S3 ODT[0]
MA_ODT[1] On-Die Termination VDDIO_MEM_S3 ODT[1]
MA_CKE[0] Clock Enable VDDIO_MEM_S3 CKE[0]
MA_CKE[1] Clock Enable VDDIO_MEM_S3 CKE[1]
MA_DQS_H/L[7:0] Data Strobe VSS DQS[7:0]

DQS[7:0]#
MA_DATA[63:0] Data Bus VSS DQ[63:0]
MA_DM[7:0] Data Mask VSS DM[7:0]
MA_RESET_L DIMM Reset VSS ^ VDDIO_MEM_S3 RESET#
MA_EVENT_L Memory Thermal Event VSS or VDDIO_MEM_S3 EVENT#
MA_PAROUT Command and Address Parity Input VSS ^ VDDIO_MEM_S3 PARITY
MA_ALERT_L Multi-function : CRC error flag and VSS ^ VDDIO_MEM_S3 ALERT_L

Command and Address parity error
Table 15 shows the pin connections between the processor and the DDR4 UDIMM and intended reference
plane(s) for each net for a one UDIMM-per-channel memory configuration. The connections for Channel B are
identical to Channel A.

Table 15. Signals and Connections for One DDR4 UDIMM

Processor Pin Name Pin Definition Reference Plane UDIMM0
MA_CS_L[1:0] Chip Selects VDDIO_MEM_S3 S1# / S0#
MA_ODT[1:0] On-Die Termination VDDIO_MEM_S3 ODT[1:0]
MA_CKE[1:0] Clock Enable VDDIO_MEM_S3 CKE[1:0]
MA_ADD[12:0] Memory Address VDDIO_MEM_S3 A[12:0]
MA_ADD13_BANK2 Memory Address / VDDIO_MEM_S3 A13/BA2

Bank Address
MA_BG[1:0] Bank Group VDDIO_MEM_S3 BG[1:0]
MA_BANK[1:0] Bank Address VDDIO_MEM_S3 BA[1:0]
MA_ACT_L Activation Command VDDIO_MEM_S3 ACT#
MA_RAS_L_ADD[16] Row Address Strobe/Address 16 VDDIO_MEM_S3 RAS#/A16
MA_CAS_L_ADD[15] Column Address Strobe/Address 15 VDDIO_MEM_S3 CAS#/A15
MA_WE_L_ADD[14] Write Enable/Address 14 VDDIO_MEM_S3 WE#/A14
MA_DQS_H/L[7:0] Data Strobe VSS DQS[7:0]

DQS[7:0]#
MA_DATA[63:0] www.teknisi-indonesia.comData Bus VSS DQ[63:0]
MA_DM[7:0] Data Mask VSS DM[7:0]
MA_RESET_L DIMM Reset VSS ^ VDDIO_MEM_S3 RESET#
MA_EVENT_L Memory Thermal Event VSS or VDDIO_MEM_S3 EVENT#
MA_PAROUT Command and Address Parity Input VSS ^ VDDIO_MEM_S3 PARITY
MA_ALERT_L Multi-function : CRC error flag and VSS ^ VDDIO_MEM_S3 ALERT_L

Command and Address parity error
5.1.2.2 DRAM Down Signals and Connections

Table 16 shows the pin connections between the processor and the DRAM, terminating components, if any, and
intended reference plane(s) for each net for a DDR4 DRAM-down memory configuration. For designs
supporting single rank, only Rank 0 needs to be connected. For designs supporting dual rank, both Rank 0 and
Rank 1 need to be connected.
Table 16. Signals and Connections for DDR4 DRAM Down

Processor Pin Name Pin Definition Termination1 Reference Plane Rank 0 Rank 1
MA_CLK_H/L[1]2 DRAM Clock See Figure 53 VSS or No Connection CK/CK#

and Figure 58 VDDIO_MEM_S3

Table 16. Signals and Connections for DDR4 DRAM Down (continued)
MA_CLK_H/L[0]2 DRAM Clock See Figure 53 VSS or CK/CK# No Connection

and Figure 58 VDDIO_MEM_S3
MA_CS_L[1] Chip Selects 39Ω to VTT VSS or No Connection S0#

VDDIO_MEM_S3
MA_CS_L[0] Chip Selects 39Ω to VTT VSS or S0# No Connection

VDDIO_MEM_S3
MA_ODT[0] On-Die Termination 39Ω to VTT VSS or ODT[0] No Connection

VDDIO_MEM_S3
MA_ODT[1] On-Die Termination 39Ω to VTT VSS or No Connection ODT[1]

VDDIO_MEM_S3
MA_CKE[0] Clock Enable 39Ω to VTT VSS or CKE[0] No Connection

VDDIO_MEM_S3
MA_CKE[1] Clock Enable 39Ω to VTT VSS or No Connection CKE[1]

VDDIO_MEM_S3
MA_ADD[12:0] Column/Row Address 39Ω to VTT VSS or A[12:0] A[12:0]

VDDIO_MEM_S3
MA_ADD13_BANK2 Column/Row Address 13 / 39Ω to VTT VSS or A[13] / BA2 A[13] / BA2
Bank Address 2 VDDIO_MEM_S3
MA_BG[1:0] Bank Group 39Ω to VTT VSS or BG[1:0] BG[1:0]
MA_BANK[1:0]
Bank Address 39Ω to VTT
VDDIO_MEM_S3
VSS or BA[1:0] BA[1:0]

VDDIO_MEM_S3
MA_ACT_L Activation Command 39Ω to VTT VSS or ACT# ACT#

VDDIO_MEM_S3
MA_RAS_L_ADD[16] Row Address Strobe/ 39Ω to VTT VSS or RAS#_ADD[16] RAS#_ADD[16]

Address 16 VDDIO_MEM_S3
MA_CAS_L_ADD[15] Column Address Strobe/ 39Ω to VTT VSS or CAS#_ADD[15] CAS#_ADD[15]

Address 15 VDDIO_MEM_S3
MA_WE_L_ADD[14] Write Enable/Address 14 39Ω to VTT VSS or WE#_ADD[14] WE#_ADD[14]

VDDIO_MEM_S3
MA_PAROUT Command and Address 39Ω to VTT VSS or PAR PAR

Parity VDDIO_MEM_S3
MA_DQS_H/L[7:0] Data Strobe – VSS DQS[7:0] DQS[7:0]

DQS[7:0]# DQS[7:0]#
MA_DATA[63:0] Data Bus – VSS DQ[63:0] DQ[63:0]
MA_DM[7:0] Data Mask – VSS DM[7:0] DM[7:0]
MA_RESET_L DRAM Down Reset – VSS or RESET# RESET#

VDDIO_MEM_S3
MA_ALERT_L DRAM CRC error and 1 kΩ to VSS or ALERT_n ALERT_n

Cmd/Addr parity error VDDIO_MEM VDDIO_MEM_S3
alert _S3

Table 16. Signals and Connections for DDR4 DRAM Down (continued)
MA_EVENT_L3 Memory Thermal Event 1 kΩ to VSS or No Connection No Connection

VDDIO_MEM VDDIO_MEM_S3
_S3
Note: 1. Use 5% resistor tolerance.

2. CLK reference plane must match CLK termination.
3. A pull-up resistor is required.
Table 17 lists the pin connections between the FP6 processor and memory Channel A, and intended reference
plane(s) for each net. The FP6 processor supports LPDDR4x on two main memory channels labeled Channel A
and Channel B. The memory configuration in this section describes a LPDDR4x x32 DRAM configuration on
main memory Channel A. Each LPDDR4x main memory Channel (A and B) have two x32 subchannels that are
referred to as subchannel a and subchannel b (where the lower case "a" or "b" denotes a subchannel within a
main channel). The signals shown are for Channel A (denoted by "MA" in the Processor Pin Name column). The
same connections apply to Channel B which uses "MB" in place of "MA" for the Processor Pin Name column in
Table 17.
Connect M_LPDDR4 to VDDIO_MEM_S3 and M_DDR4 to VSS to select LPDDR4 mode. See Table 113 for a
Table 17. Signals and Connections for LPDDR4x DRAM Down —LPDDR4x x32
Processor Pin Name Pin Definition Reference Plane LPDDR4x x32 DRAM
MAA_CKT DRAM Clock True Channel A VSS CK_t_a
subchannel a
MAA_CKC DRAM Clock Complement Channel VSS CK_c_a

A subchannel a
MAB_CKT DRAM Clock True Channel A VSS CK_t_b

subchannel b
MAB_CKC DRAM Clock Complement Channel VSS CK_c_b

A subchannel b
MAA_CS_L[0] Chip Select 0 Channel A subchannel VSS CS0_n_a

a
MAA_CS_L[1] Chip Select 1 Channel A subchannel VSS CS1_n_a

a
MAB_CS_L[0] Chip Select 0 Channel A subchannel VSS CS0_n_b

b
MAB_CS_L[1] Chip Select 1 Channel A subchannel VSS CS1_n_b

b
MAA_CKE[1] Clock 1 Enable Channel A VSS CKE1_a

subchannel a
MAA_CKE[0] Clock 0 Enable Channel A VSS CKE0_a

subchannel a
MAB_CKE[1] Clock 1 Enable Channel A VSS CKE1_b

subchannel b

Table 17. Signals and Connections for LPDDR4x DRAM Down —LPDDR4x x32 (continued)
Processor Pin Name Pin Definition Reference Plane LPDDR4x x32 DRAM
MAB_CKE[0] Clock 0 Enable Channel A VSS CKE0_b

subchannel b
MAA_CA[5:0] Column Address Channel A VSS CA[5:0]_a

subchannel a
MAB_CA[5:0] Column Address Channel A VSS CA[5:0]_b

subchannel b
MAA_DQS_H[3:0] Data Strobe True Channel A VSS DQS_[3:0]_ta

subchannel a
MAA_DQS_L[3:0] Data Strobe Complement Channel VSS DQS_[3:0]_ca

A subchannel a
MAB_DQS_H[3:0] Data Strobe True Channel A VSS DQS_[3:0]_tb

subchannel b
MAB_DQS_L[3:0] Data Strobe Complement Channel VSS DQS_[3:0]_cb

A subchannel b
MAA_DATA[31:0] Data Bus Channel A subchannel a VSS DQ[31:0]_a
MAB_DATA[31:0] Data Bus Channel A subchannel b VSS DQ[31:0]_b
MAA_DM[3:0] Data Mask Channel A subchannel a VSS DM[3:0]_a
MAB_DM[3:0] Data Mask Channel A subchannel b VSS DM[3:0]_b
MA_RESET_L
DRAM Reset VSS RESET_n
5.1.3 Memory Layer/Signal Assignments

The following sections show the layer and signal assignments for the memory subsystem.
5.1.3.1 Memory Layer/Signal Assignments

The minimum number of motherboard layers required depends on the design. Refer to Valid Memory
Configurations for specific board density information related to memory.
Note: Routing net segments too close to plane splits can cause signal integrity issues (fringe effects).
Figure 31 shows the memory signal assignment for 8-layer board designs.

OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER OTHER
VSS
DATA DQS DQS DATA DATA DQS DQS DATA DATA DQS DQS DATA
OTHER POWER
OTHER POWER
ADD CLK CLK ADD ADD CLK CLK ADD ADD CLK CLK ADD
VDDIO_MEM_S3
Figure 31. DIMM Memory Signal Assignment—Eight-Layer Board
Figure 32 shows the memory signal assignment for 10-layer DRAM Down board designs.
DATA DQS DQS

DATA ADD CLK CLK ADD DATA DQS DQS DATA
VSS
VDDIO_MEM_S3
DATA DQS DQS DATA ADD CLK CLK ADD DATA DQS DQS DATA
Other Power
VDDIO_MEM_S3
VSS VSS
VDDIO VSS
Figure 32. DRAM Down Memory Signal Assignment—Ten-Layer Board

Figure 33 shows the memory signal assignment for 12-layer DRAM Down board designs.
VSS VDDIO
VSS VSS
VSS
VDDIO_MEM_S3
Other POWER
VSS
VSS
VSS www.teknisi-indonesia.com
VSS
VDDIO VSS
Figure 33. DRAM Down Memory Signal Assignment—Twelve-Layer Board
5.1.4 Memory Length Matching

The goal for memory routing is to match all signal lengths for each DIMM or DRAM within a given tolerance.
Both Data and Address/Command are source-synchronous buses. Address/Command propagates relative to
CLK, and Data propagates relative to DQS.
A fairly loose length-matching tolerance is allowed for Target Length to all 64 bits of Data to each DIMM or
DRAM. A fairly loose length-matching tolerance is allowed for Address/Command to all 64 bits of Data to each
DIMM or DRAM. The tight length-matching tolerances are within groups, as in Address, Command, and
Control relative to CLK and Data relative to DQS.

5.2 UDIMM Memory Design Guidelines
These sections describe the processor interconnect, layout rules, routing rules, and terminations for memory
designs that use one or two UDIMMs. Follow these rules to ensure a robust design at higher frequencies under
different loading conditions.
5.2.1 UDIMM Design Topology

Table 18 lists the routing topology of the signals in the memory bus interface for DDR4 UDIMM memory
designs.
Table 18. Routing Topology for One DDR4 UDIMM per Channel
Signal Group Signal Reference Plane Topology Reference
Clocks CLK VDDIO_MEM_S3 Point to point DDR4 UDIMM Layout

Guidelines—CLK
Address ADD VDDIO_MEM_S3 DDR4 UDIMM Layout

Guidelines—ADD/CMD/CTL
BANK GROUP VDDIO_MEM_S3 DDR4 UDIMM Layout

BANK VDDIO_MEM_S3 DDR4 UDIMM Layout

Command ACT_L VDDIO_MEM_S3 DDR4 UDIMM Layout
RAS_L_ADD[16] VDDIO_MEM_S3 DDR4 UDIMM Layout

CAS_L_ADD[15] VDDIO_MEM_S3 DDR4 UDIMM Layout

WE_L_ADD[14] VDDIO_MEM_S3 DDR4 UDIMM Layout

Control CKE VDDIO_MEM_S3 Point to point DDR4 UDIMM Layout

ODT VDDIO_MEM_S3 Point to point DDR4 UDIMM Layout

CS_L VDDIO_MEM_S3 Point to point DDR4 UDIMM Layout

Data Data VSS DDR4 UDIMM Layout

Guidelines—Data/DM
DM VSS DDR4 UDIMM Layout

Guidelines—Data/DM
DQS VSS DDR4 UDIMM Layout

Guidelines—DQS

5.2.2 UDIMM Placement
5.2.2.1 UDIMM Population Order

For valid UDIMM combinations, refer to Table 3. Figure 34 shows the order for UDIMM placement.
XDIMM = ( Max {CLK} + Min {CLK} ) / 2
6 6
CK1 CK1
Processor CK0
CK0
6
6
UDIMM A0
UDIMM B0
Figure 34. UDIMM Placement—Two UDIMMs
5.2.2.2 UDIMM Pitch

The spacing between DIMM sockets is referred to as DIMM pitch (DP). DIMM pitch is measured from the
center of one DIMM socket to the center of the next DIMM socket. AMD recommends a UDIMM DIMM pitch
of 8 to 10 mm.

5.2.2.3 UDIMM Layout Procedure

The layout sequence varies based on the routing method in the UDIMM region. Follow the steps in Layout
Sequence for UDIMMs to lay out UDIMMs.
5.2.2.3.1 Layout Sequence for UDIMMs

Follow these steps to lay out two UDIMMs.
1. Route each clock pair.

a) Choose the longest average clock-pair length to serve as the target length for the channel: XDIMM.
b) Adjust the processor placement relative to the UDIMMs until this length is shorter than the maximum.
The target length range, measured pin-to-pin, is specified in Table 19.
2. For each data group, route the Breakout portion of the nets such that the net order matches the Breakout
order of UDIMM0. (The signals must not cross one another when routed.)
All nets in a data group must be routed on the same layer.
3. Route all the remaining portion of the DDR nets to UDIMM0.
5.2.3 UDIMM Layout Guidelines

The UDIMM layout guidelines cover memory Clock (CLK) signals; Address, Command, and Control
(ADD/CMD/CTL) signals; differential Data Strobe (DQS) signals; Data (Data) signals; and memory
Miscellaneous (MISC) signals.

5.2.3.1 DDR4 UDIMM Layout Guidelines—CLK

Each UDIMM socket receives two differential clock pairs from the processor. Figure 35 shows that the memory
clocks do not need onboard termination. The target Bus Channel impedance for the clocks allows for 10%
variance, which includes manufacturing tolerances. All memory CLK signal pairs are routed as shown in Table
18. See Table 15 for signal connections.
BREAK DIMM
BUS CHANNEL
Processor OUT FIELD DIMM
12.7 mm
CLK_H/L[1] CK[1]/#
CLK_H/L[0] CK[0]/#
Figure 35. CLK Routing Model (DDR4 UDIMMs)
CLK uses the layout and length-matching routing rules in Table 19.
Table 19. Routing Rules for CLK (DDR4 UDIMMs)

CLK_H[1:0]
Length
Matching
True and complement traces in a differential pair are length matched
within:
1.80 ps
CLK_L[1:0] Clock trace pairs to each DIMM are length matched within: 4.25 ps
Length Limits Minimum trace length ≥ 25.4 mm
Maximum trace length ≤ 101.6 mm
Note: Lengths are measured from processor pin to DIMM finger contact. All PCB trace lengths and connector contacts are included.
Table 19. Routing Rules for CLK (DDR4 UDIMMs) (continued)

Signals Rule Breakout Bus Channel DIMM Field
µS SL µS SL µS SL
Max Layer 0
Changes
Test Points Not Permitted
Plane Split Not Permitted

Crossings
CLK_H[1:0]
ZOD ≥ 0.1 / 0.1 / 0.1 mm Single Ended: 45Ω ± 10% Single Ended: 50Ω ± 10%
CLK_L[1:0]
Differential: 75Ω ± 10% Differential: 80Ω ± 10%
or ≥ 0.1 / 0.1 / 0.1 mm
Trace Spacing ≥ 0.1 mm ≥ 7H ≥ 5H ≥ 0.1 mm
Self Spacing Not Permitted ≥ 7H ≥ 5H Not Permitted

(serpentine)

5.2.3.2 DDR4 UDIMM Layout Guidelines—ADD/CMD/CTL

ADD/CMD/CTL signals are routed as shown in Table 18. See Table 15 for signal connections. Figure 36 shows
the ADD/CMD/CTL routing model.
BREAK
DIMM
OUT BUS CHANNEL
Processor 12.7 mm
FIELD UDIMM0
ADD[12:0] ADD[12:0]
ADD13_BANK2 ADD13/BA2
BANK[1:0] BA[1:0]
BG[1:0] BG[1:0]
ACT_L ACT#
CS_L[1:0] S0[1:0]#
ODT[1:0] ODT[1:0]
CKE[1:0] CKE[1:0]
RAS_L_ADD[16] RAS#/A16
CAS_L_ADD[15] CAS#/A15
WE_L_ADD[14] WE#/A14
PAROUT PAROUT
Figure 36. ADD/CMD/CTL Routing Model (DDR4 UDIMMs)
ADD, BANK, CS_L, ODT, CKE, RAS_L, CAS_L, PAROUT, and WE_L use the layout and length-matching
routing rules in Table 20.
Table 20. Routing Rules for ADD/CMD/CTL (DDR4 UDIMMs)

ADD[12:0] Device If changing layers or reference planes is unavoidable, add 1 stitching 1.27 mm
ADD13_BANK2 Spacing via for every 3 signal vias (excluding the vias associated with power
BANK[1:0] and ground pins of DIMM connector)
BG[1:0] Plane Edge Trace spacing from reference plane edge ≥ 3H
ACT_L
CS_L[1:0] 0.1-mm trace spacing encroaching plane edge rule is: ≤ 2.54 mm
ODT[1:0]
Length Traces are length matched to the average of the two clock pairs of the ±42.5 ps
CKE[1:0]
Matching respective DIMM
RAS_L_ADD[16]
CAS_L_ADD[15] Length Limits Minimum trace length ≥ 25.4 mm
WE_L_ADD[14]
PAROUT
Note: Lengths are measured from processor pin to DIMM finger contact. All PCB trace lengths and connector contacts are included. AMD
recommends one via length for every power AND ground pin on the DIMM connector.

Table 20. Routing Rules for ADD/CMD/CTL (DDR4 UDIMMs) (continued)

Max Layer 0
Changes

ADD[12:0]
ADD13_BANK2 Plane Split Not Permitted
Crossings
BANK[1:0]
ZO ≥ 0.1 mm 40Ω ± 10% 40Ω ± 10% 50Ω ± 10%
BG[1:0]
ACT_L or ≥ 0.1 mm
CS_L[1:0]
ODT[1:0] Trace Spacing ≥ 0.1 mm ≥ 5H ≥ 3H ≥ 0.1 mm
CKE[1:0]
To Data/DM/DQS ≥ 8H
RAS_L_ADD[16]
CAS_L_ADD[15] Trace Spacing ≥ 0.1 mm N/A 0.1 mm
WE_L_ADD[14] (3 traces between length ≤ 2.54 mm
PAROUT 2 vias/pins)
Self Spacing Not permitted ≥ 5H ≥ 3H Not permitted

(serpentine)

5.2.3.3 DDR4 UDIMM Layout Guidelines—DQS

All DQS signals are routed as shown in Table 18. See Table 15 for signal connections. Figure 37 shows the DQS
routing model.
BREAK DIMM
BUS CHANNEL UDIMM0
Processor OUT FIELD
12.7 mm
DQS_H[7:0] DQS[7:0]
DQS_L[7:0] DQS[7:0]#
Figure 37. DQS Routing Model (DDR4 UDIMMs)
Table 21 shows the layout and length-matching routing rules for DQS.
Table 21. Routing Rules for DQS (DDR4 UDIMMs)

Device If changing layers or reference planes is unavoidable, add 1 stitching ≤ 1.8 mm

Spacing via per differential pair (excluding the vias associated with power and
Plane Edge
ground pins of DIMM connector)
Trace spacing from reference-plane edge ≥ 3H
0.1-mm trace spacing encroaching plane-edge rule for ≤ 2.54 mm
Length True and complement traces are length matched on a DIMM by 1.80 ps
DQS_H[7:0] Matching DIMM basis to within:
DQS_L[7:0]
DQS can be shorter than CLK (same DIMM) using effective lengths 180 ps
by up to:
DQS can be longer than CLK (same DIMM) using effective lengths 360 ps
by up to:
recommends one via for every power and ground pin on the DIMM connector.
Table 21. Routing Rules for DQS (DDR4 UDIMMs) (continued)

Signals Rule Breakout Bus Channel1 DIMM Field
Max Layer 0
Changes
DQS_H[7:0] Plane Split Not Permitted

DQS_L[7:0] Crossings
ZOD 0.1 / 0.1 / 0.1 mm Single Ended: 45Ω ± 10% Single Ended: 50Ω ± 10%
Differential: 75Ω ± 10% Differential: 80Ω ± 10%
or ≥ 0.1 / 0.1 / 0.1 mm

Table 21. Routing Rules for DQS (DDR4 UDIMMs) (continued)

To Adjacent Data Groups ≥ 9H To Adjacent Data

DQS_H[7:0]
To ADD/CMD/CTL ≥ 8H Groups ≥ 0.51 mm
DQS_L[7:0]
(serpentine)
Note: 1. Trace spacing in Channel must be met before traces change geometries to meet Channel ZOD

5.2.3.4 DDR4 UDIMM Layout Guidelines—Data/DM

All Data/DM signals are routed as shown in Table 18. See Table 15 for signal connections. Figure 38 shows the
model for Data/Data Mask nets.
BREAK DIMM
Processor OUT
BUS CHANNEL
FIELD UDIMM0
12.7 mm
DATA[63:0] DQ[63:0]
DM[7:0] DM[7:0]
Figure 38. Data/DM Routing Model (DDR4 UDIMMs)
Table 22 shows the Data/Data Mask layout and length-matching routing rules.
Table 22. Routing Rules for Data/DM (DDR4 UDIMMs)

Device If changing layers or reference planes is unavoidable, add 1 stitching 1.27 mm

Spacing via for every 3 signal vias (excluding the vias associated with power
and ground pins of DIMM connector)
Plane Edge Trace spacing from reference-plane edge
0.1-mm trace spacing encroaching plane-edge rule for

≥ 3H
≤ 2.54 mm
DATA[63:0] Length Length matched within group (including DQS) 8.5 ps
Matching
DM[7:0] Data can be shorter than CLK (same DIMM) using effective lengths 180 ps
by up to:
Data can be longer than CLK (same DIMM) using effective lengths by 360 ps
up to:
recommends one via for every power and ground pin on the DIMM connector.
Table 22. Routing Rules for Data/DM (DDR4 UDIMMs) (continued)

Max Layer 0
Changes

DATA[63:0]
DM[7:0] Crossings
ZO ≥ 0.1 mm 40Ω ±10% 40Ω ±10% ≥ 0.1 mm
Trace Spacing ≥ 0.1 mm ≥5H ≥ 3H ≥ 0.1 mm

Table 22. Routing Rules for Data/DM (DDR4 UDIMMs) (continued)

Trace Spacing ≥ 0.1 mm To Adjacent Data Groups ≥ 9H To Adjacent Data

To ADD/CMD/CTL ≥ 8H Groups ≥ 0.51 mm
Trace Spacing ≥ 0.1 mm N/A 0.1 mm

DATA[63:0]
(3 traces length ≤ 2.54 mm
DM[7:0] between
2 vias/pins)
Self Spacing Not Permitted ≥5H ≥ 3H Not Permitted

(serpentine)
Note: 1. Trace spacing in Channel must be met before traces change geometries to meet Channel ZO.

5.2.3.5 DDR4 UDIMM Layout Guidelines—Miscellaneous

MA_RESET_L, MA_EVENT_L, and MA_ALERT_L signals are routed as shown in Table 18. See Table 15 for
signal connections. Figure 39 shows the routing model for MA_RESET_L, MA_EVENT_L, and
MA_ALERT_L nets. M_EVENT_L is an optional signal. It is supported only by UDIMMs equipped with a
thermal sensing device.
BREAK DIMM
Processor OUT BUS CHANNEL FIELD UDIMM0
12.7 mm
RESET_L RST#
REVENT
EVENT_L EVENT#
ALERT_L ALERT#
Figure 39. Miscellaneous Routing Model (DDR4 UDIMMs)
The termination component value for M_EVENT_L is listed in Table 23.

Table 23. Component Table—DDR4 Miscellaneous Termination
Ref
REVENT
Value
1 kΩ
Tolerance
5%
Package
0402
Comments
EVENT_L termination to VDDIO_MEM_S3
To maintain layout consistency for the memory subsystem, use the layout and length-matching routing rules in
Table 24.
Table 24. Routing Rules for Miscellaneous (DDR4 UDIMMs)


RESET_L 0.1-mm trace spacing encroaching plane-edge rule for ≤ 2.54 mm
EVENT_L
ALERT_L Length Limits Minimum trace length ≥ 25.4 mm
Table 24. Routing Rules for Miscellaneous (DDR4 UDIMMs) (continued)

Max Layer 2
Changes
RESET_L
EVENT_L Test Points Not Permitted
ALERT_L
Crossings

Table 24. Routing Rules for Miscellaneous (DDR4 UDIMMs) (continued)

ZO ≥ 0.1 mm 40 to 60Ω 50 to 60Ω

RESET_L
EVENT_L or ≥ 0.1 mm
ALERT_L
Trace Spacing ≥ 0.1 mm ≥1H ≥ 0.1 mm

5.3 SO-DIMM Memory Design Guidelines
These sections describe the processor interconnect, layout rules, routing rules, and terminations for memory
designs that use one or two SO-DIMMs. Follow these rules to ensure a robust design at higher frequencies under
different loading conditions.
5.3.1 SO-DIMM Design Topology

Table 25 lists the routing topology of the signals in the memory bus interface for one DDR4 SO-DIMM per
channel memory configurations.
Table 25. Routing Topology for One DDR4 SO-DIMM on Channel A or Channel B
Signal Group Signal One DDR4 SO-DIMM
Routing Topology
Clocks CLK Point to point
Address ADD Point to point
BANK ADDRESS
BANK GROUP
Command ACT_L Point to point
RAS_L_ADD[16]
CAS_L_ADD[15]
WE_L_ADD[14]
Command and Address Parity MA_ALERT_L Point to point
Control CKE Point to point
ODT
CS_L
Data DATA Point to point
DM
DQS Point to point
Miscellaneous MA_RESET_L Point to point
MA_EVENT_L
5.3.2 SO-DIMM Placement
5.3.2.1 SO-DIMM Population Order

For valid combinations, refer to Table 3. Figure 40 shows the order SO-DIMMs are placed and the target length
(XDIMM).

Processor
SO-DIMM A0 SO-DIMM B0
Figure 40. SO-DIMM Placement —Two SO-DIMMs
Figure 41 shows the placement of SO-DIMMs in a side-by-side configuration.


SO-DIMM
A0
CK1
CK0
Two CLK
Pairs
Processor
Two CLK
Pairs
SO-DIMM
B0
CK1
CK0
Figure 41. SO-DIMM Placement —Two SO-DIMMs (Side-by-Side)
5.3.2.2 SO-DIMM Pitch

The spacing between DIMM sockets is referred to as DIMM pitch (DP). DIMM pitch is measured from the
center of one DIMM socket to the center of the next DIMM socket. AMD recommends a SO-DIMM DP of 16 to
20 mm.
5.3.2.3 SO-DIMM Layout Procedure

The layout sequence varies based on the routing method in the SO-DIMM region. Follow the steps in Layout
Sequence for SO-DIMMs to layout SO-DIMMs.
5.3.2.3.1 Layout Sequence for SO-DIMMs
1. Place the SO-DIMMs in order A0 then B0 with SO-DIMM A0 closest to the processor.

2. Place one via for every power and ground pin on the SO-DIMM connector before routing any signal.
3. Route each clock pair used in Channel A—MA_CLK_H[1:0] / MA_CLK_L[1:0].
a) Choose the longest average clock pair length to serve as the target length for the channel: XDIMM_A.
b) Adjust the processor placement relative to the SO-DIMMs until this length is shorter than the maximum.
The target length range for each channel, measured pin to pin, is specified in Table 26.
4. Route each clock pair used in Channel B—MB_CLK_H[1:0] / MB_CLK_L[1:0].
a) Choose the longest average clock pair length to serve as the target length for the channel: X DIMM_B.
b) Adjust the processor placement relative to the SO-DIMMs until this length is shorter than the maximum.
The target length range for each channel, measured pin to pin, is specified in Table 26.
5. For each data group of Channel A, route the Breakout portion of the nets such that the net order matches the
Breakout order of SO-DIMM A0.
Two layers are required to break out Channel A. All nets in a data strobe group must be routed on the same
layer.
6. For each data group of Channel B, route the Breakout portion of the nets such that the net order matches the
Breakout order of SO-DIMM B0.
One layer is required to break out Channel B. All nets in a data strobe group must be routed on the same
layer.
7. Route the remaining Channel A nets to SO-DIMM A0.
The nets leading to the SO-DIMM field must be routed on inner layers.
8. Route all the remaining portion of the Channel B nets to SO-DIMM B0.
The nets leading to the SO-DIMM field must be routed on inner layers.
9. The signals must not cross one another when routed.
10. Data strobe group swap is allowed within a channel.
11. Bits within a data strobe group may be swapped in any order.
5.3.2.4 SO-DIMM Socket Skew

Optimal performance of the DDR subsystem may be achieved by considering many design variables. Due to
increased DDR speeds, considering the variances in SO-DIMM sockets across manufacturers has become an
integral part of designing a robust system. SO-DIMM socket pin lengths can vary greatly across SO-DIMM
sockets causing a timing skew, known as SO-DIMM socket skew.
When multiple sources of SO-DIMM sockets are desired, the designer must consider the differences between
sockets. Using SO-DIMM sockets that share common mechanical and electrical attributes minimizes variances
and provide increased reliability.
5.3.3 SO-DIMM Layout Guidelines—One DDR4 SO-DIMM

These sections provide board layout design rules and guidelines for one DDR4 SO-DIMM configurations.

5.3.3.1 One DDR4 SO-DIMM per Channel Layout Guidelines—CLK

Each DDR4 SO-DIMM socket receives two differential clock pairs from the processor. Memory clocks do not
need onboard termination. The target Bus Channel impedance for the clocks allows for 10% variance, which
includes manufacturing tolerances.
All memory CLK signal pairs are routed as shown in Table 25. See Table 14 for signal connections.
Figure 42 shows the CLK routing model for DDR4 SO-DIMMs.
BREAK DIMM
BUS CHANNEL
Processor OUT FIELD DIMM
12.7 mm
CLK_H/L[1] CK[1]/#
CLK_H/L[0] CK[0]/#
Figure 42. CLK Routing Model (DDR4 SO-DIMMs)
Table 26 shows the CLK layout and length-matching routing rules.
Table 26. Routing Rules for CLK (One DDR4 SO-DIMM per Channel)
Plane Edge Trace spacing from reference plane edge ≥ 3H
Length Matching Difference between H and L traces within a differential pair ≤ 1.80 ps
Clock trace pairs to each DIMM ≤ 4.25 ps

CLK_H[1:0]
CLK_L[1:0] Length Limits Minimum trace length ≥ 25.4 mm
If bus channel is routed stripline, the length of microstrip segments routed to SO-DIMM ≤ 7.62 mm
pads is:
Table 26. Routing Rules for CLK (One DDR4 SO-DIMM per Channel) (continued)
Signals Rule Breakout Bus Channel DIMM Field End Route
µS SL µS SL µS SL µS
Max Layer 2, Not Permitted in the Channel

Changes

CLK_H[1:0]
CLK_L[1:0]
Crossings
ZOD 0.1 / 0.1 / 0.1 mm Single Ended: 40Ω ± 10%

Differential: 72Ω ± 10% or ≥ 0.1 / 0.1 / 0.1 mm

Table 26. Routing Rules for CLK (One DDR4 SO-DIMM per Channel) (continued)
Trace ≥ 0.15 mm ≥ 7H ≥ 4H ≥ 2.5H ≥ 2.5H

CLK_H[1:0] Spacing
CLK_L[1:0] Self Spacing Not Permitted ≥ 7H Not Permitted
(serpentine)

5.3.3.2 One DDR4 SO-DIMM per Channel Layout Guidelines—ADD/CMD/CTL

All ADD/CMD/CTL signals are routed as shown in Table 25. See Table 14 for signal connections.
Figure 43 shows the ADD/CMD/CTL routing model for DDR4 SO-DIMMs.
BREAK
DIMM
OUT BUS CHANNEL
Processor 12.7 mm
FIELD SO-DIMM0
ADD[12:0] ADD[12:0]
ADD13_BANK2 ADD13/BA2
BANK[1:0] BA[1:0]
BG[1:0] BG[1:0]
ACT_L ACT#
CS_L[1:0] S0[1:0]#
ODT[1:0] ODT[1:0]
CKE[1:0] CKE[1:0]
RAS_L_ADD[16] RAS#/A16
CAS_L_ADD[15] CAS#/A15
WE_L_ADD[14] WE#/A14
PAROUT PAROUT
Figure 43. ADD/CMD/CTL Routing Model (DDR4 SO-DIMMs)
ADD, BANK, CS_L, ODT, CKE, RAS_L, CAS_L, PAROUT, and WE_L use the layout and length-matching
Table 27. Routing Rules for ADD/CMD/CTL (One DDR4 SO-DIMM per Channel)
ADD[12:0] Device Spacing For reference plane changes, add 1 stitching via for every three signal vias (excluding the ≤ 3 mm
ADD13_BANK2 vias associated with power and ground pins of DIMM connector)
BANK[1:0] Plane Edge Trace spacing from reference plane edge ≥ 3H
BG[1:0]
ACT_L 1.5H trace spacing encroaching plane edge rule is: ≤ 2.54 mm
CS_L[1:0]
Length Matching Traces are length matched to the average of the two clock pairs of the respective DIMM ± 42.50 ps
ODT[1:0]
CKE[1:0] Length Limits Minimum trace length ≥ 25.4 mm
RAS_L_ADD[16]
CAS_L_ADD[15]
WE_L_ADD[14] If bus channel is routed stripline, the length of microstrip segments routed to SO-DIMM ≤ 7.62 mm
PAROUT pads is:

Table 27. Routing Rules for ADD/CMD/CTL (One DDR4 SO-DIMM per Channel) (continued)

Changes
ADD[12:0] Plane Split Not Permitted

ADD13_BANK2 Crossings
BANK[1:0]
ZO ≥ 0.1 mm 40Ω ±10% 40Ω ±10% or ≥ 0.1 mm 50Ω ±10% or
BG[1:0]
≥ 0.1 mm
ACT_L
CS_L[1:0] Trace Spacing ≥ 0.1 mm ≥ 4H ≥ 3H ≥ 0.2 mm ≥ 0.15 mm
ODT[1:0]
CKE[1:0] To Data/DM/DQS
RAS_L_ADD[16] ≥ 8H
CAS_L_ADD[15]
WE_L_ADD[14] Trace Spacing ≥ 0.1 mm N/A ≥ 1.5H
PAROUT (3 traces between for length ≤ 2.54 mm
2 vias/pins)

(serpentine)

5.3.3.3 One DDR4 SO-DIMM Layout Guidelines—DQS

All DQS signals are routed as shown in Table 25. See Table 14 for signal connections.
Figure 44 shows the DQS routing model for DDR4 SO-DIMMs.
BREAK DIMM
BUS CHANNEL DIMM
Processor OUT FIELD
12.7 mm
DQS[7:0]
DQS_H[7:0]
DQS[7:0]#
DQS_L[7:0]
Figure 44. DQS Routing Model (DDR4 SO-DIMMs)
The DQS nets use the layout and length-matching routing rules in Table 28.
Table 28. Routing Rules for DQS (One DDR4 SO-DIMM per Channel)
Device Spacing For reference plane changes, add 1 stitching via per differential pair for every three ≤ 3 mm
signal vias (excluding the vias associated with power and ground pins of DIMM
www.teknisi-indonesia.com connector)
1.5H trace spacing encroaching plane edge rule is: ≤ 2.54 mm
Length Matching True and complement traces are length matched on a DIMM by DIMM basis to within: ≤ 1.80 ps
DQS_H[7:0] DQS can be shorter than CLK (same SO-DIMM) using effective lengths by up to: 165 ps
DQS_L[7:0]
DQS can be longer than CLK (same SO-DIMM) using effective lengths by up to: 345 ps
Within Group (Data, DQS, DM) 8.50 ps
If bus channel is routed stripline, the length of microstrip segments routed to SO- ≤ 7.62 mm
DIMM pads is:
Table 28. Routing Rules for DQS (One DDR4 SO-DIMM per Channel) (continued)

DQS_H[7:0] Changes
DQS_L[7:0]

Table 28. Routing Rules for DQS (One DDR4 SO-DIMM per Channel) (continued)

Crossings
ZOD 0.1 / 0.1 / 0.1 mm Single Ended: 50Ω ± 10% Single Ended: 50Ω ± 10% Differential: 80Ω
Differential: 80Ω ± 10% ± 10% or ≥ 0.1 / 0.1 / 0.1 mm
Trace Spacing ≥ 0.1 mm ≥ 5H ≥ 4H ≥ 0.2 mm ≥ 0.15 mm
DQS_H[7:0] To ADD/CMD/CTL
DQS_L[7:0] ≥ 8H
Trace Spacing ≥ 0.1 mm N/A ≥ 1.5H

(3 traces between for length ≤ 2.54 mm
2 vias/pins)

(serpentine)

5.3.3.4 One DDR4 SO-DIMM per Channel Layout Guidelines—Data/DM

Table 25 lists the routing topology for the Data/DM signals. See Table 14 for signal connections.
Figure 45 shows the Data/Data Mask routing model for DDR4 SO-DIMMs.
BREAK DIMM
Processor OUT
BUS CHANNEL
FIELD DIMM
12.7 mm
DATA[63:0] DQ[63:0]
DM[7:0] DM[7:0]
Figure 45. Data/DM Routing Model (DDR4 SO-DIMMs)
The Data/Data Mask nets use the layout and length-matching routing rules in Table 29.
Table 29. Routing Rules for Data/DM (One DDR4 SO-DIMM per Channel)
Device Spacing For reference plane changes, add 1 stitching via for every 3 signal vias (excluding the ≤ 3 mm
vias associated with power and ground pins of DIMM connector)
1.5H trace spacing encroaching plane edge rule is: ≤ 2.54 mm
Length Matching Data can be shorter than CLK (same SO-DIMM) using effective lengths by up to: 165 ps
DATA[63:0]
Data can be longer than CLK (same SO-DIMM) using effective lengths by up to: 345 ps
DM[7:0]
Within Group (Data, DQS, DM) 8.50 ps
If bus channel is routed stripline, the length of microstrip segments routed to SO-DIMM ≤ 7.62 mm
pads is:
Table 29. Routing Rules for Data/DM (One DDR4 SO-DIMM per Channel) (continued)
DATA[63:0] Max Layer 2 total; Not permitted in the Channel

Changes
DM[7:0] Test Points Not Permitted

Table 29. Routing Rules for Data/DM (One DDR4 SO-DIMM per Channel) (continued)

Crossings
ZO N/A ≥ 0.1 mm 50Ω ±10% 50Ω ±10% or ≥ 0.1 mm
Trace Spacing N/A ≥ 0.1 mm ≥ 4H ≥ 3H ≥ 0.2 mm ≥ 0.15 mm
DATA[63:0] To ADD/CMD/CTL
≥ 8H
DM[7:0]
Trace Spacing ≥ 0.1 mm N/A 1.5H
2 vias/pins)

(serpentine)

5.3.3.5 One DDR4 SO-DIMM Layout Guidelines—Miscellaneous

RESET_L, EVENT_L, and ALERT_L signals are routed as shown in Table 25. See Table 14 for signal
connections.
Figure 46 shows the RESET_L, EVENT_L, and ALERT_L routing model for SO-DIMMs.
BREAK DIMM
Processor OUT BUS CHANNEL FIELD SO-DIMM0
12.7 mm
RESET_L RST#
REVENT
EVENT_L EVENT#
ALERT_L ALERT#
Figure 46. Miscellaneous Routing Model (DDR4 SO-DIMMs)
The termination component value for M_EVENT_L is listed in Table 30.

Table 30. Component Table—DDR4 Miscellaneous Termination
Ref Value Tolerance Package Comments
REVENT
1 kΩ 5% 0402 EVENT_L termination to VDDIO_MEM_S3
To maintain layout consistency for the memory subsystem, follow the layout guidelines and length-matching
Table 31. Routing Rules for Miscellaneous (One DDR4 SO-DIMM )

RESET_L Length Limits Minimum trace length ≥ 25.4 mm

EVENT_L Maximum trace length ≤ 152.4 mm
ALERT_L
If bus channel is routed stripline, the length of microstrip segments routed to SO- ≤ 7.62 mm
DIMM pads is:
Table 31. Routing Rules for Miscellaneous (One DDR4 SO-DIMM ) (continued)
RESET_L Max Layer 3

EVENT_L Changes
ALERT_L Test Points Not Permitted

Table 31. Routing Rules for Miscellaneous (One DDR4 SO-DIMM ) (continued)

Crossings
ZO ≥ 0.1 mm 40 to 60Ω ≥ 0.1 mm
Trace Spacing ≥ 0.1 mm ≥ 1H ≥ 0.2 mm
RESET_L To Data/DM/DQS
EVENT_L ≥ 1H
ALERT_L
Trace Spacing ≥ 0.1 mm N/A ≥ 1.5H
2 vias/pins)

(serpentine)

5.4 DDR4 DRAM Down Memory Design Guidelines
These sections describe the processor interconnect, layout rules, routing rules, and terminations for DDR4
memory designs that use DRAM down (on the motherboard).
Follow these rules to ensure a robust design at higher frequencies under different loading conditions.
5.4.1 DDR4 DRAM Down Population Order

For valid combinations, refer to Table 4.
FP6 processor-based systems support up to two ranks of DRAM down. For single die-per-package DRAMs
place Rank 0 on the same side of the board as the processor and place Rank 1 on the opposite side of board as
the processor. For dual die-per-package DRAMs both Ranks are placed on the same side of the board as the
processor.
5.4.1.1 Routing and Placement for x8 DDR4 Configurations

Routing and placement for x8 DDR4 configurations follow these guidelines:
• ADD/CMD/CTL/CLK routing makes a U-turn through two rows of DRAMs.
• DRAMs are arranged such that the ADD/CMD pins are on the inner circle and the Data pins are on the outer
circle.
Figure 47 shows U-turn routing for ADD/CMD/CTL/CLK x8 DRAMs.
BYTE1 www.teknisi-indonesia.com
BYTE3 BYTE5 BYTE7
TERM
ADD ADD ADD ADD
ADD ADD ADD ADD
BYTE0 BYTE2 BYTE4 BYTE6
U-turn Routing
APU
ADD/CMD/CTL/CLK
Figure 47. U-Turn Routing for ADD/CMD/CTL/CLK—x8
Figure 48 shows SRx8 SDP DRAM or DRx8 DDP DRAM placement.

C2 C2 C2 C2 C2
DRAMs
C2 C2 C2 C2 C2
on Top
C2 C2 C2 C2 C2
Side
Only
C2 C2 C2 C2 C2
Processor C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
R R R R R R R R R R R R R R R R
C C C C C C C C
Figure 48. DRAM Placement—Single-Rank x8 SDP DRAMs or Dual-Rank x8 DDP DRAMs
Figure 49 shows dual-rank (DR) x8 single-die package (SDP) DRAM placement.
C2 C2 C2 C2 C2
www.teknisi-indonesia.com C2 C2 C2 C2 C2
DRAMs
on Top
C2 C2 C2 C2 C2
and
Bottom
C2 C2 C2 C2 C2
Processor C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C C C C C C C C
Figure 49. DRAM Placement—Dual-Rank x8 SDP DRAMs
5.4.1.2 Routing and Placement for x16 DDR4 Configurations

Routing and placement for x16 DDR4 configurations follow these guidelines:
• ADD/CMD/CTL/CLK route through a single row of DRAMs.
• DRAMs are arranged such that the ADD/CMD pins are away from the processor and the Data pins are close
to the processor.
Figure 50 shows the routing for ADD/CMD/CTL/CLK x16 DRAMs.

TERM
ADD ADD ADD ADD
BYTE[1:0] BYTE[3:2] BYTE[5:4] BYTE[7:6]
APU
ADD/CMD/CTL/CLK
Figure 50. Single Row Fly-By Routing for ADD/CMD/CTL/CLK— x16
Figure 51 shows x16 DRAM placement.
C2 C2 C2 C2 C2
DRAMs
on Top
Side
Only
C2 C2 C2 C2 C2
Processor
C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C C C C C C C C
Figure 51. DRAM Placement— Single-Rank x16 SDP DRAMs or Dual-Rank x16 DDP DRAMs
Figure 52 shows dual-rank (DR) x16 single-die package (SDP) DRAM placement.

C2 C2 C2 C2 C2
Four SDP x16 DRAMs on

Top
and
C2 C2 C2 C2 C2
Four SDP x16 DRAMs on
Bottom
Processor
FP4 C2 C2 C2 C2 C2
C2 C2 C2 C2 C2
C C C C C C C C
Figure 52. DRAM Placement—Dual-Rank x16 SDP DRAMs
5.4.2 DDR4 DRAM Down Decoupling

Table 32. DDR4 DRAM Down Per-Channel Decoupling Capacitors
Capacitor Configuration VDDIO_MEM_S3-VSS VDDIO_MEM_S3-VTT VTT-VSS VREF_CA-
VDDIO_MEM_S3
Value Package
Size /
Material
0.1 µF 0402 X5R SRx8 - - - 8
SRx16 - - - 4
DRx8 - - - 16
DRx16 - - - 8
0.22 µF 0402 X5R SRx8 36 5 5 -
SRx16 18 5 5 -
DRx8 75 5 10 -
DRx16 36 10 10 -
Note: For ECC support, add 12.50% more decoupling capacitors on each rail.
5.4.3 DRAM Down Layout Procedure

Layout sequence varies based on routing method in the DRAM down region. Layout Sequence for DRAM
Down lists the layout sequence for DRAM down. XCH is the target CLK length for DRAM down.
Note: Dual-rank (DR) memory configurations use Tee routing to the second rank.

5.4.3.1 Layout Sequence for DRAM Down
1. Place the DRAMs as shown in Figure 47 through Figure 52.

For single-die package (SDP) DRAMS, place DRAMs for single-rank (SR) memory configurations on one
side of the board and SDP DRAMs for dual-rank (DR) memory configurations on both sides of the board.
For dual-die package (DDP) DRAMS, place all DDP DRAMS on the same side of the board.
2. Route each clock pair used M_CLK_H[1:0] / M_CLK_L[1:0].
a) Choose the average clock pair length to serve as the target length for the channel.
b) Adjust the processor placement relative to the DRAMs until this length of XCH is shorter than the
maximum.
• The clock pair length to the first DRAM is the target CLK length for the channel: XCH.
• The range of target CLK length, measured pin-to-pin, is specified in the Routing Rules for CLK table.
3. For each data group, route the Breakout portion of the nets such that the net order matches the Breakout
order of the DRAM.
• The signals must not cross one another when routed.
• All nets in a data strobe group must be routed on the same layer.
• Data strobe group swap is allowed within a channel.
• Bits within a data strobe group may be swapped in any order.
4. Route all the remaining portions of the DDR nets to the DRAMs.
• The nets leading to the DRAM Pin Field must be routed on inner layers.
• Target trace lengths for DRAM down are specified in the Routing Rules tables.
• For SDP DRAM dual-rank configurations, route the shortest possible tee-route between DRAM for Rank
0 and DRAM for Rank 1.
5. Continue routing the Data, Address, and Command nets to the remaining DRAMs.

5.4.3.1.1 DDR4 x8 DRAM Down Layout Guidelines—CLK

Each rank receives one differential clock pair from the processor. Use MA_CLK_H/L[0] for Rank 0. Dual-rank
configurations use MA_CLK_H/L[1] for Rank 1. Figure 53 shows the memory clock routing. The target bus-
channel impedance for the clocks allows for 10% variance, which includes manufacturing tolerances. All
memory CLK signal pairs are routed point to point and reference either the VSS plane or the VDDIO_MEM_S3
plane. CLK uses the layout and length-matching routing rules in Table 34. Use the same Channel A rules and
guidelines for Channel B.
VSS
DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM or
VDDIO_MEM_S3
CTT
L7 L7 L7
L3 L3 L3 L7 L5 RTT
RTT
L4
L3 L3 L3
L7 L7 L7 L7
DRAM
DRAM
DRAM
DRAM DRAM DRAM DRAM DRAM
Processor
CK0=184/185
Via
CK1=63/64 L1 L2
Rank 0
CLK_H
CLK_L
Figure 53. CLK Routing Model (DDR4 x8 DRAM Down)
The termination component values for MA_CLK are listed in Table 33.
Table 33. Component Table—DDR4 x8 CLK Termination
RTT 39Ω 5% 0402 CLK termination
CTT 0.1 µF 5% 0402 CLK termination to VSS or VDDIO_MEM_S3.

CLK termination must match the CLK reference
plane.

Table 34. Routing Rules for CLK (DDR4 x8 DRAM Down)

Plane Edge Trace spacing from reference-plane edge. ≥ 3H
Length Matching True and complement traces in a differential pair are length matched within: 1.8 ps
Clock trace pairs to each Rank are length matched within: 9.0 ps
SRx8:
MA_CLK_H[0] Length Limits Minimum trace length to first DRAM. ≥ 25.4 mm
MA_CLK_L[0] Maximum trace length to first DRAM. ≤ 127 mm
DRx8: Trace segment length between DRAM tee-route vias (L3). 13.9 to 14.0 mm
MA_CLK_H[1:0]
MA_CLK_L[1:0] Trace segment length between DRAM via to DRAM (L7). ≤ 3 mm
Trace segment length of U-turn trace (L4). 41.9 to 42.0 mm
Trace segment length from the last DRAM tee-route via to the RTT termination ≤ 7.62 mm
(L5).
Note: Lengths are measured from processor pin to first DRAM pin. AMD recommends one via for every power and ground pin on the DRAM chip.
Table 34. Routing Rules for CLK (DDR4 x8 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Between Vias DRAM Via to U-turn Trace End Route to
for DRAM (L3) DRAM (L7) (L4) Term (L5)
µS SL µS SL µS SL µS SL µS SL µS SL
Layer 3
Changes

Crossings
ZOD N/A 0.1/ N/A 72Ω N/A 80Ω 80Ω N/A N/A 72Ω N/A 80Ω
SRx8: 0.1/0.1 ± 10% ± 10% ± 10% ± 10% ± 10%
MA_CLK_H[0] mm
MA_CLK_L[0] Trace N/A 0.15 m N/A ≥ 5H N/A ≥ 0.15 ≥ N/A N/A ≥ 0.15 N/A ≥ 0.15
DRx8: Spacing m mm 0.15 m mm mm
MA_CLK_H[1:0] m
MA_CLK_L[1:0]
Trace N/A 0.1 mm
Spacing length ≤ 2.54 mm
(3 traces
between
2 vias/pins)

(serpentine)

5.4.3.1.2 DDR4 x8 DRAM Down Layout Guidelines—ADD/CMD/CTL

Figure 54 shows the ADD/CMD/CTL routing model for a single-rank x8 configuration. For SDP DRx8
configuration install Rank 1 DRAMs on opposite side of board and mirror the layout of Rank 0. All signals
routed reference either the VSS plane or the VDDIO_MEM_S3 plane.
DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM
VTT
L7 L7 L7 L7 RTT
L5
L3 L3 L3
L4
L3 L3 L3
L7 L7 L7 L7
DRAM DRAM DRAM DRAM
DRAM
DRAM DRAM
DRAM DRAM DRAM
DRAM DRAM
Processor
L1 L2
Via ADD/BANK/
Rank 0 RAS_L/CAS_L /
Rank 1 WE_L
Figure 54. ADD/CMD/CTL Routing Model (DDR4 x8 DRAM Down)
The termination component values for ADD/CMD/CTL are listed in Table 35.
Table 35. Component Table—DDR4 x8 ADD/CMD/CTL Termination
RTT 39Ω 5% 0402 ADD/CMD/CTL termination to VTT
ADD/CMD/CTL use the layout and length-matching routing rules in Table 36.
Table 36. Routing Rules for ADD/CMD/CTL (DDR4 x8 DRAM Down)


ADD[12:0]
ADD13_BANK2 0.1-mm trace spacing encroaching plane-edge rule for: ≤ 2.54 mm
BANK[1:0]
Length Matching Traces are length matched to the average of the clock pair of the respective Rank ±22.70 ps
BG[1:0]
(processor to DRAM).

Table 36. Routing Rules for ADD/CMD/CTL (DDR4 x8 DRAM Down) (continued)
Length Limits Minimum trace length to first DRAM. ≥ 25.4 mm

ACT_L Maximum trace length to first DRAM. ≤ 127 mm
CS_L[1:0]
ODT[1:0] Trace segment length between DRAM tee-route vias (L3). 13.9 to 14.0 mm
CKE[1:0]
Trace segment length between DRAM via to DRAM (L7). Address nets. ≤ 5.2 mm
RAS_L_ADD[16]
CAS_L_ADD[15] Trace segment length between DRAM via to DRAM (L7). CMD nets. ≤ 2.1 mm
WE_L_ADD[14]
Trace segment length of U-turn trace (L4). 41.9 to 42.0 mm
PAROUT
Trace segment length from the last DRAM tee-route via to the RTT termination (L5). ≤ 7.62 mm
Signals Rule Breakout (L1) Channel (L2) Between Vias DRAM Via to U-turn Trace End Route to
for DRAM (L3) DRAM (L7) (L4) Term (L5)
µS SL µS SL µS SL µS SL µS SL µS SL
Layer 3
Changes
Crossings
ADD[12:0]
ZO N/A ≥ 0.1 N/A 40Ω N/A 50Ω 50Ω N/A N/A 40Ω N/A 50Ω
ADD13_BANK2
mm ± 10% ± 10% ± 10% ± 10% ± 10%
BANK[1:0]
BG[1:0] Trace N/A ≥ 0.1 N/A ≥ 2H N/A ≥ 0.1 ≥ 0.1 N/A N/A ≥ 0.1 N/A ≥ 0.1
ACT_L Spacing mm mm mm mm mm
CS_L[1:0] To To
ODT[1:0] Data/D Data/D
CKE[1:0] M/DQ M/DQ
RAS_L_ADD[16] S ≥ 8H S ≥ 8H
CAS_L_ADD[15]
Trace ≥ 0.1 mm N/A 0.1 mm
WE_L_ADD[14]
PAROUT Spacing length ≤ 2.54 mm
(3 traces
between
2 vias/pins)
Self Spacing Not Permitted N/A ≥ 3H Not Permitted

(serpentine)

5.4.3.1.3 DDR4 X8 DRAM Down Layout Guidelines—DQS

The DQS nets are modeled in Figure 55 and use the layout and length-matching routing rules in Table 37.
Rank 0 Rank 1
DRAM DRAM
Via
Rank 0
Rank 1
L 3a L 3b
Processor
L1 L2
DQS_H
DQS_L
Figure 55. DQS Routing Model (DDR4 X8 DRAM Down)
Table 37. Routing Rules for DQS (DDR4 X8 DRAM Down)

µS SL
0.1-mm trace spacing encroaching plane-edge rule is: ≤ 2.54 mm
Length Length matched within group (including Data/DM). 9 ps

Matching
DQS can be shorter than CLK (first DRAM) using effective lengths by 360 ps
up to:
MA_DQS_H
DQS can be longer than CLK (first DRAM) using effective lengths by up 180 ps
[7:0]
to:
MA_DQS_L
[7:0] True and complement traces are length matched on a DRAM by DRAM 1.80 ps
basis to within:
Length Limits Minimum trace length to first DRAM. N/A ≥ 25.4 mm
Maximum trace length to first DRAM. N/A ≤ 152.4 mm
Trace segment length between tee-route vias and DRAM. (L3a, L3b) ≤ 2.6 mm N/A
Note: Lengths are measured from processor pin to DRAM pin. AMD recommends one via for every power and ground pin on the DRAM chip.
Table 37. Routing Rules for DQS (DDR4 X8 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Tee Route to DRAM
(L3a and L3b)
MA_DQS_H Layer Changes 2

[7:0] Test Points Not Permitted

Table 37. Routing Rules for DQS (DDR4 X8 DRAM Down) (continued)
(L3a and L3b)

Crossings
ZOD N/A ≥ 0.1/ 0.1/0.1 N/A 80Ω ±10% 80Ω ±10% N/A
mm
Trace Spacing N/A ≥ 0.1 mm N/A ≥ 4H ≥ 0.15 mm N/A
To
MA_DQS_L ADD/CMD/CTL
[7:0] ≥ 8H

between
2 vias/pins)

(serpentine)

5.4.3.1.4 DDR4 x8 DRAM Down Layout Guidelines—Data/DM

The Data/Data Mask nets are modeled in Figure 56 and use the layout and length-matching routing rules in
Table 38.
Rank 0 Rank 1
DRAM DRAM
Via
Rank 0
Rank 1
L 3a L 3b
Processor
L1 L2
DATA/DM
Figure 56. Data/DM Routing Model (DDR4 x8 DRAM Down)
Table 38. Routing Rules for Data/DM (DDR4 x8 DRAM Down)

µS SL
Length Length matched within group (including DQS). N/A ≤ 9.0 ps

Matching
MA_DATA[63:0] (Processor to Data can be shorter than CLK (first DRAM) using effective lengths by up to: 360 ps
Via)
MA_DM Data can be longer than CLK (first DRAM) using effective lengths by up to: 180 ps
[7:0]
Length Limits Minimum trace length to first DRAM. N/A ≥ 25.4 mm
Maximum trace length to first DRAM. N/A ≤ 152.4 mm
Trace segment length between tee-route vias and DRAM. (L3a, L3b) ≤ 2.2 mm N/A
Table 38. Routing Rules for Data/DM (DDR4 x8 DRAM Down) (continued)
(L3a and L3b)
Layer Changes 2
MA_DATA[63:0]
MA_DM
[7:0]
Crossings

(L3a and L3b)
ZO N/A 0.1 mm N/A 50Ω ±10% 50Ω ±10% N/A
Trace Spacing N/A ≥ 0.1 mm N/A ≥ 3.3H ≥ 0.15 mm N/A
To
ADD/CMD/CTL
MA_DATA[63:0] ≥ 8H

MA_DM
[7:0] (3 traces length ≤ 2.54 mm
between
2 vias/pins)

(serpentine)

5.4.3.1.5 DDR4 x8 DRAM Down Layout Guidelines—Miscellaneous

M_RESET_L is modeled in Figure 57. M_RESET_L is routed point to point and references the VSS or
VDDIO_MEM_S3 plane. To maintain layout consistency of the memory subsystem, use the layout and routing
rules in Table 39.
DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM
L7 L7 L7 L7
L3 L3 L3
L4
L3 L3 L3
L7 L7 L7 L7
DRAM DRAM DRAM DRAM

DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM
Processor
L L
ALERT_L 1 2
Via
RESET_L
Rank 0
Rank 1
Figure 57. Miscellaneous Routing Model (DDR4 x8 DRAM Down)
Table 39. Routing Rules for Miscellaneous (DDR4 x8 DRAM Down)

Plane Edge Trace spacing from reference- ≥ 1H

plane edge.
MA_ALERT_L 0.1-mm trace spacing encroaching ≤ 2.54 mm

MA_RESET_L plane-edge rule is:
Length Limits Minimum trace length. ≥ 25.4 mm
Maximum trace length. ≤ 177.8 mm

Table 39. Routing Rules for Miscellaneous (DDR4 x8 DRAM Down) (continued)
Signals Rule Breakout Channel DRAM Area End Route
µS SL µS SL µS SL µS SL
Layer 3, Not Permitted in the Channel

Changes

Crossings
ZO ≥ 0.1 mm 40 to 60Ω 40 to 60Ω 40 to 60Ω
Trace ≥ 0.1 mm ≥ 1H ≥ 0.1 mm ≥ 0.1 mm

MA_ALERT_L Spacing
MA_RESET_L
(3 traces
between
2 vias/pins)
Self Not Permitted ≥ 0.2 mm Not Permitted

Spacing
(serpentine)

5.4.3.1.6 DDR4 x16 DRAM Down Layout Guidelines—CLK

The DDR4 x16 DRAMs receive one differential clock pair from the processor. Use MA_CLK_H/L[0] for Rank
0. Dual-rank configurations use MA_CLK_H/L[1] for Rank 1. Figure 58 shows the memory clock routing. The
target bus-channel impedance for the clocks allows for 10% variance, which includes manufacturing tolerances.
The memory CLK signal pairs are routed point to point and reference either the VSS plane or the
VDDIO_MEM_S3 plane. The CLK termination must match the CLK reference plane. CLK uses the layout and
length-matching routing rules in Table 41.
VSS
DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM or
VDDIO_MEM_S3
Processor
CTT
L7 L7 L7
L1 L2 L3 L4 L3 L7 L5 RTT
CLK_H RTT
CLK_L
Figure 58. CLK Routing Model (DDR4 x16 DRAM Down)
The termination component values for MA_CLK are listed in Table 40.
Table 40. Component Table—DDR4 x16 CLK Termination
RTT 39Ω 5% 0402 CLK termination
CTT
0.1 µF 5% 0402 CLK termination to VSS or VDDIO_MEM_S3.
CLK termination must match the CLK reference
plane.
Table 41. Routing Rules for CLK (DDR4 x16 DRAM Down)
Length Matching True and complement traces in a differential pair are length matched within: 1.80 ps
Length Limits Minimum trace length to first DRAM. ≥ 25.4 mm
Maximum trace length to first DRAM. ≤ 127 mm
MA_CLK_H[0] Trace segment length between DRAM 1 tee-route via to DRAM 2 tee-route via and 14.0 to 14.5 mm
MA_CLK_L[0] DRAM 3 tee-route via to DRAM 4 tee-route via (L3).
Trace segment length DRAM 2 tee-route via to DRAM 3 tee-route via (L4). L4 can 29.0 to 29.5 mm
be 14.00 mm to 15.00 mm, if needed.
Trace segment length between DRAM via to DRAM (L7) ≤ 3 mm
Trace segment length from the last DRAM tee-route via to the RTT termination ≤ 7.62 mm
(L5).

Table 41. Routing Rules for CLK (DDR4 x16 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Between Vias for DRAM Via to End Route to
DRAM (L3, L4) DRAM (L7) Term (L5)
µS SL µS SL µS SL µS SL µS SL
Layer 5
Changes

Crossings
ZOD N/A 0.1/ N/A 72Ω N/A 80Ω 80Ω N/A 80Ω ± 10%
0.1/0.1 ± 10% ± 10% ± 10%
MA_CLK_H[0] mm
MA_CLK_L[0]
Trace Spacing N/A 0.15 mm N/A ≥ 5H N/A ≥ 0.15 mm ≥ 0.15 mm N/A ≥ 0.15 mm
Trace Spacing N/A 0.1 mm

between
2 vias/pins)

(serpentine)

5.4.3.1.7 DDR4 x16 DRAM Down Layout Guidelines—ADD/CMD/CTL

Figure 59 shows the ADD/CMD/CTL routing model for a single-rank x16 configuration. All signals routed
reference either the VSS plane or the VDDIO_MEM_S3 plane.
DRAM DRAM DRAM DRAM

VTT
Processor L7 L7 L7 L7 RTT
L1 L2 L5
ADD/CMD/CTRL
L3 L4 L3
Figure 59. ADD/CMD/CTL Routing Model (DDR4 x16 DRAM Down)
The termination component values for ADD/CMD/CTL are listed in Table 42.
Table 42. Component Table—DDR4 x16 ADD/CMD/CTL Termination
RTT 39Ω 5% 0402 ADD/CMD/CTL termination to VTT
ADD/CMD/CTL use the layout and length-matching routing rules in Table 43.
Table 43. Routing Rules for ADD/CMD/CTL (DDR4 x16 DRAM Down)
0.1-mm trace spacing encroaching plane-edge rule for: ≤ 2.54 mm

ADD[12:0]
Length Matching Traces are length matched to the average of the clock pair. ± 22.70 ps
ADD13_BANK2
BANK[1:0] Length Limits Minimum trace segment length between processor to first DRAM (L1+ L2). ≥ 25.4 mm
BG[1:0]
ACT_L Maximum trace segment length between processor to first DRAM (L1+ L2). ≤ 127 mm
CS_L[1:0] Trace segment length between DRAM 1 tee-route via to DRAM 2 tee-route via and 14.0 to 15.0 mm
ODT[1:0] between DRAM 3 tee-route via to DRAM 4 tee-route via (L3).
CKE[1:0]
RAS_L_ADD[16] Trace segment length between DRAM 2 tee-route via to DRAM 3 tee-route via (L4). 29.0 to 30.0 mm
CAS_L_ADD[15] This trace segment (L4) can be 14.00 mm to 15.00 mm, if needed.
WE_L_ADD[14]
Trace segment length between DRAM tee-route via to DRAM (L7). Address nets. ≤ 3.0 mm
PAROUT
Trace segment length between DRAM tee-route via to DRAM (L7). CMD nets. ≤ 2.1 mm
Trace segment length from the last DRAM tee-route via to the RTT termination (L5). ≤ 7.62 mm

Signals Rule Breakout (L1) Channel (L2) Between Vias for DRAM Via to End Route to
DRAM (L3, L4) DRAM (L7) Term (L5)
µS SL µS SL µS SL µS SL µS SL
Layer 5
Changes

ADD[12:0]
Crossings
ADD13_BANK2
BANK[1:0] ZO N/A ≥ 0.1 N/A 40Ω N/A 50Ω 50Ω N/A 50Ω ± 10%
BG[1:0] mm ± 10% ± 10% ± 10%
ACT_L
CS_L[1:0] Trace Spacing N/A ≥ 0.1 N/A ≥ 3H N/A ≥ 0.1 ≥ 0.1 N/A N/A ≥ 0.1
ODT[1:0] mm mm mm mm
To Data/DM/DQS
CKE[1:0] ≥ 8H
RAS_L_ADD[16]
CAS_L_ADD[15] Trace Spacing ≥ 0.1 mm N/A 0.1 mm
WE_L_ADD[14] (3 traces length ≤ 2.54 mm
PAROUT between
2 vias/pins)

(serpentine)

5.4.3.1.8 DDR4 x16 DRAM Down Layout Guidelines—DQS

DRAM
L 3
Processor
L1 L2
DQS_H
DQS_L
Figure 60. DQS Routing Model (DDR4 x16 DRAM Down)
Table 44. Routing Rules for DQS (DDR4 x16 DRAM Down)
µS SL
Plane Edge Trace spacing from reference-plane edge.
0.1-mm trace spacing encroaching plane-edge rule is:

≥ 3H
≤ 2.54 mm
Length Length matched within group (including Data//DM). 9 ps

Matching
DQS can be shorter than CLK (first DRAM) using effective lengths by 180 ps
up to:
MA_DQS_H[7:0] DQS can be longer than CLK (first DRAM) using effective lengths by up 180 ps
MA_DQS_L[7:0] to:
True and complement traces are length matched on a DRAM by DRAM 1.80 ps
basis to within:
Length Limits Trace segment length between tee-route vias and DRAM. ≤ 2.6 mm N/A
Minimum trace length to first DRAM. ≥ 25.4 mm
Maximum trace length to first DRAM. ≤ 101.6 mm
Table 44. Routing Rules for DQS (DDR4 x16 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Tee Route to DRAM (L3)
MA_DQS_H[7:0] Layer Changes 2

MA_DQS_L[7:0] Test Points Not Permitted

Table 44. Routing Rules for DQS (DDR4 x16 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Tee Route to DRAM (L3)

Crossings
ZOD N/A ≥ 0.1/ 0.1/0.1 N/A 80Ω ±10% 80Ω ±10% N/A
mm
Trace Spacing N/A ≥ 0.1 mm N/A ≥ 4H ≥ 0.15 mm N/A
To
MA_DQS_H[7:0] ADD/CMD/CTL
MA_DQS_L[7:0] ≥ 8H

between
2 vias/pins)

(serpentine)

5.4.3.1.9 DDR4 x16 DRAM Down Layout Guidelines—Data/DM

Table 45.
DRAM
L 3
Processor
L1 L2
DATA/DM
Figure 61. Data/DM Routing Model x16 DRAM Down)
Table 45. Routing Rules for Data/DM (DDR4 x16 DRAM Down)
µS SL
Length Length matched within group (including DQS). ≤ 9.0 ps

Matching
Data can be shorter than CLK (first DRAM) using effective lengths by 180 ps
(Processor to
MA_DATA[63:0] up to:
Via)
MA_DM[7:0] Data can be longer than CLK (first DRAM) using effective lengths by up 180 ps
to:
Length Limits Trace segment length between tee-route vias and DRAM. ≤ 2.2 mm N/A
Minimum trace length to first DRAM. ≥ 25.4 mm
Maximum trace length to first DRAM. ≤ 101.6 mm
(L3)
Layer Changes 2
MA_DATA[63:0] Test Points Not Permitted

MA_DM[7:0] Crossings
ZO N/A 0.1 mm 50Ω ±10% 50Ω ±10% N/A

(L3)
Trace Spacing N/A ≥ 0.1 mm N/A ≥ 3.3H ≥ 0.15 mm N/A
To
ADD/CMD/CTL
≥ 8H
MA_DATA[63:0] ≥ 0.1 mm N/A

Trace Spacing 0.1 mm
MA_DM[7:0]
between
2 vias/pins)

(serpentine)
5.4.3.1.10 DDR4 x16 DRAM Down Layout Guidelines—Miscellaneous

M_RESET_L is modeled in Figure 62. M_RESET_L is routed point to point and references the VSS or
VDDIO_MEM_S3 plane. M_EVENT_L is an optional signal. It is supported only if the motherboard design
implements a thermal sensing device. To maintain layout consistency of the memory subsystem, use the layout
and routing rules in Table 46.
DRAM DRAM DRAM DRAM
Processor
L7 L7 L7 L7
L1 L2
RESET_L
ALERT_L
L3 L3 L3
Figure 62. Miscellaneous Routing Model (DDR4 x16 DRAM Down)
Table 46. Routing Rules for Miscellaneous (DDR4 x16 DRAM Down)
MA_ALERT_L 0.1-mm trace spacing encroaching plane-edge rule is: ≤ 2.54 mm

MA_RESET_L
Length Limits Minimum trace length. ≥ 25.4 mm
Maximum trace length. ≤ 177.8 mm
Signals Rule Breakout Channel DRAM Area
MA_ALERT_L Layer Changes 5, Not Permitted in the Channel

MA_RESET_L Test Points Not Permitted

Signals Rule Breakout Channel DRAM Area

Crossings
ZO ≥ 0.1 mm 40 to 60Ω 40 to 60Ω
Trace Spacing ≥ 0.1 mm ≥ 0.2 mm ≥ 0.1 mm
MA_ALERT_L To Data/DM/DQS ≥ 1H
MA_RESET_L ≥ 0.1 mm N/A
Trace Spacing 0.1 mm
between
2 vias/pins)
Self Spacing Not Permitted ≥ 0.2 mm Not Permitted

(serpentine)

5.5 LPDDR4x DRAM Down Memory Design Guidelines
This section describes the FP6 processor interconnect, layout rules, routing rules, and terminations for
LPDDR4x memory designs that use x32 LPDDR4x DRAM down for the memory subsystem. LPDDR4x
memory designs use point-to-point topology with two x32 LPDDR4x DRAMs per Channel, four total for
Channel A and Channel B. The LPDDR4x guidance is the same for LPDDR4 throughout this chapter except
where LPDDR4x / LPDDR4 differences are explicitly noted.
Connect M_LPDDR4 to VDDIO_MEM_S3 and M_DDR4 to VSS to select LPDDR4 mode. See Table 113 for a
Follow these rules to ensure a robust design.
Note: These LPDDR4x DRAM down routing rules assume a minimum ten-layer stackup using 1080 prepreg
for both microstrip and stripline.
5.5.1 LPDDR4x DRAM Down Layer Assignments

This section shows the layer assignments for a LPDDR4x DRAM down design.
Note: Routing net segments too close to a reference-plane split can cause signal integrity issues (fringe
effects).
The LPDDR4x x32 DRAM down memory configuration requires at least a 10-layer board. The LPDDR4x x32
DRAM down configuration uses two LPDDR4x x32 DRAMs per memory channel, a total of four LPDDR4x
x32 DRAMs for Channel A and Channel B. All four of the LPDDR4x x32 DRAMs are placed on the top side of
the board.
Figure 63 shows the DDR signal assignments for a 10-layer LPDDR4x DRAM down board.
DDR Power DQS DATA ADD CLK ADD DATA DQS DDR Power
VSS
VSS
VSS
VSS
VSS
DDR Power
Figure 63. Memory Signal Assignment LPDDR4x x32—Ten-Layer Board
5.5.2 LPDDR4x DRAM Down Placement

This section describes LPDDR4x x32 DRAM down placement.

5.5.2.1 Routing and Placement for LPDDR4x DRAM Down Configuration

Follow these guidelines for routing and placement of LPDDR4x DRAM down configurations.
• The processor supports a range of bus-channel lengths to the LPDDR4x DRAM. Choose a target length “X”
for each LPDDR4x DRAM based on the length of the longest MEMCLK in the Bus Channel. The target
length “X” is a gauge for length matching.
• Place the LPDDR4x DRAMs in close proximity to processor to minimize bus-channel length
• ADDR/CMD/CTL/CKE/CLK routed as point-to-point/tee
• LPDDR4x x32
• 10-layer stackup
• Two LPDDR4x x32 DRAMs per memory channel in a point-to-point/tee topology configuration
• Four LPDDR4x x32 DRAMs placed on top side (processor side) board
Figure 64 shows the general placement for ADD/CMD/CTL/CLK LPDDR4x x32 DRAM point-to-point/tee
topology.
LPDDR4x
X32
x16
x16
ADDR/CMD
CLK
LPDDR4x
X32
x16
x16
ADDR/CMD
CLK
Processor
ADDR/CMD
CLK
LPDDR4x
X32
x16
x16
ADDR/CMD
CLK
LPDDR4x
x16
X32
x16
Figure 64. LPDDR4x x32 DRAM Down Routing for ADD/CMD/CTL/CLK
Figure 65 shows LPDDR4x x32 DRAM placement.

Four LPDDR4x x32

DRAMs on Top Side
APU
LPDDR4x x32 DRAMs
Figure 65. LPDDR4x x32 DRAM Down Placement
5.5.2.2 Decoupling for LPDDR4x DRAM Down
Table 47. LPDDR4x DRAM Down Decoupling Capacitors

Capacitor DRAM VDD1-VSS VDD2-VSS VDDQ -VSS
Value Package Configuration +MEM_1.8V +APU_VDDIO_SUS +MEM_VDDQ

Size /
Material www.teknisi-indonesia.com
LPDDR4x 1.8V 1.1V 0.6V
LPDDR4 1.1V
22 µF 0603 X5R x32 2 1 1
0.22 µF 0402 X5R x32 – 20 –
0.1 µF 0402 X5R x32 5 – 15
180 pF 0402 X5R x32 1 – 1
Note: • Place decoupling capacitors close to DRAM device.

• Capacitor quantities listed are per DRAM device.
5.5.3 LPDDR4x DRAM Down Layout Guidelines

Layout sequence varies based on routing method in the DRAM down region.
The Layout Sequence for LPDDR4x x32 DRAM Down section lists the layout sequence for an LPDDR4x x32
DRAM down configuration for Channel A. Route Channel B using the same guidelines replacing the "MA" in
the signal name with "MB" for Channel B.
The sections that follow provide the layout guidelines.
5.5.3.1 Layout Sequence for LPDDR4x x32 DRAM Down
1. Place the DRAMs as shown in Figure 65.

Place two LPDDR4x x32 DRAMs per Channel (four for both Channel A and Channel B) on one side of the
board.
2. Route the memory Channel A clock pair MAA_CKT / MAA_CKC to one of the LPDDR4x x32 DRAMs.

a) Adjust the processor placement relative to the DRAMs until this length of XCH is shorter than the
maximum.
• The clock pair length to the DRAM is the target CLK length for the channel: XCH.
• The range of target CLK length, measured pin-to-pin, is specified in Table 48.
3. Route the other memory Channel A clock pair MAB_CKT / MAB_CKC to the other LPDDR4x x32 DRAM.
a) Adjust the processor placement relative to the DRAM until this length of XCH is shorter than the
maximum.
• The clock pair length to the DRAM is the target CLK length for the channel: XCH.
• The range of target CLK length, measured pin-to-pin, is specified in Table 48.
4. For each data group, route the Breakout portion of the nets so the net order matches the Breakout order of the
DRAM.
•
The signals should not cross one another when routed.
•
Two layers are required to break out channel MAx. One layer is required to break out channel MBx.
•
All nets in a data strobe group must be routed on the same layer.
•
All bit swapping must be reported to the memory controller via the BIOS interface defined in the AGESA
specifications.
• Bits may be swapped within a data strobe group.
• Bytes within a 16-bit LPDDR4x channel may be swapped.
5. Route all the remaining portions of the DDR nets to the DRAMs.
• The nets leading to the DRAM Pin Field (the channel route) must be routed on inner layers.
• Target trace lengths for LPDDR4x x32 DRAM down are specified in Table 48 through Table 53.
6. Continue routing the Data, Address, and Command nets to the remaining DRAMs.
7. Repeat steps 1 through 6 for memory Channel B, replacing "MA" with "MB" in the signal name for memory
Channel B.

5.5.3.1.1 LPDDR4x x32 DRAM Down Layout Guidelines—CLK

Each channel (group of two LPDDR4x DRAM devices in one x32 package) receives one differential clock pair
from the processor. Use MAA_CKT / MAA_CKC for one LPDDR4x x32 DRAM package and MAB_CKT /
MAB_CKC for the other LPDDR4x x32 DRAM package. The target Bus Channel impedance for the clocks
allows for 10% variance, which includes manufacturing tolerances. CLK uses the layout and length-matching
routing rules in Table 48. Use the same Channel A rules and guidelines for Channel B replacing the "MA" in the
signal name with "MB" for Channel B.
LPDDR4x DRAM x32 LPDDR4x DRAM x32
L7 L7 L7 L7
DRAM DRAM DRAM DRAM
16b 16b 16b 16b
Processor L2 L2
L1
MAA_CKT
MAA_CKC
MAB_CKT
MAB_CKC
Tee Via
L1
Figure 66. CLK Routing Model (LPDDR4x x32 DRAM Down)
Table 48. Routing Rules for CLK (LPDDR4x x32 DRAM Down)
µS SL
Length True and complement traces in a differential pair are length matched .90 ps
MAA_CKT/
Matching within:
MAA_CKC
MAB_CKT/ Length Limits Breakout trace length from processor (L1) ≤ 12.7 mm
MAB_CKC
Trace length from Tee to DRAM pin (L7) ≤ 2.54 mm
Maximum trace length to DRAM (L1 + L2 + L7) ≤ 50.8 mm
Note: Lengths are measured from processor pin to first DRAM pin.

Table 48. Routing Rules for CLK (LPDDR4x x32 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Pin/Via Field of DRAM
(L7)
Layer Changes 2
Plane Split Crossings Not Permitted
ZOD 0.1/ 0.1/0.1 mm N/A Single Single Ended: 50Ω ±10%

Ended: 50Ω Differential: 72Ω ±10%
±10%
Differential:
MAA_CKT/MAA_CKC
72Ω ±10%
MAB_CKT/MAB_CKC
Trace Spacing ≥ 0.15 mm N/A ≥ 4H ≥ 3H
Trace Spacing N/A 0.1 mm

(3 traces between length ≤ 2.54 mm
2 vias/pins)

(serpentine)

5.5.3.1.2 LPDDR4x x32 DRAM Down Layout Guidelines—ADD/CMD/CTL

Figure 67 shows the ADD/CMD/CTL routing model.
LPDDR4x DRAM x32 LPDDR4x DRAM x32
L7 L7 L7 L7
DRAM DRAM DRAM DRAM
16b 16b 16b 16b
Processor L2 L2
L1
MAA_CA/CKE/CS_L
MAB_CA/CKE/CS_L
L1
Tee Via
Figure 67. ADD/CMD/CTL Routing Model (LPDDR4x x32 DRAM Down)
ADD, CS_L, and CKE use the layout and length-matching routing rules in Table 49. Termination is not required
on ADD/CMD/CTL for LPDDR4x x32 configurations.
Table 49. Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM Down)
µS SL
0.1-mm trace spacing encroaching plane-edge rule for: ≤ 2.54 mm

MAA_CA[5:0]
Length Traces are length matched to the average of the clock pair of the respective ±20 ps
MAB_CA[5:0]
Matching Rank
MAA_CKE[1:0]
MAB_CKE[1:0] Length Limits Breakout trace length from processor (L1) ≤ 12.7 mm
MAA_CS_L[1:0]
MAB_CS_L[1:0]
Minimum trace length to DRAM (L1 + L2 + L7) ≥ 12.7 mm
Note: Lengths are measured from processor pin to DRAM pin.

Table 49. Routing Rules for ADD/CMD/CTL (LPDDR4x x32 DRAM Down) (continued)
Layer Changes 2
ZO ≥ 0.1 mm N/A 50Ω ±10% 50Ω ±10%
MAA_CA[5:0] Trace Spacing ≥ 0.1 mm N/A ≥ 3H ≥ 2H

MAB_CA[5:0]
MAA_CKE[1:0] N/A To
MAB_CKE[1:0] Data/DM/D
MAA_CS_L[1:0] QS ≥ 8H
MAB_CS_L[1:0]
2 vias/pins)

(serpentine)

5.5.3.1.3 LPDDR4x x32 DRAM Down Layout Guidelines—DQS

DRAM
Via
L3
Processor L2
L1
DQS_H R1 R2
DQS_L R1 R2
RTT RTT
VSS
Figure 68. DQS Routing Model (LPDDR4x x32 DRAM Down)
The termination component values for DQS are listed in Table 50.
Table 50. Component Table—LPDDR4x DQS Termination
Ref LPDDR Value Tolerance Package Comments
RTT
Mode
1% 0402 DQS termination to VSS for LPDDR4x

LPDDR4x 453Ω
mode.
LPDDR4 DNI - - No DQS termination for LPDDR4 mode.
Table 51. Routing Rules for DQS (LPDDR4x x32 DRAM Down)
µS SL
Length True and complement traces are length matched on a DRAM by DRAM 1.80 ps
Matching basis to within:
MAA_DQS_H[3:0] Averaged differential pair trace length to the average of the clock pair −100 ps
MAA_DQS_L[3:0] trace length(min):
MAB_DQS_H[3:0]
MAB_DQS_L[3:0] Averaged differential-pair trace length to the average of the clock pair 100 ps
trace length(max):
Length matched within group (including Data/DM/DQS) 9 ps
Length Limits Breakout Region1 trace length from processor (L1R1) ≤ 3.81 mm
Breakout Region1 + Region2 trace length from processor (L1) ≤ 12.7 mm

Table 51. Routing Rules for DQS (LPDDR4x x32 DRAM Down) (continued)
µS SL
MAA_DQS_H[3:0] Length Limits Trace length from Tee to DRAM pin (L3) ≤ 2.54 mm
MAA_DQS_L[3:0] Maximum trace length to DRAM (L1 + L2 + L3) ≤ 50.8 mm
MAB_DQS_H[3:0]
MAB_DQS_L[3:0]
Note: Lengths are measured from processor pin to DRAM pin.
Table 51. Routing Rules for DQS (LPDDR4x x32 DRAM Down) (continued)
Signals Rule Breakout (L1) Channel (L2) Pin/Via Field of DRAM (L3)
Region 1 Region 2 µS SL µS SL
µS SL
Layer Changes 2

Crossings
ZOD ≥ 0.1/ 0.1/0.1 mm N/A Single-ended 50Ω ± 10% Single-ended 50Ω ± 10%
Differential 80Ω ± 10% Differential 80Ω ± 10%
MAA_DQS_H[3:0]
MAA_DQS_L[3:0]
≥ 0.1 mm ≥ 0.2 ≥ 0.1 ≥ 4H ≥ 2H
Trace Spacing N/A
MAB_DQS_H[3:0]
mm mm
MAB_DQS_L[3:0] To ADD/CMD/CTL ≥ 8H

2 vias/pins)

(serpentine)

5.5.3.1.4 LPDDR4x x32 DRAM Down Layout Guidelines—Data/DM

Table 52.
DRAM
Via
L3
Processor L2
L1
DATA/DM R1 R2
Figure 69. Data/DM Routing Model (LPDDR4x x32 DRAM Down)
Table 52. Routing Rules for Data/DM (LPDDR4x x32 DRAM Down)
µS SL
MAA_DATA[31:0]
Length
Matching
Length matched within group (including Data/DM/DQS) ≤ 9.0 ps
MAA_DM[3:0] (Channel)
MAB_DATA[31:0]
Length Limits Breakout Region1 trace length from processor (L1R1) ≤ 3.81 mm
MAB_DM[3:0]
Breakout Region1 + Region2 trace length from processor (L1) ≤ 12.7 mm
Table 52. Routing Rules for Data/DM (LPDDR4x x32 DRAM Down) (continued)
(L3)
µS SL
Layer Changes 2
MAA_DATA[31:0] Test Points Not Permitted

MAA_DM[3:0]
MAB_DATA[31:0] Plane Split Not Permitted
MAB_DM[3:0] Crossings
ZO 0.1 mm N/A 50Ω ± 10% 50Ω ± 10%

Table 52. Routing Rules for Data/DM (LPDDR4x x32 DRAM Down) (continued)
(L3)
µS SL
Trace Spacing ≥ 0.1 mm ≥ 0.2 ≥ 0.1 N/A ≥ 3H ≥ 2H

mm mm
Byte to Byte Boundary
≥ 3H
To ADD/CMD/CTL
MAA_DATA[31:0] ≥ 8H
MAA_DM[3:0]
MAB_DATA[31:0]
MAB_DM[3:0] (3 traces length ≤ 2.54 mm
between
2 vias/pins)

(serpentine)

5.5.3.1.5 LPDDR4x x32 DRAM Down Layout Guidelines—Miscellaneous

Route MA_RESET_L either Daisy Chain or point-to-point/tee topology. Length matching for Miscellaneous
signals is not required. MA_EVENT_L is an optional signal. It is supported only if the motherboard design
implements a thermal sensing device. If used, MA_EVENT goes to a discrete thermal sensor. To maintain layout
consistency of the memory subsystem, use the layout and routing rules in Table 53.
Table 53. Routing Rules for Miscellaneous (LPDDR4x x32 DRAM Down)
µS SL
Plane Edge Trace spacing from ≥ 1H

reference-plane edge
MA_EVENT_L, 0.1-mm trace spacing ≤ 2.54 mm

MA_RESET_L encroaching plane-edge
rule is:
Length Limits Minimum trace length 25.4 mm
Table 53. Routing Rules for Miscellaneous (LPDDR4x x32 DRAM Down) (continued)
Signals Rule Breakout Channel DRAM Area End Route
µS SL µS SL µS SL µS SL
Layer
Changes www.teknisi-indonesia.com 3

Crossings
ZO ≥ 0.1 mm 40–60Ω 40–60Ω 40–60Ω N/A
Trace ≥ 0.1 mm ≥ 0.2 mm ≥ 0.2 mm ≥ 0.2 mm ≥ 0.2 mm N/A

Spacing
MA_EVENT_L, To Data/DM/DQS To Data/DM/DQS
MA_RESET_L ≥ 1H ≥ 1H

(3 traces
between
2 vias/pins)
Self Not Permitted ≥ 0.2 mm ≥ 0.2 mm Not Permitted

Spacing
(serpentine)

6 PCIe® Link Design Guidelines

This chapter contains specific termination, routing, and layout rules for the PCIe® links.
6.1 PCIe® Technology Overview

PCI Express® (PCIe) links are used to connect the processor to various system peripherals.
6.1.1 PCIe® Link Signals

The PCIe interface is an interconnection topology that contains links, and links are made of controller ports and
lanes. Each PCIe link consumes a controller port. Each PCIe lane consists of two low-voltage unidirectional
differential pairs: a transmit pair and a receive pair. The clock is embedded with the data. PCIe links are built by
combining PCIe lanes (a transmit differential pair and a receive differential pair).
• FP6 processors support a total of 8 GFX lanes (up to Gen 3) on a PCIe controller with up to 3 ports and 16
lanes.
• FP6 processors support a total of 12 GPP lanes (up to Gen 3) on a PCIe controller with up to 7 ports and 16
lanes.
PCIe links can be made from the combination of ports and lanes as shown in Table 54 for GFX and Table 55 for
GPP. All lanes of each PCIe controller must be assigned to a port, regardless of whether the lanes are pinned out
or not and of the operating mode of the Phy for each lane. Note that each Phy can only operate in one mode at a
time, either PCIe or SATA. Refer to PCIe and SATA to M.2 Connector Routing section. Combinations other
than those shown in the tables are not possible. GPP links are limited to x4 link width, and as shown in the table,
cannot be made into a x8 link. Also, all links must be of widths divisible by powers of 2 (for example, x1, x2,
x4...) that are on boundaries divisible by powers of 2 (for example, GPP[5:2] cannot be made into a x4 link; but
GPP[3:0] can be made into a x4 link).
Table 54. Possible Port/Lane Usages for GFX PCIe Controller
®
3 x 16 PCIe Controller
Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
N/A N/A x4 Phy x4 Phy
N/A N/A N/A N/A N/A N/A N/A N/A GFX0 GFX1 GFX2 GFX3 GFX4 GFX5 GFX6 GFX7
*Note 2 x8 PCIe
x4 PCIe x4 PCIe
Note: 1. This table represents all possible configurations of the PCIe controllers' Port/Lane asignments. Each row is not intended to show a valid
configuration. All Lanes of the PCIe controller must be allocated to 1 of the 3 ports of the controller. Even if the Lane is not pinned out.
2. Use x8 port config to consume only 1 controller port for Lanes [8:15] which are not pinned out (this allows for PCIe lane reversal support
on GFX[0:7] in x8 link config using a second port).

Table 55. Possible Port/Lane Usages for GPP PCIe Controller

®
7 x 16 PCIe Controller
x2 SATA x2 SATA
Controller Controller
Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane Lane
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
x2 Phy x2 Phy x4 Phy x4 Phy N/A
GPP0 GPP1 GPP2 GPP3 GPP4 GPP5 GPP6 GPP7 GPP8 GPP9 GPP10 GPP11 N/A N/A N/A N/A
x4 PCIe x4 PCIe x4 PCIe *Note 2 *Note 2, 3
x2 PCIe x2 PCIe x2 PCIe x2 PCIe x2 PCIe x2 PCIe
x2 PCIe x1 x1 x2 PCIe x1 x1 x2 PCIe x1 x1

PCIe PCIe PCIe PCIe PCIe PCIe
x1 x1 x2 PCIe x1 x1 x2 PCIe x1 x1 x2 PCIe

PCIe PCIe PCIe PCIe PCIe PCIe
x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1
PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe
x2 PCIe x1 x1 x1 x1 *Note *Note

*Note 4 2, 6 2, 6
SATA SATA SATA SATA
*Note *Note *Note *Note
4 4 2 2
x1 x1 x1 x1
PCIe PCIe SATA SATA
*Note *Note
5 5
Note: 1. This table represents all possible configurations of the PCIe and SATA controllers' Port/Lane asignments. Each row is not intended to
show a valid configuration. All Lanes of the PCIe controller must be allocated to 1 of the 7 ports of the controller. Even if the Lane is not
pinned out or the GPP for that Lane is used as SATA.
2. Use x8 port config to consume only 1 controller port for Lanes [8:15] when GPP[8:11] are used as x4 or SATA (PCIe lane reversal
cannot be supported in this config; GPP8 must be lane 0 at the downstream device).
3. Use x4 port config to consume only 1 controller port for Lanes[12:15] when GPP[8:11] are used as less than x4.
4. Use x4 port config to consume only 1 controller port for Lanes[0:3] when GPP[0:3] are used as x2 PCIe + 2x SATA. (PCIe lane reversal
cannot be supported in this config; GPP0 must be lane 0 at the downstream device)
5. Use x2 port config to consume only 1 controller port for Lanes[2:3] when GPP[0:3] are used as x1 PCIe + x1 PCIe + 2x SATA (for a total
of 3 ports consumed).
6. PCIe cannot be supported when the x4 Phy is in SATA mode.
PCIe is an AC-coupled bus. PCIe add-in boards are responsible for providing the AC-coupling capacitors on
their TX signals. Table 56 shows AC-coupling capacitor placement and value recommendations for PCIe.
Note: PCIe add-in boards allow lane connections to be reverse ordered to simplify PCB routing.
Figure 70 shows an example PCIe interface to connector.
PCIe® Link Design Guidelines 127

Processor PCIe® Connector

CCoupling
P_GFX_TXP[7:0] PETp[0:7]
P_GFX_TXN[7:0] PETn[0:7]
P_GFX_RXP[7:0] PERp[0:7]
P_GFX_RXN[7:0] PERn[0:7]
Processor PCIe Connectors

CCoupling
P_GPP_TXP[11:0] PETp[11:0]
P_GPP_TXN[11:0] PETn[11:0]
P_GPP_RXP[11:0] PERp[11:0]
P_GPP_RXN[11:0] PERn[11:0]
Figure 70. Block Diagram—PCI Express® Interface to Connector
Figure 71 shows examples of the PCIe interface to onboard devices. PCIe is an AC-coupled bus. Table 56 shows
AC-coupling capacitor placement and value recommendations for PCIe.
x4
®
Processor PCIe Device
CCoupling
P_GFX_TXP[7:0] RXP[7:0]
P_GFX_TXN[7:0] RXN[7:0]
CCoupling
P_GFX_RXP[7:0] TXP[7:0]
P_GFX_RXN[7:0] TXN[7:0]
x1, x2, or x4
Processor PCIe Devices
CCoupling
P_GPP_TXP[11:0] RXP[11:0]
P_GPP_TXN[11:0] RXN[11:0]
CCoupling
P_GPP_RXP[11:0] TXP[11:0]
P_GPP_RXN[11:0] TXN[11:0]
Figure 71. Block Diagram—PCI Express® Interface to Onboard Device
Table 56. Component Table—PCIe® Interface to Connector or Onboard Device

Ref Value 1 Tolerance Package Placement Location
Place as pairs 2, 3
®
CCoupling PCIe 10% 0402
• Gen3 Allowable Range: 176 to 265 nF

Recommended Value: 220 nF
• Gen2 Allowable Range: 75 to 200 nF
Note: 1. Capacitor material is X5R.

2. Placing capacitors as pairs requires traces to be length matched.
3. Place the AC-coupling capacitors for each pair as a pair within 0.889 mm of each other. See PCIe AC-Coupling Capacitors for more
details.

6.1.2 PCIe® and SATA to M.2 Connector Routing

The order of routing signals to the M.2 connector determines M.2 module support. See Figure 72 and Figure 73
for processor signals to M.2 connector routing options. See the bullets below each figure for the SSD support
information.
FP6 uses a x2 phy for GPP/SATA lanes GPP[3:2]/SATA[1:0] and a x4 phy for GPP[11:10} and GPP[9:8]/
SATA[3:2]. Each phy can only operate in either PCIe mode or SATA mode. If configured for PCIe all lanes
must be PCIe. If configured for SATA all lanes must be SATA. For example; In the case of the x4 phy for
GPP[11:8] and GPP[9:8]/SATA[3:2], if configured for SATA using SATA[3:2], lanes GPP{11:10] cannot be
used.
Processor M.2 Connector

CCoupling
P_GPP_TXP[0] PETp0/SATA-A+
P_GPP_TXN[0] PETn0/SATA-A-
P_GPP_RXP[0] PERp0/SATA-B-
P_GPP_RXN[0] PERn0/SATA-B+
CCoupling
P_GPP_TXP[1] PETp1
P_GPP_TXN[1] PETn1
P_GPP_RXP[1] PERp1
P_GPP_RXN[1] PERn1
CCoupling
P_GPP_TXP[2]/SATA0_TXP PETp2
P_GPP_TXN[2]/SATA0_TXN PETn2
P_GPP_RXP[2]/SATA0_RXP PERp2
P_GPP_RXN[2]/SATA0_RXN PERn2
P_GPP_TXP[3]/SATA1_TXP
P_GPP_TXN[3]/SATA1_TXN
CCoupling
PETp3
PETn3

CCoupling
P_GPP_TXP[11] PETp0/SATA-A+
P_GPP_TXN[11] PETn0/SATA-A-
P_GPP_RXP[11] PERp0/SATA-B-
P_GPP_RXN[11] PERn0/SATA-B+
CCoupling
P_GPP_TXP[10] PETp1
P_GPP_TXN[10] PETn1
P_GPP_RXP[10] PERp1
P_GPP_RXN[10] PERn1
CCoupling
CCoupling
Figure 72. Block Diagram—PCI Express® and SATA to M.2 Connector (PCIe SSDs Supported—SATA SSDs Not
Supported)

Using the connections shown in Figure 72 FP6 processors support the following SSDs in M.2 connectors:
• SATA SSDs are NOT supported using this connection option
• x4 PCIe SSDs are supported using this connection option

CCoupling
P_GPP_TXP[3]/SATA1_TXP PETp0/SATA-A+
P_GPP_TXN[3]/SATA1_TXN PETn0/SATA-A-
P_GPP_RXP[3]/SATA1_RXP See ‘polarity’ Note PERn0/SATA-B+

P_GPP_RXN[3]/SATA1_RXN for these signals PERp0/SATA-B-
CCoupling
CCoupling
P_GPP_TXP[1] PETp2
P_GPP_TXN[1] PETn2
P_GPP_RXP[1] PERp2
P_GPP_RXN[1] PERn2
CCoupling
P_GPP_TXP[0] PETp3
P_GPP_TXN[0] PETn3
P_GPP_RXP[0] PERp3
P_GPP_RXN[0] PERn3
CCoupling
P_GPP_TXP[8]/SATA2_TXP PETp0/SATA-A+
P_GPP_TXN[8]/SATA2_TXN PETn0/SATA-A-
P_GPP_RXP[8]/SATA2_RXP See ‘polarity’ Note PERn0/SATA-B+

P_GPP_RXN[8]/SATA2_RXN for these signals PERp0/SATA-B-
CCoupling
CCoupling
P_GPP_TXP[10] PETp2
P_GPP_TXN[10] PETn2
P_GPP_RXP[10] PERp2
P_GPP_RXN[10] PERn2
CCoupling
P_GPP_TXP[11] PETp3
P_GPP_TXN[11] PETn3
P_GPP_RXP[11] PERp3
P_GPP_RXN[11] PERn3
Figure 73. Block Diagram—PCI Express® and SATA to M.2 Connector (PCIe SSDs or SATA SSDs Supported)
Note: Connect the P_GPP_RXP[3]/SATA1_RXP and P_GPP_RXN[3]/SATA1_RXN signals or the the

P_GPP_RXP[8]/SATA2_RXP and P_GPP_RXN[8]/SATA2_RXN signals as shown to the M.2
connector according to the M.2 connector SATA polarity (SATA-B+/SATA-B-), not the PCIe polarity
(PERn0/PERp0). PCIe supports automatic polarity inversion. This will insure that both M.2 SATA and
PCIe SSDs will operate correctly.
Using the connections shown in Figure 73 processors support the following SSDs in M.2 connectors:
• x4 PCIe SSDs or SATA SSDs are supported using this connection option

6.2 Layer Assignments—PCIe®

Routing net segments too close to plane splits can cause signal integrity issues (fringe effects). Figure 74 shows
the signal assignments for a six-layer board.
GFX GFX GFX GFX GFX GFX GPP GPP GPP GPP GPP GPP
OTHER POWER
VSS
Figure 74. PCIe® Signal Assignment for a Six-Layer Board
Figure 75 shows the signal assignments for an eight-layer board.
GFX GFX www.teknisi-indonesia.com

GFX GFX GFX GFX GPP GPP GPP GPP GPP GPP
VSS
OTHER POWER
OTHER POWER
VSS
Figure 75. PCIe® Signal Assignment for an Eight-Layer Board
6.3 PCIe® AC-Coupling Capacitors

The PCIe interface requires series AC-coupling capacitors between the transmitter of one device and the receiver
of another device.

• Capacitors must be placed as pairs with fairly uniform placement.

• Staggering between pairs is strongly recommended.
• If staggering is not possible, capacitor pairs must have sufficient spacing between pairs.
Figure 76 illustrates placement of AC-coupling capacitors. Table 57 contains the recommended distances for the
AC-coupling capacitors.
LCoupling LCoupling
LConsecutive_Vias
4
RX TX
4
4
4
Onboard 4
4
4
4
Processor
Device
4
RX
4
TX 4
4
4
Microstrip
Aligned
Within Pair
4
4 Stagger the
4 Capacitor Pairs
4 Misaligned
Within Pair
4
4 LMisaligned
4 LCoupling
4
Stripline LOther_Cap 4
4
4
TX 4
TX
Processor
4
4
4
RX RX
Stripline
Important Lengths
LMisaligned < 0.889 mm
LOther_Via LOther_Via > 1.905 mm
4
LOther_Cap > 1.905 mm
4
LConsecutive_Vias > 1.905 mm
4 LCoupling < 25.4 mm
4
Reference plane
cut-out for
AC-coupling
capacitors
Figure 76. PCIe® AC-Coupling Capacitor Placement
Table 57. Recommended AC-Coupling Component Placement

LMisaligned LOther_Via LOther_Cap LConsecutive_Vias LCoupling
< 0.889 mm ≥ 2.54 mm ≥ 2.54 mm ≥ 12.7 mm ≥ 12.7 mm
• LMisaligned: Maximum allowed misalignment of AC-coupling capacitors within a differential pair. This
applies to physical placement as well as electrical distance, that is, trace mismatch.
• LOther_Via: Minimum physical distance separating vias of neighboring via pairs (vias are staggered).
• LOther_Cap: Minimum physical distance separating AC-coupling capacitor pads.
• LConsecutive_Vias: Minimum electrical distance separating layer change vias or AC-coupling capacitor pads on
the same net.

• LCoupling: Minimum electrical distance of AC-coupling capacitors from pins sourcing the signal. If overall
trace length is less than 76.2 mm, LCoupling distance is not applicable although the capacitors are still required.
If the reference plane under the AC-coupling capacitor is voided, then the rule can be relaxed to 7.62 mm to
ease placement requirements.
6.4 Routing Guidelines for PCIe® Interface

This section provides the routing requirements for the PCIe interface.
PCIe signals are high-frequency signals that must be properly routed. Follow the general layout and routing rules
from PCB Planning. Specific requirements are listed in the guidelines that follow. Note that guidelines listed in
this section supersede recommendations in PCB Planning for routing of PCIe signals. There are specific length-
matching requirements as well.
6.4.1 Layout Guidelines—PCIe® Interface to Onboard Devices

All PCIe signal pairs are routed point to point and reference VSS or the power plane. Figure 77 illustrates the
transmission line model for the PCIe nets. Table 58 lists the routing and length-matching rules.
BREAK PIN PCIe® Device

Processor BUS CHANNEL
OUT FIELD
12.7 mm
P_GFX_TXP/N[7:0] AC PERp/n[7:0]
AC
P_GFX_RXP/N[7:0] AC
PETp/n[7:0]
AC
PCIe Device
P_GPP_TXP/N[11:0] AC PERp/n[11:0]
AC
P_GPP_RXP/N[11:0] AC
AC PETp/n[11:0]
Figure 77. PCIe® Interface Routing Model to PCIe Onboard Device
Table 58. Routing Rules for PCIe® Interface to Onboard Device

µS SL
Device Component placement and spacing Refer to Figure 76 and Table 57.
Spacing1
Minimum distance between layer change via and the ≥ 12.70 mm
capacitor body is:

P_GFX_TXP/N[7:0]
P_GFX_RXP/N[7:0] Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
P_GPP_TXP/N[11:0] Length Difference between P and N traces within a differential pair ≤ 0.5 ps
P_GPP_RXP/N[11:0] Matching
Difference between differential pairs lane to lane ≤ 1250 ps
Difference between differential pairs lane to CLK ≤ 9000 ps
Maximum Maximum trace length Refer to Table 60.

Length

Table 58. Routing Rules for PCIe® Interface to Onboard Device (continued)
µS SL
P_GFX_TXP/N[7:0] Minimum Minmum trace length ≥ 25.4 mm

P_GFX_RXP/N[7:0] Length
P_GPP_TXP/N[11:0]
P_GPP_RXP/N[11:0]
Note: 1. The rules are waived for trace lengths shorter than 78.2 mm.
2. Unless specified otherwise, all lengths are electrical lengths instead of physical lengths.
Table 58. Routing Rules for PCIe® Interface to Onboard Device (continued)
Signals Rule Breakout Bus Channel Pin Field
Max Layer TX 6, 4 in channel

Changes RX 6, 4 in channel
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ±10% 85Ω ±10%
Trace Spacing ≥ 0.15 mm ≥ 5H Gen2 ≥ 3H ≥ 0.15 mm

P_GFX_TXP/N[7:0]
Gen3 ≥ 5H
P_GFX_RXP/N[7:0]
P_GPP_TXP/N[11:0] Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,
P_GPP_RXP/N[11:0] (exceptions) length ≤ 2.54 mm length ≤ 2.54 mm length ≤ 2.54 mm
(serpentine)

Crossings
6.4.2 Layout Guidelines—PCIe® Interface to Connector

All PCIe signal pairs are routed point to point and reference VSS or the power plane. Keep all unused lanes
unconnected. Surface-mount connectors are recommended to help reduce or eliminate end-point stubs. Route
signals to the connector on the microstrip layer opposite the connector if through-hole connectors are
implemented. Figure 78 illustrates the transmission line model for the PCIe nets.
PIN
Processor BREAKOUT BUS CHANNEL
FIELD PCIe® Connector
Regions
AC PETp/n[7:0]
P_GFX_TXP/N[7:0] AC
P_GFX_RXP/N[7:0] PERp/n[7:0]
PCIe Connector
P_GPP_TXP/N[11:0] AC PETp/n[11:0]
AC
P_GPP_RXP/N[11:0] PERp/n[11:0]
Figure 78. PCIe® Interface Routing Model to PCIe Connector

Table 59. Routing Rules for PCIe® Interface to PCIe Connector

Device Spacing1 Component placement and spacing Refer to Figure 76 and Table 57.
Minimum distance between connector pin and via to the ≥ 6.35 mm

connector (if through-hole connector is used and trace is
routed on top layer) is:
Minimum distance between layer change via and the ≥ 12.70 mm

capacitor body is:

P_GFX_TXP/N[7:0]
P_GFX_RXP/N[7:0] Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
P_GPP_TXP/N[11:0]
P_GPP_RXP/N[11:0] Length Matching Difference between P and N traces within a differential pair ≤ 0.50 ps
Difference between differential pairs lane to lane ≤ 1250 ps
Difference between differential pairs lane to CLK ≤ 9000 ps

Length
Minimum Minimum trace length ≥ 25.4 mm

Length
Table 59. Routing Rules for PCIe® Interface to PCIe Connector (continued)
Signals Rule Breakout Regions Bus Channel
Region 1 Region 2 µS SL Pin Field

2.54 mm 12.7 mm
Preferred Microstrip or Lower Stripline

Routing
Layer
Max Layer 4 total Vias Allowed:

Changes 1 Via in Breakout near processor
1 Via in Pin Field near connector
2 Vias near AC-coupling capacitors
P_GFX_TXP/N[7:0]
P_GFX_RXP/N[7:0]
P_GPP_TXP/N[11:0]
P_GPP_RXP/N[11:0] ZOD ≥ 0.1 / 0.1 / 85Ω ±10% 85Ω ±10% 85Ω ±10%
0.1 mm
Trace ≥ 0.1 mm ≥ 2.5H ≥ 5H ≥ 5H ≥ 5H

Spacing1

(serpentine)

Crossings

Table 59. Routing Rules for PCIe® Interface to PCIe Connector (continued)
Signals Rule Breakout Regions Bus Channel
Region 1 Region 2 µS SL Pin Field

2.54 mm 12.7 mm
Note: 1. Increase microstrip pair-to-pair spacing to 7H between AC-coupling capacitors and connector.
6.5 Length Matching—PCIe®

Both timing uncertainty and signal integrity must be considered when routing the PCIe bus. Therefore, signals
must be matched within a differential pair, and signals must be matched lane-to-lane. The signal group length-
matching rules are based upon propagation rates of 150 ps/in for microstrip and 180 ps/in for stripline. All the
length-matching numbers are direct derivatives of the PCIe specification for PCB skew assumptions.
P_Gxx_TX[0]
P_GPP or P_GFX
P_Gxx_TX[1]
{
P_Gxx_TX[3] LTXP to LTXN
P_Gxx_RX[0] (diff pair)
P_Gxx_RX[1]
P_Gxx_RX[3]
Skew (LLane to LLane)
Figure 79. PCIe® Length Matching

6.6 Length Limits—PCIe®

Length limits for PCIe depend greatly on PCB implementation. Via stubs are major factors in limiting PCIe net
lengths.
Table 60. PCIe® Routing Lengths vs. Topology

Signals Connected to Routing Layer Maximum Length
P_GFX TX,RX Onboard Device Microstrip ≤ 304.8 mm

or Stripline ≤ 304.8 mm
P_GPP TX, RX
P_GFX TX,RX PCIe® or M.2 Connector Microstrip ≤ 228.6 mm

or Stripline ≤ 228.6 mm
P_GPP TX, RX
P_GFX TX,RX U.2 Connector Microstrip ≤ 228.6 mm

or Direct-to-Drive Stripline ≤ 228.6 mm
P_GPP TX, RX (i.e., no cables)
Note: • The maximum trace lengths are derived from simulations and are based on the following:
1. Stripline traces are routed on bottom most stripline layer.

7 Display Interface Design Guidelines

FP6 processors provide display controllers and interfaces as outlined in Table 61.
Table 61. Display Feature Compatibility

Digital Display Interface Features FP6 Processors
Display Controllers Four
Display Interfaces Four
The FP6 processor supports the following digital display interfaces (DDI):
• DisplayPort (DP)
• Embedded DisplayPort (eDP)
• Digital visual interface (DVI)
• High-definition multimedia interface (HDMI™)
• Low voltage differential signaling (LVDS)1 (via external translator)
• VGA2 (via external translator)
Note: 1. LVDS is supported by DP and converted to LVDS output by an external translator.
2. VGA is supported by DP and converted to analog output by an external translator.
3. Recommend using surface-mount connectors for DVI, HDMI, and DP. If thru-hole connector is used,
recommend routing to the connector on the bottom microstrip layer to avoid stubs.
FP6 processor Display Ports
•
•
DisplayPort 0: eDP/DP/TMDS
DisplayPort 1: eDP/DP/TMDS
• DisplayPort 2: eDP/DP/TMDS; or USB-C® with DP alt mode
• DisplayPort 3: eDP/DP/TMDS; or USB-C with DP alt mode
• Maximum of 4 simultaneous outputs
7.1 DisplayPort Interface

This section provides details outlining the relevant connectivity for the DisplayPort MainLink (ML) signals, as
well as the Auxiliary (AUX) channel and I2C selection logic.
Each of the DisplayPort interfaces have a x4 MainLink (ML), one x1 Auxiliary (AUX) channel, and one hot-
plug detect (HPD) pin.
Table 62. DisplayPort MainLink (ML), Auxiliary (AUX), and Hot Plug Detect HPD) Signals
x4 MainLink x1 Auxiliary Channel Hot Plug Detect Pin
DP0_TXP/N [3:0] DP0_AUXP/N DP0_HPD
DP1_TXP/N [3:0] DP1_AUXP/N DP1_HPD

Table 62. DisplayPort MainLink (ML), Auxiliary (AUX), and Hot Plug Detect HPD) Signals (continued)
x4 MainLink x1 Auxiliary Channel Hot Plug Detect Pin
USBC0_RX1P/USB0_RXP/DP2_TXP[3] DP2_AUXP/N DP2_HPD

USBC0_RX1N/USB0_RXN/DP2_TXN[3]
USBC0_TX1P/USB0_TXP/DP2_TXP[2]
USBC0_TX1N/USB0_TXN/DP2_TXN[2]
USBC0_TX2P/DP2_TXP[1]
USBC0_TX2N/DP2_TXN[1]
USBC0_RX2P/DP2_TXP[0]
USBC0_RX2N/DP2_TXN[0]
UUSBC4_RX1P/USB4_RXP/DP3_TXP[3] DP3_AUXP/N DP3_HPD

Table 63 lists the processor pin names and descriptions for the DisplayPort interface.
Table 63. DisplayPort Signal Descriptions

Processor Signal Name Signal Description Direction1
DP0_TXP[3:0]
DP0_TXN[3:0]
DisplayPort[0] MainLink OUT
DP0_AUXP DisplayPort[0] Auxiliary Channel BI
DP0_AUXN
DP0_HPD DisplayPort[0] Hot Plug Detect IN
DP1_TXP[3:0] DisplayPort[1] MainLink OUT
DP1_TXN[3:0]
DP1_AUXN

DP2_TXN[3:0]

DP2_AUXN
DP3_TXN[3:0]
Display Interface Design Guidelines 139

Table 63. DisplayPort Signal Descriptions (continued)

Processor Signal Name Signal Description Direction1
DP3_AUXN DisplayPort[3] Hot Plug Detect IN
DP3_HPD
Panel Control Signals
DP_BLON LCD Backlight Inverter On OUT
DP_DIGON Control to Power LCD Logic Circuits OUT
DP_VARY_BL LCD Backlight Intensity OUT
Note: 1. Direction is relative to the processor.
The MainLink, AUX channel, and HPD pins are covered in following sections.
7.1.1 StereoSync
The FP6 processor supports various stereo 3D video configurations:
• HDMI 1.4a Display, shutter glasses, and video player
• Line Interleaved Panel, passive polarized glasses, and video player
StereoSync is required to precisely align shutter glasses with the appropriate interleaved video frame.
Figure 80 illustrates an example circuit to drive the StereoSync output.
+1.8 V RUN +3.3V
+5V
R1 R2
3 5
7
DP_STEREOSYNC STEREOSYNC
Q1
Figure 80. Schematic Diagram—StereoSync Interface
Table 64 shows component values for a StereoSync interface.
Table 64. Component Table—StereoSync Interface

R1, R2 Q1
10 kΩ, 5%, 0402 MMBT3904, SOT-23
7.2 DisplayPort Configurations

The FP6 processor DisplayPort interface supports the following signaling levels:
• DisplayPort (DP0, DP1, DP2, and DP3)
• TMDS (DVI or HDMI)
This section describes each of the applications of the DisplayPort using schematic diagrams. Design rules are
given in the following sections.
Table 65 lists various interfaces and the required DisplayPort configurations.

Table 65. DisplayPort Configurations

Display Interface Display Interface Configurations
DP DP x4 DP Aux DP Aux HPD DP_ BLON

+ -
3 2 1 0 DP_ DIGON
DP_ VARY_BL
DP0, DP1 MainLink[3:0] AUX1 HPD not connected
DP2 USBC0_RX1P/USB0_RXP/DP2_TXP[3] DP2_AUXP/N DP2_HPD not connected

internally muxed USBC0_RX1N/USB0_RXN/DP2_TXN[3]
with USBC0_TX1P/USB0_TXP/DP2_TXP[2]
USB Port 0 USBC0_TX1N/USB0_TXN/DP2_TXN[2]
DP3 USBC4_RX1P/USB4_RXP/DP3_TXP[3] DP3_AUXP/N DP3_HPD not connected

internally muxed USBC4_RX1N/USB4_RXN/DP3_TXN[3]
with USBC4_TX1P/USB4_TXP/DP3_TXP[2]
USB Port 4 USBC4_TX1N/USB4_TXN/DP3_TXN[2]
DP++ DP MainLink[3:0] AUX1 HPD not connected
DVI or Channel Ch 0 Ch 1 Ch 2 DDC DDC HPD not connected

Clock2 Data2
™
HDMI Clock
Single-Link DVI Channel Ch 0 Ch 1 Ch 2 DDC DDC HPD not connected

Clock Clock2 Data2
HDMI Channel Ch 0 Ch 1 Ch 2 DDC DDC HPD not connected

Clock Clock2 Data2
LVDS (Panel) N/C N/C LVDS Translator LVDS Translator1 HPD Inverter Power
LCD Logic Power
Inverter Control
eDP (Panel) MainLink[3:0] AUX1 HPD Inverter Power
LCD Logic Power
Inverter Control
VGA VGA Translator VGA Translator1 HPD not connected
Note: 1. Auxiliary Mode, AC coupled (see DisplayPort Plus Plus (DP++) Connector).
2. I2C Mode, DC coupled (see DisplayPort Plus Plus (DP++) Connector).

7.2.1 DisplayPort Connectors (No DVI or HDMI™ Support)

Figure 81 illustrates a schematic diagram for a DisplayPort interface used for connecting to DisplayPort
connectors. MainLink and AUX signals require AC-coupling capacitors. HPD signals do not require AC-
coupling capacitors. See DisplayPort AC-Coupling Capacitors for more details.
Note: There are no provisions in this implementation to support DVI or HDMI signaling to DVI or HDMI
connectors. To support DVI or HDMI with a DisplayPort connector refer to DisplayPort to DVI
Connector.
Processor DP
DP Connector
CCoupling DESD
DPn_TXP[0] ML_Lane 0(p)
DPn_TXN[0] ML_Lane 0(n)



DPn_AUXP AUX CH(p)

Vss
RAUX
DPn_AUXN AUX CH(n)
3.3
RAUX CAD
Vss GND
DPn_HPD Hot Plug Detect
RHPD
Figure 81. Schematic Diagram—DisplayPort to DisplayPort Connector (DP Only)
7.2.2 Embedded DisplayPort Panel—eDP

Figure 82 illustrates a schematic diagram for an Embedded DisplayPort interface used for connecting to
DisplayPort panels. AC-coupling capacitors are used on MainLink and Auxilliary Channel signals.

Processor eDP Panel

DP
CCoupling



DPn_AUXP AUX CH(p)
AUX CH(n)
DPn_AUXN
DPn_HPD HPD
Vss RHPD
DP_BLON Level Shift BL_ENABLE
DP_VARY_BL Level Shift BL_PWM_DIM
DP_DIGON Level Shift LCD_VCC_ENABLE
Figure 82. Schematic Diagram—DisplayPort to eDP Panel
Components for DisplayPort to DP and eDP connectors are listed in Table 66. Level shift options and details for
HPD are shown in later figures.
Table 66. Component Table—DisplayPort to DP and eDP Connectors
Ref Value Tolerance Package Comment
CCoupling 100 nF 10% 0402 Allowable Range: 75 to 200 nF

Place as pairs1, 2
RAUX3 100 kΩ 5% 0402 AUXN: Pull-up resistor to +3.3 V

AUXP: Pull-down resistor to VSS
RHPD 100 kΩ 5% 0402 Pull-down resistor to VSS
DESD4 8 kV – – Required: ESD-specific device placed close to the connector.

See Layout Guidelines—DisplayPort ML to DP or eDP
Connectors for details.
Note: 1. Placing AC-coupling capacitors as pairs requires traces to be length matched. See Layout Guidelines—DisplayPort ML to DP or eDP
Connectors for details on component placement.
2. Capacitor material is X5R.
3. DP to DP connector only. RAUX not required for eDP connector.
4. DP to DP connector only. DESD not required for eDP connector. AMD requires low insertion loss, low capacitive-loading ESD-
suppression devices. See Table 134.
Table 67 lists the DP connections from the processor to a four lane Embedded DisplayPort panel with LED
backlight. DisplayPort0 is used in this example. Other DisplayPorts can be connected similarly.

Table 67. DisplayPort Signals to eDP Panel

DP Connections eDP Panel
Processor Signal Name DP Connector Processor Signal

Name
Pin Pin Name Pin Name Pin
DP0_TXP0 13 Lane 0_P Lane 0_N 12 DP0_TXN0
DP0_AUXP 15 AUX CH_P AUX CH_N 16 DP0_AUXN
DP0_HPD 23 HPD LCD_VCC 18, 19 DP_DIGON
DP_BLON 28 BL_ENABLE BL_PWM_DIM 29 DP_VARY_BL
VSS 24, 25, 26, 27 Return BL_PWR 32, 33, 34, 35 (to battery)

7.2.3 DisplayPort Plus Plus (DP++) Connector

The DisplayPort DP++ interface supports
• DisplayPort devices
• require an AC-coupled AUX channel
• DVI or HDMI devices
• require the use of a dongle
• require a DC-coupled AUX channel
Figure 83 shows a schematic diagram of the DisplayPort interface with the DP++ AUX conversion block
necessary to support either DisplayPort signal levels or TMDS levels (DVI or HDMI).
Processor DP++
DP++ Connector
DESD
CCoupling


AUX Conversion Block
DPn_AUXP AUX CH(p)
DPn_AUXP AUX_P
Vss
RAUX
DPn_AUXN DPn_AUXN AUX_N AUX CH(n)
(See Schematic) 3.3
CAD RAUX CAD (Config1)
Vss GND
RHPD
Figure 83. Schematic Diagram—DisplayPort to DisplayPort Plus Plus (DP++) Connector
Table 68 lists DisplayPort to DP++ connector components. Figure 84 shows level-shift options and details for
HPD.
Table 68. Component Table—DisplayPort to DP++ Connector


Place as pairs1, 2
RAUX 100 kΩ 5% 0402 AUXN: Pull-up resistor to +3.3 V

AUXP: Pull-down resistor to VSS
RHPD 100 kΩ 5% 0402 VSS

Table 68. Component Table—DisplayPort to DP++ Connector (continued)

DESD3 8 kV – – Required: ESD-specific device placed close to

the connector. See Layout Guidelines—
DisplayPort ML to DP++ Connector for details.
Note: 1. Placing capacitors as pairs requires traces to be length matched. See Layout Guidelines—DisplayPort ML to DP++ Connector for details
about component placement.
3. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134.
Figure 84 shows the details of the DP++ AUX Conversion Block in Figure 83.
Q1 Q2
C1
DP0_AUXP AUX_P
DP0_AUXN AUX_N
C2
Q3 Q4
Q5 Q6
CAD
R1 R2
(Config1)
R3
Vin Vin
U1
DP0_HPD HPD
R8 R9
+1.8
Figure 84. Schematic Diagram—AUX Conversion Block and HPD Level Shifter
Table 69 lists DP++ AUX Conversion Block components.

Table 69. Component Table—DP++ AUX Conversion Block

C1 ,C2 100 nF 10% 0402 Allowable Range: 75 to 200 nF
Place as pairs1, 2
R1 – R3 1 MΩ 10% 0402 –
R8 4.7 kΩ 5% 0402 Pull-up resistor to +1.8 V
R9 100 kΩ 5% 0402 Pull-down resistor to VSS
U1 - – SOT-23 –
Note: 1. Placing capacitors as pairs requires traces to be length matched. See Section Layout Guidelines—DisplayPort Hot Plug Detect to
Connector for details on component placement.
Table 70 lists the DP connections from the processor to the DisplayPort or DP++ connector pins. DisplayPort0 is
used in this example. DisplayPort1 pins can be connected similarly.
Table 70. DisplayPort Signals to DP or DP++ Connector
Processor Signal Name DP Connector Processor Signal Name
VSS 2 GND ML_Lane 0(p) 1 DP0_TXP[0]
DP0_TXP[1] 4 ML_Lane 1(p) ML_Lane 0(n) 3 DP0_TXN[0]
DP0_TXN[1] 6 ML_Lane 1(n) GND 5 VSS
VSS 8 GND ML_Lane 2(p) 7 DP0_TXP[2]
DP0_TXP[3] 10 ML_Lane 3(p) ML_Lane 2(n) 9 DP0_TXN[2]
DP0_TXN[3] 12 ML_Lane 3(n) GND 11 VSS
VSS 16 GND AUX CH(p) 15 DP0_AUXP
DP0_HPD 18 Hot Plug Detect AUX CH(n) 17 DP0_AUXN
+3.3V 203 DP_PWR Return 19 VSS
1. Pin 13 is GND in DP mode and Cable Adaptor Detect (CAD) in DP++, DVI and HDMI Modes.
™
Note:
2. Pin 14 is GND in DP and DVI modes and is Consumer Electronics Control (CEC) in HDMI mode.
3. +3.3 V supplied by motherboard.
7.2.4 DisplayPort to DVI Connector

Digital visual interface (DVI) supports PC video formats. DVI uses transition-minimized differential signaling
(TMDS), which incorporates 8b/10b, DC balanced encoding. A single-link DVI connection consists of four
TMDS links; each link transmits data from the source to the device over one TMDS pair. Three of the links
correspond to the RGB components of the video signal: red, green, blue. The fourth link carries the pixel clock.
7.2.4.1 Single-Link DVI Interface

Figure 85 illustrates a schematic diagram for a single-link DVI interface.

DVI
Processor Connector
PHYlet
(TMDS Mode) +5V +5V Power
V3.3_S0
CCoupling QTMDS DESD
DPn_TXP[0] TMDS Data2+
RTMDS
RTMDS
DPn_TXN[0] TMDS Data2–
DPn_TXP[3] TMDS Clock+
DPn_TXN[3] R AU X TMDS Clock–

+5V
DPn_AUXP Level DDC_CLK (SCL)
DPn_AUXN Shift DDC_DAT (SDA)
+5V
RAUX
DPn_HPD Level Shift Hot Plug Detect
RHPD
Figure 85. Schematic Diagram—Single-Link DVI Interface
Component values for DVI are listed in Table 71. The sideband signals of DVI shown in Figure 85 are referred
to as display data channel (DDC), which is composed of I2C compatible signals, serial clock (SCL), and serial
data (SDA).
• The RTMDS resistors provide the proper DC bias to the AC-coupled signals from the processor.
• The FET prevents the system from drawing power from a DVI panel while the system is off.
Table 71. Component Table—DisplayPort to Single-Link DVI Connector

Place as pairs1, 2
RTMDS 499Ω 1% 0402 Value includes RDS-ON of FET
RAUX 2.2 kΩ (can be 5% 0402 Pull-up resistor to +5 V

part of Level
Shift circuit)
RHPD 100 kΩ 5% 0603 VSS
DESD3 8 kV – – Required: ESD-specific device placed close to the connector.
QTMDS – – SOT-23 RDS-ON(max) = 20Ω, VGS-TH(max) = 4 V

Table 71. Component Table—DisplayPort to Single-Link DVI Connector (continued)

Note: 1. Placing capacitors as pairs requires traces to be length matched. See Layout Guidelines—DisplayPort ML to DVI or HDMI Connector for
details.
3. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134. See DisplayPort AC-Coupling
Capacitors for device placement details.
Table 72 lists the DP connections from the processor and the AUX Conversion Block to the DVI connector pins.
DisplayPort1 is used in this example. DisplayPort2 can be connected similarly.
Table 72. Connections for DisplayPort to Single-Link DVI Interface
Processor Signal Name DVI Connector CCoupling DESD RTMDS QTMDS Other Components
DP1_TXP0 TMDS Data2+ CCoupling DESD RTMDS QTMDS –
DP1_TXN0 TMDS Data2- CCoupling DESD RTMDS QTMDS –
DP1_TXP3 TMDS Clock+ CCoupling DESD RTMDS QTMDS –
DP1_TXN3 TMDS Clock- CCoupling DESD RTMDS QTMDS –
DP1_AUXP
DDC Clock – DESD – – RAUX
DP1_AUXN DDC Data – DESD – – RAUX
DP1_HPD Hot Plug Detect – DESD – – RHPD
7.2.4.2 DVI Connectors

The following are common DVI connector types.
• DVI-D (digital only)
• DVI-A (analog only)
The DVI-D connector only supports digital signals. The DVI-A only supports analog signals.
7.2.5 DisplayPort to HDMI™ Connector

High-Definition Multimedia Interface (HDMI) supports PC and Television video formats and up to eight digital
audio channels. HDMI uses TMDS, which incorporates 8b/10b, DC balanced encoding. HDMI contains digital
audio.
Figure 86 illustrates a schematic diagram for an HDMI interface.

HDMI™
Processor Connector
PHYlet +5V
(TMDS Mode) +5V Power
CCoupling
DESD
RTMDS

V3.3_S0
DPn_TXN[3] TMDS Clock–
RAUX +5V
Level DDC_CLK (SCL)
DPn_AUXP Shift
DPn_AUXN DDC_DAT (SDA)
RAUX +5V
GND
DPn_HPD Level Shift Hot Plug Detect
RHPD
Figure 86. Schematic Diagram—HDMI™ Interface
Component values for an HDMI interface are listed in Table 73.
• The RTMDS resistors provide the proper DC bias required by the HDMI specification, to the AC-coupled
signals from the processor.
• The FET prevents the system from drawing power from an HDMI panel while the system is off.
Table 73. Component Table—Display Interface to HDMI™ Connector

Place as pairs1, 2
RTMDS 499Ω 1% 0402 Value includes RDS-ON of FET
RAux 2.2 kΩ (can be 5% 0402 Pull-up resistor to +5 V

part of Level Shift
circuit)
RHPD 100 kΩ 5% 0603 VSS
DESD3 8 kV – – Required: ESD-specific device placed close to the connector. See Layout
Guidelines—DisplayPort ML to DVI or HDMI Connector for details.
FET – – SOT-23 RDS-ON (max) = 20Ω, VGS-TH (max) = 4 V
details.
3. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134. See DisplayPort AC-Coupling
Capacitors for device placement details.

Table 74 lists the connections from the to the HDMI connector pins. DisplayPort0 is used in this example.
Table 74. Connections for DisplayPort to HDMI™ Interface
Processor Signal Name DVI Connector CCoupling DESD RTMDS QTMDS Other Components
DP0_TXP3 TMDS Clock+ CCoupling DESD RTMDS QTMDS –
DP0_TXN3 TMDS Clock- CCoupling DESD RTMDS QTMDS –
DP0_AUXP DDC Clock – DESD – – RAUX
DP0_AUXN DDC Data – DESD – – RAUX
DP0_HPD Hot Plug Detect – DESD – – RHPD

7.2.5.1 DisplayPort to HDMI™ 2.0 Retimer / Redriver to Connector

HDMI 2.0 requires the use of an external retimer/redriver. An external retimer retimes the input stream to
compensate for random jitter. An external redriver provides additional signal drive strength.
Figure 87 is an example schematic diagram for an HDMI 2.0 to retimer/redriver to connector interface.
The maximum trace length

APU
and trace impedance from HDMI™Connector
Display the Retimer/Redriver IC to
Interface the connector must be
HDMI 2.0 specified by the retimer/
redriver vendor.
+5V +5V Power
CCoupling
HDMI 2.0
Retimer/
DPn_TXN[0] Redriver TMDS Data2–
Signal
DPn_TXP[1] Conditioner TMDS Data1+

`
DPn_TXN[3] TMDS Clock–
RAUX 3.3V RAUX +5V
DPn_AUXP DDC_CLK (SCL)
DPn_AUXN DDC_DAT (SDA)
RAUX 3.3V RAUX +5V
GND
This is an example retimer/redriver. Refer to the retimer/redriver vendor

schematic for connection details.
Figure 87. Schematic Diagram—HDMI™ 2.0 to Retimer/Redriver to Connector
Component values for a processor display interface to a vendor supplied HDMI 2.0 redriver/retimer to connector
interface are listed in Table 75.
Note: • Any ESD device required between the retimer/redriver and connector must be specified by the
retimer/redriver vendor. The ESD device used must protect both the retimer/redriver and the AMD
APU.
• The trace impedance between the retimer/redriver and connector must be specified by the retimer/
redriver vendor.
• The maximum trace length between the APU and retimer/redriver must be specified by the retimer/
redriver vendor.
• The maximum trace length between the retimer/redriver and connector must be specified by the
retimer/redriver vendor.

Table 75. Component Table—Display Interface to HDMI™ 2.0 Retimer/Redriver to Connector

Place as pairs1, 2
RAux 2.2 kΩ 5% 0402 Pull-up resistor to +3.3 V

Pull-up resistor to +5 V (verify with retimer/redriver vendor specification)
details.
7.2.6 DisplayPort to LVDS and VGA Translator
7.2.6.1 DisplayPort to LVDS Translator

Low voltage differential signaling (LVDS) levels are not natively supported on the processor and require the use
of an external translator or adapter. Figure 88 is a block diagram of a DP to LVDS translator for an LCD
interface.
www.teknisi-indonesia.com LVDS(U)
LVDS(L)
DP_Main
I2C LCD Panel
DP_AUX
LVDS DP_BLEN
Processor DP_HPD 3 data bits per
Translator DP_DIGON channel
DP_VARY_BL
DP_VARY_BL
Level Inverter
Shift
Figure 88. DisplayPort to LVDS Translator Block Diagram
Figure 89 is a more detailed schematic diagram view of the block diagram shown in Figure 88.

Translator Specific LED

Backlight Backlight
AUXCAL
CALRN Control
VDD_LED_BL(6)
GND(6)
LCD_BKL_PWM
VDD_LED_BL(6) LCD_BLK_EN
GND(6)
SENSE_0 LED_STRING_0
DP-to-LVDS SENSE_1 LED_STRING_1
LED_STRING_2
SENSE_2
Translator SENSE_3 LED_STRING_3
LED_STRING_4
SENSE_4
Processor SENSE_5 LED_STRING_5
BL_EN ENABLE
(DP Mode) VARY_BL PWM
DIGON Power FET VDD_DIGITAL

+3.3V
RDDC
DDC_DATA LCD_DDC_DATA
DDC_CLK LCD_DDC_CLK
RDDC +3.3V
TXOUT_L0_P LCD_TX_L2P
TXOUT_L0_N LCD_TX_L2N
TXOUT_L1_N LCD_TX_L1N
DP_DIGON CPU_DIGITAL_ON TXOUT_L2_N LCD_TX_L0N
Level
DP_BLON BL_ENABLE
Trans.
DP_VARY_BL CPU_VARY_BL
CCoupling TXOUT_CLKL_P LCD_TX_CLKLP
TXOUT_CLKL_N LCD_TX_CLKLN
DPn_TXP[0] ML_LVDS_L0_P
DPn_TXN[0] ML_LVDS_L0_N
DPn_TXP[1] ML_LVDS_L1_P TXOUT_U0_P LCD_TX_U2P

DPn_TXN[1] ML_LVDS_L1_N TXOUT_U0_N LCD_TX_U2N
TXOUT_U1_P LCD_TX_U1P
TXOUT_U1_N LCD_TX_U1N
TXOUT_U2_P LCD_TX_U0P
TXOUT_U2_N LCD_TX_U0N
DPn_AUXP AUX_LVDS_CH_P
DPn_AUXN AUX_LVDS_CH_N
TXOUT_CLKU_P LCD_TX_CLKUP
DPn_HPD LVDS_HPD TXOUT_CLKU_N LCD_TX_CLKUN
Figure 89. Schematic Diagram—DisplayPort, Translator and LCD (LVDS)
Note: For more design details pertaining to the LVDS translator see ANX9834: Ultra Low Power Receiver
with VGA and LVDS Output, or consult with the manufacturer.
Table 76. Component Table—DisplayPort, Translator and LCD (LVDS)

RDDC 4.7 kΩ 5% 0402 Pull-up resistor to +3.3V

7.2.6.2 DisplayPort to VGA Translator

Video Graphics Array (VGA) signaling levels are not natively supported on the processor and require the use of
an external translator or adapter.
For information on the translator, see ANX9834: Ultra Low Power Receiver with VGA and LVDS Output.
Figure 90 is a schematic diagram of a DP-to-VGA translator for a typical VGA interface. The processor
DisplayPort, the DisplayPort to VGA Translator, and the VGA filter network are shown in Figure 90. Refer to
the translator manufacturer design details for VGA component placement and routing guidelines.
L1PI L2PI VGA

Processor VGA RT1 RT2 C1PI C2PI C3PI DB-15
DisplayPort Translator RED RED
RED_L RGND
p Filter p Filter
RT1 RT2 C1PI C2PI C3PI

GREEN GREEN
GREEN_L GGND
CCoupling
DPn_TXP[0] ML_VGA_L0_P RT1 RT2 C1PI C2PI C3PI
DPn_TXN[0] ML_VGA_L0_N BLUE BLUE
BLUE_L BGND
DPn_TXP[1] ML_VGA_L1_P
DPn_TXN[1] ML_VGA_L1_N 5V
DPn_TXP[2] ML_VGA_L2_P H-SYNC HSYNC

DPn_TXN[2] ML_VGA_L2_N V-SYNC VSYNC
VSS 5V SGND
DPn_TXP[3] ML_VGA_L3_P
DPn_TXN[3] ML_VGA_L3_N RPU ID0
VGA_DDC_SDA ID1(SDA)
DPn_AUXP AUX_VGA_CH_P ID2
RPU
DPn_AUXN AUX_VGA_CH_N VGA_DDC_SCL ID3(SCL)
DAC_RSET Alternate Pi Filter

DPn_HPD VGA_HPD
C4PI L3PI C5PI
p Filter
Figure 90. Schematic Diagram—DisplayPort, Translator and VGA
Table 77 shows component values for a DisplayPort to Translator and VGA interface.
Table 77. Component Table—DisplayPort to Translator and VGA Interface
Place as pairs.1, 2
RT1, RT2 150Ω 1% 0402 Part of the VGA filter network.
RPU 2 kΩ 5% 0402 Pull-up resistor to +5V
C1PI—C5PI 3 pF to 6 pF 10% 0603 Allowable Range: 3 to 6 pF
L1PI—L3PI 47 nH 1% 0603 Part of the VGA filter network.
Note: 1. Placing capacitors as pairs requires traces to be length matched. See DisplayPort AC-Coupling Capacitors for details on component
placement.
7.3 Layer Assignments—DisplayPort

Routing net segments too close to a reference-plane split can cause signal integrity issues (fringe effects).

For a dielectric height H, a net segment in the Bus Channel that is less than 5H from a reference-plane split must
not exceed 2.54 mm in length for that spacing.
The DP layer assignments for 6-layer and 8-layer boards are shown in Figure 91 and Figure 92.
Figure 91. DP Signal Assignment for a 6-Layer Board
Figure 92. DP Signal Assignment for an 8-Layer Board
7.4 DisplayPort AC-Coupling Capacitors

The DisplayPort interface requires series AC-coupling capacitors between the transmitter of one device and the
receiver of another device.
• If staggering is not possible, capacitor pairs must be of sufficient spacing between pairs.
• For via spacing, if the board thickness is ≤ 1.27 mm, use 1.2X board thickness.

Figure 93 illustrates placement of AC-coupling capacitors and ESD components near external connectors. Table
78 shows the recommended distances for the AC-coupling capacitors.
LCoupling
LConsecutive_Vias
Onboard 4
ML TX
4
4
4
Device APU
4
4
Microstrip
Aligned
Within Pair
4
4 Stagger the
4 Capacitor Pairs
4 Misaligned
Within Pair
4
4 LMisaligned
LESD 4 LCoupling
4
ML
4
TX
4
APU
4
4
4
ESD
ML TX
4
4
4
4
4
Stripline
Important Lengths
LMisaligned
LOther_Via LOther_Via
4
LOther_Cap
4
LConsecutive_Vias
4 LESD
4 LCoupling
Figure 93. DisplayPort AC-Coupling Capacitor Placement
Table 78. Recommended AC-Coupling Component Placement

LMisaligned LOther_Via LOther_Cap LConsecutive_Vias LESD LCoupling
< 0.889 mm ≥ 1.905 mm ≥ 2.54 mm ≥ 12.7 mm ≥ 12.7 mm ≥ 12.7 mm
• LMisaligned: Maximum allowed misalignment of AC-coupling capacitors within a differential pair. This applies
to physical placement as well as electrical distance, that is, trace mismatch.
the same net.
• LESD: Minimum electrical distance of ESD component pads from connector pin. If the reference plane under
the ESD component is voided, then the rule can be relaxed down to 7.62 mm to ease placement requirements.
• LCoupling: Minimum electrical distance of AC-coupling capacitors from ESD device (if applicable) or from
pins sourcing the signal. If the reference plane under the coupling capacitor is voided, then the rule can be
relaxed to 7.62 mm to ease placement requirements.

7.5 Routing Guidelines for DisplayPort

This section provides the routing requirements for the DisplayPort signals to the display device or connector.
DisplayPort signals are high-frequency differential signals that must be properly routed. Follow the general
layout and routing rules from PCB Planning. Specific requirements are listed in the guidelines that follow. Note
that guidelines listed in this section supersede any recommendations in PCB Planning for routing of DisplayPort
signals. There are specific length-matching requirements as well, and these depend on the interface that is being
supported.
7.5.1 Layout Guidelines—DisplayPort ML to DP or eDP Connectors

All DisplayPort signals are routed point to point and reference VSS or the power plane. Surface-mount
connectors are recommended as they eliminate end-point stubs. The preferred routing layer is a microstrip layer
or bottom stripline layer. Route signals to the connector on the microstrip layer opposite the connector if
through-hole connectors are implemented.
Void the reference plane under the pads of the surface mount DP/eDP connector to reduce excess pad
capacitance. Figure 94 illustrates the routing model for the DisplayPort MainLink to a connector.
BREAK PIN
Processor OUT BUS CHANNEL FIELD DP/eDP Connector
12.7 mm
DPn_TXP/N[3:0] AC ESD ML_Lane[3:0](p/n)
AC ESD
ESD devices used for
DP Connector, not for
eDP connector
Figure 94. DP Routing Model (MainLink to DP or eDP Connector)
The DisplayPort MainLink nets to a connector rules and recommendations are listed in Table 79.
Table 79. Routing Rules for DP (MainLink to DP or eDP Connector)

µS SL

connector (if through-hole connector is used and trace is routed
on top layer) is:

DPn_TXP/N[3:0]
Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
Length Difference between P and N traces within a differential pair ≤ 0.50 ps

Matching
Difference between differential pairs per MainLink ≤ 400 ps

Length

Table 79. Routing Rules for DP (MainLink to DP or eDP Connector) (continued)

Breakout Bus Channel Pin Field
Signals Rule
Max Layer 4 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ±10% 85Ω ±10%
Trace Spacing ≥ 0.3 mm ≥ 5H ≥ 4H ≥ 0.3 mm6

DPn_TXP/N[3:0] Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,
(exceptions) length ≤ 2.54 mm length ≤ 2.54 mm length ≤ 2.54 mm

(serpentine)

Crossings
3. All unused DP lanes are kept unconnected.
4. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134. ESD protection is not required on eDP
interface.
5. The use of stacked connectors is discouraged.
6. Increase spacing between microstrip pairs in the section between the AC-coupling capacitors, ESD-suppression devices, and connectors
to 7H.
7.5.2 Layout Guidelines—DisplayPort AUX Channel to DP or eDP Connectors

All DisplayPort signals are routed point to point and reference VSS or the power plane. Surface-mount
connectors are recommended as they eliminate end-point stubs. Route signals to the connector on the microstrip
layer opposite the connector if through-hole connectors are implemented.
Figure 95 illustrates the routing model for the DisplayPort AUX Channel to a DP or eDP connector. The series
resistors on DPn_AUXP/N are for DP HBR3 Only.
BREAK PIN
Processor OUT BUS CHANNEL FIELD DP/eDP Connector
12.7 mm
RAUX
AC ESD
DPn_AUXP/N AUX CH (p/n)
AC ESD
RAUX
Figure 95. DP Routing Model (AUX to DP or eDP Connector)
The DisplayPort AUX Channel nets to a connector rules and recommendations are listed in Table 80.
Table 80. Routing Rules for DP (AUX to DP or eDP Connector)

µS SL
DPn_AUXP/N Device Spacing1 Component placement and spacing Refer to Figure 93 and Table 78.

Table 80. Routing Rules for DP (AUX to DP or eDP Connector) (continued)

µS SL
Plane Edge Trace spacing from reference plane edge ≥5H

DPn_AUXP/N
Length Matching Difference between P and N traces within a differential pair ≤ 0.50 ps
Maximum Length Maximum trace length Refer to Table 88.
4. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134. ESD protection is not required on eDP
interface.
Table 80. Routing Rules for DP (AUX to DP or eDP Connector) (continued)

Signals Rule
Max Layer 4 Total

Changes
ZOD
Trace Spacing
≥ 0.1/ 0.1/0.1 mm
≥ 0.15 mm ≥ 4H
85Ω ± 10%
≥ 3H
85Ω ± 10%
≥ 0.3 mm
DPn_AUXP/N Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,

(serpentine)

Crossings
7.5.3 Layout Guidelines—DisplayPort ML to DP++ Connector

All DisplayPort signals are routed point to point and reference the VSS plane or any other power plane. Surface-
mount connectors are recommended as they eliminate end-point stubs. The preferred routing layer is a microstrip
layer or bottom stripline layer. Route signals to the connector on the microstrip layer opposite the connector if
Void the reference plane under the pads of the surface mount DP/DP++ connector to reduce excess pad
capacitance.
Figure 96 illustrates the routing model for the DisplayPort MainLink to a DP++ connector.

BREAK PIN
Processor OUT BUS CHANNEL FIELD DP++ Connector
12.7 mm
AC ESD
DPn_TXP/N[3:0] ML_Lane[3:0](p/n)
AC ESD
Figure 96. DP Routing Model (MainLink to DP++ Connector)
The DisplayPort MainLink nets to a DP++ connector rules and recommendations are listed in Table 81.
Table 81. Routing Rules for DP (MainLink to DP++ Connector)

µS SL

routed on top layer) is:

DPn_TXP/N[3:0]
Difference between differential pairs per MainLink ≤ 200 ps
Maximum Length Maximum trace length
Table 81. Routing Rules for DP (MainLink to DP++ Connector) (continued)

Refer to Table 88.

Signals Rule
Max Layer 2 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%
Trace Spacing ≥ 0.3 mm ≥ 5H ≥ 4H ≥ 0.3 mm 6


(serpentine)

Crossings

Table 81. Routing Rules for DP (MainLink to DP++ Connector) (continued)

Signals Rule
3. All unused DP++ lanes are kept unconnected.
to 7H.
7.5.4 Layout Guidelines—DisplayPort AUX Channel to DP++ Connector

mount connectors are recommended as they eliminate end-point stubs. Route signals to the connector on the
microstrip layer opposite the connector if through-hole connectors are implemented.
Figure 97 illustrates the routing model for the DisplayPort AUX Channel to a DP++ connector.
BREAK PIN
Processor OUT BUS CHANNEL FIELD DP++ Connector
12.7 mm
RAUX
Auxiliary
DPn_AUXP/N N
Conversion
N ESD AUX CH (p/n)
P P ESD
Block
RAUX
Figure 97. DP Routing Model (AUX to DP++ Connector)
DisplayPort AUX Channel nets to DP++ connector rules and recommendations are listed in Table 82.
Table 82. Routing Rules for DP (AUX to DP++ Connector)

µS SL
DPn _AUXP/N Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
3. All unused DP++ lanes are kept unconnected.

Table 82. Routing Rules for DP (AUX to DP++ Connector) (continued)

Signals Rule
Max Layer 2 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%

DPn _AUXP/N Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,

(serpentine)

Crossings
7.5.5 Layout Guidelines—DisplayPort ML to DVI or HDMI™ Connector

mount connectors are recommended as they eliminate end-point stubs. The preferred routing layer is a microstrip
layer or bottom stripline layer. Route signals to the connector on the microstrip layer opposite the connector if
Void the reference plane under the pads of the surface mount DVI/HDMI connector to reduce excess pad
capacitance.
Figure 98 illustrates the routing model for DP MainLink to a DVI or HDMI connector.
BREAK PIN
Processor OUT BUS CHANNEL FIELD TMDS Connector
12.7 mm Can Share
One FET RTMDS
TMDS
AC ESD
DPn_TXP/N[3:0] Data[2:0]+/-
AC ESD Clock+/-
RTMDS
Figure 98. DP Routing Model (MainLink to DVI or HDMI™ Connector)
The DisplayPort MainLink nets to a DVI or HDMI connector rules and recommendations are listed in Table 83.
Table 83. Routing Rules for DP (MainLink to DVI or HDMI™ Connector)

µS SL

DPn_TXP/N[3:0] routed on top layer) is:

Table 83. Routing Rules for DP (MainLink to DVI or HDMI™ Connector) (continued)
µS SL
DPn_TXP/N[3:0] Difference between differential pairs per MainLink ≤ 200 ps
Table 83. Routing Rules for DP (MainLink to DVI or HDMI™ Connector) (continued)
Signals Rule
Max Layer 2 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%
Trace Spacing ≥ 0.3 mm ≥ 5H ≥ 4H ≥ 0.3 mm5


(serpentine)
Crossings
3. All unused TMDS lanes are kept unconnected.
to 7H.
7.5.6 Layout Guidelines—DisplayPort AUX Channel to DVI or HDMI™ Connector

mount connectors are recommended as they eliminate end-point stubs. Route signals to the connector on the
microstrip layer opposite the connector if through-hole connectors are implemented.
Figure 99 illustrates the routing model for DP AUX Channel to a DVI or HDMI connector.
BREAK PIN
Processor OUT BUS CHANNEL FIELD TMDS Connector
12.7 mm
RAUX
DDC_CLK (SCL)
DPn_AUXP/N Level Shift
ESD DDC_DAT (SDA)
ESD
RAUX
Figure 99. DP Routing Model (AUX to DVI or HDMI™ Connector)

The DisplayPort AUX Channel nets to a DVI or HDMI connector rules and recommendations are listed in Table
84.
Table 84. Routing Rules for DP (AUX to DVI or HDMI™ Connector)

µS SL
DPn_AUXP/N Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
3. All unused TMDS lanes are kept unconnected.
Table 84. Routing Rules for DP (AUX to DVI or HDMI™ Connector) (continued)
Signals Rule
Max Layer 2 Total
Changes
ZO ≥ 0.1/ 0.1/0.1 mm1 85Ω ± 10%2 85Ω ± 10%2

DPn_AUXP/N Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,

(serpentine)

Crossings
Note: 1. Single-ended trace width is 0.1 mm.

2. Single-ended impedance is 50Ω ±10%.
7.5.7 Layout Guidelines—DisplayPort ML to Translator

All DisplayPort signals are routed point to point and reference the VSS plane or any other power plane. The
preferred routing layer is a microstrip layer or bottom stripline layer. Figure 100 illustrates the routing model for
DisplayPort MainLink to an onboard device. The DisplayPort MainLink nets to an onboard device rules and
recommendations are listed in Table 85.

BREAK PIN
Processor OUT BUS CHANNEL FIELD DP Graphics Device
12.7 mm
ML_Lane[3:0](p/n)
AC
DPn_TXP/N[3:0]
AC
Figure 100. DP Routing Model (MainLink to Translator)
Table 85. Routing Rules for DP (MainLink to Translator)

µS SL
DPn_TXP/N[3:0]
Difference between differential pairs per MainLink. If a re- ≤ 400 ps
driver or re-timer is used, consult the device manufacturer for
its inherent intra-pair skew which will need to be budgeted
into the pcb skew total.
Table 85. Routing Rules for DP (MainLink to Translator) (continued)

Signals Rule
Max Layer 4 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ±10% 0.1/ 0.1/0.1 mm


(serpentine)

Crossings

7.5.8 Layout Guidelines—DisplayPort AUX Channel to Translator

All DisplayPort signals are routed point to point and reference the VSS plane or any other power plane. The
preferred routing layer is a microstrip layer or bottom stripline layer. Figure 101 illustrates the routing model for
the DisplayPort AUX Channel to onboard devices. The DisplayPort AUX Channel nets to onboard devices rules
and recommendations are listed in Table 86.
BREAK PIN
Processor OUT BUS CHANNEL FIELD DP Graphics Device
12.7 mm
RAUX
AUX CH (p/n)
AC
DPn_AUXP/N
AC
RAUX
Figure 101. DP Routing Model (AUX to Translator)
Table 86. Routing Rules for DP (AUX to Translator)

µS SL
DPn _AUXP/N Cumulative trace length encroaching plane edge rule ≤ 2.54 mm
Table 86. Routing Rules for DP (AUX to Translator) (continued)

Signals Rule
Max Layer 4 Total

Changes
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%

DPn _AUXP/N Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,

(serpentine)

Crossings

7.5.9 Layout Guidelines—DisplayPort Hot Plug Detect to Connector

All DisplayPort signals are routed point to point and reference the VSS plane. Figure 102 illustrates the routing
model for DisplayPort HPD nets to a DP, eDP,DVI or HDMI connector. Although not shown in the figure, HPD
nets from the processor do not route to an LVDS panel. Instead, they are pulled up to +3.3 V with a 100-kΩ
resistor. The preferred routing layer is a microstrip layer or bottom stripline layer.
BREAK PIN
Processor OUT BUS CHANNEL FIELD DP, DP++, eDP,
12.7 mm DVI, HDMI™
Connector
Level
DPn_HPD Shift ESD HPD
RHPD
Figure 102. DP HPD Routing Model to Connector
DisplayPort hot-plug detect (HPD) to connector routing rules and recommendations are listed in Table 87.
Table 87. Routing Rules for DP HPD to Connector

Signals Rule
Max Layer 4 Total

Changes
ZO ≥ 0.1 mm ≥ 0.1 mm ≥ 0.1 mm

DPn_HPD Trace Spacing 0.1 mm, 0.1 mm, 0.1 mm,

(serpentine)

Crossings
7.6 Length Limits—DisplayPort

Both timing uncertainty and signal integrity must be considered when routing the DisplayPort bus. Signals must
be length matched within a differential pair, and signals must be length matched lane to lane. The length-
matching rules for the signal group are based upon propagation rates of 150 ps per inch for microstrip and 180 ps
per inch for stripline. All the length-matching numbers are direct derivatives of the DisplayPort specification for
PCB skew assumptions.
• SKEWDIFF_PAIR: Difference between true and complement traces within a differential pair.
• SKEWLANE_LANE: Difference between differential pairs.

Table 88. Display Interface Maximum Trace Length vs. Topology

Display Mode Chipset / Retimer / Redriver Connector
Microstrip Stripline Microstrip Stripline
DP HBR 203.2 mm 203.2 mm 203.2 mm 203.2 mm

(2.7 GT/s)
DP HBR2 Not Supported Not Supported 203.2 mm 203.2 mm

(5.4 GT/s)
DP HBR3 Implementation Dependent Implementation Dependent 139.7 mm 88.9 mm

(8.1 GT/s)
eDP HBR Not Supported Not Supported 177.8 mm 177.8 mm

(2.7 GT/s)
eDP HBR2 Not Supported Not Supported 203.2 mm 203.2 mm

(5.4 GT/s)
eDP HBR3 Implementation Dependent Implementation Dependent N/A N/A

(8.1 GT/s)
TMDS Implementation Dependent Implementation Dependent 177.8 mm 177.8 mm

(2.25 GT/s)
177.8 mm 127 mm
TMDS Implementation Dependent Implementation Dependent
(3 GT/s)
TMDS2 Implementation Dependent Implementation Dependent 203.2 mm 203.2 mm

(3.4 GT/s)
TMDS2 Implementation Dependent Implementation Dependent 101.6 mm 152.4 mm

(6GT/s)
DP++ Not Supported Not Supported 203.2 mm 203.2 mm
Note: 1. Simulations for eDP channel confirmed meeting the eDP specification requirements using a 12 inch AWG 40 coaxial cable.
Implementations significantly different from this should be simulated by the OEM/ODM to confirm specification compliance.
2. HDMI 2.0 routes to an onboard external retimer/redriver then to a connector. The maximum trace length and trace impedance from the
retimer/redriver to the connector must be specified by the retimer/redriver vendor in order to meet the HDMI 2.0 specification
requirements. Designs utilizing retimer/redrivers must be simulated.
3. TMDS applies to either DVI or HDMI.

8 USB Interface Design Guidelines

8.1 USB Interface Signals
8.1.1 USB Controller to Port Mapping
Figure 103 shows the USB controller to port mapping for FP6 processors when USB-C® connectors are not
implemented.
FP6 USB Controller Port Mapping

(No USB-C port)
APU
Controller 0 Controller 1
USB 3.2 G2 (10Gbps) compatible USB 3.2 G2 (10Gbps) compatible
USB 2.0 compatible protocol USB 2.0 compatible protocol
protocol protocol
HCP HCP HCP HCP HCP HCP HCP HCP HCP HCP HCP HCP
IP0 IP1 IP2 IP3 IP4 IP5 IP6 IP7

USB1_TX[P/N] : USB1_RX[P/N]
USB0_DP/N
USB4_DP/N
USB3_DP/N
USB2_DP/N
USB1_DP/N
USB7_DP/N
USB6_DP/N
USB5_DP/N
C0 C1 C2 C3 C4 C5 C6 C7
USB-A USB-A USB-A USB-A USB-A USB-A USB-A USB-A
USB Port 0 USB Port 1 USB Port 2 USB Port 3 USB Port 4 USB Port 5 USB Port 6 USB Port 7
Figure 103. FP6 Processor USB Controller to Port Mapping—No USB-C® Connector
Note: To support the Microsoft USB certification requirement to have a platform support USB debug port, at
least one USB 3.2 compatible port must be routed to a connector to support system level debug.
Table 89 lists the signal to port mapping for USB:

Table 89. FP6 Platform—USB Signal to USB Port Mapping

USB Ports Signals USB Protocols
USB Port 0 USBC0_TX1P/USB0_TXP/DP2_TXP[2] USB 3.2 G2 (10Gbps)

USBC0_RX1P/USB0_RXP/DP2_TXP[3] USB 2.0
USBC0_DP/USB0_DP
USBC0_DN/USB0_DN
USB Port 1 USB1_TXP USB 3.2 G2 (10Gbps)

USB1_TXN
USB1_RXP USB 2.0
USB1_RXN
USB1_DP
USB1_DN
USB Port 2 USB2_DP USB 2.0

USB2_DN

USB3_DN
USB Port 4 USBC4_TX1P/USB4_TXP/DP3_TXP[2] USB 3.2 G2 (10Gbps)

USBC4_RX1P/USB4_RXP/DP3_TXP[3] USB 2.0
USBC4_DP/USB4_DP
USBC4_DN/USB4_DN
USB Port 5 USB5_TXP USB 3.2 G2 (10Gbps)

USB5_TXN
USB5_RXP USB 2.0
USB5_RXN
USB5_DP
USB5_DN

USB6_DN

USB7_DN
USB Interface Design Guidelines 171

Figure 104 illustrates a USB2.0/SS HUB tier mismatch between xHCI external port and a USB A connector that
is not allowed per the xHCI specification. If additional USB ports are needed on a design, a USB3.2 HUB must
be used and both the USB2.0 and USB3.2/SuperSpeed ports routed from the USB3.2 HUB to the external
connector.
Processor
xHCI Controller
USB2.0
USB3.2
USB2.0
HUB
Onboard
Device USB3.2
External Port
USB 2.0/SS HUB Tier mismatch between xHC External Port and USB A connector is not allowed
Figure 104. USB 2.0/SS HUB Tier Mismatch—xHCI Specification Violation
8.1.2 Layout Requirements for I/O Connectors Using Metal Shielding

For all I/O connectors that use metal shielding:
• Connect the metal connector shield pins to the motherboard GND and GND copper pour around connector (if
copper pour around connector is available) shell pins across all layers by using 50-mil wide interconnecting
traces to minimize thermal relief.
• Add stitching vias to the GND copper pour around metal connector shield pins.
8.1.3 USB Micro-AB Connector Implementation Requirements

The On-The-Go (OTG) and embedded host (EH) specifications 2.0 and 3.0 have been updated to expand Micro-
AB connector usage. OTG and EH 2.0/3.0 now allow for host functionality over one or more Standard-A or
Micro-AB receptacles. FP6 processor-based platforms are compliant to the specification functioning as an
embedded host. FP6 processor-based platforms can support a Micro-AB connector with the limitation that the
processor functions only as a host. When implementing a Micro-AB connector, the circuit used to provide USB
power to the connector must use the ID pin (pin 4 on Micro-A and Micro-B plugs) to ensure that the USB VBUS
is only driven when a Micro-A plug is attached. The ID pin is used to make this determination based on the
Micro-USB specification. The specification defines that the ID pin is connected directly to ground on a Micro-A
plug and either floating or connected to ground by a resistance of 100 kΩ or greater on a Micro-B plug.
Figure 105 shows an example of a USB power switch circuit that meets these requirements. In this example, the
Texas Instruments TPS2555 device was selected based on its ability to respond to overcurrent scenarios as a
means of supporting USB overcurrent conditions via the FAULT# output.

+3.3V
+5V
R2
10k
C1
R1 0.1 µF U1
10k 2 9
3
IN OUT USB_PWR
OUT 8
IN
5 10
USB_ID EN# FAULT# USB_OC#
4
ILIM_SEL
7
ILIM0
1 6
GND ILIM1
11
PAD
R3 C2
TPS2555 47k 0.1 µF + C3
100 µF
ILIMIT=48000/R3
Figure 105. USB Power Switch for Micro-AB Receptacles

8.1.4 USB 3.2 Connector Voids

USB 3.2 high speed transfers make board layout critical to signal integrity and performance. Place VSS or
reference plane cutouts (voids) under connectors and components to help reduce capacitive impedance at high
frequencies. The following examples are based on a typical board stackup.
Figure 106 shows an example of a USB Micro-B VSS/Reference plane void that improves signal integrity. The
void is directly beneath the connector on the nearest/adjacent reference plane.
W
H
Figure 106. Example 1 USB Micro-B VSS/Reference Plane Void
Figure 107 shows an example of the VSS/Reference plane void for USB Micro-B connector. The void is directly
beneath the connector on the nearest/adjacent reference plane. Example dimensions for H = 53 mils and W =
55.975 mils.
W
H
Figure 107. Example 2 USB Micro-B VSS/Reference Plane Void

Figure 108 shows an example of SMT pads for AC-coupling capacitors utilizing VSS/Reference plane void to
improve signal integrity. Recommend 0402 size for AC-coupling capacitors. The void is directly beneath the
pads of the components on the nearest/adjacent reference plane.
H
W
Figure 108. Example 1 SMT Component Pad VSS/Reference Plane Void
Figure 109 shows an example of the VSS/Reference plane void for SMT pads for AC-coupling capacitors to
improve signal integrity. Recommend 0402 size for AC-coupling capacitors. The void is directly beneath the
pads of the components on the nearest/adjacent reference plane. Example dimensions for H = 60 mils and W =
35 mils. www.teknisi-indonesia.com
H
W
Figure 109. Example 2 SMT Component Pad VSS/Reference Plane Void

Figure 110 shows two USB 3.2 signal pairs in a USB-A connector for an example of a VSS/Reference plane
void that improves signal integrity. The void (or anti-pad) is directly beneath the connector on the nearest/
adjacent reference plane and on all layers where an anti-pad would go (all plane layers or layers where there is
just a plane shape that covers both PTHs). There are four USB 3.2 signal pairs in a USB-A connector that need
this VSS/Reference Plane void.
Figure 110. Example USB-A Connector VSS/Reference Plane Void

Figure 111 shows one USB 3.2 signal pair in a USB-C® connector for an example of a VSS/Reference plane
void that improves signal integrity. The void (or anti-pad) is directly beneath the connector on the nearest/
adjacent reference plane and on all layers where an anti-pad would go (all plane layers or layers where there is
just a plane shape that covers both PTHs). There are four USB 3.2 signal pairs in a USB-C connector that need
this VSS/Reference Plane void.
W
H
Figure 111. Example 1 USB-C® Connector VSS/Reference Plane Void
Figure 112 shows one USB 3.2 signal pair VSS/Reference plane void in a USB-C connector that improves signal
integrity. The void is directly beneath the connector on the nearest/adjacent reference plane. Example
dimensions for H = 31 mils and W = 46.06 mils.
W
H
Figure 112. Example 2 USB-C® Connector VSS/Reference Plane Void

Figure 113 shows an example of a USB ESD device VSS/Reference plane void that improves signal integrity.
The void is directly beneath the signal pins on the nearest/adjacent reference plane.
W
H
Figure 113. Example 1 USB ESD Device VSS/Reference Plane Void
Figure 114 shows an example of a USB ESD device VSS/Reference plane void that improves signal integrity.
The void is directly beneath the signal pins on the nearest/adjacent reference plane. Example dimensions for H =
61.44 mils and W = 45.21 mils.
W
H
Figure 114. Example 2 USB ESD Device VSS/Reference Plane Void

Figure 115 shows an example of a USB differential signal pair with VSS vias that improves signal integrity. It is
strongly recommended to use balanced ground vias (vias aligned so that a horizontal line could be drawn
intersecting the center of all four vias) to reduce introduction of common-mode noise. The distance from the
GND to signal vias (shown in the figure as dimension "a") must remain symmetrical. Example dimension for "a"
= 30 mils.
a
a
GND Vias Signal Vias
Figure 115. Example 1 USB Differential Signal Pair Void and VSS Vias
Figure 116 shows an example of a USB differential signal pair void that improves signal integrity.
Overlap Antipad Voids

for
Differential Signal Pairs
For Vias and Plated Through-Holes on
USB Single and Dual Stacked Connectors
Figure 116. Example 2 USB Differential Signal Pair Void

8.1.5 USB 2.0 Interface

Figure 117 depicts the schematic and layout requirements for the USB 2.0 interface.
APU
LMAX_FP
LCHOKE
Front Panel
Header
USBn_DP ESD D+
LPCB_WP_SKEW
USBn_DN Clamp D-
No trace stubs CESD

in these areas.
LMAX_CONN
USB-A
Connector
USBn_DP ESD D+
USBn_DN Clamp D-
www.teknisi-indonesia.com CESD
Figure 117. USB 2.0 Interface—Schematic and Routing Model
• Common-mode chokes are suggested but not required for all USB D+ and D− signals. Alternatively, a 0Ω
resistor pad can be used.
• ESD-suppression devices that will adequately protect the USB interfaces are required on the D+ and D−
signals. AMD requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134.
• Place the ESD devices as close as possible to the USB connector, but no farther than 12.7 mm.
• If the ESD device has a power pin, decouple it with one 470-nF capacitor or with a capacitor value specified
by the device manufacturer.
USB 2.0 Routing and Length-Matching Rules
Table 90 lists the routing and length-matching rules for the USB 2.0 interface.
Table 90. Routing Rules for USB 2.0 Interface
USBn_DP Cumulative trace length encroaching plane-edge rule ≤ 2.54 mm

USBn_DN
Length TPCB_WP_SKEW: Difference between true and complement traces in a differential ≤ 9 ps
Matching pair

Table 90. Routing Rules for USB 2.0 Interface (continued)

Minimum trace length 0 mm
USBn_DP LMAX_CONN: Maximum trace length to connector ≤ 457.2 mm

Length Limits
USBn_DN LMAX_FP: Maximum trace length to front panel connector ≤ 152.4 mm
LCHOKE: Maximum trace length to common-mode choke from connector ≤ 25.4 mm
Note: 1. Unless specified otherwise, all lengths are electrical lengths instead of physical lengths.
2. All unused USB lanes are kept unconnected.
3. No stubs are allowed when connecting common-mode choke bypass resistors and ESD devices.

Bus Channel Pin Field
Signals Rule Breakout
µS SL µS SL
Max Layer Changes 3
Plane Split 0 0 0
Crossings
ZOD ≥ 0.1/ 0.1/0.1 mm 90Ω ± 10% 90Ω ± 10%
Trace Spacing ≥ 0.1 mm ≥ 4H ≥ 3H ≥ 4H ≥ 3H

(LMAX ≤ 127 mm)
USBn_DP
USBn_DN ≥ 5H
Trace Spacing
(LMAX >127 mm)
Trace Spacing
(3 traces between 2
0.1 mm
length ≤ 2.54 mm
N/A 0.1 mm
length ≤ 2.54 mm
vias/pins)
Self Spacing Not Permitted

(serpentine)

8.1.6 USB 3.2 Interface

Figure 118 illustrates the routing model for the USB 3.2 interface.
APU
LMAX_A_CONN
USB-A
Connector
TX CCOUPLING
LPCB_WP_SKEW
USBn_TXP ESD TX_D+
USBn_TXN Clamp TX_D-
Reference plane cut-out
No trace stubs in these areas. CESD
RX CCOUPLING
USBn_RXP ESD RX_D+
USBn_RXN Clamp RX_D-

CESD
LMAX_A_CONN USB-A
Connector
USBn_TXP www.teknisi-indonesia.com
TX C COUPLING
ESD TX_D+
CESD
No trace stubs in these areas.
USBn_RXP ESD RX_D+

RX CCOUPLING
CESD
Figure 118. USB 3.2 Interface—Schematic and Routing Model
Figure 119 illustrates the routing model for a retimer/redriver on the USB 3.2 interface.

LMAX_RETIMER/REDRIVER_CONN
APU
LMIN/MAX_SIG_CONDITIONER
USB-A
Reference plane cut-out Connector
LPCB_WP_SKEW
USBn_TXP ESD TX_D+
TX CCOUPLING Retimer/ No trace

Redriver stubs in
Signal
CESD
these
Conditioner areas.
RX CCOUPLING
USBn_RXP ESD RX_D+
CESD
LMAX_RETIMER/REDRIVER_CONN USB-A
Connector
TX CCOUPLING
USBn_TXP ESD TX_D+

Retimer/ No trace
Redriver stubs in
Signal CESD
these
RX C COUPLING Conditioner areas.
USBn_RXP ESD RX_D+
CESD
Figure 119. USB 3.2 Interface with Retimer/Redriver—Schematic and Routing Model
All USB signal pairs are routed point to point and reference the VSS plane (preferred) or any other power plane.
Note: When a Retimer or Redriver is used:
• Any ESD device required between the retimer/redriver and connector must be specified by the
processor.
redriver vendor.
• The maximum trace length between the processor and retimer/redriver must be specified by the
retimer/ redriver vendor.

USB 3.2 channels can be routed to a dual connector or single connectors. Leave any unused USB channels
unconnected. Leave unused USB_OC[n:0]_L pins unconnected or used for an alternative function (see complete
signal names).
FP6 processors have internal muxes for DisplayPort and USB 3.2 G2 (10Gbps) and can support up to two USB-
C® connectors. See DisplayPort DP Alt Mode/USB-C Layout Guidelines for USB-C connector routing rules and
information.
It is preferred to route RX and TX pairs on different layers for USB 3.2 signals. If routing RX and TX pairs on
the same layer is unavoidable, then interleave RX and TX pairs so that no RX pair is adjacent to two TX pairs
and no TX pair is adjacent to two RX pairs. For example, RX/RX/TX/TX/RX/RX/TX/TX is permitted. Avoid
TX/RX/TX/RX/TX/RX/TX/RX. 7H spacing between TX and RX pairs must be met.
• ESD-suppression devices that will adequately protect the USB interfaces are required on the TX and RX
signals.
• Place the ESD devices as close as possible to the USB connector, but no farther than 12.7 mm.
by the component manufacturer.
The USB 3.2 interface requires AC-coupling capacitors between the transmitter of one device and the receiver of
another device.
• Acceptable spacing between pairs of capacitors is strongly recommended.
• Reference plane cutout for AC-coupling capacitors is required for USB 3.2 G2 (10Gbps) ports and
recommended for USB 3.2 G1 (5Gbps) ports.
Figure 120 illustrates placement of AC-coupling capacitors near external connectors. A dual USB 3.2 G1
(5Gbps) connector is used as an example; however, the use of two separate connectors is also acceptable. Table
91 contains the recommended distances for the coupling components.
LCoupling
Dual USB 3.2
Connector Processor
USB_SS_TX USB_SS_TXnN/P
USB_SS_RX LCoupling USB_SS_RXnN/P
USB_SS_TX USB_SS_TXnN/P
USB_SS_RX USB_SS_RXnN/P
LOther_Via
Reference plane LOther_Cap

cut-out for
LMisaligned
AC-coupling
capacitors
Figure 120. USB 3.2 AC-Coupling Capacitor Placement

Table 91. Recommended AC-Coupling Capacitor Placement

LCoupling1 LOther_Via LOther_Cap2 LMisaligned3
≥ 12.7 mm ≥ 1.905 mm ≥ 2.54 mm < 0.889 mm
Note: 1. LCoupling: Minimum physical distance from processor or connector pin to AC-coupling capacitor pin. If the reference plane under the AC-
coupling capacitor is voided, then the rule can be relaxed to 7.62 mm to ease placement requirements.
2. LOther_Cap: Minimum physical distance separating AC-coupling capacitor pads.
3. LMisaligned: Maximum allowed misalignment of AC-coupling capacitors within a differential pair. This applies to physical placement
mismatch.
Table 92 shows the AC-coupling capacitor component requirements for USB 3.2 interfaces.
Table 92. Component Table—USB 3.2 Interface

Reference Value Tolerance Package Component Requirements
TXCCOUPLING 220 nF 10% 0402 X5R Dielectric.
RXCCOUPLING 330 nF 10% 0402 X5R Dielectric.

USB 3.2 Routing and Length-Matching Rules

Table 93 lists the routing and length-matching rules for the USB 3.2 interface.
Table 93. Routing Rules for USB 3.2 Interface
µS SL
USB Port 0 Cumulative trace length encroaching plane-edge rule ≤ 2.54 mm

USB0_TXP/N Length TPCB_WP_SKEW: Difference between true and complement ≤ 0.9 ps
USB0_RXP/N Matching traces in a differential pair
USB Port 1 Length Limits LMIN/MAX_SIG_CONDITIONER: USB3.2 maximum trace Implementation
USB1_TXP/N dependent
length to Retimer/Redriver signal conditioner:
USB1_RXP/N
LMAX_A_CONN: USB3.2 G1 (5Gbps) maximum trace ≤ 304.8 mm

USB Port 4
USB4_TXP/N length to USB-A connector:
USB4_RXP/N
LMAX_C_CONN: USB3.2 G1 (5Gbps) maximum trace ≤ 177.8 mm
USB Port 5 length to USB-C® connector:
USB5_TXP/N
USB5_RXP/N ≤ 152.4 mm
LMAX_A_or_C_CONN: USB3.2 G2 (10Gbps) maximum trace
length to USB-A or USB-C connector:
3. No stubs are allowed when connecting ESD devices.
µS SL µS SL
Max Layer Changes Maximum of 2 vias per signal are allowed. The signal via must have very low-parasitic capacitance
to minimize signal-integrity issues. Use an equal number of vias on signals in each pair.
USB Port 0 Plane Split 0 0 0

USB0_TXP/N Crossings
USB0_RXP/N
ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%
USB Port 1
Trace Spacing ≥ 0.3 mm TX to TX TX to TX or ≥ 7H ≥ 5H
USB1_TXP/N
or RX to RX RX to RX
USB1_RXP/N
≥ 7H ≥ 5H
USB Port 4
USB4_TXP/N TX to RX TX to RX
USB4_RXP/N ≥ 10H ≥ 7H
USB Port 5 N/A

USB5_TXP/N Trace Spacing 0.1 mm 0.1 mm
USB5_RXP/N (3 traces between length ≤ 2.54 mm length ≤ 2.54 mm
2 vias/pins)
Self Spacing N/A

(serpentine)

9 DisplayPort Alternate Mode/USB to USB-C® Connector

Design Guidelines
DP Alt Mode/USB Controller to USB-C® Port Mapping
Use the following ports when designing a FP6 processor-based platform to support USB-C:
• FP6 processor—DisplayPort 2 and USB Port 0 are internally muxed to support USB-C
• FP6 processor—DisplayPort 3 and USB port 4 are internally muxed to support USB-C
Note: Please note that the USB-C mux programming model has changed for FP6. Ensure your USB-PD
controller follows the correct programming model. Contact your AMD representative for details.
Figure 121 shows the FP6 processor DisplayPort and USB controller to port mapping that includes two internal
muxes to support DisplayPort and USB on USB-C connectors. To ensure proper synchronization of the USB-PD
controller and the APU Mux control logic during an APU reset sequence, connect RESET_L to the USB-PD
controller through a level shifter appropriate for the USB-PD controller I/O.
DP Alt Mode/USB Controller Port Mapping to USB-C® Connector
APU
USB Controller 0 USB Controller 1 DP Controller

USB 3.2 G2 USB 2.0 USB 3.2 G2 USB 2.0
(10Gbps) (10Gbps)
HCP HCP HCP HCP DP2 DP3
MUX MUX
TX/RX[1]
TX/RX[1]
TX/RX[2]
TX/RX[2]
IP0 IP4 I2C RESET_L

RESET_L
USBC_I2C_SCL/SDA
USBC0_RX1P/N/DP2_TXP/N[3]
DP2_AUXP/N
USBC0_TX1P/N/DP2_TXP/N[2]
DP3_AUXP/N
USBC0_DP/N
USBC4_DP/N
Level
Shifter
USB-PD
External Controller DP2_HPD
Mux GPIO(s)
External DP3_HPD
Mux
SBU1/SBU2
SBU1/SBU2
USB-C USB-C
C0 C4 CC1/CC2
CC1/CC2
USB-C® Port 0 USB-C Port 4
Figure 121. FP6 Processor—DP Alt Mode/USB Controller to Port Mapping—USB-C® Connector
DisplayPort Alternate Mode/USB to USB-C® Connector Design Guidelines 187

Table 94 lists the DP/USB signal to port mapping:
Table 94. FP6 Platform—DP Alt Mode/USB Signal to Port Mapping

Signals DisplayPort/USB Port DisplayPort/USB Protocols
USBC0_RX1P/N/DP2_TXP/N[3] DisplayPort2 DisplayPort

USBC0_TX1P/N/DP2_TXP/N[2] USB Port 0 USB 3.2 G2 (10Gbps)
USBC0_TX2P/N/DP2_TXP/N[1] USB 2.0
DP2_AUXP/N
DP2_HPD1
USBC0_DP
USBC0_DN
USBC4_RX1P/N/DP3_TXP/N[3] DisplayPort3 DisplayPort

USBC4_TX1P/N/DP3_TXP/N[2] USB Port 4 USB 3.2 G2 (10Gbps)
USBC4_TX2P/N/DP3_TXP/N[1] USB 2.0
DP3_AUXP/N
DP3_HPD1
USBC4_DP
USBC4_DN
Note: 1. DP2_HPD and DP3_HPD cannot be driven high when VDD_33 is not up.
9.1 DisplayPort/USB AC-Coupling Capacitors and ESD Device Placement

DisplayPort interface and USB3.2 transmit signals require series AC-coupling capacitors between the transmitter
of one device and the receiver of another device.
• AC-coupling capacitors must be placed as pairs with fairly uniform placement.
• If staggering is not possible, capacitor pairs must be of sufficient spacing between pairs.
• For via spacing, if the board thickness is ≤ 1.27 mm, use 1.2X board thickness.
• Reference plane cut-out for AC-coupling capacitors is required for USB 3.2 G2 (10Gbps) ports and
recommended for USB 3.2 G1 (5Gbps) ports.
Figure 122 illustrates placement of AC-coupling capacitors and ESD devices near external connectors. Table 95
shows the recommended distances for the AC-coupling capacitors and ESD devices.
188 DisplayPort Alternate Mode/USB to USB-C® Connector Design Guidelines

LCoupling
LESD LConsecutive_Vias
4
RX
4
4
4
APU
ESD
4
TX
4
4
4
4
4
Microstrip
Aligned
Within Pair
4
4 Stagger the
4 Capacitor Pairs
4 Misaligned
Within Pair
4
4 LMisaligned
LESD 4 LCoupling
4
TX
4
APU
4
4
4
ESD
RX
4
4
4
4
4
Stripline
Important Lengths
LMisaligned
LOther_Via LOther_Via
4
LOther_Cap
4
LConsecutive_Vias
4 LESD
www.teknisi-indonesia.com4 LCoupling
Figure 122. DisplayPort/USB AC-Coupling Capacitor and ESD Device Placement
Table 95. Recommended AC-Coupling Capacitor and ESD Device Placement

LMisaligned LOther_Via LOther_Cap LConsecutive_Vias LESD LCoupling
< 0.889 mm ≥ 1.905 mm ≥ 2.54 mm ≥ 12.7 mm ≥ 12.7 mm ≥ 12.7 mm
• LMisaligned: Maximum allowed misalignment of AC-coupling capacitors within a differential pair. This applies
to physical placement as well as electrical distance, that is, trace mismatch.
the same net.
• LESD: Minimum electrical distance of ESD device pads from connector pin. If the reference plane under the
ESD device is voided, then the rule can be relaxed down to 7.62 mm to ease placement requirements.
• LCoupling: Minimum electrical distance of AC-coupling capacitors from ESD device (if applicable) or from
pins sourcing the signal. If the reference plane under the coupling capacitor is voided, then the rule can be
relaxed to 7.62 mm to ease placement requirements.

9.2 DisplayPort DP Alt Mode/USB-C® Layout Guidelines

• FP6 processors provide two internal MUXes for MUXing DisplayPort 2 /USB 3.2 G2 (10Gbps) Port 0 to a
USB-C® connector and DisplayPort 3 /USB 3.2 G2 (10Gbps) Port 4 to a USB-C connector.
Figure 123 illustrates a schematic diagram for a multiplexed DisplayPort/USB3.2 G2 (10Gbps) interface and the
USB 2.0 signals used for connecting to a USB-C connector. AC-coupling capacitors are used on DP AUX and
USB 3.2 G2 (10Gbps) TX signals. DisplayPort 2 / USB Port 0 is shown. DisplayPort 3 / USB Port 4 can be
connected in a similar way.
Processor
(USB-C® Mode) LMAX_C_CONN USB-C
Connector
RX Ccoupling DESD
USBC0_RX2P/DP2_TXP[0] A11 (RX2+)
RX Ccoupling
USBC0_RX2N/DP2_TXN[0] A10 (RX2-)

TX Ccoupling
USBC0_TX2P/DP2_TXP[1] B2 (TX2+)
TX Ccoupling
USBC0_TX2N/DP2_TXN[1] B3 (TX2-)
TX Ccoupling
USBC0_TX1P/USB0_TXP/DP2_TXP[2] A2 (TX1+)
TX Ccoupling
USBC0_TX1N/USB0_TXN/DP2_TXN[2] A3 (TX1-)
RX Ccoupling
USBC0_RX1P/USB0_RXP/DP2_TXP[3] B11 (RX1+)
RX Ccoupling
USBC0_RX1N/USB0_RXN/DP2_TXN[3] B10 (RX1-)
RAUXPU
External
DP2_AUXN B8 (SBU2)
Mux
DP2_AUXP A8 (SBU1)
RPU RPU
RAUXPD
DP2_HPD USB PD
USBC_I2C_SCL Controller A5 (CC1)
USBC_I2C_SDA B5 (CC2)
Level GPIO(s) LCHOKE
RESET_L Shifter
A6 (D+)
USBC0_DP B6 (D+)
ESD
Clamp
USBC0_DN A7 (D-)
B7 (D-)
CESD
Figure 123. Schematic Diagram—DisplayPort/USB to USB-C® Connector
Figure 124 illustrates a schematic diagram for a multiplexed DisplayPort/USB 3.2 G2 (10Gbps) interface and the
USB 2.0 signals with a retimer/redriver signal conditioning device used for connecting to a USB-C connector.
AC-coupling capacitors are used on DP MainLink, AUX, and USB 3.2 G2 (10Gbps) TX/RX signals.
DisplayPort 2 / USB Port 0 is shown.
DisplayPort 3 / USB Port 4 can be connected in a similar way.

Processor LMIN/MAX_SIG_CONDITIONER
(USB-C® Mode) USB-C
Connector
RX Ccoupling DESD
USBC0_RX2P/DP2_TXP[0] A11 (RX2+)
RX Ccoupling
USBC0_RX2N/DP2_TXN[0] A10 (RX2-)
TX Ccoupling
USBC0_TX2P/DP2_TXP[1] B2 (TX2+)
TX Ccoupling
USBC0_TX2N/DP2_TXN[1] B3 (TX2-)
TX Ccoupling
USBC0_TX1P/USB0_TXP/DP2_TXP[2] A2 (TX1+)
TX Ccoupling Retimer/
Redriver A3 (TX1-)
USBC0_TX1N/USB0_TXN/DP2_TXN[2] Signal
RX Ccoupling
Conditioner B11 (RX1+)
USBC0_RX1P/USB0_RXP/DP2_TXP[3]
RX Ccoupling
USBC0_RX1N/USB0_RXN/DP2_TXN[3] B10 (RX1-)
RAUXPU
DP2_AUXN B8 (SBU2)
DP2_AUXP A8 (SBU1)
RPU I2C
RPU
RAUXPD
DP2_HPD USB PD
USBC_I2C_SCL Controller A5 (CC1)
USBC_I2C_SDA B5 (CC2)
Level 2
IC LCHOKE
RESET_L Shifter
A6 (D+)
USBC0_DP B6 (D+)
ESD
Clamp
USBC0_DN A7 (D-)
B7 (D-)
CESD
Figure 124. Schematic Diagram—DisplayPort/USB with Retimer/Redriver to USB-C® Connector
All DP/USB signal pairs are routed point to point and reference the VSS plane (preferred) or any other power
plane.
Note: When a Retimer or Redriver is used:
• Any ESD device required between the retimer/redriver and connector must be specified by the
processor.
redriver vendor.
• The maximum trace length between the processor and retimer/redriver must be specified by the
retimer/ redriver vendor.
It is preferred to route RX and TX pairs on different layers for USB 3.2 signals. If routing RX and TX pairs on
the same layer is unavoidable, then interleave RX and TX pairs so that no RX pair is adjacent to two TX pairs
and no TX pair is adjacent to two RX pairs. For example, RX/RX/TX/TX/RX/RX/TX/TX is permitted. Avoid
TX/RX/TX/RX/TX/RX/TX/RX.

• ESD-suppression devices are required on the TX and RX signals. AMD requires low capacitive-loading / low
insertion loss ESD-suppression devices on the DP/USB 3.2 signals. Use low capacitive-loading ESD-
suppression devices for USB 2.0 signals.
by the component manufacturer.
Components for DisplayPort/USB to USB-C® connector are listed in Table 96.
Table 96. Component Table—DisplayPort/USB to USB-C® Connector

TXCCOUPLING 220 nF 10% 0402 Recommended value: 220 nF

Place as pairs1, 2
RXCCOUPLING 330 nF 10% 0402 Recommended value: 330 nF

Place as pairs1, 2
DESD3 See Table 134 – – AMD requires low insertion loss, low capacitive-loading ESD-
suppression devices. See Table 134. See DisplayPort/USB AC-
Coupling Capacitors and ESD Device Placement for device
placement details.
D*ESD - – – See retimer/redriver vendor datasheet for ESD device

requirements.
ESD Clamp3 - - - AMD requires low insertion loss, low capacitive-loading ESD-
suppression devices. See Table 134.
RPU
RAUXPU
4.7 kΩ
100 kΩ
5%
5%
0402
0402
Pull-up resistor to VDD_18_S5
Pull-up resistor to VDD_33
RAUXPD 100 kΩ 5% 0402 Pull-down resistor to VSS
Note: 1. Placing AC-coupling capacitors as pairs requires traces to be length matched. See DisplayPort/USB AC-Coupling Capacitors and ESD
Device Placement for details on component placement. AC-coupling capacitor values between retimer/redriver and connector are
specified by the retimer/redriver vendor.
Table 97 lists the DP2/USB port 0 connections from the FP6 processor to a USB-C connector. DP3/USB Port 4
can be connected similarly for FP6 processors.
Table 97. DisplayPort/USB Signals to USB-C® Connector

®
Processor Signal Name USB-C Connector Processor Signal Name
VSS A1 GND GND B12 VSS
USBC0_TX1P/USB0_TXP/DP2_TXP[2] A2 TX1+ RX1+ B11 USBC0_RX1P/USB0_RXP/DP2_TXP[3]
USBC0_TX1N/USB0_TXN/DP2_TXN[2] A3 TX1- RX1- B10 USBC0_RX1N/USB0_RXN/DP2_TXN[3]
VBUS A4 VBUS VBUS B9 VBUS
USBC_SS+_CONN0_CC11 A5 CC1 SBU2 B8 DP2_AUXN_MUX2
USBC0_DP_CHOKE3 A6 D+ D- B7 USBC0_DN_CHOKE3

Table 97. DisplayPort/USB Signals to USB-C® Connector (continued)

®
Processor Signal Name USB-C Connector Processor Signal Name
USBC0_DN_CHOKE3 A7 D- D+ B6 USBC0_DP_CHOKE3
DP2_AUXP_MUX2 A8 SBU1 CC2 B5 USBC_SS+_CONN0_CC21
VBUS A9 VBUS VBUS B4 VBUS
USBC0_RX2N/DP2_TXN[0] A10 RX2- TX2- B3 USBC0_TX2N/DP2_TXN[1]
USBC0_RX2P/DP2_TXP[0] A11 RX2+ TX2+ B2 USBC0_TX2P/DP2_TXP[1]
VSS A12 GND GND B1 VSS
Note: 1. Connects to a USB PD Controller. Not connected directly to the processor.

2. Connects to an external mux. Not connected directly to the processor.
3. Connects USB 2.0 through a choke. Not connected directly to the processor.

DP Alt Mode/USB 3.2 to USB-C® Connector Routing and Length-Matching Rules

Table 98 lists the routing and length-matching rules for DP Alt Mode/USB 3.2 and USB 2.0 to USB-C®
connector.
Table 98. Routing Rules for DP Alt Mode/USB to USB-C® Connector
µS SL
DP2 Alt Mode/USB Port 0 Plane Edge Trace spacing from reference-plane edge ≥ 5H
USBC0_RX2P/DP2_TXP[0] Cumulative trace length encroaching plane-edge rule ≤ 2.54 mm
DP2_AUXP
DP2_AUXN
DP2_HPD
USBC0_DP
USBC0_DN
DP3 Alt Mode/USB Port 4

DP3_AUXP
DP3_AUXN
DP3_HPD
USBC4_DP
USBC4_DN
DP2 Alt Mode/USB3.2 Port 0 Device Spacing Minimum distance between connector pin and via to the ≥ 6.35 mm
USBC0_RX2P/DP2_TXP[0] connector (if through-hole connector is used and trace is
USBC0_RX2N/DP2_TXN[0] routed on top layer) is:
USBC0_TX2P/DP2_TXP[1] Length TPCB_WP_SKEW: Difference between true and complement ≤ 0.50 ps
USBC0_TX2N/DP2_TXN[1] Matching traces in a differential pair
USBC0_TX1N/USB0_TXN/DP2_TXN[2] LMAX_C_CONN: DP HBR2/USB3.2 G1 (5Gbps) maximum ≤ 177.8 mm
®
USBC0_RX1P/USB0_RXP/DP2_TXP[3] trace length to USB-C connector:
DP2_AUXP LMAX_C_CONN: DP HBR3/USB3.2 G2 (10Gbps) ≤ 152.4 ≤ 139.7
DP2_AUXN maximum trace length to USB-C connector: mm mm
Length Limits
DP3 Alt Mode/USB3.2 Port 4


Table 98. Routing Rules for DP Alt Mode/USB to USB-C® Connector (continued)
µS SL
USBC4_TX2N/DP3_TXN[1] LMIN/MAX_SIG_CONDITIONER: DP/USB3.2 maximum trace Implementation

USBC4_TX1P/USB4_TXP/DP3_TXP[2] length to Retimer/Redriver signal conditioner: dependent
USBC4_RX1P/USB4_RXP/DP3_TXP[3] Length Limits
DP3_AUXP
DP3_AUXN
Length TPCB_WP_SKEW: Difference between true and complement ≤ 9.0 ps

USB2.0 Port 0
Matching traces in a differential pair
USBC0_DP
USBC0_DN LMAX_C_CONN: USB2.0 maximum trace length to USB-C ≤ 457.2 mm
connector:
USB2.0 Port 4 Length Limits
USBC4_DP LCHOKE: USB2.0 maximum trace length to common-mode ≤ 25.4 mm
USBC4_DN choke from USB-C connector
3. No stubs are allowed when connecting ESD devices.
Signals
www.teknisi-indonesia.com Rule Breakout
µS SL µS SL
DP2 Alt Mode/USB Port 0 Max Layer Changes Maximum of 2 vias per signal are allowed. The signal via must have very low-
USBC0_RX2P/DP2_TXP[0] parasitic capacitance to minimize signal-integrity issues. Use an equal number
USBC0_RX2N/DP2_TXN[0] of vias on signals in each pair. DP AUX and DP HPD signals can have 4
USBC0_TX2P/DP2_TXP[1] maximum.
USBC0_TX2N/DP2_TXN[1] Test Points Not Permitted
USBC0_TX1N/USB0_TXN/DP2_TXN[2] Plane Split 0 0 0
USBC0_RX1P/USB0_RXP/DP2_TXP[3] Crossings
Trace Spacing 0.1 mm N/A 0.1 mm
DP2_AUXP
DP2_AUXN (3 traces between length ≤ 2.54 mm length ≤ 2.54 mm
DP2_HPD 2 vias/pins)
USBC0_DP
USBC0_DN
DP3 Alt Mode/USB Port 4

DP3_AUXP

µS SL µS SL
DP3_AUXN Self Spacing Not Allowed, except DP AUX signals can have ≥ 7H serpentine spacing in the
DP3_HPD (serpentine) channel.
USBC4_DP
USBC4_DN
DP2 Alt Mode/USB3.2 Port 0 ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%
DP2_AUXP
DP2_AUXN

DP3_AUXP
DP3_AUXN
DP2 Alt Mode/USB3.2 Port 0 Trace Spacing ≥ 0.3 mm USB3.2 ≥ 5H ≥ 7H ≥ 5H

USBC0_RX2P/DP2_TXP[0] G1
USBC0_RX2N/DP2_TXN[0] (5Gbps)
USBC0_TX2P/DP2_TXP[1] ≥ 7H
USBC0_TX1P/USB0_TXP/DP2_TXP[2] USB3.2
USBC0_TX1N/USB0_TXN/DP2_TXN[2] G2
USBC0_RX1P/USB0_RXP/DP2_TXP[3] (10Gbps)
USBC0_RX1N/USB0_RXN/DP2_TXN[3] ≥ 9H


µS SL µS SL
DP2 Alt Mode/USB3.2 Port 0 Trace Spacing ≥ 0.3 mm ≥ 4H ≥ 3H ≥ 0.3 mm

DP2_AUXP
DP2_AUXN

DP3_AUXP
DP3_AUXN
DP2 Alt Mode/USB3.2 Port 0 ZO ≥ 0.1 mm ≥ 0.1 mm ≥ 0.1 mm

DP2_HPD Trace Spacing ≥ 0.1 mm ≥ 3H ≥ 0.3 mm

DP3_HPD
USB2.0 Port 0 ZOD ≥ 0.1/ 0.1/0.1 mm 90Ω ± 10% 90Ω ± 10%

USBC0_DP ≥ 0.1 mm ≥ 4H ≥ 3H ≥ 4H ≥ 3H
Trace Spacing
USBC0_DN
LMAX ≤ 127 mm
USB2.0 Port 4
Trace Spacing ≥ 5H ≥ 5H
USBC4_DP
USBC4_DN LMAX > 127 mm

10 SATA Interface Design Guidelines

10.1 SATA Technology Overview
The Serial ATA (SATA) interface connects to SATA compliant devices.
The processor supports the following SATA transfer rates:
• Internal SATA (iSATA):
• First Generation (1.5 Gbit/s)
• Second Generation (3.0 Gbit/s)
• Third Generation (6.0 Gbit/s)
• External SATA (eSATA):
• First Generation (1.5 Gbit/s)
• Second Generation (3.0 Gbit/s)
SATA devices automatically negotiate the highest transfer rate supported on detection.
The processor supports up to four SATA channels. The SATA interface comprises two signal groups, TX/RX
and Miscellaneous.
This section is organized as follows:
• Definition of the Miscellaneous signal group.
• Definition of AC coupling components along with schematic and layout rules.
• Definition of the TX/RX signal group along with schematic and layout rules.
10.1.1 SATA Miscellaneous Signals
SATA miscellaneous signals provide support for various functions as defined below.
• SATA_ZP0_L and SATA_ZP1_L: Zero power ODD (SATA_ZP0_L/SATA_ZP1_L) function is not
supported by these pins. Please refer to Zero Power Optical Disk Drive Platform Implementation and Design
Requirements, order# 49277 for details regarding implementing the Zero power ODD function on the
platform.
• DEVSLP[1:0]: I/O that supports DevSleep. DevSleep feature helps reduce power consumption of SATA
devices. DevSleep supports Always On Always Connected functionality. DevSleep defines the lowest power
state for SATA technology allowing the PHY and other circuitry to be completely powered off. If unused,
enable internal pull-up or pull-down resistor by software.
• If SATA Port 0 connects to an HDD device, connect the APU DEVSLP[0] pin to the SATA connector
DEVSLP pin. No onboard pull-up resistor is needed.
Note: This connection is not needed for SATA ports connected to an ATAPI device.
• If SATA Port 1 connects to an HDD device, connect the APU DEVSLP[1] pin to the SATA connector
DEVSLP pin. No onboard pull-up resistor is needed.
Note: This connection is not needed for SATA ports connected to an ATAPI device.
• FP6 supports four SATA ports but only two DEVSLP pins. DEVSLP[0] can be used for SATA Port 0 or
2. DEVSLP[1] can be used for SATA Port 1 or 3. Refer to the Processor Programming Reference (PPR)
Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA) for IOMUX and
SATA controller programming.

10.1.2 SATA AC-Coupled Bus

The SATA interface requires series AC-coupling capacitors between the transmitter of one device and the
receiver of another device. The actual distance of the capacitors from either end of the route is not critical. The
spacing relationship between capacitors is what is important. Follow these rules when placing the series AC-
coupling capacitors.
• Place pairs of capacitors in a staggered but fairly uniform pattern.
• If staggering is not possible, ensure that capacitor pairs still meet the LOther_Cap spacing rule.
Table 99 lists the AC-coupling capacitor specifications.
Table 99. Component Table—SATA Interface TX and RX Signals
Ref Value Tolerance Package Component Requirements
CCoupling 10 nF 10% 0402 Use of capacitor packs is not allowed.
Figure 125 illustrates the AC-coupling capacitor placement guidance. Table 100 specifies the spacing rules.
Capacitor Pairs are Staggered
RX TX
TX RX
Processor
LCoupling
LMisaligned
LOther_Cap
Stripline
Figure 125. SATA AC-Coupling Capacitor Placement
Table 100. Recommended AC-Coupling Capacitor Placement

LMisaligned1 LOther_Cap2 LCoupling3
< 0.635 mm ≥ 2.54 mm ≥ 12.7 mm
SATA Interface Design Guidelines 199

Table 100. Recommended AC-Coupling Capacitor Placement (continued)

LMisaligned1 LOther_Cap2 LCoupling3
Note: 1. LMisaligned: Maximum allowed misalignment of AC-coupling capacitors within a differential pair. This applies to physical placement
mismatch.
2. LOther_Cap: Minimum physical distance separating AC-coupling capacitor pads. Measured from edges of the closest footprint pads.
3. LCoupling: Minimum physical distance from processor or connector pin to AC-coupling capacitor pin. If the reference plane under the
coupling capacitor is voided, then the rule can be relaxed to 7.62 mm to ease placement requirements.
10.1.3 SATA Interface

The SATA TX/RX signal group is comprised of the following signals:
• CHANNEL 0: SATA0_RXP, SATA0_RXN, SATA0_TXP, SATA0_TXN
All SATA signal pairs are routed point to point and reference the VSS plane (preferred) or any other power
plane. If a surface-mount SATA connector is used, no more than one layer change occurs along the entire route.
If two layer changes are absolutely necessary, place a VSS stitching via as close as possible, but no farther than
1.27 mm (50 mils) from the two signal layer-change vias.
Table 101 lists the routing and length-matching rules for the SATA interface.
Table 101. Routing Rules for SATA Interface
www.teknisi-indonesia.com Cumulative trace length encroaching plane-edge rule ≤ 2.54 mm
Length Matching SKEWWITHIN_PAIR: Difference between true and ≤ 0.75 ps

complement traces in a differential pair
Minimum trace length ≥ 0 mm
SATA (Gen3) LMAX: Maximum trace length to iSATA ≤ 152.4 mm

SATA0_RXP/N connector
SATA0_TXP/N
SATA1_RXP/N SATA (Gen2) LMAX: Maximum trace length to iSATA ≤ 203.2 mm
SATA1_TXP/N connector
SATA2_RXP/N
SATA2_TXP/N Mobile Direct SATA (Gen3) (i.e., no cables) LMAX: ≤ 177.8 mm
SATA3_RXP/N Maximum trace length to connector pin
SATA3_TXP/N
Mobile Direct SATA (Gen2) (i.e., no cables) LMAX: ≤ 254 mm
Length Limits
Maximum trace length to connector pin
eSATA (Gen2) LMAX: Maximum trace length ≤ 152.4 mm
SATA to re-driver LMAX: Maximum trace length to Implementation dependent

redriver pin
SATA (Gen3) to M.2 connector Direct-to-Drive (i.e., no ≤ 177.8 mm

cables) LMAX: Maximum trace length to connector pin
SATA_ZP0_L LMAX: Maximum trace length to termination resistor ≤ 25.4 mm

SATA_ZP1_L

Table 101. Routing Rules for SATA Interface (continued)

Note: • Unless specified otherwise, all lengths are electrical lengths instead of physical lengths.
• Connections to top-mounted Through-Hole connectors must be through the bottom microstrip layer.
• Interleave TX and RX pairs so that no RX pair is adjacent to two TX pairs.
• Use a SATA specification-compliant connector.
• No reference plane under mounting pads of AC-coupling capacitors.
• All unused SATA lanes are kept unconnected.
• If a redriver IC is used, trace lengths and impedance to any SATA connector meet the redriver IC vendor’s recommendation.
Table 101. Routing Rules for SATA Interface (continued)

µS SL µS SL
Max Layer Changes 1 via is preferred, but 1 more can be added with additional ground stitching vias - (2 max. vias
including Through-hole connector pin), 0 LC in the Bus Channel. Return loss margin is expected
to be reduced with additional vias.
Plane Split Crossings 0 0 0

SATA0_RXP/N
SATA0_TXP/N ZOD ≥ 0.1/ 0.1/0.1 mm 85Ω ± 10% 85Ω ± 10%
SATA1_RXP/N
SATA1_TXP/N Trace Spacing ≥ 0.1 mm ≥ 5H ≥ 5H
SATA2_RXP/N Trace Spacing (TX to ≥ 7H
SATA2_TXP/N RX)
SATA3_RXP/N
SATA3_TXP/N N/A
Trace Spacing 0.1 mm, 0.1 mm,
(3 traces between length ≤ 2.54 mm length ≤ 2.54 mm
2 vias/pins)
(serpentine)
10.1.3.1 SATA Mobile Design

Each SATA channel may be connected to an eSATA connector, an iSATA direct-to-drive connector, M.2
connector, a SATA redriver IC, a Docking Station connector, or it may be left unconnected. Redriver ICs are
used for applications requiring extended signal routes to a connector.
See PCIe and SATA to M.2 Connector Routing for SATA M.2 connector connectivity options.
Four SATA channels are available and the connectivity options are shown in Figure 126.
SATA Interface Design Guidelines 201

APU
SKEWWITHIN_PAIR CCOUPLING
SATAn_TXP TX+
SATAn_TXN TX- iSATA
Connector
SATAn_RXP RX+
SATAn_RXN RX-
iSATA Cable
iSATA Drive
CCOUPLING
SATAn_TXP TX+
Direct-to-Drive
SATAn_TXN
Connector
TX-
iSATA
LMAX iSATA Drive
SATAn_RXP RX+
SATAn_RXN RX-
DESD
CCOUPLING
SATAn_TXP TX+
SATAn_TXN TX- eSATA
Connector
SATAn_RXP RX+
SATAn_RXN RX-
eSATA Cable
eSATA
Drive
CCOUPLING eSATA Redriver

SATAn_TXP TX+
SATAn_TXN TX-
IC
SATAn_RXP RX+
SATAn_RXN RX-
eSATA Cable eSATA
eSATA Connector
Drive
CCOUPLING DESD
SATAn_TXP TX+
Docking Station
Connector
SATAn_TXN TX-
LMAX
SATAn_RXP RX+
SATAn_RXN RX-
Where n= 0 through 3
RX- RX+ TX- TX+
SKEWWITHIN_PAIR and LMAX rules apply to all examples. eSATA Drive SATA Redriver IC
or Connector
on Docking Station
Figure 126. SATA Mobile Routing Model
• ESD-suppression devices are on ESATA and external connector (Docking Station) TX and RX signals. AMD
requires low insertion loss, low capacitive-loading ESD-suppression devices. See Table 134.
• Place the ESD devices as close as possible to the connector, but no farther than 12.7 mm. If the reference
plane under the ESD component is voided, then the rule can be relaxed to 7.62 mm to ease placement
requirements.

11 Audio Interface Design Guidelines

11.1 HD Audio Interface Signals
The FP6 processor implements a High Definition Audio 1.0-compliant digital controller. Any CODEC attached
to the HD Audio interface must be HD Audio 1.0 compliant. FP6 processor designs can support multiple
CODEC configurations on a single board as long as all CODECs operate on the same voltage.
Figure 127 illustrates the schematic and layout requirement rules for HD Audio signals. Note that these
requirements cover a simple topology as found on many platforms. More complex topologies are also supported,
provided they follow the Layout Guidelines found in the High Definition Audio Specification.
All HD Audio signal pairs are routed point to point and reference the VSS plane (preferred) or any other power
plane.
APU
Speaker
Circuit
Motherboard
Audio CODEC
SPKR PC_BEEP
AZ_SDINn* SDIN*
AZ_SDOUT SDOUT
AZ_BITCLK BCLK
AZ_SYNC SYNC
AZ_RST RST#
HD Audio Header
or Connector
SDOUT
BCLK
SYNC
RST#
AZ_SDINn+1* SDIN*
(*) LCOMMON rule does not apply to these signals.

Follow CODEC vendor termination requirements.
Figure 127. HD Audio Interface—Schematic and Routing Mode
Table 102 shows routing rules for the HD Audio Interface.
Table 102. Routing Rules for HD Audio Interface

HDA Common Group Signals: Plane Edge Trace spacing from reference-plane edge ≥ 5H
AZ_RST_L Cumulative trace length encroaching plane- ≤ 2.54 mm

AZ_SYNC edge rule
AZ_SDIN0
AZ_SDIN1 Length Limits LCOMMON: Minimum trace length ≥ 38.1 mm
AZ_SDIN2
Audio Interface Design Guidelines 203

Table 102. Routing Rules for HD Audio Interface (continued)

AZ_SDOUT Length Limits LCOMMON: Maximum trace length ≤ 292.1 mm

AZ_BITCLK
Table 102. Routing Rules for HD Audio Interface (continued)

Pin Field
Signals Rule Breakout Bus Channel
µS SL
Max Layer Changes 3
Test Points Provide test points or other means to allow access for debug purposes
HDA Common Group Signals:
AZ_RST_L
AZ_SYNC ZO ≥ 0.1 mm 50Ω ± 10% 50Ω ± 10%
AZ_SDIN0 Trace Spacing ≥ 0.1 mm ≥ 3H ≥ 3H
AZ_SDIN1
AZ_SDIN2
Trace Spacing 0.1 mm, length ≤ 2.54 mm N/A 0.1 mm, length ≤ 2.54
(3 traces between mm
AZ_SDOUT
2 vias/pins)
AZ_BITCLK
Self Spacing N/A ≥ 5H N/A

(serpentine)

11.2 I2S Bus Audio Interface Signals

The processor implements an inter-IC sound (I2S) bus for digital audio. FP6 processor designs can support
multiple CODEC configurations on a single board as long as all CODECs operate on the same voltage.
Figure 128 illustrates the schematic and layout requirements rules for I2S bus signals. Table 103 lists component
requirements. Note that these requirements cover a simple topology as found on many platforms. More complex
topologies are also supported, provided they follow the Layout Guidelines found in the I2S Bus Specification.
All I2S Bus signal pairs are routed point to point and reference the VSS plane (preferred) or any other power
plane.
APU Motherboard
Audio CODEC
RIN
TDM_BCLK_MIC BCLK2
TDM_DATA_MIC SDOUT[0]
TDM_FRM_MIC LRCK2
RIN
TDM_BCLK_PLAYBACK BCLK1
TDM_FRM_PLAYBACK LRCK1
ROUT
TDM_DATA_PLAYBACK SDIN1
www.teknisi-indonesia.com WLAN/BT
Module
RIN
TDM_BCLK_BT BT_I2S_CLK
FCH_ACP_I2S_LRCLK_BT BT_I2S_WS
FCH_ACP_I2S_SDIN_BT BT_I2S_DOUT
ROUT
TDM_DOUT_BT BT_I2S_DIN
Figure 128. I2S Bus Interface—Schematic and Routing Mode
Table 103. Component Table—I2S Bus Audio Interface

Ref Value Tolerance Package Component Requirements
ROUT 22 to 33Ω 5% 0402 Specific value is CODEC/routing dependent
RIN 22 to 33Ω 5% 0402 Specific value is CODEC/routing dependent
Table 104 shows routing rules for the HD Audio Interface.
Table 104. Routing Rules for I2S Bus Audio Interface

I2S Bus Signals: Plane Edge Trace spacing from reference-plane edge ≥ 5H
TDM_BCLK_MIC Cumulative trace length encroaching plane-edge rule ≤ 2.54 mm

TDM_DATA_MIC
TDM_FRM_MIC Length Limits Minimum trace length ≥ 38.1 mm
TDM_BCLK_PLAYBACK

Table 104. Routing Rules for I2S Bus Audio Interface (continued)
TDM_DATA_PLAYBACK Length Limits Maximum trace length ≤ 292.1 mm

TDM_FRM_PLAYBACK
TDM_BCLK_BT
FCH_ACP_I2S_LRCLK_BT
FCH_ACP_I2S_SDIN_BT
TDM_DOUT_BT
Table 104. Routing Rules for I2S Bus Audio Interface (continued)
Signals Rule Breakout Bus Channel Pin Field
I2S Bus Signals: Max Layer Changes 3

TDM_BCLK_MIC Test Points Provide test points or other means to allow access for debug purposes
TDM_DATA_MIC
TDM_FRM_MIC Plane Split Crossings 0 0 0
TDM_BCLK_PLAYBACK
ZO 0.10 mm 50Ω ± 10% 50Ω ± 10%
TDM_DATA_PLAYBACK
TDM_FRM_PLAYBACK Trace Spacing ≥ 0.10 mm ≥ 3H ≥ 3H
TDM_BCLK_BT
FCH_ACP_I2S_LRCLK_BT Self Spacing N/A ≥ 3H N/A
FCH_ACP_I2S_SDIN_BT (serpentine)
TDM_DOUT_BT

11.3 Wake on Voice (WoV) Interface Signals

The FP6 processor supports Wake-on-Voice (WoV) that enables voice activation from a screen-off, lower power
state, to a screen-on full power state.
Figure 129 illustrates the schematic and layout requirement rules for WoV signals.
WoV CLK routes to all WoV mics. WoV data routes daisy chain from each left and right mic pair to the FP6
processor. Please refer to the DMIC component datasheet and specification for the right and left channel
definition to connect to the FP6 processor. Ensure right and left channels are not reversed.
APU
VDDIO_AUDIO
DMIC
ACP_WOV_MIC0_MIC1_DATA
DMIC
ACP_WOV_CLK DMIC
DMIC
DMIC
DMIC
Figure 129. WoV Interface—Schematic and Routing Mode
Table 105 shows routing rules for the WoV Interface.
Table 105. Routing Rules for WoV Interface


ACP_WOV_CLK Cumulative trace length encroaching plane- ≤ 2.54 mm
ACP_WOV_MIC0_MIC1_DATA edge rule
ACP_WOV_MIC4_MIC5_DATA Length Limits Minimum trace length ≥ 38.1 mm

Table 105. Routing Rules for WoV Interface (continued)

Pin Field
Signals Rule Breakout Bus Channel
µS SL
Max Layer Changes 3
Test Points Provide test points or other means to allow access for debug purposes
ZO ≥ 0.1 mm 50Ω ± 10% 50Ω ± 10%

ACP_WOV_CLK
ACP_WOV_MIC0_MIC1_DATA Trace Spacing ≥ 0.1 mm ≥ 3H ≥ 3H
ACP_WOV_MIC4_MIC5_DATA Trace Spacing 0.1 mm, length ≤ 2.54 mm N/A 0.1 mm, length ≤ 2.54
(3 traces between mm
2 vias/pins)
Self Spacing N/A ≥ 5H N/A

(serpentine)

12 Secure Biometric Camera Solution

12.1 Secure Biometrics Introduction
This chapter describes the requirements for the implementation of a Secure Biometric camera solution, on an
AMD Family 17h Models 60h-6Fh processor-based platform, that is compliant to Microsoft Modern Devices
Security.
12.2 Secure Biometrics Overview

Biometrics is the use of physical characteristics like fingerprint, face, Iris, etc. to authenticate user identity.
Microsoft uses fingerprint and or face biometrics for Windows “Hello”. Secure Biometrics is used to
“Authenticate and protect fresh raw biometric data using virtualization technologies” and then authenticate the
identity. Secure Biometrics hardens Windows “Hello” security. Windows Hello can be enabled with or without
Secure Biometrics.
Secure Biometrics is part of Microsoft Modern Devices Security. If a platform has a camera then the device has
to be Secure Bio compliant. Microsoft requires that USB host controllers used for a Secure Bio camera do not
serve any non-secure USB devices. The AMD Family 17h Models 60h-6Fh processor has two USB host
controllers with a balanced number of ports on each controller. The Secure Bio requirement would reduce the
number of available ports by half. To avoid the loss of available ports AMD will require the use of a discrete
USB host controller dedicated to the Secure Bio camera’s use.
12.3 Secure Biometrics Camera Solution Requirements

12.3.1 Secure Biometrics Camera Solution Overall Requirements
Refer to the Secure Biometrics requirements listed in the Windows Hardware Compatibility Specification in
section System.Fundamentals.Security.SecureBiometrics for the overall requirements.
12.3.2 Secure Biometrics Camera Requirements

Not all camera ISPs are supported by Microsoft for Secure Biometrics. Confirm the camera Secure Bio
capabilities with the camera vendor or with Microsoft.
A Secure Bio camera must have a mechanism for blocking firmware updates to the camera, typically this is
handled by a GPIO pin. (OEMs need to work with Microsoft on definition of secure mechanism) The GPIO pin
for the firmware lockout must be included in the cabling definition by the OEM.
12.3.3 Secure Biometrics Platform Hardware Requirements

AMD Family 17h Models 60h-6Fh processor-based platforms require the use of a discrete USB host controller
dedicated to the Secure Bio camera’s use. AMD recommends using the Renesas μPD720202 USB host
controller. Refer to the block diagram in Figure 130 for an example solution.
Secure Biometric Camera Solution 209

3.3V_S5 3.5V_S0
VR 3.3V_S0
1.05V
POWER_GATE
SPI VDD33 VDD10 CamVCC IRVCC

SPI
GPIO ROM AVDD33
FP6 PCIe Renesas USB 2.0 HS

mPD720202
CLK_REQ_L CLKREQ PECREQB
USB
PCIE_RST_L PERSTB
GPIO Camera
NC PEWAKEB
Module
GPIO WRITE PROTECT FW_WP
ACP_WOV_CLK DMIC_CLK MCLK

ACP_WOV_DATA DMIC_DATA MDATA
Figure 130. Secure Biometrics Camera Solution — Block Diagram
The diagram in Figure 130 shows the connectivity with respect to the AMD SoC and platform solution. Please
refer to Renesas for design collateral and any specific requirements for implementation of the μPD720202
controller.
Note that the GPIOs allocated for firmware write protection, power gating, and dedicated PCIe reset are shown
to be from the SoC in this example. However, GPIOs from the system EC could be used for these purposes as
well. Ensure ACPI control methods are defined for each GPIO so that the OS can make appropriate use of them.
It is recommended to power the Renesas μPD720202 by 3.3V AUX (S5 domain) in order to preserve the FW
context through low power states like S0i3 or S3. The Renesas μPD720202 supports D3 cold for low power
consumption when the camera is not in use, which is most of the time. However, if power to the controller is
removed the FW must be reloaded. Therefore, AMD recommends the platform implement a local FW ROM for
the Renesas μPD720202. This allows the controller FW to be reloaded quickly without BIOS intervention.
The camera module in Figure 130 is a representative example only. The other signal and voltage requirements
may vary. OEMs should follow the design requirements of the camera module vendor. The option for a power
gate to reduce the camera power consumed to zero is recommended.
12.3.4 Secure Biometrics System Level Requirements

The system must support Windows Hardware Compatibility Specification
System.Fundamentals.Security.VirtualizationSupport.
SecureBIO capable camera
Populate camera device in SDEV Table (ACPI ver 6.2, Section 5.2.26) For complete BIOS requirements refer to
“SecureBIO Function BIOS Implementation Guide” (PID# 56560).
Implement TPM 2.0
Ensure your OS version supports SecureBIO. Please contact Microsoft for specific requirements.
210 Secure Biometric Camera Solution

13 ACPI Interface Design Guidelines

The FP6 processor supports many ACPI-related signals that are used for power sequencing, wake, reset, and
various other related functions. Although there are many possible implementations of these signals, this
document covers some of the most common usages for typical mobile platforms.
13.1 Modern Standby Introduction

Modern Standby is a new power model that is capable of instant resume from low power idle state that
consumers expect from modern devices. It requires support from silicon, platform hardware, software, and
firmware. The AMD Modern Standby implementation supports two low-power states: S0i2 and S0i3, their major
differences from end-user point of view is: power consumption and resume latency from low power state.
13.1.1 Modern Standby Overview

This section covers the systems implementation requirements to enable Modern Standby on the AMD Family
17h Model 60h–6Fh FP6 package. The AMD Modern Standby implementation allows a platform to go into low
power (S0i2 or S0i3) states during operating system (OS) idle. The main characteristics are:
• Low power states typically initiated by pressing the power button or display off timer.
• OS remains in S0 state, looks and feels like desktop idle. But system will enter lowest possible power states.
• In case of a self-refresh capable display, the display will stay on and showing a static image. Otherwise the
display will turn off.
• Fast response to user interactions: Keyboard, mouse, touch pad, LAN, USB, AC power, etc.
Note: Since S0i2 functionality is a subset of S0i3, throughout this document only the term “S0i3” is cited,
while the same will apply to S0i2.
13.1.2 Modern Standby Power State Design

From a platform design point of view, the power configuration of the system during S0i3 is similar to that of S3
state. Since S0i3 has the lowest power state, this is generally the state most Modern Standby system would
implement. In this state:
• CPU core and graphics core are powered off, but OS stays at ACPI S0 state.
• System memory remains powered up.
• Platform components at lowest power setting (“DRIPS” per Microsoft spec), including off if possible.
Table 106. Acronyms and Terminologies

Terminology Description
ACPI Advanced Configuration and Power Interface; an open standard that allows computer operating system to discover,
control, and manage system functions.
DIPM/ HIPM Device / Host Initiated Power Management; a power management mode for storage devices.
EC Embedded Controller; also called keyboard controller in some systems.
GPIO General Purpose Input Output; signal pins that provide electrical signaling between the SoC and outside components.
AGPIO GPIO pins that are capable of interrupt and wake input function.
OS Operating System
PEP Power Engine Plug-in; a driver that AMD provides that coordinates low-power state of platform devices.
S0i2 Low power state under Modern Standby; in S0i2, the SoC goes into low power / retention mode, whereas the rest of the
system is mostly powered off, except for the wake devices.
ACPI Interface Design Guidelines 211

Table 106. Acronyms and Terminologies (continued)

Terminology Description
S0i3 Low power state under Modern Standby; in S0i3, the SoC as well as most of the system is powered off, except for the
wake devices.
SoC System on Chip. In this document it is the AMD FP6 processor.
NVMe Non-Volatile Memory interface for solid state storage devices connected to the PCI Express bus.
SATA Serial AT Attachment; computer interface that connects to storage devices such as hard disk drives or solid-state drives.
SSD Solid State Drive; storage device that uses solid state semiconductor devices for fast access.
UWP Universal Windows Platform; used to describe applications that will run on all devices that run Windows 10.
Wake Device A system component that can initiate events to signal the system exit low-power state and return to S0 state. See
reference: https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-standby-wake-sources
WOV/ KWS Wake On Voice / Keyword Spotting; the ability for a system to exit low power state by voice activation. More
specifically, when a specific pattern of words is detected, as in Keyword Spotting. See reference: https://
docs.microsoft.com/en-us/windows-hardware/drivers/audio/voice-activation
13.1.3 Modern Standby References
Table 107. Modern Standby References

Reference Link
Microsoft top page https://msdn.microsoft.com/en-us/windows/hardware/commercialize/design/device-experiences/modern-standby
Modern Standby design https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-standby-design-decisions

decisions:
Behavior differences
between S3 and Modern
Standby:
https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/behavior-differences-between-s3-and-
modern-standby
Modern Standby system https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-standby-system-behavior-

behavior verification: verification
Modern Standby user https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-standby-user-experiences

experiences:
Hardware requirements https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/hardware-requirements-for-soc-based-platforms

for SoC-based platforms:
Platform design for https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/platform-design-for-modern-standby

Modern Standby:
Functional overview of https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/functional-overview-of-modern-standby

Modern Standby:
Functionality with https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/functionality-wiht-networking-devices

networking devices:
Other Modern Standby https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/other-modern-standby-functionality

functionality:
Power policy https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/power-policy-configuration

configuration:
Integrating apps with https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/integrating-apps-with-modern-standby

Modern Standby:
Modern Standby wake https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-standby-wake-sources

sources:
Validating Modern https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/validating-modern-standby

Standby:

Table 107. Modern Standby References (continued)

Reference Link
Device-specific power https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/device-specific-power-management-for-

management for Modern modern-standby
Standby:
Adaptive Hibernate: https://docs.microsoft.com/en-us/windows-hardware/customize/power-settings/adaptive-hibernate
13.2 Modern Standby Platform Hardware

This section provides a general overview of key aspects of platform design, including power rails and key
signals. The AMD S0i3 implementation tries to leverage existing S3 architecture, while maintaining all behavior
and characteristics of S0i3 design. This ensures a cost-effective design while maintaining full compliance to the
requirements of Modern Standby.
13.2.1 Modern Standby Power Rails

In AMD’s FP6 platform hardware implementation, S0i3 power rail control is similar to S3 implementation. This
simplifies system design:
• One platform design will be able to support either S0i3 or legacy S3.
• See Figure 131 and Figure 132 for the state of FP6 power rails under S0i2, S0i3, and S3.
Figure 131. System Power Rail Summary
13.2.2 Modern Standby Power/Reset Design PCIe® Devices

• All PCIe® devices on the Modern Standby platform need to support D3-hot or D3-cold. The AMD APU PCIe
controller and PHY are shut off during S0i3 and require BIOS (ASL) to control proper power/reset timing for
re-training.

• Power/reset timing need to meet device requirements during power on, D3-cold (S0i3)/S3 entry and resume.
A typical PCIe device power/reset timing sequence is shown in Figure 132. Ta has a minimum requirement
and Tb has a maximum requirement. A dedicated GPIO from the EC is recommended to make the device
PERST controllable.
Ta Tb
S0 Power
Reset#
RP Training
Figure 132. System Power-Up/Reset Sequence
Ta (min) = 100 mS
• Use AUX_RESET# to ensure device power is stable before Reset is released.
Tb (max) = 20 mS
• Device must enter link training within 20 mS of reset.
• Devices that have a long resume latency (such as certain WLAN controllers) should be powered from S5 rail
and kept powered up during S0i3, to avoid the long latency during resume. The WLAN power should be
gated by EC GPIO during S3, S4 and S5.
13.2.3 Modern Standby Sleep Control Signal

SLP_S3# is used to control S0i3 state transition, same as in a legacy S3 platform:
• During initialization, system BIOS needs to set the ACPI object LOW_POWER_S0_IDLE_CAPABLE. This
flag will indicate to the EC whether the system is configured for S0i3 or S3.
• In both cases (S0i3 or S3), the SoC asserts SLP_S3# to signal entering the low power state. The EC needs to
discern between the two states based on the setting of the ACPI object and take appropriate action.
• Refer to the Modern Standby BIOS Implementation Guide, order# 56358 for more details.
• Refer to the AMD FP6 customer reference board (CRB) schematics for Modern Standby implementation for
details on signal routing.

13.2.4 Modern Standby Wake Signals - General

• Wake signals are the mechanism for various platform components to signal the SoC to exit S0i3 state.
• In case where wake signals from platform components wake the SoC directly, the SoC uses SLP_S3# de-
assert to signal the EC to wake from S0i3.
• In case where the EC is the wake source (e.g., battery power state changes, which are monitored by the EC),
the EC would use a separate wake signal to wake the SoC to exit from S0i3. This needs to be connected to
one of the S5 domain GEVENT AGPIO pins on the FP6 package.
13.2.5 Modern Standby Hardware-Reduced ACPI Design

On a Hardware-reduced ACPI platform, the wake sources must use S5 domain AGPIO pins on the FP6 package
to signal wake event.
13.2.6 Modern Standby - AC_PRES signal

On a Modern Standby system, the AC_PRES pin needs to be connected to the Platform AC_OK signal, to
indicator whether the system is in AC mode or DC mode.
13.3 Modern Standby Platform Components

This section provides Modern Standby platform component selection guidelines.
13.3.1 Modern Standby Component Selection

General guidelines for selection of Modern Standby platform components:
• The AMD Approved Vendor List (AVL) System Components for AMD Family 17h Models 60-6Fh
Processors (NDA), order # 56641 provides a list of platform components that AMD is enabling for S0i3
implementation. Please contact your AMD representative.
• All platform components must be able to support D3-hot and/or D3-cold.
• For devices that have long resume latency ( > 100mS) such as WLAN, they may need to be kept powered up
during S0i3, in order to ensure fast response to wake events. This is a design balance between power savings
versus response time.
13.3.2 Modern Standby Storage Devices

• SSD or NVMe storage devices are required for Modern Standby systems, to meet response time
requirements.
• SATA SSD devices should be powered from S5 rail during S0i3, and should support DEVSLP as well as
HIPM functionality. The SATA SSD power should be gated by EC GPIO during S3, S4, and S5.
• NVMe (PCIe or M.2) devices should be powered from S0 rail. The NVMe power should be off during S3,
S0i3 S4 and S5.
• To ensure the reset timing of the NVMe drive meets the PCIe specification, NVMe storage devices must use
AGPIO40 for its AUX_RESET signal. Do not use any other GPIO because AGPIO40 is hardcoded in the
BIOS to ensure that the NVMe drive is always available after exiting from S0i3.
• Connect AGPIO40 and global PCIe reset to a AND logic IC’s inputs and connect IC’s output to NVMe’s
PERST#. Put one 10 kΩ pulldown resistor on AGPIO40.
• Refer to Microsoft’s Modern Standby guidelines on part selection: https://docs.microsoft.com/en-us/
windows-hardware/design/device-experiences/part-selection

13.3.3 General Information for Modern Standby Wake Sources/Wake Events

The following provides information Modern Standby system wake source/wake event :
• PEP monitors the system power state. Only when PEP driver sees all selected devices have been in targeted
power states, one of the requirements of S0i3 entry is met.
• The system BIOS needs to enumerate the system devices for the PEP driver which in turn communicates with
the OS to set the devices to DRIPS (Deepest Runtime Idle Platform State).
• Platform BIOS needs to maintain and provide device power state capabilities to the PEP driver.
• To ensure the reset timing of the NVMe drive meets the PCIe specification, NVMe storage devices must use
AGPIO40 for its AUX_RESET signal. Do not use any other GPIO because AGPIO40 is hardcoded in the
BIOS to ensure that the NVMe drive is always available after exiting from S0i3.
• Connect AGPIO40 and global PCIe reset to a AND logic IC’s inputs and connect IC’s output to NVMe’ s
PERST#. Put one 10K pull down on AGPIO40.
• Refer to Microsoft’s Modern Standby guidelines on part selection: https://docs.microsoft.com/en-us/
windows-hardware/design/device-experiences/part-selection
13.4 Modern Standby Wake Sources/Wake Events

This section provides information on Modern Standby Wake Sources/Wake Events.
13.4.1 General Information for Modern Standby Wake Sources/Wake Events

The following provides general information about Modern Standby system wake source/wake events:
• Modern Standby allows the system to wake and exit S0i3 (and back into S0) typically under 500mS from
input detected to display on.
• Typical wake events and wake sources include the S3-exit triggers, such as power button, lid switch,
keyboard, mouse, touchpad, USB, etc.,.
• There are two (2) main classes of Wake sources:
• Devices that wake the system and turn on display, for example, a USB keyboard or a touchpad.
• Devices that wake the system but do not turn on the display, for example, an SD Card reader.
• For more information on Modern Standby wake sources/wake events refer to Microsoft’s Modern Standby
wake sources: https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/modern-
standby-wake-sources
13.4.2 Modern Standby Wake Devices/Event List

Table 108 is a table of various devices and events that take place on the system, and the potential impact on
waking from Modern Standby.
Note: Some events behave differently depending on whether the system is AC powered or DC powered.
Table 108. Modern Standby Wake Source/Events

Device Wake from Turn On Description
S0i3 Display
Power button Yes Yes Power button must always wake from S0i3 and turn on the display.
Windows key (on

®
Yes Yes Windows key must always wake from S0i3 and turn on the display.
keyboard)
Lid switch - open Yes Yes Opening the display cover must always wake from S0i3 and turn on the display.

Table 108. Modern Standby Wake Source/Events (continued)

S0i3 Display
Internal keyboard Yes Yes Pressing any key on the internal keyboard must wake from S0i3 and turn on the display.
Volume up/down Yes No Volume control keys must wake the system, but not turn on display.
keys
USB keyboard Yes Yes Pressing any key on a USB-connected keyboard must wake from S0i3 and turn on the display. It’s
acceptable for the first keystroke to wake the system but not processed by the OS.
Bluetooth keyboard Yes Yes Pressing any key on a Bletooth-connected keyboard must wake from S0i3 and turn on the display.
It’s acceptable for the first keystroke to wake the system but not processed by the OS.
Internal touchpad Yes Yes If the touchpad is visible to the user (and not folded away as in a convertible notebook), it must
(I2C connected) wake from S0i3 and turn on the display.
USB touchpad Yes Yes If the touchpad is visible to the user (and not folded away as in a convertible notebook), it must
wake from S0i3 and turn on the display.
USB mouse Yes Yes Pressing any key on a USB-connected mouse must wake from S0i3 and turn on the display. It’s
acceptable for the first click to wake the system but not processed by the OS.
Bluetooth mouse Yes Yes Pressing any key on a Bluetooth-connected mouse must wake from S0i3 and turn on the display.
It’s acceptable for the first click to wake the system but not processed by the OS.
Finger print reader Yes Yes Finger print swipe on the reader must wake from S0i3 and turn on the display.
Voice input Varies Varies The ACP in FP6 SoC, which has external PDM digital mics directly connected. AMD’s platform
will support Wake On Voice with Realtek audio DSP connected in the system. Refer to reference
schematics for WOV.
Dock attach/ Varies Varies Attach / detach a dock is treated the same as attaching / detaching each of the devices in the dock.
detach
Insert / eject an optical disc must wake from S0i3 and turn on the display.
Optical disc drive Yes Yes
Skype call - Varies Varies In AC mode, Skype calls must wake from S0i3 and turn on display. In DC mode, Skype calls may
incoming wake from S0i3, depending on user’s setting for UWP app priority blocking.
Skype IMs - Varies Varies In AC mode, Skype calls must wake from S0i3 and turn on display. In DC mode, Skype calls may
incoming wake from S0i3, depending on user’s setting for UWP app priority blocking.
VOIP incoming call Varies Varies In AC mode, Skype calls must wake from S0i3 and turn on display. In DC mode, Skype calls may
wake from S0i3, depending on user’s setting for UWP app priority blocking.
Other IMs/ KWS Varies Varies In AC mode, Skype calls must wake from S0i3 and turn on display. In DC mode, Skype calls may
wake from S0i3, depending on user’s setting for UWP app priority blocking.
Bluetooth device: Varies No Same scenario as in Skype incoming call above. In all cases, Bluetooth notification is not expected
notify to turn on the display.
Bluetooth device: Varies No Same scenario as in Skype incoming call above. In all cases, Bluetooth connect is not expected to
connect turn on the display.
Location services Varies Varies Same scenario as in Skype incoming call above.
Other UWP apps Varies Varies Same scenario as in Skype incoming call above.
Remote desktop Yes Yes Remote desktop functionality requires a wired Ethernet connection. This typically implies the
platform is on AC power.
File sharing Yes No Same scenario as in Remote desktop above.
Power source Yes Yes This wake event is typically routed through the EC, which needs to wake the system through
change GPIO interrupt when the power source has changed.
AC/DC timer Yes No Internal HW component to the SoC. This may wake the system from S0i3 for a variety of reasons;
however, the display is not turned on. Note: AC_PRES must be connected to platform AC_OK in
order to trigger the timer.
SD card attach / Yes No When CD SD controller detects a card insertion, it needs to wake the system, which reads the SD
detach card content without turning on the display, then returns back to Modern Standby state.


S0i3 Display
USB drive attach / Yes No Same scenario as in SD card attach / detach above.
detach
eSATA attach / Yes No Same scenario as in SD card attach / detach above.

detach
Headphone or Yes No Attaching a headphone or microphone must wake the OS to update the audio signal routing. Then
microphone the OS will return to Modern Standby state.
attach / detach
WiFi radio Varies No In a Connected Modern Standby system, WiFi radio will wake the system but not turn on the
display. In a Disconnected Modern Standby system, WiFi radio will not wake the system.
Wireless WAN Varies No In a Connected Modern Standby system, Wireless WAN radio will wake the system but not turn
radio on the display. In a Disconnected Modern Standby system, Wireless WAN radio will not wake the
system.
Bluetooth radio Varies Varies In the case of Bluetooth keyboard, mouse, or other user-input devices, the Bluetooth device will
wake the system and turn on the display. In the case of other devices such as Bluetooth headphone,
the display will not turn on.
Wired LAN Yes No Wired LAN devices need to support magic packet pattern-matching and wake the system, but not
turn on the display.
Windows update - Yes No Windows update will wake the system for scanning but will not turn on the display.
scan
Windows update - Yes No In AC mode, Windows Update will wake the system and download the update, without turning on
download the display. In DC mode, Windows Update will wake the system, but download is limited by the
OS to interactive mode only.
Windows update - Yes No In AC mode, Windows Update will wake the system to install the update when ready. In DC
install
Windows update - www.teknisi-indonesia.com

Yes No
mode, Windows Update will not wake the system to install updates.
In AC mode, Windows Update will wake the system and restart when ready. In DC mode,
restart Windows Update will not wake the system to restart.
UWP applications Yes No In both AC and DC modes, Universal Windows Platform app will download app contents in the
– background background but will not turn on the display.
content upload /
download
UWP applications Yes No In AC mode, UWP apps will sync mail in the background but will not turn on the display. In DC
– Mail sync mode, UWP apps will not sync mail in the background, and will not turn on the display.
UWP applications Yes No Same scenario as in Mail sync above.

– Contact sync

– Calendar sync

– sync with
Bluetooth devices
UWP applications Yes No In both AC and DC modes, UWP apps will enable network operation in the background, but will
– operations that not turn on the display.
require network
UWP applications Yes No In both AC and DC modes, UWP apps will enable audio recording in the background, but will not
– Background turn on the display.
audio recording
Audio playback: Yes No In both AC and DC modes, audio playback requires the system to support S0i2 mode, but will not
local and streaming turn on the display. Playback exit allows the system to enter S0i3.
on internal
speakers


S0i3 Display
Audio playback: Yes No In both AC and DC modes, audio playback requires the system to support S0i2 mode, but will not
local and streaming turn on the display.
on Bluetooth
speakers
Thermal event Yes No In both AC and DC modes, temperature sensors must wake the system in case of temperature
trigger events but will not turn on the display.
Battery Charge Yes No When the system battery is fully charged, it must wake the system to indicate battery state change
completion but will not turn on the display.
Battery threshold Yes No When the system battery charge reaches below the designated value, it must wake the system to
change initiate hibernate / deeper sleep activities but will not turn on the display.
13.4.3 Modern Standby Power Rail Assignment – Wake Sources

• If a device is designated as a wake source, the wake function inside the device must be powered from the S5
rail.
• If the device is not designated as a wake source, it can be powered by the S0 rail, or a power-gated S5 rail.
The power-gated S5 rail can power on devices as required. (for example, power off (D3cold) in OS runtime
because of IDLE, power on only when device is required to function after S0i3 resume).
13.4.4 Modern Standby Wake Signal Input to SoC

• Legacy S3 wake GPIOs should be GEVENT GPIOs. S0i3 wake GPIOs can be any S5 domain AGPIO.
• Separate interrupt GPIOs should be assigned for each wake device. Interrupt GPIOs should be AGPIO and
SCI capable GPIO.
Table 109 summarizes the AMD recommended GPIO signals for Modern Standby platform implementation.
Table 109. Modern Standby Platform Component I/O and GPIO Assignment
Component Interface Power Power Power Gate Wake/INT GPIO Aux Reset Comments
Domain Gate GPIO
WiFi GPP7 S5 Yes EC IOX 1A.4 AGPIO18 EC GPIO101 Separate wake interrupts
needed per device
LAN GPP6 S5 Yes EC IOX 1A.2 AGPIO24 EC GPIO172 -
WWAN GPP5 S5 Yes EC IOX 1A.3 AGPIO17 EC GPIO102 -
PCIe SSD GPP[1..0] S0 Yes EC IOX 1A.5 No Wake FCH NVMe SSD powered off in
AGPIO40 S0i3 via Runtime_D3 call by
OS
Bluetooth USB2.0 S5 Yes EC IOX 1A.4 USB in-band wake N/A USB in-band wake
UART/I2S S5 Yes EC IOX 1A.4 AGPIO3 N/A -
SATA SSD SATA0 S5 Yes EC IOX 1A.1 No Wake N/A SATA SSD requires DevSlp
support
Touch Pad I2C0 S5 No N/A AGPIO9 N/A -
Touch Panel I2C0 S5 No EC IOX 1B.0 AGPIO12 (no N/A -

wake)
NFC I2C1 S0 No N/A AGPIO69 (no N/A -

wake)
Ambient Light I2C1 S0 No N/A AGPIO144 (no N/A -

Sensor wake)

Table 109. Modern Standby Platform Component I/O and GPIO Assignment (continued)
Component Interface Power Power Power Gate Wake/INT GPIO Aux Reset Comments
Domain Gate GPIO
Codec HP/MIC HDA S5 No N/A AGPIO11 or SDI N/A -
ACP DMIC Integrated S5 No N/A Integrated N/A WoV support. Inband wake
EC eSPI G3 No N/A AGPIO22 N/A -
Keyboard EC S5 No N/A EC N/A -
TPM SPI S5 No N/A AGPIO88 N/A -
PD Controller I2C G3 No N/A N/A N/A -
LID GPIO S5 No N/A EC N/A -
USB Hub USB S5 No N/A USB In band wake N/A -
13.5 Modern Standby Wake on Voice

This section provides information on Modern Standby Wake on Voice implementation.
13.5.1 Modern Standby Wake on Voice Overview

Modern Standby allows a system to detect voice input from a user, to wake the system from S0i3 and back to
idle. This is typically done by scanning for a particular sequence of spoken words, such as:
• “Hey Cortana” under Windows 10
• “OK Google / Hey Google” for Google Home
• “Alexa” in case of Amazon Echo
13.5.2 Modern Standby Wake on Voice System Overview
AMD’s implementation for Wake On Voice / Keyword Spotting (WOV/KWS) uses the FP6 SoC Audio
CoProcessor (ACP) to perform the analog data processing and keyword spotting, and an audio CODEC for
speaker / headphone support. The system overview is as follows:

Figure 133. Modern Standby Wake on Voice/ Keyword Spotting System System Block Diagram
Refer to the FP6 Processor Motherboard Schematic Checklist, order# 56179 and the FP6 Processor Motherboard
Layout Checklist, order# 56180 for detailed design regarding DSP.

13.6 ACPI Modern Standby and Legacy System Schematic and Routing Design
Guidelines
This section covers Modern Standby and Legacy platform design schematic and layout guidelines for typical
mobile platforms.
Figure 134 shows Modern Standby support platform design schematic and layout guidelines for ACPI interface
signals. Table 110 lists the Mobile ACPI interface routing rules.
3.3 V_S5
APU
VDD_18_S5
PWR_BTN_L
SYS_RESET_L
RSMRST_L
0 ohms System Power
Supplies
SLP_S3_L
DNI S3_STATE#
S0A3_GPIO
SLP_S5_L S5_STATE#
PWR_GOOD PWR_GOOD
Keyboard Ctrl
KBRST_L KRST#
(Optional)
GA20IN GA20IN
PCIe® Devices/Slots
GPIOx/per device/slot *
RST#
PCIE_RST0_L1
* "each PCIe device/slot needs an
GPIOx/per device/slot * individual GPIO for reset "
PCIe Devices/Slots
Buffer RST#
PCIE_RST1_L2
(Optional)
TPM/LPC
LPC_RST_L RST#
3.3V_S5
PCIe Devices/Slots
WAKE_L or AGPIOx WAKE#
"each device needs an individual 3.3V_S5
wake pin (AGPIO or WAKE_L) " Battery Charger
Circuit
LLB_L LOW_LOW_BAT#
S5 Rail
1.8 V / 3.3 V
BLINK
Thermal Sensor
ALERT_L ALERT#
Platform AC/Battery
Detection circuit
AC_PRES AC_PRES
Connect to platform circuit that indicates whether
system is in AC mode or DC (battery) mode
Figure 134. Modern Standby ACPI Interface Routing Model
Note: 1. PCIE_RST0_L has standard PCIe reset timing. Use PCIE_RST0_L for devices supporting faster
PCIe reset timing.
2. PCIE_RST1_L has a programmable reset timing. Use PCIE_RST1_L for devices that require longer
reset timing. Add a buffer (optional) if devices have pull up resistors.

S0i2 Modern Standby support platform:
When the system is in S0i2, the deepest runtime idle platform state (DRIPS) seen by the OS, and the platform
HW is S0 power state.
Schematic notes:
• Follow legacy platform design for S0, S3, and S5 power rails enablement.
• Design power gate for devices that are intended to be put into D3 cold in S0i2. If device doesn’t exceed 1mW
in D3hot, power gate can be saved.
• Use an AND circuit for a GPIO (default Low) with global PCIe reset as PCIe devices reset in. This
AUX_RESET (GPIO) circuit should be per device.
• Devices that support wake up from S0i2 should be powered in S0i2. Wake pin should be per device.
S0i3 Modern Standby support platform:
When the system is in S0i3, the deepest runtime idle platform state (DRIPS) seen by the OS, and the platform
HW is S3 power state.
Schematic notes:
• Follow legacy platform design for S3 and S5 power rails enablement. S0 power rails enablement is by an
AND circuit of SLP_S3# and S0A3_GPIO, reserve 0 ohm bypass-resistor to override S0A3_GPIO.
• Design power gate for devices that are intended to be put into D3 cold in S0i3. If device doesn’t exceed 1mW
in D3hot, power gate can be saved.
• Use an AND circuit with a GPIO (default Low) and global PCIe reset as PCIe devices reset in. This
AUX_RESET (GPIO) circuit should be per device.
• Devices that support wake up from S0i3 should be powered in S0i3. Wake pin should be per device.
• Keep device’s power on in S0i3 if it is intended to be active in S0i3, i.e., Wifi for Modern Standby connected
mode.
For the devices selection/wake source, please refer to MSFT requirement. Confirm with device vendor if desired
power state is supported (D3cold, D3hot).
See the AMD Approved Vendor List (AVL) System Components for AMD Family 17h Models 60-6Fh
Processors (NDA) and the Modern Standby BIOS Implementation Guide for more information.

Figure 135 shows legacy platform design schematic and layout guidelines for ACPI interface signals. Table 110
lists the Mobile ACPI interface routing rules.
3.3 V_S5
APU
VDD_18_S5
PWR_BTN_L
SYS_RESET_L
RSMRST_L
System Power
Supplies
SLP_S3_L S3_STATE#
SLP_S5_L S5_STATE#
S0A3_GPIO No Connect
PWR_GOOD PWR_GOOD
Keyboard Ctrl (Optional)

KBRST_L KRST#
GA20IN GA20IN
GPIOx/per device/slot* PCIe® Devices/Slots
PCIE_RST0_L 1 RST#
GPIOx/per device/slot*
PCIe Devices/Slots
2 Buffer RST#
PCIE_RST1_L
(Optional)
*GPIO recommended, but not required TPM/LPC
LPC_RST_L
www.teknisi-indonesia.com 3.3V_S5
RST#
PCIe Devices/Slots
WAKE_L WAKE#
S5 Rail 3.3V_S5
Battery Charger
BLINK
Circuit
LLB_L LOW_LOW_BAT#
1.8 V / 3.3 V
Thermal Sensor
ALERT_L ALERT#
Touch Pad
AC_PRES AC_PRES
Figure 135. Legacy ACPI Interface Routing Model (No Modern Standby support)
Note: 1. PCIE_RST0_L has standard PCIe reset timing. Use PCIE_RST0_L for devices supporting faster
PCIe reset timing.
2. PCIE_RST1_L has a programmable reset timing. Use PCIE_RST1_L for devices that require longer
reset timing. Add a buffer (optional) if devices have pull up resistors.
Table 110. Routing Rules for Mobile ACPI Interface

Signals Rule Breakout Channel
PWROK, Trace Width ≥ 0.1 mm ≥ 0.1 mm

AC_PRES,

Table 110. Routing Rules for Mobile ACPI Interface (continued)

Trace Spacing ≥ 0.1 mm ≥ 3H

PCIE_RST0_L,
PCIE_RST1_L, PWR_BTN_L,
PWR_GOOD, RSMRST_L,
VDDBT_RTC_G, SLP_S3_L,
SLP_S5_L, SYS_RESET_L,
WAKE_L,
BLINK,
LLB_L,
KBRST_L
SPKR

14 Miscellaneous Signals Design Guidelines

Miscellaneous Signals Design Guidelines
This section describes how to properly design the circuits that accept the various inputs and outputs. Table 111 is
a quick reference guide for these signals. The signal groups are defined as follows:
• Clock Signals
• Driver Strength (Auto Compensation) Signals
• Voltage Regulator Signals
• DDR Voltage Reference
• Global Signals
• USB Miscellaneous Signals
• SMBus Signals
• I2C Bus Signals
• UART Signals
• LPC Signals
• SPI ROM Signals
• SPI TPM Signals
• LCD Panel Signals
• Test, Debug, and Validation
• Reserved Pins
• Thermal Related Signals
• GPIO Signals

Table 111. Miscellaneous Signals Quick Reference

Group Signal Name Connection Termination1 Termination
Voltage
CLK_REQ0_L/SATA_IS0_L/ PCI Express device supporting 10 kΩ VDD_33

SATA_ZP0_L/AGPIO922 CLKREQ_L
CLK_REQ1_L/AGPIO1152 PCI Express device supporting 10 kΩ VDD_33

CLKREQ_L
CLK_REQ2_L/AGPIO1162 PCI Express device supporting 10 kΩ VDD_33

CLKREQ_L
CLK_REQ3_L/SATA_IS1_L/ PCI Express device supporting 10 kΩ VDD_33

SATA_ZP1_L/EGPIO1312 CLKREQ_L
CLK_REQ4_L/OSCIN/ PCI Express graphics device 10 kΩ VDD_33

EGPIO1322 supporting CLKREQ_L
Clock Signals CLK_REQ5_L/EGPIO1202, 3 PCI Express device supporting 10 kΩ VDD_33
CLKREQ_L
CLK_REQ6_L/EGPIO1212 PCI Express graphics device 10 kΩ VDD_33

supporting CLKREQ_L
RTCCLK Connected to device requiring – –

a 32-kHz clock in S5 state
(optional)
X48M_OSC Connect to device that requires a 22Ω –

48MHz single-ended OSC input series resistor
SMU_ZVDD Pull-up resistor 196Ω VDDP

Driver Strength Signals
SVC07 VDDCR/VDDCR_SOC regulator
(± 1%)
0-Ω series resistor –

and a 27pF
capacitor to VSS
(DNI)
SVD07 VDDCR/VDDCR_SOC regulator 0-Ω series resistor –

and a 27pF
capacitor to VSS
(DNI)
SVT07 VDDCR/VDDCR_SOC regulator 0-Ω series resistor –

and a 27pF
capacitor to VSS
Voltage Regulator and Related (DNI)
Signals
VDDCR_SENSE VDDCR regulator – –
VDDCR_SOC_SENSE10 VDDCR_SOC regulator – –
VDDP_SENSE11 VDDP regulator – –
VDDP_S5_SENSE11 VDDP_S5 regulator – –
VSS_SENSE_A VSS sense pin for VDDCR / – –

VDDCR_SOC regulator
VSS_SENSE_B VSS sense pin for VDDP regulator – –
VDDIO_MEM_S3_SENSE VDDIO_MEM_S3 regulator – –
Pull-up resistor 1 kΩ VDDIO_MEM_S3
VREFCA Pull-down resistor 1 kΩ VSS

DDR VREF
(on DIMM) Decoupling capacitor 0.1 µF VSS
Decoupling capacitor 1 nF VSS
Miscellaneous Signals Design Guidelines 227

Table 111. Miscellaneous Signals Quick Reference (continued)

Voltage
PWROK Connect to PWROK on VDDCR/ 4.7 kΩ OD5 VDD_18_S5

VDDCR_SOC regulator
RESET_L HDT+ header, pin 12 through buffer 4.7 kΩ OD5 VDD_18_S5
SYS_RESET_L/AGPIO1 Connected to the system reset button. 10 kΩ VDD_33_S5

PWR_GOOD deassertion does not
assert SYS_RESET_L.
PCIE_RST0_L/EGPIO263 PCI Express slots and devices- fixed 22 to 33Ω series –

reset. PCIE_RST0_L/EGPIO26 is resistor
cleared by every PCIE_RST event
regardless of the setting of 100 to 150 pF VSS
corresponding IOMUX registers. It is
not recommended to use this signal as
a GPIO unless this condition can be
tolerated.
PCIE_RST1_L/EGPIO2713 PCI Express slots and devices- 22 to 33Ω series –

programmable reset. PCIE_RST1_L/ resistor
EGPIO27 is cleared by every
PCIE_RST event regardless of the 100 to 150 pF VSS
setting of corresponding IOMUX
10 kΩ VSS
registers. It is not recommended to
use this signal as a GPIO unless this optional buffer
condition can be tolerated. after pulldown
depending on
system loading
PWR_BTN_L/AGPIO0 Power switch 10 kΩ VDD_33_S5
Global Signals
PWR_GOOD System power supply circuit or
(Optional) connect to SYS_RESET_L
with a diode (DNI). If an external
8.2 kΩ
pull-up resistor
VDD_33_S5
buffer is used to drive PWR_GOOD

100 kΩ VSS
to the processor, the output of the
external PWR_GOOD buffer must pull-down resistor
not be allowed to float in any sleep Only if
state (S3-S5). The external buffer VDD_33_S0
must either use 3.3V S5 to power the supply is used.
buffer or add a pull-down resistor if Not needed if
3.3V S0 is used to power the buffer. VDD_33_S5 is
See the PWR_GOOD section for used.
more information.
RSMRST_L Input signal to APU, asserted for 10 22 kΩ VDD_18_S5

ms after S5 power rail is within spec. Required only if
Use external RC circuit for 10 ms or using external RC
use EC or SIO to generate the 10 ms circuit
delay.
10 µF VSS
VDDBT_RTC_G Connected to either a 3.3V coin cell + 3.3 V Either 3.3V coin cell
or 3.3V from EC. See the RTCCLK through a or 3.3V from EC
Real Time Clock (RTC) and Battery 1 kΩ series
Interface section for more resistor and diode
information.
SLP_S3_L System power supply circuit – –
SLP_S5_L System power supply circuit – –
WAKE_L/AGPIO214 WAKE_L of PCIe expansion slot 10 kΩ VDD_33_S5
BLINK/AGPIO11 BLINK LED (Optional) LED with VDD_33_S5

series resistor


Voltage
BLINK/AGPIO11 BLINK LED (Optional) or VDD_33_S5

10 kΩ
pull-up resistor
if LED is not
implemented.
ESPI_RESET_L/KBRST_L/ Enhanced SPI Reset, or Reset output – –

AGPIO129 from KB controller or SIO.
Configured as 3.3V when it is
KBRST_L or GPIO.
Global Signals S0A3_GPIO/AGPIO10 If Modern Standby S0i3 is supported, 2.2 kΩ VDD_33_S5

connect to system power-supply pull-up resistor
circuit as the S0A3 indicator signal. Implementation
Dependent
INTRUDER_ALERT Connect to hardware monitor – –

or if not used leave unconnected to
disable.
LLB_L/AGPIO123 Connect to battery-monitor circuit 10 kΩ VDD_33_S5

or if not used leave unconnected.
USB_OC0_L/AGPIO16 OC signal from USB connector Implementation –

Dependent

Dependent
USB Signals
Dependent

Dependent
I2C2_SCL/EGPIO113/ Primary SMBus clock 2.2 kΩ VDD_33

SMBUS0_I2C_SCL3 pull-up resistor
I2C3_SCL/AGPIO19/ Secondary SMBus clock 2.2 kΩ VDD_33_S5

SMBUS1_I2C_SCL3 pull-up resistor
SMBus Signals
I2C2_SDA/EGPIO114/ Primary SMBus data 2.2 kΩ VDD_33
SMBUS0_I2C_SDA3 pull-up resistor
I2C3_SDA/AGPIO20/ Secondary SMBus data 2.2 kΩ VDD_33_S5

SMBUS1_I2C_SDA3 pull-up resistor
I2C0_SCL/EGPIO1453 I2C Bus 0 clock 2.2 kΩ VDD_18

pull-up resistor or
VDD_3315
I2C0_SDA/EGPIO1463 I2C Bus 0 data 2.2 kΩ VDD_18

I2C Bus Signals8 pull-up resistor or
VDD_3315
I2C1_SCL/EGPIO1473 I2C Bus 1 clock 2.2 kΩ VDD_18

pull-up resistor or
VDD_3316


Voltage
I2C1_SDA/EGPIO1483 I2C Bus 1 data 2.2 kΩ VDD_18

pull-up resistor or
VDD_3316
I2C2_SCL/EGPIO113/ I2C Bus 2 clock 2.2 kΩ VDD_18

SMBUS0_I2C_SCL3 pull-up resistor or
VDD_3317
I2C2_SDA/EGPIO114/ I2C Bus 2 data 2.2 kΩ VDD_18

SMBUS0_I2C_SDA3 pull-up resistor or
VDD_3317
I2C3_SCL/AGPIO19/ I2C Bus 3 clock 2.2 kΩ VDD_18_S5

I2C Bus Signals8 SMBUS1_I2C_SCL3 pull-up resistor or
VDD_33_S518
I2C3_SDA/AGPIO20/ I2C Bus 3 data 2.2 kΩ VDD_18_S5

SMBUS1_I2C_SDA3 pull-up resistor or
VDD_33_S518
USBC_I2C_SCL USB-C® Controller Configuration 4.7 kΩ VDD_18_S5

Interface Implementation
I2C Clock Port Dependent
USBC_I2C_SDA USB-C Controller Configuration 4.7 kΩ VDD_18_S5

Interface Implementation
I2C Data Port Dependent
SFH1_SCL SFH clock 2.2 kΩ VDD_18_S5
pull-up resistor or
VDD_33_S519
SFH1_SDA SFH data 2.2 kΩ VDD_18_S5

pull-up resistor or
VDD_33_S519
Sensor Fusion Hub Signals8 SFH_IPIO39 SFH sensor 10 kΩ VDD_33_S5
SFH_IPIO41 SFH sensor 10 kΩ VDD_33_S5
EGPIO140/UART0_CTS_L/ UART0 'Clear To Send' signal – –

UART1_TXD
EGPIO142/UART0_RTS_L/ UART0 'Request To Send' signal – –

UART1_RXD
EGPIO141/UART0_RXD UART0 'Received Data' signal – –

UART Signals
EGPIO143/UART0_TXD UART0 'Transmitted Data' signal – –
AGPIO144/SHUTDOWN_L/ UART0 Interrupt signal – –

UART0_INTR
EGPIO140/UART0_CTS_L/ UART1 'Transmitted Data' signal – –

UART1_TXD


Voltage
EGPIO142/UART0_RTS_L/ UART1 'Received Data' signal – –

UART Signals
UART1_RXD
LFRAME_L/EGPIO1093 LFRAME# on LPC device(s) – –
LPCCLK0/EGPIO743 LPCCLK0 on LPC device(s) 22Ω series resistor –
LPCCLK1/EGPIO753 LPCCLK1 on LPC device(s) 22Ω series resistor –
LPC_CLKRUN_L/AGPIO88 LPC_CLKRUN# on LPC device(s) – –
LPC_PD_L/AGPIO213 LPC_PD# on LPC device(s) – –
LPC_PME_L/AGPIO22 LPC_PME# on LPC device(s) – –
LPC_RST_L/AGPIO323 8 LPC_RST# on LPC device(s) 33Ω series resistor –
150 pF capacitor VSS

to VSS placed
after series resistor
LAD0/ESPI1_DATA0/ LPC device(s) 10Ω series resistor –

EGPIO1048

LPC Signals EGPIO1058

EGPIO1068

EGPIO1078
ESPI_ALERT_L/LDRQ0_L/
EGPIO108
LDRQ0# on LPC device(s)
LDRQ0_L configuration is set to
10 kΩ VDD_18 or
VDD_33
3.3V. Regardless if ESPI_ALERT_L/
LDRQ0_L/EGPIO108 is used or not
used, connect to a 10 kΩ pull-up
resistor to 1.8V or 3.3V depending on
which interface is enabled eSPI or
LPC. This signal must remain at a
logic high through the boot process. It
is not recommended to use this signal
as a GPIO unless it can meet this
condition.
SERIRQ/AGPIO87 SERIRQ on LPC device(s) – –
SPI_HOLD_L/ESPI_DAT3 Hold# of SPI ROM or DQ3 on multi- 10 kΩ VDD_18_S5

I/O SPI or ESPI device Install 10K only if
the SPI ROM
supports hardware
RESET function,
otherwise DNI to
improve Quad I/O
performance.
ESPI/SPI ROM Signals
SPI_WP_L/ESPI_DAT2 WP# of SPI ROM or DQ2 on multi- 10 kΩ VDD_18_S5
I/O SPI or ESPI device Install 10K only if
the SPI ROM
supports hardware
WP function,
otherwise DNI to
improve Quad I/O
performance.


Voltage
SPI_CLK/ESPI_CLK Clock of multi-I/O SPI or ESPI 10Ω –

device. series resistor
An isolation FET is required if Implementation
implementing ROM sharing. Dependent
See the SPI ROM Sharing section for
more information.
AGPIO86/SPI_CLK2 Clock#2 of multi-I/O SPI or ESPI 10Ω –

device series resistor
Implementation
Dependent
SPI_DO Data input of SPI ROM or DQ0 on – –

multi-I/O SPI or ESPI device
SPI_DI/ESPI_DATA Data output of SPI ROM or DQ1 on 10 kΩ VDD_18_S5

multi-I/O SPI or ESPI device
LAD0/ESPI1_DATA0/ DQ0 on multi-I/O of ESPI1 device 10 kΩ VDD_18 or

EGPIO104 VDD_33

EGPIO105 VDD_33

EGPIO106 VDD_33

EGPIO107 VDD_33
SPI_CS1_L Chip Select#1 of SPI device 10 kΩ VDD_18_S5
ESPI/SPI ROM Signals SPI_CS2_L/ESPI_CS_L/ Chip Select#2 of second SPI or ESPI VDD_18_S5
10 kΩ
AGPIO30 device
SPI_CS3_L/AGPIO31 Chip Select#3 of second SPI or ESPI 10 kΩ VDD_18_S5

device
SPI_ROM_GNT/EGPIO76 ESPI Device [Embedded Controller] – –

GPIO to monitor the ROM sharing
Grant signal
SPI_ROM_REQ/EGPIO67 ESPI Device [Embedded Controller] – –

GPIO to Control the ROM sharing
Request signal. This signal must
remain at a logic low through the boot
process. It is not recommended to use
this signal as a GPIO unless it can
meet this condition.
ESPI_ALERT_L/LDRQ0_L/ Connected to ESPI Device ALERT# 10 kΩ VDD_18 or

EGPIO108 Configuration is set to 1.8V. VDD_33
Regardless if ESPI_ALERT_L/
LDRQ0_L/EGPIO108 is used or not
used, connect to a 10 kΩ pull-up
resistor to 1.8V or 3.3V depending on
which interface is enabled eSPI or
LPC. This signal must remain at a
logic high through the boot process. It
is not recommended to use this signal
as a GPIO unless it can meet this
condition.
ESPI_RESET_L/KBRST_L/ Connected to ESPI Device RESET#. 10 kΩ VDD_33

AGPIO129


Voltage
SPI_TPM_CS_L/AGPIO293 Chip Select# of SPI TPM 10 kΩ VDD_18_S5

Note: If TPM is on a S0 rail, disable
the integrated pull-up and populate an 22 pF VSS
external pull-up resistor to VDD_18
S0 rail.
PCIE_RST0_L/EGPIO263 or Reset of SPI TPM – –

LPC_RST_L3
SPI_CLK/ESPI_CLK Clock of SPI TPM. 10Ω –

An isolation FET is required if series resistor
SPI TPM Signals implementing ROM sharing. Implementation
See the SPI ROM Sharing section for Dependent
more information.
SPI_DI/ESPI_DATA Data output of SPI TPM 10 kΩ VDD_18_S5

required only
when BIOS enable
TPM and TPM
ROM is
not present.
SPI_DO Data input of SPI TPM – –
DP_DIGON LCD interface, and BP header pin 11 – –
DP_BLON LCD interface, and BP header pin 13 – –
LCD Panel Control DP_VARY_BL LCD interface, and BP header pin 15 – –
DP0_HPD, DP1_HPD
DP2_HPD
DP or TMDS interface
DP or TMDS interface
–
–
–
TEST4/TEST5 TP or Via – –
TEST6 No Connect – –
TEST14 BP, pin 1 or TP (DNI) 10 kΩ VDD_18

Test
TEST31 TP or Via – –
MA_ALERT_L/TEST31A TP or Via – –
MB_ALERT_L/TEST31B TP or Via – –
TEST41 TP or Via – –
DP_STEREOSYNC TP and connect to the 1 kΩ VSS

STEREOSYNC circuit to the Stereo
Sync connector
(DNI) 1 kΩ VDD_18
Reserved Pins RSVD No Connect – –
PROCHOT_L Thermal monitor device or circuit 1 kΩ VDD_33
Thermal Related Signals THERMTRIP_L Connect to thermal shutdown circuit. VDD_33

1 kΩ
See the THERMTRIP_L section for
details on THERMTRIP_L shutdown.


Voltage
SIC Thermal monitor device or circuit6 1 kΩ VDD_18

or
VDD_3320
SID Thermal monitor device or circuit6 1 kΩ VDD_18

or
VDD_3320
Thermal Related Signals
ALERT_L Thermal monitor device or circuit 1 kΩ VDD_33
FANIN0/AGPIO84 Fan0 tachometer input 8.2 kΩ VDD_33
FANOUT0/AGPIO85 Fan0 PWM output 1 kΩ VDD_33
Note: 1. All termination resistor values within ± 5% tolerance, unless otherwise specified.
2. CLK_REQ[6:0]_L control GPP_CLK[6:0]P/N outputs. Refer to the Processor Programming Reference (PPR) for AMD Family 17h,
Models 60h-6Fh Processors (NDA) and the Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 50h,
Revision A0 Processors (NDA) for details.
3. If unused, enable internal pull-up or pull-down resistor by software.
4. VSYS—Voltage must be a system specific always on voltage. Pulled up to a power rail per design implementation. Left unconnected if
unused.
5. OD (Open Drain)—Pull-up resistors are needed on the motherboard if the processor input is driven by open-drain driver(s).
6. No external termination components are needed if two (or fewer) devices are connected to the pin.
7. Connect SVx to serial VID pins on the VRM through 0Ω series resistor. Series resistor/capacitor values are design specific based on
resistor/capacitor placement and voltage regulator. Adjust the series resistor values for SVC0, SVD0, and SVT0 to meet the requirements
in the AMD Serial VID Interface 2.0 (SVI2) Specification.
8. Termination resistor value is dependent on implementation (bus loading - trace length and number of loads, etc.), a common value is
listed.
9. Termination can be DNI if nothing is connected to USB_OC3#.
10. Provide an accessible probing point near the processor.
11. If VDDP and VDDP_S5 share the same PWM, the VDDP_SENSE must be connected to PWM feedback pin with a switching circuit that
gates off remote sensing in S3/S4/S5. Take caution on the switch circuit design to avoid high voltage on VDDP or VDDP_S5 because of
feedback pin sharing. Provide an accessible probing point near the processor.
12. If unused, left unconnected.
13. Refer to the Processor Programming Reference (PPR) for AMD Family 17h, Models 60h-6Fh Processors (NDA) and the Preliminary
Processor Programming Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA) for PCIE_RST1/EGPIO27
Enhancement implementation.
14. If unused, leave internal pull-up resistor enabled (default).
Processor Programming Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA) for programming the input
voltage via the I2CRXSEL field in the FCH::MISC::I2C0_PADCTRL register. Defaults to 3.3V
voltage via the MP_I2C1_OUTPUT_I2cRxSel field in the MP::MP2I2C::MP2_I2C1_REG_OUTPUT register. Defaults to 3.3V
voltage via the I2cRxSel field in the SMU::THM::SMUSBI_SMBUS register.

Any miscellaneous signal that does not have a specific routing rule in Table 112 for the routing rules may be
routed with a minimum 0.1-mm trace width and 3H spacing to other nets. Wider traces are acceptable. Wider
spacing to other nets is also acceptable.
Note: The trace/spacing rules may be temporarily relaxed down to PCB manufacturing minimums inside the
processor Breakout area only.
Table 112 lists the minimum recommended trace widths and spaces.
Table 112. Routing Rules for Miscellaneous Signals

Net Name Breakout Bus Channel Max Length
Trace or T/S/T Min. Space Trace or T/S/T Min. Space
SVC0 0.1 mm 0.1 mm 0.1 mm 3H Series resistor placed

within 12.7 mm of
APU and capacitor
within 12.7mm of
series resistor.
SVD0 0.1 mm 0.1 mm 0.1 mm 3H Series resistor placed

within 12.7 mm of
APU and capacitor
within 12.7mm of
series resistor.
SVT0 0.1 mm 0.1 mm 0.1 mm 3H Series resistor placed

within 12.7 mm of
voltage regulator and
capacitor within
12.7mm of series
resistor.
VDDCR_SOC_SENSE 0.1 mm 0.1 mm 0.125 / 0.125 / 0.125 3H –

mm
VDDCR_SENSE 0.1 mm 0.1 mm 0.125 / 0.125 / 0.125 3H –

mm
VDDP_SENSE 0.1 mm 0.1 mm 0.125 / 0.125 / 0.125 3H –

mm
VSS_SENSE_A 0.1 mm 0.1 mm 0.125 / 0.125 / 0.125 3H –

VSS_SENSE_B mm
VREFCA(on DIMM) 0.1 mm 0.1 mm 0.762 mm 0.38 mm 152.4 mm

(Resistor Placement) (38.1 mm)
(Capacitor Placement) (25.4 mm)
TEST4/TEST5 0.2 / 0.125 / 0.2 mm 0.1 mm 0.125 / 0.125 / 0.125 3H 25.4 mm

mm
14.1 Strapping Options

There are two types of straps, Strap Type I and Strap Type II. Straps are captured at the rising edge of
RSMRST_L or the rising edge of PWR_GOOD.
• Strap Type I straps become valid immediately after capture with the rising edge of RSMRST_L. Strap Type I
straps are used by modules in the S5 power well, therefore they are captured only once when power is first
applied to the processor.
• Strap Type II straps become valid after PWR_GOOD is asserted, which prevents the strap logic that resides
in the standby power well from capturing un-powered logic. Strap Type II straps are captured when the

system powers up from the S5 state. A transition from S3 to S0 does not trigger capture. Pull up Strap Type II
straps to S0 power rail to prevent leakage when the signal is connected to a device in the S0 power domain.
See Table 113 for FP6 processor strapping options.
Table 113. Strapping Options

SIGNAL Name Strap Name Strap Type Default Value Bit Value Description
SPI_CLK CLKGEN Strap II 1 0 Reserved
1 Configured for internal

clock-generator (Default)
10 kΩ (± 5%)
pull-up resistor
to VDD_18_S5
SYS_RESET_L ShortReset Strap I 1 0 Reserved
1 Normal powerup/reset timing

(Default)
10 kΩ (± 5%)
pull-up resistor
to VDD_33_S5
M_DDR4 EnableDDR4 Strap II platform dependent 0 Disable DDR4 (need to have

LPDDR4x enabled)
0Ω (± 5%) pull-down resistor
or direct connect to VSS
1 Enable DDR4 memory controller
www.teknisi-indonesia.com 0Ω (± 5%) pull-up resistor

or direct connect to
VDDIO_MEM_S3
M_LPDDR4 EnableLPDDR4 Strap II platform dependent 0 Disable LPDDR4x (need to have

DDR4 enabled)
0Ω (± 5%) pull-down resistor
or direct connect to VSS
1 Enable LPDDR4x memory

controller
0Ω (± 5%) pull-up resistor

or direct connect to
VDDIO_MEM_S3
Note: • Either M_DDR4 strap or M_LPDDR4 strap

must be pulled-up (one or the other -
NEVER both) to select either DDR4 mode
or LPDDR4x mode.
Note:
All strap pins must be configured with either external pull-up or pull-down resistors or direct connections as listed in table.
14.2 Voltage Regulator Signals

The processor has several pins dedicated to sensing and controlling the various voltage sources. The basic
control requirements for power supplies are described in the following subsections. It is desirable to have
regulators that support differential feedback to reduce common-mode noise. If the voltage regulator does not
support differential feedback, the low of the feedback pair may be left unconnected. A summary of power related
signals is listed in Table 114.

Table 114. Voltage Regulator Signals

Signal Description
SVC0, SVD0, SVT0 SVC0 and SVD0 are the clock and serial data of the serial VID interface.
Serial VID telemetry (SVT) transmits VR power status to the processor. See the SVI2 Current Telemetry Hardware
Requirement and Calibration Application Note for a straightforward procedure to measure the full-scale current value of
an SVI2 voltage regulator.
The SVI protocol provides for a PSI bit in the data packet.
Adjust the series resistor values for SVC0, SVD0, and SVT0 to meet the requirements in the AMD Serial VID Interface
2.0 (SVI2) Specification. The series resistor value listed in Table 111 at the source is an acceptable starting point, but the
series resistor value may need to be tuned based on the voltage regulator used and board layout. The series resistor value
tuning dampens the overshoot/undershoot, but must also meet the rise/fall time specifications for the interface.
Avoid reference-plane splits and layer changes.
Route on single routing layer.
VDDCR_SENSE, VDDCR_SENSE and VSS_SENSE_A are internally tied to the substrate and are used for sensing the core voltage level at
VSS_SENSE_A the processor. These signals are used for differential feedback schemes.
VDDCR_SOC_SENSE VDDCR_SOC_SENSE and VSS_SENSE_A are internally tied to the substrate and are used for sensing the Northbridge
VSS_SENSE_A voltage level at the processor. These signals are used for differential feedback schemes.
VDDP_SENSE VDDP_SENSE and VSS_SENSE_B are tied internally to the processor substrate and are used for sensing the
VSS_SENSE_B DisplayPort, SATA, and GPP PHY voltage level at the processor.
VDDIO_VPH VDDIO_VPH is a dedicated power supply for DisplayPort 0. When
• DP0 is used for eDP, connect VDDIO_VPH to VDDIO_MEM_S3 source (1.2V DDR4) or other 1.2V source to
improve battery life. Or connect to VDD_18 source (1.8V) if no 1.2V source is available.
• DP0 is used for DP or HDMI, connect VDDIO_VPH to VDD_18 source (1.8V).
14.2.1 Routing of Voltage Feedback Signals

Route the voltage feedback nets uniformly as differential traces. Figure 136 illustrates the trace routing of the
sense signals.

VDDCR_SENSE VDDIO_MEM_S3_SENSE
L1 L2
VDDCR
VDDIO_MEM_S3
Regulator
L1 L2 Regulator
VSS_SENSE_A VSS_SENSE_A
VSS_SENSE_B VSS_SENSE_A
L3 L4 VDDCR_SOC
VDDP Regulator
Regulator
L3 L4
VDDP_SENSE VDDCR_SOC_SENSE
Figure 136. Routing Diagram for Voltage Sense Signals
Refer to Figure 10 for an illustration of the recommended routing method for sense signals around vias. Also,
route the voltage feedback pair such that both signals are exposed to similar noise environments (common-mode
noise). Refer to Figure 11 for an illustration of routing sense signals away from other signals and noisy sources.
14.3 DDR4 VREF

VREF is the reference voltage for the memory interface. The following lists the VREF signal for DDR4:
• VREFCA (at DIMM, for the control/command/address bus)
The VREFCA signal may be generated by using either a passive circuit or an active circuit. Either method requires
decoupling capacitors as specified in Table 111.
The trace lengths specified in Table 112 apply to the net between the VREFCA circuit and the first device
(DIMM). The length of nets connecting multiple DIMMs is not included in this rule.
Figure 137 shows an example VREFCA (DIMM) circuit.
VDDIO_MEM_S3
R1 (place resistors close to DIMMs)

1 k ohms
1% DIMM
(place capacitors close to DIMMs)
VREFCA
R2
1 k ohms C1 C2
1%
0.1 μF 1 nF
Figure 137. VREF Circuit: VREFCA (DIMM)

14.4 Global Signals
14.4.1 Edge Rates and Signal Quality

Some signals are driven by open-drain outputs. Rising edges are determined by the value of the pull-up resistors.
The falling edges are driven by a transistor, and therefore, are faster. Perform proper signal simulation to ensure
adequate signal quality. To achieve acceptable signal quality, a signal may need to be terminated or buffered and
redriven to the various loads. The buffer may also provide level translation where needed. See the applicable
voltage regulator for information.
Example:
• The open-drain driver drives a signal to the processor and a second load such as a voltage regulator or a
multi-drop bus.
• A pull-up resistor to VDD_18 is required for the open-drain output.
• The pull-up resistor cannot be placed near the device because a VDD_18 voltage plane is unavailable under
the device.
• VDD_18 is located near the processor.
To address signal integrity with a multi-drop net, each of the loads may need a series resistor (RSnub) isolating
the load from the main signal path. AMD recommends using a 10- to 33-ohm resistor (RSnub).
There are many different ways to implement control of these signals. Figure 138 shows a schematic diagram of
the network and where the RSnub resistors should be located.
VDD_18_S5
RPullup
Processor PWROK VDD Regulator

Rsnub Rsnub
Figure 138. Schematic Diagram—Multi-Drop Net
14.4.2 PWR_GOOD
PWR_GOOD is a processor input signal driven by the system PWR_GOOD circuit. Assert PWR_GOOD signal
to the processor after all power rails are at nominal voltages and the clock inputs to the processor have reached
specified operation. Optionally PWR_GOOD can be de-asserted when SYS_RESET_L is asserted to reset the
processor. To implement this connect PWR_GOOD to SYS_RESET_L with a diode. See Table 111 for
connection and termination information.
14.4.3 PWROK
PWROK is an APU output signal used to indicate when the APU has locked the internal phase lock loop (PLL).
PWROK signal is asserted by the APU after all power planes are active and the system clock generators are
powered up and allowed to run stably for at least one millisecond.
To achieve acceptable signal quality, the PWROK signal may need to be buffered with an open-drain VDD_18
input level buffer and redriven to the various loads. The open-drain VDD_18 input level buffer is also beneficial
because it provides level translation to the various input levels of the different loads.

14.4.4 RESET_L
RESET_L is an active-low bidirectional signal that resets the APU when asserted. This is normally controlled by
an internal state machine but can also be asserted by a second external source if system design should require
additional delay of the reset to the APU. This reset signal coincides with the global reset that is distributed over
the entire motherboard to all the various ICs (this reset deasserts last comparing to other reset outputs from SOC
when system comes out from a reset sequence). If a second external reset source to this pin is added by the
system design, an open drain output must be used to avoid signal contention with the internal open drain output
from SOC. If an onboard device is used to monitor this signal, it must employ a receiver that has a threshold
corresponding to the VDD_18 supply.
14.5 Headers
Debug, Test, and Validation headers are recommended in order to provide a standardized interface for AMD
hardware and software tools.
14.5.1 Header Placement

Place debug and probing headers in such a way that they may be easily accessed while the heatsink is in place
and/or without removing the board from the chassis. When placing the headers, avoid the keepout regions such
as the heatsink, other mechanical devices, and the backplate.
Part numbers for headers are listed in Table 115. Specific pinouts are defined in the respective paragraphs.
Table 115. Header Part Numbers

Header Description Keying Mfg Part Number Placement
HDT+
10x2 1.27 mm pitch Connector Tab Samtec ASP-137098-05 Processor
BP Probing 5×2 2.54 mm pitch None Any non-specific Processor
VREF 4×1 1.27 mm pitch Connector Tab Molex 53398-0490 DIMM
14.5.2 HDT+ Header

The HDT+ interface is used for general system debug and combines the Joint Test Action Group (JTAG) and
Debug signals. This header is required for interfacing to the Wombat version of the Hardware Debug Tool
(HDT). HDT is a hardware and software tool that system designers can use to control and monitor the internal
workings of the processor. This tool aids in debugging the vast network of interconnects among the integrated
circuits. HDT is accessed with the standard Test Access Port (TAP) feature of the JTAG interface.
Table 116 lists the pin assignments for the HDT+ connector.
The JTAG and Debug signals of the HDT+ header are connected as shown in Table 116.
Table 116. HDT+ Header Pinout

HDT+ Header Connections
Connector Side 1 Connector Side 2
Pin# Signal Pin# Signal
1 VDD_HDT 1 2 TCK 3
3 VSS 4 TMS 3
5 VSS 6 TDI 3

Table 116. HDT+ Header Pinout (continued)

HDT+ Header Connections
7 VSS 8 TDO
9 TRST_L 2, 3 10 APU_PWROK_BUF
11 PD114 12 APU_RST_L_BUF
13 PD134 14 No Connect
15 PD154 16 DBREQ_L 3
17 VSS 18 No Connect
19 VDD_HDT 1 20 No Connect
Note: 1. Connect to VDD_18_S5.

2. TRST_L is connected to pin 9 through a RC circuit placed close to the connector. The series resistor in the RC circuit is 33Ω 5%. The 10-
nF capacitor in the RC circuit is connected towards the processor end of the 33-Ω series resistor.
3. Pulled up to VDD_18_S5 with a 1-kΩ resistor.
4. Connect these pins on the HDT+ connector to VSS with 10-kΩ resistors.
14.5.3 HDT Over USBC
An optional debug feature for systems during development is to implement HDT over USBC. This
implementation allows debug capability for systems in chassis without mechanical modification. Refer to the
HDT Over USBC Design Guide for more information.
14.5.4 BP Probing Header

The Break Point (BP) Probing interface is used to trigger external test equipment such as oscilloscopes and logic
analyzers. Table 117 lists the TEST signals dedicated to BP Probing.
Table 117. BP Probing Signals

1 TEST14 2 GND
3 TEST15 4 GND
5 TEST16 6 GND
7 TEST17 8 GND
9 DP_STEREOSYNC 10 GND
11 DP_DIGON 12 GND
13 DP_BLON 14 GND
15 DP_VARY_BL 16 GND

14.6 Validation Related Signals

AMD makes available support equipment for Margin Tool. The reference voltage (VREF) cable coming out of
the Margin Tool has a CD-ROM drive audio female connector.
14.6.1 Voltage Margining

Voltage margin testing, or voltage margining, ensures rated performance at upper and lower margins. This
information provides details for testing. Figure 139 shows the reference voltage (VREF) margin connections to
DIMM pins for VREFCA.
Preferred Method
Onboard Reference
· Place header on top (Processor) side VDDIO_MEM_S3

· Place header close to resistors RU
RD
VSS
VREF
1 GND
+Force
2
+Sense
3
-Sense
VREF
4
-Force
Acceptable Method
VREF
1 GND
+Force
2
+Sense
3
-Sense
4 VREF
-Force
Figure 139. Margin Tool Connector—VREF on DIMMs
The VREF connector through-hole or surface-mount layout rules for routing the +Force and −Force, shown in
Table 118, were constructed to provide guidelines for trace geometries for the +Force and −Force signals. The
designer may select geometries other than those found in Table 118 if they meet the 300-mΩ maximum
requirement.
The remaining two signals, +Sense and −Sense, can be routed with the minimum trace width and length that is
physically possible.

Table 118. Routing Requirements for VREF +Force and −Force Signals
Layer Max Trace Length Trace Width (mm) Copper Thickness (mm) Copper Weight Max Trace Resistance
(mm) (ounces) (mΩ)
Outer 114.30 0.127 0.03556 0.50 + plate 300
Outer 91.44 0.100 0.03556 0.50 + plate 300
Inner 152.40 0.254 0.01778 0.50 300
Inner 76.20 0.127 0.01778 0.50 300
Inner 30.48 0.100 0.01778 0.50 300
VREF headers have a 1.27 mm pin pitch. See Figure 140 for an example of one of the headers.
Figure 140. Margin Tool Connector
14.7 System Control Signals—Power, Reset, and Warm Reset Headers

Motherboards are required to have mechanisms that allow for the following actions:
• Controlling system power
• Issuing a cold reset (toggle SYS_RESET_L low which toggles PWR_GOOD, PCIE_RST0_L,
PCIE_RST1_L, and PWROK)
• Issuing a warm reset (toggle KBRST_L only while PWROK remains asserted)
Any type of header is permitted. Headers must be accessible with the heatsink installed and the motherboard in
the chassis. Figure 141 shows the headers for power and reset. Use either SMT or through-hole headers with pins
having a pitch of either 1.27 or 2.54 mm.
Or Or +
Figure 141. Power Button and Reset Headers
Employ proper termination to prevent unintended assertions and deassertions. Connect the following signals on
the header:
• PWR_BTN_L (for Power On)
• SYS_RESET_L (for cold reset)
• KBRST_L (for warm reset)
• PWROK

• VSS
Figure 142 shows how to include the validation header to the power and reset button circuitry.
+V
Rubato Momentary
Margining Switch PWR_BTN_L
Power Button Tool
Connection
+V
Rubato Momentary
Margining Switch SYS_RESET_L
Reset Button Tool
Connection
(Cold)
www.teknisi-indonesia.com +V
Rubato Momentary
Margining Switch KBRST_L
Reset Button Tool
Connection
(Warm)
Figure 142. Power and Reset Button Schematic
14.8 Test Points

AMD recommends that test points be placed a distance of 0.51 mm to 4.572 mm from a GND/VSS pad or via.
Figure 143 shows one type of probe used in the debug labs at AMD. This probe can accommodate variable
spacing (0.51 mm to 4.572 mm) between probe points as shown.

0.508 mm Min
TP GND
TP
GND
4.572 mm Max
Figure 143. Variable Spacing Differential Probe
14.9 Voltage Translation (Level Shifting)

Depending on the system requirements and interfaces, some signals may be of voltage levels not tolerated by the
processor. These signals may require voltage translation, or level shifting.
Voltage translation can be a difficult problem. Care must be taken to follow the data sheet worst-case
parameters. To illustrate this issue, take the I2C bus with an ideal pass FET translator. I2C uses a VOL of 0.2 ×
VDD and a VIL of 0.3 × VDD, which yields a noise margin of 0.1 × VDD.
Figure 144 shows the related voltage thresholds.

1.0 * VDD1 1.0 * VDD1
0.9 * VDD1 0.9 * VDD1
0.8 * VDD1 0.8 * VDD1
VOH
0.7 * VDD1 0.7 * VDD1
VIH
0.6 * VDD1 0.6 * VDD1
0.5 * VDD1 0.5 * VDD1

1.0 * VDD2 1.0 * VDD2
0.4 * VDD1 0.9 * VDD2 0.9 * VDD2 0.4 * VDD1
0.8 * VDD2 0.8 * VDD2 VIL
0.7 * VDD2 0.7 * VDD2
0.3 *VVDD1
OL VOH 0.3 * VDD1
0.6 *VVDD2
IH 0.6 * VDD2
0.5 * VDD2 0.5 * VDD2
0.2 * VDD1 0.2 * VDD1
0.4 *VVDD2
IL 0.4 * VDD2
VOL
0.3 * VDD2 0.3 * VDD2
0.1 * VDD1 0.2 * VDD2 0.2 * VDD2 0.1 * VDD1
0.1 * VDD2 0.1 * VDD2
3.3 V to 1.8 V 1.8 V to 3.3 V
Figure 144. Voltage Thresholds for 3.3 V and 1.5 V
An ideal pass field-effect transistor (FET) alters the high levels, but does not modify the low level. If the driver
has a VDD of 3.3 V, the VOL is 3.3 V × 0.2 = 0.66 V. If the receiver has a VDD of 1.8 V, the VIL is 1.8 × 0.3 =
0.54 V. By worst-case analysis this does not work—VIL is lower than VOL even when ignoring noise, and the
driver cannot be guaranteed to drive a valid 0 to the receiver.
While worst-case analysis often shows the circuit cannot be guaranteed to work as in the previous example,
frequently they do work reliably. Often there are parameters that are not easily considered in the simplistic
analysis shown previously. One simple example of this is the VOL level; that is probably for a maximum DC
load, which might not be present here; thus, the worst real VOL might be substantially lower than the value in the
data sheet.
Unidirectional voltage translation is by far the easiest and should be used whenever possible. Buffering usually
involves the voltage amplification of the signal, which can easily overcome the difficulty described above. If
possible, a bidirectional signal can be split into two unidirectional signals, thereby avoiding the bidirectional
problem. An example is PROCHOT_L. Consider two unidirectional high-voltage signals—one that forces the
APU into a reduced P-State and another that senses if the APU is in a reduced P-State. In this scenario, the
design is easy. On the other hand, a high-voltage bidirectional signal can be problematic.
Bidirectional voltage translation suffers from having to sense which direction is driving. If explicitly controlled,
the analysis follows the unidirectional case and can be easy if well designed. If the translator auto-detects the
direction, then it can be more difficult. One method of determining the direction is to look at the voltages
carefully and never drive the voltage far enough to be sensed as a valid input level to the device, essentially
making VIL lower than VOL and VIH higher than VOH for each side of the translator. This type of detection
places the burden of driving nearly to the rails on the devices driving to the translator. In the presence of low DC
loads, the CMOS drivers typically drive to the rails. In the presence of high DC loads, the drivers are able to
reach the VIL and VIH levels of this type of translator.
Design is highly dependent on the specific parts used and the specific implementation. Such detailed design
considerations are beyond the scope of these guidelines. Take sufficient care with voltage translation circuits to
ensure reliable operation under all conditions of voltage levels, voltage sequences, and changes of power states.

Figure 145 shows a voltage translator for single-ended nets. The circuit is based on a pass transistor and works in
either direction. Unidirectional nets may use two cascaded inverters. For low-voltage applications, an integrated
solution may be required.
VDD_1 VDD_2
R1 R3 R5
V1
Processor System
D1
R4 C1
VDD_1 < VDD_2
VDDIO_MEM_S3 VDD_2
R1 R3 R5
V1
Processor System
D1
R4 C1
VDDIO_MEM_S3 < VDD_2
Figure 145. Voltage Translation Circuit Example for Single-Ended Signals
Figure 146 shows a voltage translator for SB-TSI. The circuit is based on pass transistors and works in either
direction. For low-voltage applications, an integrated solution may be required to achieve proper threshold
levels.

VDD_1 VDD_2
R1 R2 R3 R5 R6
V1
SB-TSI SCL KBC SCL
D1
V2
SB-TSI SDA KBC SDA
D2
R4 C1
VDD_1 < VDD_2
VDDIO_MEM_S3 VDD_2
R1 R2 R3 R5 R6
V1
SB-TSI SCL
D1
KBC SCL
V2
SB-TSI SDA KBC SDA
D2 R4 C1
VDDIO_MEM_S3 < VDD_2
Figure 146. Voltage Translation Circuit for SB-TSI
Table 119 lists recommended values for the components in Figure 146.
Table 119. Voltage Translator Recommended Component Values

Component Recommended Value
R1 through R6 1 kΩ
C1 0.1 µF
14.10 SMBus Interface

The FP6 processor supports two SMBus ports.
The SMBus ports can be used to connect a variety of different devices.
The following restrictions apply to the different SMBus ports:

• SCL0/SDA0 is the SMBus port in the S0 power domain. Use this port for generic SMBus devices that reside
in the S0 power domain. DIMM SPD can only be connected to SMBUS0.
• SCL1/SDA1 is the SMBus port in the S5 power domain. Use this port for either Option 1: an Alert Standard
Format (ASF)-capable device that resides in the S5 power domain or Option 2: a Synaptics InterTouch
device.
Figure 147 shows the schematic and layout guidelines for SMBus interface signals.
3.3V_S0
Processor Memory Slots

SCL0 SCL
SDA0 SDA
Clock Generator
SCL
SDA
3.3V_S5
Option 1
ASF Device -
SCL1 SCL Onboard or on
SDA1 SDA
PCIe® slot
Option 2
SCL Synaptics
SDA InterTouch Device
Figure 147. SMBus Interface Routing Model

Table 120 lists routing rules for the SMBus interface signals.
Table 120. Routing Rules for SMBus Interface
SCL0/ Trace Width ≥ 0.1 mm ≥ 0.1 mm

SCL1/ Trace Spacing ≥ 0.1 mm ≥ 3H
SDA0/
SDA1/
14.11 Sensor Fusion Hub (SFH)

Refer to the AMD FP6 SFH Design Guide PID# 56467 for Sensor Fusion Hub implementation details.
Figure 148 shows the schematic and layout guidelines for SFH signals.

APU Sensor
SFH1_SCL Fusion
SFH1_SDA Devices
SFH_IPIO39
SFH_IPIO41
SFH
SFH_IPIO271
SFH_IPIO272
SFH_IPIO273
SFH_IPIO274
Figure 148. SFH Routing Model
The termination component values for SFH are listed in Table 121.
Table 121. Component Table—SFH Termination
Signal Name Value1 Tolerance Package Termination
SFH1_SCL 2.2 kΩ 5% 0402 VDD_18_S5

SFH clock
SFH1_SDA 2.2 kΩ 5% 0402 VDD_18_S5

SFH data
SFH_IPIO39 10 kΩ 5% 0402 VDD_33_S5
SFH_IPIO41
10 kΩ 5% 0402
SFH sensor
VDD_33_S5
SFH sensor
SFH_IPIO271 10 kΩ 5% 0402 VDD_33_S5

SFH sensor
SFH_IPIO272 10 kΩ 5% 0402 VDD_33_S5

SFH sensor
SFH_IPIO273 10 kΩ 5% 0402 VDD_33_S5

SFH sensor
SFH_IPIO274 10 kΩ 5% 0402 VDD_33_S5

SFH sensor
Note: 1. Termination resistor value is dependent on implementation, a common value is listed.
Table 122 lists routing rules for the SFH signals.

Table 122. Routing Rules for SFH
SFH1_SCL Trace Width ≥ 0.1 mm ≥ 0.1 mm

SFH1_SDA Trace Spacing ≥ 0.1 mm ≥ 3H
SFH_IPIO39
SFH_IPIO41
SFH_IPIO271
SFH_IPIO272
SFH_IPIO273
SFH_IPIO274

14.12 LPC Bus Interface

The FP6 processor provides a Low Pin Count (LPC) interface to support legacy I/O devices. This interface can
be used to connect to LPC devices such as Super I/O (SIO), Embedded Controller (EC), Trusted Platform
Management (TPM), or memory Flash ROM devices. The interface can support up to two DMA or Bus
Mastering devices.
The interface is powered in S0 through S5 states. In S3 and S5 states the LPC signals LDA[3:0] and LFrame_L
are tri-stated. LPCCLK0 and LPCCLK1 are driven low in S3, S4, and S5 states. LPC clock 0 is free running in
Sx states if the integrated microcontroller (IMC) is enabled. LPC clock 0 should be connected to LPC devices
that are powered in S5 when the APU IMC is enabled. Connect LPC devices reset input to LPC_RST_L.
The LPC interface supports up to two LPC clocks that can be connected directly to the LPC devices. Serialized
IRQ (SERIRQ) and Power Management Event (PME_L) protocols are also supported.
Figure 149 shows the schematic and layout guidelines for LPC interface signals.
Processor LPC ROM

0" < L1 < 1.0"
LFRAME#
LPCPD#
LAD[3:0]
LPC_RST_L RST#
L1
LPC DEVICE
LFRAME#
CLKRUN#
LPCPD#
LAD[3:0]
SERIRQ
LDRQn+1_L LDRQ#
LPME#
RST#
LPC DEVICE
CLKRUN#
LFRAME#
LDRQn_L
LAD[3:0]
LDRQ#
SERIRQ
LPCPD#
LPME#
RST#
LPC_PD_L
CLKRUN_L
PME_L
SERIRQ
LFRAME_L
LAD[3:0]
Notes:
* IMC disabled: LPC devices can reside in either the S0 or S5 ACPI power domain.
* IMC enabled: LPC devices can reside in the S0 ACPI power domain only if IMC/System BIOS reside in SPI ROM.
If LPC ROM is used for IMC/System BIOS, then all LPC devices must reside in the S5 ACPI power domain.
Figure 149. LPC Interface Routing Model
Table 123 lists routing rules for the LPC interface signals.
Table 123. Routing Rules for LPC Interface
LFRAME_L Trace Width ≥ 0.1 mm ≥ 0.1 mm

LPCCLK0, LPCCLK1,
LPC_CLKRUN_L,
LPC_PD_L/,
LPC_PME_L/,

Table 123. Routing Rules for LPC Interface (continued)

LPC_RST_L, Trace Spacing ≥ 0.1 mm ≥ 3H
LAD0, LAD1, LAD2,

LDRQ0_L,
SERIRQ/
14.13 LPC Clock Interface

The FP6 processor provides LPC clocks for use by system LPC devices. Note that these clock outputs are
available whether the processor is configured for internal or external clock-generator modes. Figure 150 shows
the schematic and layout guidelines for the LPC clock-interface signals.
APU
* Note: Connect LPCCLK0 to LPC ROM
if EC is enabled.
Motherboard
LPCCLKn *
LPC Device
Motherboard
LPCCLKn+1
LPC Device
Figure 150. LPC Clock Interface Routing Model
• Connect LPC devices to LPC clocks.

• Connect LPC clock 1 to LPC devices that are powered in S0.
• Connect LPC clock 0 to LPC devices that are powered in S5 only if the integrated microcontroller (IMC) is
enabled.
Table 124 lists Clock to LPC device connections.
Table 124. Clock to LPC Device Connections
Clocks for LPC Devices LPC Device 1 LPC Device 2
LPCCLK0 Use LPCCLK0 if LPC device 1 is on S5 rail and IMC

is enabled
LPCCLK1 Use LPCCLK1 if LPC device 1 is on S0 rail Use LPCCLK1 if LPC device 2 is on S0 rail and
LPCCLK1 is available
Table 125 lists routing rules for the LPC Clock interface signals.
Table 125. Routing Rules for LPC Clock Interface
LFRAME_L Trace Width ≥ 0.1 mm ≥ 0.1 mm

LPCCLK0, LPCCLK1, Trace Spacing ≥ 0.1 mm ≥ 3H
LPC_CLKRUN_L,

Table 125. Routing Rules for LPC Clock Interface (continued)

LPC_PD_L/, Length Limits ≤ 25.4 mm

LPC_PME_L/, Maximum trace
LPC_RST_L, length from source
pin to series resistor:
LAD0, LAD1, LAD2,
LDRQ0_L,
SERIRQ/

14.14 Serial Peripheral Interface (SPI)

The FP6 processor supports Serial Peripheral Interface (SPI), which is typically used for the system BIOS
function. Figure 151 shows the schematic and layout guidelines for SPI signals.
VDD_18_S5
A diode is only required if in-circuit

ROM programming is supported.
Processor SPI ROM
VDD
SPI_HOLD_L HOLD#
SPI_CS1_L CE#
Connected to Chip Select pin of
SPI_CS2_L second SPI device
SPI_WP_L WP#
SPI_CLK SCK
SPI_DO SI
SPI_DI SO
Embedded Controller
SPI_ROM_REQ GPIO/REQ#
REQ
SPI_ROM_GNT GPIO/GNT#
GNT
Figure 151. SPI Routing Model

Table 126 lists routing rules for the SPI signals.
Table 126. Routing Rules for SPI
SPI_TPM_CS_L Trace Width ≥ 0.1 mm ≥ 0.1 mm

SPI_HOLD_L Trace Spacing ≥ 0.1 mm ≥ 3H
SPI_WP_L
SPI_CLK Maximum Trace Length ≤ 101.6 mm
SPI_CS1_L
Length Matching N/A ≤ 12.7 mm
SPI_CS2_L
SPI_DI (to SPI_CLK)
SPI_DO
SPI_ROM_GNT
SPI_ROM_REQ

The FP6 processor supports multiple devices on the Serial Peripheral Interface (SPI). Figure 152 shows the
schematic and layout guidelines for multiple SPI devices. See the PCB Planning Chapter for general routing and
layout guidelines.
Processor SPI Device #1

SPI_CLK CLK
SPI_DI DATA OUT
SPI_DO DATA IN
SPI_CS1_L CE#
VDD VDD
SPI Device #2
CLK
DATA OUT
DATA IN
SPI_CS2_L CE#
VDD
Figure 152. Multiple SPI Device Routing Model
Note: If an SPI device does not tri-state DATA OUT use a’ buffer on the SPI DATA OUT signal gated by
CHIP SELECT (CE#).
Table 127 lists routing rules for multiple SPI devices.
Table 127. Routing Rules for Multiple SPI Devices
Trace Width ≥ 0.1 mm ≥ 0.1 mm

SPI_CLK
SPI_CS1_L
SPI_CS2_L Maximum Trace Length Implementation dependent
SPI_DI
Length Matching N/A Implementation dependent
SPI_DO
(to SPI_CLK)
14.14.1 SPI ROM Sharing

The FP6 processor supports Serial Peripheral Interface (SPI), which is typically used for the system BIOS
function. Figure 153 shows a block diagram of SPI ROM sharing signals.
The FP6 APU supports a SPI ROM configuration that allows sharing one ROM between the APU and an
onboard discrete device, such as an embedded controller (EC) (see Figure 153). This SPI ROM configuration
support reduces system cost. Shared-ROM configuration: The EC powers up when system is powered on. The
VDD_18_S5 rail is on, and other APU power rails are off, which tri-states the APU inputs and outputs (with the
exception of SPI_CLK which requires an isolation FET controlled by VDD_33_S5 to avoid contention), and
allows the EC to perform a fetch of the firmware code without contention from the APU. This occurs only once
as the EC stores the fetched firmware code in the EC memory. When the EC firmware load is complete, the EC
powers down the VDD_18_S5 rail and waits for a wake event to power up the system. Isolate APU SPI_CLK
pin while APU VDD_18_S5 is on and VDD_33_S5 is off. Connect an N-Channel MOSFET with Source to
APU SPI_CLK pin, Drain to SPI clock signal (ROM, EC, etc.), Gate to VDD_33_S5.

Embedded Controller (EC)

FLCS0#
FLCLK
FLDATAOUT
FLDATAIN
GPIO GPIO/REQ#
GPIO/GNT#
1.8V Processor
1.8 V S5
Regulator Power
EN
VDD_18_S5
Type 2 FP4 SPI ROM

Processor SPI_ROM_GNT
VDD
3.3 V SPI_ROM_REQ VDD_33_S5
Regulator SPI_HOLD_L HOLD#
SPI_CS1_L CE#
Connected to Chip Select pin of
SPI_CS2_L second SPI device
SPI_WP_L WP#
SPI_CLK SCK
DNI
SPI_DO
SPI_DO/GPIO163 SI
SPI_DI
SPI_DI/GPIO164 SO
Figure 153. SPI ROM Sharing Routing Model
14.15 Enhanced Serial Peripheral Interface (eSPI)

The FP6 processor supports Enhanced Serial Peripheral Interface (eSPI).
Table 128 lists the eSPI features of the FP6 processor.
Table 128. eSPI Features of FP6 Processor
eSPI Feature Support FP6 Processors
eSPI V0.75 spec compliant Yes
ALERT_L pin support In-band ALERT and dedicated ALERT Event supported
Data transfer over eSPI Bus support Single, Dual, and Quad data transfer
16.67MHz (Default)
Bus Speed 33MHz
66.67MHz (Max speed)
I/O Voltage 1.8 V
eSPI Device Configuration Support One Master and One Slave configuration supported only
Flash Channel support Supported with software assistance
Note: Not all features listed in Revision 0.75 eSPI specification are supported.
Table 129 lists the eSPI signal pin names and descriptions.
Table 129. eSPI Signal Descriptions
Pin Name Direction Description
O eSPI Clock: This pin provides reference timing for all serial input and output operations.
ESPI_CLK
Note: Shared by all slave devices
ESPI_CS_L O eSPI device Chip Select#: Drive ESPI_CS_L low to select an eSPI device for transaction

Table 129. eSPI Signal Descriptions (continued)

Pin Name Direction Description
I/O eSPI device Input Data to processor

Number of pins used depends on I/O mode:
• Single I/O mode:
• ESPI_DAT0
• Dual I/O Mode:
• ESPI_DAT[1:0]
• Quad I/O Mode:
• ESPI_DAT[3:0]
ESPI_DAT[3:0]
eSPI Output Data from processor to eSPI device
Number of pins used depends on I/O mode:
• Single I/O mode:
• ESPI_DAT0
• Dual I/O Mode:
• ESPI_DAT[1:0]
• Quad I/O Mode:
• ESPI_DAT[3:0]
I eSPI Slave ALERT Input:

This pin is used by eSPI slave to request service from eSPI master.
ESPI_ALERT_L
This pin is optional for Single Master-Single Slave configuration when I/O [1]
I
Note:
can be used to signal the ALERT event.
Side Band signal: Use for Slave to reset the System. Use PCIE_RST0_L if ESPI slave
ESPI_RESET_L device requires a ESPI Reset signal from ESPI Master. (This pin is part of ACPI, not ESPI
controller)
Figure 154 shows the schematic guidelines for eSPI signals.

VDD
Processor
RPU
eSPI Device
ESPI_CLK CLK
RS
ESPI_DAT[3:0] I/O[3:0]
ESPI_CS_L CS#
ESPI_ALERT_L ALERT#
ESPI_RESET_L RESET#
Figure 154. eSPI Single Master-Single Slave with eSPI_RESET_L Master to Slave Routing Model
SPI and eSPI share CLK and DATA pins. Loading, routing, placement of series resistors, and how to split traces
between the SPI ROM and eSPI device, all must be considered to optimize signal integrity. The eSPI CLK and
DATA signals must be routed over a solid reference plane (VSS preferred). Keep the clock frequency low (e.g.
33MHz or lower) if loading is large. See the Edge Rates and Signal Quality section for more information. Table
130 lists routing rules for the eSPI signals.

Table 130. Routing Rules for eSPI Bus

Trace Width ≥ 0.1 mm ≥ 0.1 mm
Maximum Trace Length ≤ 101.6 mm

ESPI_CLK
ESPI_DAT[3:0] Length Limits ≤ 25.4 mm
ESPI_CS_L ESPI_CLK maximum trace
ESPI_ALERT_L length from source pin to
ESPI_RESET_L series resistor:
Length Matching N/A ≤ 12.7 mm

(to ESPI_CLK)
The FP6 -processor supports muxing eSPI data onto the LPC LAD pins. If the LPC interface is not used, these
pins can be configured for eSPI to connect to an eSPI EC, for example. The SPI ROM should remain on the FP6
-processor SPI pins as this is the default location for the processor to fetch from. The EC may still connect a
shared ROM SPI interface to the SPI ROM. The pre-boot flash sharing access for the EC is still supported, as is
the runtime SPI access by SPI_ROM_REQ/ SPI_ROM_GNT or eSPI flash access channel. Figure 155 shows
schematic guidelines for connecting REQ/GNT to the EC and CS_L signals.
Note: S0/S5 isolation shown in Figure 155 may not be required if the EC can handle the eSPI pins being low
without leakage when the S0 rails are low. SPI_CLK requires isolation for ROM sharing. Refer to the
SPI ROM Sharing section.
Processor
Embedded Controller (EC)
SPI_ROM_REQ ROM_REQ
SPI_ROM_GNT ROM_GNT
S0/S5
1.8V S0 isolation 1.8V S5
LPC/SPI/(ESPI) ESPI SHD SPI
S0 1.8V/3.3V S5 1.8V S5 1.8V
ROM
1.8V S5
SPI
S5 1.8V SHD_CS#
TPM FP
SPI/ESPI 1.8V S5 1.8V S5

SPI SPI
S5 1.8V S5 1.8V S5 1.8V
SPI_CS1_L
SPI_DI/GPIO164
SPI_CS2_L/ESPI_CS_L
SPI_TPM_CS_L
SPI_CS3_L
Figure 155. LPC eSPI Data Mux

14.16 Thermal Management Signals

This section explains the various thermal monitoring and thermal alarm output signals. The processor has a
thermal sensor with which the on-chip temperature can be monitored. The processor also has thermal-monitoring
logic incorporated within that trips an output to shut down the system if a thermal alarm temperature is reached.
14.16.1 THERMTRIP_L
This pin is a thermal alarm output that is used to power down the system and prevent processor damage due to
overheating. THERMTRIP_L is an open-drain processor output signal and requires an external pull-up resistor.
This signal may need voltage level translation if a device receiving this signal is not compatible. See termination
voltage(s) for THERMTRIP_L in Table 111.
The system must power off the processor within a specified time after THERMTRIP_L is asserted. This time
limit is specified in the Electrical Data Sheet for AMD Family 17h Models 60h-6Fh Processors and the
Electrical Data Sheet for AMD Family 19h Models 50h-5Fh Processors .
FP6 processors require the system return to G3 after a THERMTRIP_L condition or they will fail to boot.
14.16.2 PROCHOT_L
PROCHOT_L is an active-low signal, which is used by the processor as an input. External hardware can assert
PROCHOT_L to reduce processor power consumption by forcing HTC activation. For example, if the VDD
power supply is getting near the maximum allowed temperature, it can assert PROCHOT_L. This forces HTC
and reduces processor power, thus reducing the load on the VDD supply and helping it remain within
specification. Pull up the PROCHOT_L signal to VDD_33.
Enabling PROCHOT_L may require action by the firmware. See the Processor Programming Reference (PPR)
Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors (NDA) for details regarding
configuration of PROCHOT_L.
See Figure 156 for an example schematic of PROCHOT_L.
VDD_33
R1
Processor
Level REGULATOR_HOT_L
PROCHOT_L
(Open Drain) Shifter MEMORY_HOT_L
Level
VDD_5V Shifter AND Gate
R2
PWM_Controller
Figure 156. Example PROCHOT_L Schematic

14.16.3 SIC, SID and ALERT_L

SIC, SID and ALERT_L are pins used in the AMD Side Band Interface. SIC, SID, and ALERT_L pins need
pull-up resistors on the motherboard. An on-die thermal device is provided on the processor. The on-die thermal
device readout can be used for thermal-based system management. An internal circuit monitors the temperature,
and a parameter called TCONTROL (temperature control value) may be read through the SIC and SID bus. The
thermal management circuit utilizes TCONTROL readout values to control the cooling system.
For more information on the AMD SB-TSI bus, refer to the Processor Programming Reference (PPR) for AMD
Family 17h, Models 60h-6Fh Processors (NDA) and the Preliminary Processor Programming Reference (PPR)
for AMD Family 19h Model 50h, Revision A0 Processors (NDA).
See Figure 157 for an example schematic of an AMD Validation Environment Header.
VDD VDD
4.7k
1k 1k 1k
Management
Subsystem
Processor
SMB_CLK
SCL SIC
SMB_DAT
SDA SID
PU4.7k
ALERT_L
SMB_ALERT ALERT_L
nc
GND
GND
(No Pop) PROCHOT_L
Place header on accessible side SA[0]
Figure 157. Schematic Diagram for AMD Validation Environment Header
14.17 General Purpose I/O

The GPIO pins of the APU are multiplexed with other functions.
• AGPIO: Advanced GPIO - can be used for interrupt, wake, or GPIO.
• EGPIO: Enhanced GPIO - can be used only for GPIO.
For information on how to configure the GPIO pins for the desired functions for FP6 processors, see the
Processor Programming Reference (PPR) for AMD Family 17h, Models 60h-6Fh Processors (NDA) and the
Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 50h, Revision A0 Processors
(NDA).
For specific information about GPIO pin types, levels, and default states see the FP6 Processor Functional Data
Sheet.

15 Power Distribution Network Design Guidelines

15.1 Power Distribution Network Design Guidelines
The purpose of the -based motherboard power distribution network (PDN) is to provide regulated voltage at
sufficient current levels to satisfy the requirements of the motherboard components. Each PDN consists of a
voltage regulator (VR), bulk electrolytic capacitors, distributed SMT ceramic capacitors, copper planes and
copper interconnects. Each element plays a specific role in the overall power delivery. Table 131 lists the
relative performance of the various elements.
Refer to the regarding specific voltage and current specifications.
Table 131. Attributes of PDN Components

Component1 Capacitance ESR ESL
Electrolytic Capacitors 1000s µF 10s mΩ 1s nH
Ceramic Capacitors 100s µF 100s mΩ 10 to 100 pH
Copper Plane 100s pF <10 mΩ <1 nH
Copper Interconnects < 10 pF <10 mΩ 1s nH
Note: 1. Component values are for illustrative purposes only.
The goal of the power-distribution scheme is to best use all layers of the motherboard to reduce the inductance of
the planes, provide better power profiles as well as unbroken and continuous reference planes for high-speed
signals.
This topic discusses the decoupling requirements for all and memory power supplies for -based platform. These
power requirements assist the motherboard designer in properly laying out and managing the power supplies that
are necessary to support the s. However, this chapter does not supersede the data sheet. Refer to the regarding
specific voltage and current specifications. Likewise, this document does not replace applicable design guides
from the chipset vendors.
15.2 High-Frequency Design Considerations

Capacitor selection, placement, and orientation are critical for optimizing the power distribution network
performance. Ceramic capacitors are capable of responding to short-duration, high-frequency current transients.
As such, it is necessary to select the proper ceramic (high-frequency) capacitors and place them as close as
possible to the final load while keeping the interconnect length to a minimum. The goal is to minimize
inductance. Device orientation also plays a role in inductance.
15.2.1 Capacitor Selection

High-frequency capacitors are often multi-layered ceramic (MLC) in surface-mount packages. Due to their
construction, MLCs have a lower effective series inductance (ESL) than their predecessors. ESL is the most
critical factor that directly limits the effectiveness of the power delivery network (PDN). Higher ESL contributes
to higher power and ground noise.
Designers may replace a capacitor with another having a smaller body size, provided it has the same capacitance
value and it is constructed of the same dielectric material. Never use capacitors with longer bodies if capacitors
with shorter bodies are specified, as the inductance is likely to be higher.
The total inductance of a chip capacitor is determined both by length to width ratio and inductance of the
electrodes. A 1210 capacitor therefore has lower inductance than a 1206 one.
• Capacitors with wider body sizes have a lower parasitic inductance than narrower ones of equivalent length.
Power Distribution Network Design Guidelines 261

• Capacitors with longer body sizes have higher parasitic inductance than shorter ones of equivalent width.
Some capacitor vendors offer a transposed body style, for example, a 0508 (transposed) compared to a 0805
(standard) package. The transposed body is shorter and wider than the standard capacitor. The parasitic
inductance is greatly reduced by this change. Refer to Figure 158(a) and (b) for body-style comparison. A third
body style is shown in Figure 158(c). The multi-terminal ceramic capacitor (MTCC), also known as an
interdigitated capacitor (IDC), has greatly reduced mutual inductance.
- + - +
0805
0508 0508 MTCC
+ - + -
(a) (b) (c)

Figure 158. Capacitor Aspect Ratio—Standard, Transposed, and Multi-Terminal
Capacitors are specified according to the Electronic Industries Association (EIA) Standard 198. There are three
classes of capacitors—Class I, Class II, and Class III. This document references only two:
• Class I - C-Zero-G (C0G), Ultra-Stable Capacitor is made from materials not sensitive to temperature and has
virtually no aging affects.
• Class II - X5R, Stable Capacitor has very low aging tolerance. The X6R and X7R, which have wider
temperature ranges, may also be used.
15.2.2 Capacitor Placement

Distributed SMT capacitors are best suited for responding to fast, short-duration current transients. The smaller
packages, 0402 and 0603, typically respond the quickest. A simple rule is to place the capacitors with the lowest
values closest to the load (close to the processor or next to the DIMMs). The smaller body sizes are least likely
to interfere with the dense routing in those areas. Next, place higher-value capacitors as close to the processor as
possible. However, due to their larger body size, place them farther away from the processor than the smaller
(lowest value) capacitors.
15.2.3 Capacitor Orientation

Capacitor orientation contributes to the overall performance of the PDN. Where possible, align the vias of the
processor and the decoupling capacitors such that the currents form loops, as illustrated in Figure 159.

Processor
Figure 159. Alignment of VDD and VSS Vias to Minimize Mutual Inductance
15.2.4 Capacitor Interconnect

AMD recommends side escapes over end escapes. Side escapes significantly reduce the self-current loop area,
allowing the best possible performance from the capacitor. For a comparison of the difference in area, see Figure
160. Additionally, AMD recommends the use of several plated through-hole (PTH) vias whenever possible to
reduce capacitor-connection impedance to the power and ground planes on the motherboard.

Inductive Loop
(a)
MLC (Multi Layer Capacitor)

0805
with one side escape
Inductive
Loop
(b)
LICC (Low Inductance Chip Capacitor)

0508
with multiple side escapes
Inductive
Loop
(c)
- + - +
0508
MTCC (Multi-Terminal Chip Capacitor)
+ - + -
with multiple side escapes
+ - + - =
Effective
Inductive
Loop
=
(d)
Figure 160. Decoupling Interconnection Comparison
AMD recommends that the traces from the capacitor pads to the PTH vias be as wide as possible. They also need
to accommodate the placement of additional vias to minimize inductance. Using copper pours or mini planes on
the external (top—or processor side—and bottom) signal layers further establishes a solid, low-inductance
connection. Because signals are not routed through the center of the area beneath the processor, these mini
planes are not likely to interfere with signal routing.

L
Inductance per segment is governed by trace
0805 W geometry. Most importantly, the Length-to-
Width ratio of the trace (L:W) is the largest
Segment Segment
Inductance Inductance
factor in controlling and reducing decoupled-
trace inductance.
L:W = 2:1
L L
AMD recommends that the Length-to-Width ratio
of the trace (L:W) does not exceed 2:1 on either
W 0805 W decoupled trace.
A higher ratio of 2:1 causes increased
inductance, common-mode (CM) ground noise,
and EMI radiated emissions.
L:W = 1:1
W L
L W
0508
0805
W
AMD recommends that the Length-to-Width ratio of
- + - +
L the trace (L:W) be 1:1 whenever possible, for MLC,
0508 LICC, and MTCC capacitor-package types.
+ - + -
Figure 161. Length-to-Width Ratio of Decoupling Interconnection
AMD recommends that the traces from the capacitor pads maintain a controlled aspect ratio of trace length and
width. AMD recommends that the Length-to-Width ratio of the trace (L:W) does not exceed 2:1 on either
decoupled trace.
Trace segments that are higher than a L:W ratio of 2:1 tend to cause increased inductance, common-mode (CM)
ground noise, and EMI radiated emissions.

Inductance of copper pour connections

is mainly governed by distance from
capacitor to the closest via to power or
ground plane.
Each decoupling capacitor must have

one dedicated ground via connected
directly to ground plane(s), located within
the ground copper pour or mini plane
and within 2.0 mm of the ground pin.
Each decoupling capacitor must also

have one dedicated power via connected
directly to power plane(s), if applicable,
located within the power copper pour or
mini plane and within 2.0 mm of the
power pin.
Device Pin Decoupling

Capacitor
SO-DIMM0
SO-DIMM1
Figure 162. Copper Pour—Mini-Plane Decoupling Interconnection
Using copper pours or mini planes on the external layers (top or processor side and bottom) for decoupling can
establish a solid, low-inductance connection and loop impedance. It is important to connect these capacitors
correctly to their respective power and ground vias using connections as short as possible.
AMD recommends that each decoupling capacitor have one dedicated ground via within the ground copper pour
or mini-plane, connected directly to the ground plane. Locate all ground vias very close to the capacitor ground
pin.
AMD recommends that each decoupling capacitor have one dedicated power via within the copper pour, and
connected directly to the power plane.
15.2.5 Guideline Adherence

Although other matters sometimes play a role in proper processor functionality, following the exact decoupling
capacitor and layout recommendations provided in this document helps to ensure correct operation of the
processor.
Capacitor combinations other than those listed in this document may also lead to proper operation of the
processor. Such success depends on the quality and specific mix of decoupling capacitors, the quality of the
power-network layout, and the regulator design.
If a design deviates from the stated recommendations, it must be tested in accordance with the AMD System
Validation Manual (SVM). The SVM provides details about the electrical test procedures. Perform these tests to
help ensure all processor voltage requirements are met. Refer to the processor data sheet for the requirements.
AMD has no liability for any deviations from the design as presented in this Design Guide.

A test plan should be provided by the motherboard design/test team and made available at the time of the design
review.
15.2.6 Component Substitution

Designers may choose to replace one capacitor with another capacitor if the replacement meets the following
criteria:
• One of any recommended EIA Standard 198 Class II dielectric materials (X7R, X7S, X6S, X5R)
• One with the same capacitance value
• One with a smaller body size
Note: This type of substitution is not considered a deviation from the guidelines because smaller components
typically have lower ESL values, which makes them more effective in suppressing noise.
Any other substitutions are considered a deviation from the guidelines.
Never substitute decoupling capacitors with another capacitor with a larger body size (even of same value and
material type). Larger components typically have larger ESL values. Larger ESL values make these larger
capacitors less effective in suppressing the noise on the power supply (generated by the processor) to limits
listed in the data sheets.
Capacitor reliability is dependent on operating voltage and operating temperature. When selecting lower-rated
capacitors, consider the manufacturer's voltage exponent and temperature exponent. Contact the capacitor
supplier for details.
15.2.7 Routing and Decoupling

For processor power, the optimum location for the decoupling capacitors is the area directly under the processor
on the bottom layer of the motherboard. This area provides maximum capacitance and minimum inductance. To
maximize the number of capacitors in this area, use 0805 or 0603 body styles, which offer a good combination
of capacitance values per available board area.
Once all the available area under the processor is filled with capacitors, the next best location to place additional
capacitors is on the topside (processor side) of the motherboard. Place these capacitors as close to the processor
as possible without interfering with the routing.
A power plane provides the processor core power. It is recommended that the separation between the power-
plane and ground-plane pair be kept to a minimum. Take care to avoid heavy perforations, which are the result
of either an excessive placement of components or of vias that are not devoted to decoupling of the core power.
Make the processor power plane at least as wide as the processor.
Maximize the copper area used in the attachment of the power FETs. This helps in the thermal management of
the device. Refer to the FET supplier data sheet for specific copper-area recommendations.
The high-frequency capacitors are located as close to the processor as possible on the backside of the board. All
the capacitors listed in this chapter that are placed between the processor and the VRMs must be located as close
to the processor as possible.
15.3 Power Generation and Distribution Guidelines

The guidelines for power generation and distribution design include placement, routing, and decoupling
recommendations for the processor-related power supplies.
Refer to the FP6 Infrastructure Roadmap regarding specific voltage and current specifications.
Figure 163 shows the various power connections for the processor and a dual-plane supply.

Regulators Processor
SVT SVT0
SVC SVC0
SVD SVD0
APU_VDD_RUN VDDCR
SENSE_H VDDCR_SENSE
SENSE_L VSS_SENSE_A Legend
Routed as differential pair
APU_VDDCR_SOC VDDCR_SOC
Required
SENSE_H VDDCR_SOC_SENSE
Return Path
SENSE_L VSS_SENSE_A
Optional
Return Path
APU_VDDIO_VPH VDDIO_VPH
Filter Optional Power

Source
APU_VDDIO_SUS VDDIO_MEM_S3
VDDBT_RTC_G RTC Battery
VDDP_RUN VDDP
VDDP_ALW VDDP_S5
SENSE_H VDDP_SENSE
SENSE_L VSS_SENSE_B
SENSE_L
+1.8 V ALW, VDDIO_AUDIO
+1.5 V ALW, or
+1.2 V ALW
+1.8 V RUN VDD_18 VPP

+1.8 V ALW VDD_18_S5 Memory
VDD_33 VDDIO_
+3.3 V RUN
VDD_33_S5 MEM_S3 VTT VSS
+3.3 V ALW
VSS
VTT
+2.5 V
VPP
MGT
Figure 163. Power Connections for Processor and Dual-Plane Supply

15.3.1 VDDP Power Delivery and Decoupling

VDDP is the supply voltage for PCIe GPP, PCIe GFX, DisplayPort, and SATA PHY logic. Use VDDP_SENSE
and VSS_SENSE_B to regulate this voltage rail. See Table 132 for a detailed list of required capacitors for
VDDP. The voltage for VDDP is listed in the AMD Family 17h Models 60h-6Fh Processor Power and Thermal
Data Sheet.
15.3.2 VDDP_S5 Power Delivery and Decoupling

VDDP_S5 is the voltage rail for the USB physical layer. Use VDDP_S5_SENSE and VSS_SENSE_B to
regulate this voltage rail. See Table 132 for a detailed list of required capacitors for VDDP_S5. The voltage for
VDDP_S5 is listed in the AMD Family 17h Models 60h-6Fh Processor Power and Thermal Data Sheet.
15.3.3 VDD_18 Power Delivery and Decoupling

VDD_18 is the 1.8V supply voltage rail for analog circuits. If a switch mode regulator is used to power the
VDD_18 rail, the switch mode regulator should ensure the steady-state switching voltage ripple measured at the
processor balls meets the specification listed in the FP6 Infrastructure Roadmap. See Table 132 for a detailed list
of required capacitors. The voltage specifications for VDD_18 are listed in the FP6 Infrastructure Roadmap.
15.3.4 VDD_18_S5 Power Delivery and Decoupling

VDD_18_S5 is the 1.8V always on supply voltage rail for analog circuits. See Table 132 for a detailed list of
required capacitors for VDD_18_S5. If a switch mode regulator is used to power the VDD_18_S5 rail, the
switch mode regulator should ensure the steady-state switching voltage ripple measured at the processor balls
meets the specification listed in the FP6 Infrastructure Roadmap. The voltage specifications for VDD_18_S5 are
listed in the FP6 Infrastructure Roadmap.
15.3.5 VDDIO_VPH Power Delivery and Decoupling

VDDIO_VPH is the dedicated supply voltage for DisplayPort 0 and PCIe phys. When DisplayPort 0 is used for
eDP, the source of VDDIO_VPH may be 1.2V nominal and can be the same source as VDDIO_MEM_S3 (if
1.2V for DDR4) or another 1.2V source if available. This allows lower power and better battery life. When
DisplayPort 0 is used for DP or TMDS, the source of VDDIO_VPH must be 1.8V nominal and can be the same
source as VDD_18. This ensures compliance for external display interfaces. VDD_18 may also be used when
DisplayPort 0 is used for eDP if a 1.2V source is not available. See Figure 163 for VDDIO_VPH connection
options. If a switch mode regulator is used to power the VDDIO_VPH rail, the switch mode regulator should
ensure the AC ripple voltage measured at the processor balls meets the specification listed in the FP6
Infrastructure Roadmap. See Table 132 for a detailed list of required capacitors. The voltage specifications for
VDDIO_VPH are listed in the FP6 Infrastructure Roadmap.
15.3.6 VDDIO_MEM_S3 Power Delivery and Decoupling

VDDIO_MEM_S3 is the main power supply for the DIMMs and also an auxiliary supply for the DDR section of
the processor. Make VDDIO_MEM_S3 a plane that runs beneath the DIMMs and partially under the processor.
Place the smallest-valued (and smaller body sized) capacitors near the processor; follow these with larger
capacitors. Because VDDIO_MEM_S3 provides power to the DIMMs as well, placement of additional
decoupling capacitors near each DIMM connector may be required. Check with the DIMM manufacturer for
motherboard decoupling capacitor quantity, value, and placement recommendations.
See Table 132 for a detailed list of required capacitors for VDDIO_MEM_S3 .

15.3.7 VDDCR_SOC Power Delivery and Decoupling

VDDCR_SOC is the supply voltage for the SOC core logic. See Table 132 for a detailed list of required
capacitors for VDDCR_SOC.
15.3.8 VDDSPD Power

VDDSPD is the power supply for the Serial presence detect (SPD) device on a DIMM. Refer to the
specification from the DIMM vendor for the required VDDSPD voltage.

15.3.9 Decoupling Capacitors for Processor Power

Table 132 lists the recommended decoupling capacitance for each power rail for standard power processors.
Sizes are specified as largest allowed, meaning smaller, lower-inductance capacitors are permitted (for example,
0603 is recommended, but 0402 may be substituted). Transposed body styles are also permissible substitutes (for
example, 0603 is recommended, but 0306 may be substituted).
For each capacitor, there is information as to the quantity, capacitance value, body style (size), dielectric
material, and location relative to the processor. Critical placements are labeled. For example:
• B indicates the capacitors are placed on the bottom side of the board, thereby allowing the shortest possible
distance from the power pins.
• DNI = Do Not Install. Placement of capacitor footprint is required, but population of component is optional.
All of the decoupling capacitors listed in Table 132 connect to VSS.
Table 132. Decoupling Capacitors for Processor Power

Capacitor
VDDCR
VDDCR_SOC
VDDIO_MEM_S31, 2
VDDP
VDDP_S5
VDD_18
VDD_18_S5
VDD_33_S5
VDD_33
VDDIO_AUDIO
VDDBT_RTC_G
Value
Package Size / Material
22 µF 0603
X5R
16BU www.teknisi-indonesia.com
7BU 9BU 2BO 1BO 1BO 1BO 1BO 1BO 1BO -
1.0 µF 0402 - 1BU 2BU 4BU + 2BU + 1BU + 1BO 1BU + 1BU + 1BU + 1BU 1BU
X5R 4BO 1BO 1BO 1BO 1BO
0.22 0402 - - 4 along split - - - - - - - 1BU

µF X5R
180 pF 0402 1BU 1BU 1BU + 2 1BU - - - - - - -

C0G along split
NP0
Key: Capacitor locations are marked as follows: BU = Bottom, Under the processor, BO = Bottom, Outside of the processor, T = Top, same side as the
Processor S = Close to VDDIO_MEM_S3 plane split
Note: 1. Capacitors on the plane split are placed evenly spaced along the VDDIO_MEM_S3/VSS split between the processor and the first DIMM.
2. EMI: If the VSS plane is cut to create a VDDIO_MEM_S3 plane between the processor keepout and the keepout of the first DIMM:
• Add two 180-pF capacitors.
• Add a total of four 180-pF capacitors if plane cut is longer than 63.5 mm.
• Place the 180-pF capacitors across the plane split between the VDDIO_MEM_S3 and VSS planes.
• Locate the 180-pF capacitors on both sides of the VDDIO_MEM_S3 plane, evenly spaced between the processor and the first
DIMM.

16 EMI and ESD Design Guidelines

Follow these design recommendations to minimize system Electromagnetic Interference (EMI) and to assist in
obtaining system compliance with applicable Electromagnetic Compatibility (EMC) standards. The emphasis is
on implementing the necessary EMC design in early stages to eliminate costly and time-consuming debug and
design changes at the end of the development cycle. In addition to following these EMC design guidelines, it is
recommended that an EMC design engineer complete EMC schematic and board layout reviews on each
hardware revision level. Also, preproduction motherboards must be EMC tested to identify potential issues and
then implement necessary design changes on subsequent revisions of the design.
16.1 Decoupling, Bypass, Stitching, and Filtering Capacitors

The following section provides capacitor selection and application information as it pertains to EMI reduction.
16.1.1 Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)

Decoupling capacitors serve as local high-frequency current sources and reduce noise on the ground and power
planes. They are critical for good EMI performance. Follow AMD decoupling recommendations defined in
Power Distribution Network Design Guidelines.
Place the smaller-value, smaller-sized SMT decoupling capacitors as close as possible to each component
voltage pin.
Use low-impedance connections to place capacitors. In practice, this means using a very short trace with a
minimum 0.508-mm (20-mil) width to connect the decoupling capacitor terminals to voltage and ground.
16.1.2 High-Frequency Bypass and Stitching Capacitors

The motherboard voltage and ground planes serve as high-frequency signal returns. For this reason, it is
important to maintain a low impedance at higher frequencies between each voltage plane and ground plane. In
practice, this is accomplished by placing bypass capacitors between each voltage plane and ground plane, and
also across the VSS and VDD plane splits. These bypass and stitching capacitors are low impedance at high
frequencies, thus offering high-speed signal-return currents a low-impedance path.
High-speed signals should not cross reference-plane splits. In the rare case where this is not possible, stitching
capacitors are used to stitch the reference planes together. Refer to Stitching Capacitors for more details.
To reduce the EMI impact of any signals that cross reference-plane splits, place a stitching capacitor across the
reference-plane split, no more than 1.27 mm (50 mils) from the reference-plane split crossing.
Failure to add these capacitors can have undesired consequences such as the following:
• Signals that cross a reference-plane split without a stitching capacitor nearby have a higher impedance and
different propagation rate than expected.
• The signal return path may become significantly large. This large return loop area contributes to a rise in
emissions from this signal.
Values for stitching and bypass capacitors typically range from 100 pF to 0.1 µF; however, the exact capacitor
value is of secondary importance compared to the use of a low-impedance connection from the capacitor
terminals to the motherboard and the use of multi-layer ceramic small package SMT capacitors.
16.1.3 DDR VDDIO_MEM_S3 to VSS Stitching Capacitor Requirements

To achieve proper DDR signal referencing when using DIMMs, cut a VDDIO_MEM_S3 voltage island on both
internal power and ground planes beneath the DDR routing.

Cutting a VDDIO_MEM_S3 voltage island requires placement of small 180-pF SMT stitching capacitors across
the VDDIO_MEM_S3-to-VSS plane split. These 180-pF stitching capacitors are critical for good EMI
performance.
See note in Table 132 for additional details about the 180-pF capacitors.
16.1.4 Voltage Filtering Requirements

Specialty voltages, such as Analog, PLL, and especially clock-voltage supplies, require high-frequency
decoupling and filtering to reduce EMI. Closely follow each vendor's data sheet design specification for
decoupling requirements.
See Power Distribution Network Design Guidelines for additional information on this topic.
16.2 Clocks and EMI

High-frequency periodic (clock) circuits are often the main source of EMI in a computer system. The following
sections provide guidelines for reducing and containing clock EMI.
16.2.1 Spread-Spectrum Clocking (SSC)

Always enable Spread-Spectrum Clocking (SSC) as the default for system clocks. This method is one of the
most effective countermeasures in reducing electromagnetic interference from the system, and is very cost
effective.
SSC generated internally by the AMD . The recommended SSC settings include 0.35% minimum and 0.40%
maximum down-spread capabilities. Designers should select the appropriate SSC solution and percentage setting
for their designs.
16.2.2 Display SSC

The external video interfaces such as DisplayPort, HDMI, and DVI may require SSC settings to meet EMI
requirements. The APU internal display clock generators DPLL0 and DPPL1 provide the ability to control SSC
settings for these external video interfaces. These spread spectrum generators are part of the APU internal
clocking system.
Table 133 lists the recommended SSC settings for the DP and eDP external video interfaces.
Table 133. Spread-Spectrum Settings for Display Mode

Display Mode Spread-Spectrum Value
DP and eDP Up to 0.4% down spread
16.2.3 Unused Clock Outputs

Disable all unused clock outputs through hardware or BIOS settings. Disabling the unused clock outputs
includes, but is not limited to, memory clocks to unpopulated memory, and unused PCIe links. One of the most
useful applications of this technique is to disable the unused clocks and PCIe links.
16.2.4 Clock Generators

Clock generators can be responsible for a substantial amount of EMI if not placed or routed correctly. Figure 164
illustrates an overhead view of a clock generator QFP footprint. The footprint has a VSS copper fill placed
within the pin pads. The VSS pins are routed to the copper fill using wide traces. For other package types, place
a VSS fill in the center of the package footprint in the same manner. Each power pin of the clock generator has a
decoupling capacitor. The clock generator is also placed on the side of the board that has a solid VSS plane in
the adjacent layer.
EMI and ESD Design Guidelines 273

In example (a), the CLOCK A and CLOCK B traces route over a solid VSS reference plane. In example (b), the
CLOCK B traces route over a reference-plane split. Avoid routing over a reference-plane split because it breaks
the return-current path of the clock generator signal.
(a) Traces Referencing a Solid Plane (b) Traces Not Referencing a Solid Plane
VSS VDD Avoid Routing over a VSS

Split Reference Plane
VSS Pin
CLOCK B CLOCK A
VSS CLOCK B CLOCK A
Copper
VSS
Fill
VSS VSS Copper
Fill
VSS copper fill on top layer is via stitched to VSS
VSS reference plane
Figure 164. Trace Routing over a Plane
Use the following placement and routing guidelines to reduce EMI from clock generators. Additional circuit
implementation details may be available in the clock generator data sheet.
• On the top layer, directly under the clock generator, create a VSS pour that connects to all ground pins of the
clock generator. Attach the VSS pour to the VSS plane with multiple vias. See Figure 165.
• Connect all of the VSS pins of the clock generator to the VSS fill with wide traces.
• Route all output clocks over a solid VSS reference plane.
• Place a high-frequency decoupling capacitor as close as physically possible to each power pin of the clock
generator and connect each capacitor using short, wide traces.
• Route the clock traces as short as possible minimizing layer changes-
• Maintain at least 2.54 mm (100 mils) of separation between clock signals and any I/O signals.
• Place oscillator and crystals at least 6.35 mm (250 mils) from the edge of the motherboard.
• Place oscillators and crystals at least 38.1 mm (1500 mils) away from external I/O cable connectors, and at
least 25.4 mm (1000 mils) away from internal cable connectors.

VSS Fill
QFP BGA Flat Pack
Figure 165. Top Layer VSS Copper Fill Beneath Clock Generator
16.2.5 Clock Signal Termination
To improve signal integrity and reduce EMI, it is important to properly terminate high-speed clock signals.
Correct signal termination can reduce ringing and reflections that generate EMI, without adversely affecting
timing or slew rate. For single-ended clock signals, locate the series terminating resistor as close as possible to
the output driver. Choose a resistor value that, when combined with the driver output impedance, matches the
trace impedance on the motherboard. Additionally, load-end terminations, such as a shunt R/C to ground, can be
used to minimize incident-wave reflections.
16.3 I/O Signal Partitioning and Separation

The separation between I/O signals and high-frequency periodic (clock) signals is the highest priority.
To minimize system-level EMI emissions, keep I/O cables free of EMI and reduce coupled EMI onto I/O signals
by doing the following:
• Place I/O logic as close as possible to the associated I/O connector to reduce the I/O trace routing on the
motherboard and reduce potential EMI noise coupling.
• Route the I/O traces in logical groups to each I/O connector and maintain a minimum of 2.54 mm separation
between the I/O and any other signals.
16.3.1 I/O Filtering

All system I/O signals include EMI filtering located close to their I/O connector. This filtering consists of a
series impedance (resistor or ferrite bead) and/or provisions for a shunt capacitor to ground on each signal, if
functionality permits. Common-mode chokes may be used on USB 2.0 ports.

16.3.2 Heatsink Grounding

Grounding the heatsink can reduce and memory EMI harmonics. The EMI and mechanical engineers can help
determine the best method for grounding the heatsink early in the design cycle.
16.3.3 Fan Cabling

High-current power supply switching activity creates locally high electromagnetic emissions that can easily
couple onto the fan wire, potentially causing EMI issues. Placing component filtering on the fan wires or using
shielded fan wires does not eliminate this potential coupling mechanism. The best solution is to ensure that the
fan connector and the fan wire each has a minimum of 30 mm (1182 mils) clearance from any high-current
switching coils and FETs.
16.4 Motherboard Grounding

Proper motherboard grounding is essential for reduced system EMI emissions. The following subsections
provide proper motherboard-grounding techniques.
16.4.1 Motherboard-to-Chassis Grounding

For optimal EMI results, connect all motherboard mounting holes directly to ground (VSS) and to the chassis.
The recommended low-impedance mounting hole connects to motherboard ground with eight vias (standard
PCB mounting holes) or six vias (edge mounting holes) as shown in Figure 166.

Figure 166. PCB Standard and Edge Mounting Holes
16.5 Power and Ground Fill Vias

When creating power or ground fills (or pours) it is important to connect those fills to the power or ground plane
with vias to reduce current loops. A good practice for connecting power or ground fills to power or ground
planes is to use four vias per square cm. The power or ground fill connects to the power or ground planes with
multiple vias in a density pattern no less than 4 vias/cm2.
16.6 Electrostatic Discharge (ESD)

Electrostatic discharge (ESD) is a serious threat to the reliability of electronic systems because it can change the
electrical characteristics of a semiconductor device or damage it altogether. The proliferation of electronic
systems such as laptops; smaller geometries used in the manufacturing of ICs; and the reduction of on-die
protection all have increased the vulnerability of electronic systems to ESD.
ESD events occur in manufacturing and in the real-world (end-user) environments. Real-world ESD takes place
when the end-user touches the pins of or plugs in displays, storage, pointing, or other peripheral devices into the
I/O ports of a system. Real-world ESD has much higher voltages and currents than ESD found in the

manufacturing environment, and those levels easily can exceed the maximum voltage and current levels of
semiconductor devices thus causing electrical damage.
Figure 167 illustrates simplified block diagrams of systems exposed to positive and negative ESD strikes.
System Chassis System Chassis

VCC VCC VCC VCC
ESD Protection ESD Protection

Positive Negative
ESD Charge Device ESD Charge Device
Source Source
ESD Protection ESD Protection
I/O I/O
Connector Connector
Figure 167. Block Diagram—System ESD Examples
Proper ESD protection of I/O interfaces against real-world threats is critical and can be accomplished by
installing appropriate Transient Voltage Suppression (TVS) components on the signals of the I/O ports available
to the end-user. Only TVS components or switching diodes designed for high-speed interfaces, i.e., components
that provide low insertion loss, ultra low capacitive loading, fast response time, and low turn-on voltage must be
used. Other components such as thyristors or polymer shunts are inadequate for ESD protection and must be
avoided as they are either too slow or have a high turn-on voltage.
Table 134 presents typical electrical specifications that a TVS device must meet to provide adequate ESD
protection for high-speed I/O interfaces.
Table 134. Electrical Specifications for TVS Devices
TVS Parameter Value
VESD ESD Voltage Protection IEC 61000-4-2, level 4

±8 kV contact discharge
±15 kV air discharge
VBR Breakdown Voltage 6V
ILR Reverse Leakage Current 1 µA
Cline Line Capacitance @ 5 GHz 0.3 pF or less
ILoss Insertion Loss @ 5 GHz - 0.3 dB or greater1
VCL Clamping Voltage ±6 V, IEC61000-4-2, ±8 kV Contact
Note: 1. Greater meaning lower loss, e.g. -0.2 dB is greater than - 0.3 dB.
AMD requires the use of ESD protection components installed on the motherboard that meet or exceed the
electrical specifications listed in Table 134. Other devices that have higher capacitance may also be used,
depending on the I/O port speed.
ESD components are installed at the I/O port and connect to the I/O signal and VSS or to the I/O signal and both
VSS and VCC. ESD devices that have connections to both VCC and VSS require a dedicated 100 nF to 470 nF
capacitor to decouple the power input. Place this capacitor as close as possible to the power pin of the ESD
device. Refer to the manufacturer's ESD component data sheet for details and information on the device.
Figure 168 shows a schematic view of a multi-channel ESD device with connections to signals and VSS; Figure
169 shows a typical board layout of that ESD device. Figure 170 shows a schematic view of a single-channel

ESD device that connects to signal, VSS, and VCC; Figure 171 presents a typical board layout of that ESD
device.
ESD components protect port interfaces effectively by shunting or dissipating ESD to either VSS or both VSS
and VCC, depending on the device used. The ESD device is the first component placed at the I/O connector.
That is, there is no other component placed between the ESD device and the I/O connector. For ESD devices that
have power connections to ground only (ESD devices without a VCC pin), there is no power to the ESD device
to decouple; therefore, no capacitor is needed.
Processor DESD ESD Device
2 I/O
Connector
4
3 8
Figure 168. Schematic Diagram—ESD Device Connecting to Signals and VSS
Figure 169. Typical Board Layout—ESD Device Connecting to Signals and VSS

+V
Processor
I/O
DESD Connector
CESD
Figure 170. Schematic Diagram—ESD Device Connecting to Signal, VSS, and VCC
Figure 171. Typical Board Layout—ESD Device Connecting to Signal, VSS, and VCC
16.6.1 ESD Component Placement

Figure 172 illustrates an example placement of an integrated ESD-protection device with decoupling capacitor.
Place the ESD-protection device as close as possible to the connector to minimize electromagnetic fields inside
the case and coupling to adjacent lines that may lead to unexpected events like system resets or lockups when
discharging to external pins. Place the decoupling capacitor as close as possible to the power pin of the ESD-
protection device.

CESD
4
TX
4
4
Processor
4
4
4
ESD
4
RX
ESD Protection Device
Figure 172. Placement of an Integrated ESD-Protection Device

17 Low EMI Noise for System Radio Integration Design

Guidelines
17.1 Most Commonly Integrated Radio Bands

This chapter presents layout and routing rules for DDR SO-DIMM-based APU designs that incorporate
integrated radio technologies.
Systems that include one or more integrated or embedded radio-module circuits must follow critical layout and
routing rules to meet several types of embedded-radio compliance testing requirements.
The design techniques presented in this chapter are focused on obtaining a low common-mode ground noise
floor that might affect the radio directly, and on minimizing differential electromagnetic emissions that the
various embedded system antennas may receive. Design rules become even more important on small form-factor
platforms.
17.2 Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)

Decoupling capacitors serve as local high-frequency current sources and reduce noise on the ground and power
planes. They are critical for good EMI performance. Follow AMD decoupling recommendations defined in
Power Distribution Network Design Guidelines.
Place the smaller-value/smaller-sized SMT decoupling capacitors as close as possible to the component voltage
pin.
Use low-impedance connections to place capacitors. In practice, this means using a very short trace with a
minimum 0.508-mm (20-mil) width to connect the decoupling capacitor terminals to power and ground.
17.3 Key Radio Bands www.teknisi-indonesia.com

Radios operate in specific frequency ranges known as "bands". Table 135 presents the most commonly
integrated and embedded radio bands.
Table 135. Key Embedded Radio Bands

Item # UMTS BAND # BAND NAME Band Radio Standard Receive Frequency
Start, MHz Stop, MHz
1 12, 13, 14, 17 700 LTE 728 768
2 28 700APT LTE 758 803
3 20 800 LTE 791 821
4 5, 19, 26 850 GSM, CDMA, EV- 859 894

DO, WCDMA, LTE
5 8 900 GSM, LTE 925 960
6 11, 21 1500 LPDC, UPDC 1476 1511
7 3, 4, 9 1800 GSM 1805 1880
8 39 1900TD TD1900+ 1880 1920
9 2, 25, 39 1900 GSM, CDMA, EV- 1930 1990

DO, WCDMA
10 34 2000 TD2000 2010 2025
282 Low EMI Noise for System Radio Integration Design Guidelines
Table 135. Key Embedded Radio Bands (continued)

Item # UMTS BAND # BAND NAME Band Radio Standard Receive Frequency
Start, MHz Stop, MHz
11 1, 4 2100 WCDMA 2110 2170
12 30, 40 2300 TD2300, WCS 2300 2400
13 X 2400 WLAN 802.11bgn /BT 2400 2484
14 41 2500 TD2500 2496 2690
15 7, 38 2600 LTE 2570 2690
16 X 3500 CRBS 5G 3550 3650
17 X 5000 WLAN 802.11 a,n,ac 5100 5850
18 X 1.575 GHz GPS L1 / GLONASS 1545 1605
Note: Rows shaded in this color are Optional Test Bands
17.4 Principal Harmonic Signal Threats to Radio Integration

Generally, electronic ICs, circuits, cables, and traces operate at known frequencies and emit electromagnetic
radiation at principal overtone frequencies also known as EMI harmonics. Some of the electromagnetic
harmonic radiation of these circuits is a potential threat to embedded radio bands. Table 136 presents potentially
threatening system signals and buses that coincide and can interfere with the commonly integrated radio bands
listed in Table 135. Identification of these signals and their related frequencies is a critical part of the radio
planning process.
Table 136. Principal System Harmonics Coinciding with Key Radio Bands
Harmonic # System Clocks Display Port DDR Speed I/O Peripheral Bus
LPC APU 1.62G 2.70G DDR DDR DDR DDR SATA USB2.0 USB3.2 PCIe
®
PCIe
Clocks Ref Disp Disp 1600 1866 2133 2400 Gen2 Gen1 Gen2 Gen3
Clock Port Port Gen3 (5Gbps)
1 66.67 100 162 270 800 933 1066 1200 1500 480 2500 2500 4000
2 133.33 200 324 540 1600 1866 2132 2400 3000 960 5000 5000 8000
3 200.00 300 486 810 2400 2799 3198 3600 4500 1440 7500 7500
4 266.67 400 648 1080 3200 3732 4264 4800 6000 1920
5 333.33 500 810 1350 4000 4665 5330 6000 2400
6 400.00 600 972 1620 4800 5598 6396 2880
7 466.67 700 1134 1890 5600 6531 3360
8 533.33 800 1296 2160 6400 3840
9 600.00 900 1458 2430 4320
10 666.67 1000 1620 2700 4800
11 733.33 1100 1782 2970 5280
12 800.00 1200 1944 3240 5760
Low EMI Noise for System Radio Integration Design Guidelines 283
Table 136. Principal System Harmonics Coinciding with Key Radio Bands (continued)
Harmonic # System Clocks Display Port DDR Speed I/O Peripheral Bus
LPC APU 1.62G 2.70G DDR DDR DDR DDR SATA USB2.0 USB3.2
®
PCIe PCIe
Clocks Ref Disp Disp 1600 1866 2133 2400 Gen2 Gen1 Gen2 Gen3
Clock Port Port Gen3 (5Gbps)
13 866.67 1300 2106 3510
14 933.33 1400 2268 3780
15 1000.00 1500 2430 4050
16 1066.67 1600 2592 4320
17 1133.33 1700 2754 4590
18 1200.00 1800 2916 4860
19 1266.67 1900 3078 5130
20 1333.33 2000 3240 5400
21 1400.00 2100 3402 5670
22 1466.67 2200 3564 5940
23 1533.33 2300 3726 6210
24 1600.00 2400 3888 6480
25 1666.67 2500 4050 6750
26 1733.33
2600 4212
27 1800.00 2700 4374
28 1866.67 2800 4536
29 1933.33 2900 4698
30 2000.00 3000 4860
31 2066.67 3100 5022
32 2133.33 3200 5184
33 2200.00 3300 5346
UMTS 2, 5, 8, 11, 20, 2, 5, 7, 1, 4, 20, 20, 28, 3, 4, 8, 1, 4 30, 40 11, 21 8, 30, 40

Band# 12, 13, 21, 28, 20, 38, 39 30, 40 9
Violation 14, 17, 30, 40 39
39
See Table
135 for
UMTS Band
#'s.
Wi-Fi 2.4G, 2.4G, 5G 5G 5G 2.4G 2.4G

Violation 5G 5G
17.5 General Rules to Optimize Differential-Mode Radio Performance

All electronic devices have multiple internal sources of electromagnetic emissions. Differential Mode (DM)
electromagnetic emissions travel through the air from nearby emission sources and can interfere with the radio
antennas. The field levels from the emission sources drop at a nonlinear and calculable rate. The same
frequency-dependent drop rate occurs with emissions from ICs, signal traces, SO-DIMM memory modules,
cables, processor heatpipes, and radiators. For example, the E-field radiation from an 800 MHz noise source
drops ~11 dB at a distance of 100 mm and ~17 dB at 200 mm.
Metal shielding can contain or redirect Differential-Mode electromagnetic emissions. This shielding may have to
be more thorough than that required for typical product EMI/EMC Compliance.
A shield can reduce radiated E-field fields by >20 dB. Shielding Effectiveness (SE) is a measure of the ability of
a shield to reduce radiated E-fields.
The following rules help optimize differential-mode radio performance:
• Maximize isolation distance from the radio antenna to noise sources, especially:
• Processor
• SO-DIMM modules or DRAM down
• Switch Mode Power Supply (SMPS) coils and FETs
• Maximize isolation distance from noise sources to the radio module
• Ensure good grounding and shielding practices for:
• DIMM modules
• cables
• USB connectors
•
• www.teknisi-indonesia.com
Ensure processor thermal solution is electrically connected in all four locations to VSS on the motherboard
Heatpipe and radiator are grounded to chassis GND in at least one location
• Ensure proper antenna ground referencing to chassis GND
• Follow all high-speed signal routing rules for EMI listed in this document
17.6 Common-Mode Ground Disturbances

Common-Mode (CM) disturbances are also a threat to successful radio integration. Also known as ground noise,
these electromagnetic effects drop at an uncertain rate from the noise source that depends on many unique
motherboard factors. These common-mode ground disturbances drop at rates more difficult to predict, and affect
the PWB and the system ground structures. These common-mode disturbances are caused primarily by
insufficient decoupling of active devices and specific types of layout errors.
The following rules help optimize common-mode radio performance:
• Ensure proper radio module grounding to VSS through standoffs or metal clips
• Maximize isolation distance from noise sources to the radio module
• Ensure coaxial cable routing away from electromagnetic noise sources
• Follow all high-speed signal routing rules for EMI listed in this document
Table 137 presents a summary of the most important factors that can adversely affect radio noise floor,
performance, and ultimately radio compliance testing.
Table 137. Differential-Mode and Common-Mode Factors Affecting Radio Compliance

System Factor Factor Description Differential-Mode Emission / Common-Mode
Noise
Antenna Placement Antenna placed away from ICs Differential Mode
Table 137. Differential-Mode and Common-Mode Factors Affecting Radio Compliance (continued)
System Factor Factor Description Differential-Mode Emission / Common-Mode
Noise
Antenna Lobe Some antennas can be directed away from Differential Mode
system noise
Antenna Reference Ground Antenna reference grounded to chassis Differential Mode
Radio Module Placement Radio Module placed away from SO-DIMM and Differential Mode and Common Mode
APU
Radio Module Grounding Radio Module grounds low-impedance Common Mode

connection to motherboard VSS
DDR SO-DIMM Differential-Mode Shielding SO-DIMM modules must be shielded well on all Differential Mode
sides
DDR Signal Referencing All DDR signals must be properly referenced Differential Mode and Common Mode
along entire trace
DDR SO-DIMM Decoupling and Copper Fills SO-DIMM decoupling capacitors and low- Differential Mode
resonance copper fills
Coaxial Cable Routing Coaxial cables routed away from noise sources Common Mode
SMPS Supply Coil Placement Antenna and Radio Module distance from Switch Differential Mode
Mode Power Supply coils
SMPS FET Decoupling VDD/VSS FET Decouple Common Mode
17.7 Design Rules for Optimal Radio Performance
As shown in Table 136, certain signals and buses contain overtone harmonics that are, based on frequency,
potential threats to radio performance and compliance.
Closely following EMI design guidelines can minimize the emissions from these principal signals and buses.
When these signals are routed correctly, much of the potential emissions are removed by the processes of self-
cancellation. Certain active devices and ICs can contain threats to radio compliance as well. Decoupling these
devices correctly can mitigate a significant portion of this threat.
Review Table 138 to maximize radio performance and minimize motherboard sources of differential-mode
radiation and common-mode ground-plane disturbances.
Table 138. Information for Radio Performance Optimization

Topic Section
PCB Planning PCB Planning
Stackups
Reference Planes
DDR DIMM Decoupling EMI and ESD Design Guidelines
Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)
High-Frequency Bypass and Stitching Capacitors
DDR VDDIO_MEM_S3 to VSS Stitching Capacitor Requirements
Voltage Filtering Requirements
Table 138. Information for Radio Performance Optimization (continued)

Topic Section
APU Decoupling Power Distribution Network Design Guidelines
High-Frequency Design Considerations
Power Generation and Distribution Guidelines
APU Heatsink, Heatpipe, and Radiator EMI and ESD Design Guidelines
I/O Signal Partitioning and Separation
Heatsink Grounding
Fan Cabling
PCI Clocks EMI and ESD Design Guidelines
High-Frequency Bypass and Stitching Capacitors
Clocks and EMI
I/O Signal Partitioning and Separation
18 Power Optimization Design Guidelines

The design guidelines for power optimization focus on selection and implementation of peripherals, BIOS, and
drivers.
18.1 Peripheral Selection and Optimization

Most systems, even under heavy workloads, are not operating at 100% utilization. Even when heavily loaded,
most systems are not utilizing all of the available peripherals. This affords the opportunity to reduce power
consumption by reducing the system performance to the level that creates near 100% utilization and by idling
peripherals that are not being used.
All peripherals integrated on the system need specific drivers loaded to control them under the operating system.
These peripherals and drivers must support, and be configured to fully implement, the low-power states that are
discussed below.
Software tuning or optimization allows the system to achieve the best combination of power usage relative to
performance. Software optimization is not a substitute for a well-designed system. Instead, it allows the system
to fully implement and utilize the power-saving features in the hardware.
18.1.1 Device Implementation—USB

Assign USB ports based on device speed and usage. Table 139 lists the usage for typical devices found in
processor-based system.
Table 139. Internal USB Device Usage Models
USB 3.2
Device
"Constantly" Used
Wireless LAN, Wireless WAN, Portable Hard Disk, Web Camera

"Seldom" Used
Flash memory card reader, Digital Camera
USB 2.0 Wireless LAN, Wireless WAN (3G, WiMAX, LTE), Web cam Flash memory card reader, Digital camera
USB 1.1 Bluetooth Fingerpint reader, SmartCard reader
The integrated FCH supports the USB subsystem.

The components consume varying levels of power. The integrated FCH USB subsystem PHYs consume the
most power. The next largest consumer of power is the xHCI (USB 3.2) controller. The individual ports
consume the least amount of power.
Design considerations include:
• When planning USB usage to obtain optimal power management, use the minimum number of controllers by
clustering USB devices on controllers. This allows controllers to be disabled if they are not being utilized.
• Power down or disable unused PHYs, controllers, and ports to conserve power.
• To maximize power savings connect any onboard USB 1.1 devices to only one controller until all the
available ports are used.
18.1.2 Selective Suspend

Support for the USB Selective Suspend state is critical to optimizing power for USB devices. All devices on a
USB controller must support the Selective Suspend state. Selective Suspend occurs when a USB bus is in the
constant idle state for a given period of time (typically ≥ 3.0 ms). The devices on this bus then enter the Suspend
state, which draws only suspend current from the bus (lower power). Refer to the USB 2.0 or 3.2 specification
for more information about power-management states.

For any integrated USB devices, ensure that the specific hardware device chosen supports Selective Suspend.
Also ensure that the USB device driver supports and is configured to enable Selective Suspend states. The driver
may also require OS registry settings to fully implement this feature. Consult the USB peripheral supplier for
specific implementation details.
18.1.3 Device Implementation—PCIe® Interface

PCIe power management consists of link-management and device-management states.
• Link management
• Defined states are L0, L0s, L1, L2, and L3.
• Power saving increases as the states progress from L0 through L3.
• Device management
• Defined states are D0, D1, D2, and D3.
• Power saving increases as the states progress from D0 through D3.
• Power states D0 and D3 must be supported.
• Power states D1 and D2 are optional.
Refer to the PCIe specification for additional details about link and device management.
Ensure all PCIe devices chosen support link-management and device-management states. Also ensure that the
device driver is configured and supports the link-management and device-management states. Disable unused
PCIe clocks in BIOS. Ensure that CLKREQ is routed to each PCIe device implemented. Use latest drivers for all
PCIe devices. PCIe devices support L1 sub-states. If idle power is a concern, connect the PCIe SSD directly to a
processor PCIe port. If the PCIe device (e.g., x4 SSD) is not a hot-pluggable device, turn off the PCIe root
complex in BIOS.
To achieve the best power management, plan PCIe device usage to minimize the number of PCIe controllers by
clustering PCIe devices on a single controller until that controller is full. This allows controllers to be disabled
when not in use.
18.1.4 Device Implementation—Discrete Graphics

AMD SG (Switchable Graphics) technology accommodates the highest performance, feature-rich capabilities of
discrete graphics and the longest system battery life using integrated graphics only. An SG-enabled system
achieves both of these goals through the ability to switch graphics processing and display outputs between the
dGPU (discrete GPU) and the iGPU (integrated graphics) on the APU. If the functionality of the dGPU device is
not required in battery mode, an SG-enabled system transfers the graphics processing and display output to the
iGPU and powers off the dGPU without the need to reboot the system. AMD PowerXpress™ 4.0 technology
introduced two new features, Muxless AMD PowerXpress and Bus Alive Chip Off (BACO). Muxless AMD
PowerXpress saves the expense and space of external circuitry and enables the APU to accept video streams
from the dGPU and reroute them to the appropriate video output; either VGA, DisplayPort, or HDMI/DVI.
Multiplexers are no longer required to switch the physical display outputs between the iGPU and dGPU. In this
muxless implementation, CrossDisplay technology offers a software solution that allows all display connectors
to be connected to the iGPU output only with display surfaces rendered in the dGPU to be transferred to the
iGPU via the PCIe graphics interface. Refer to AMD Platform Switchable Graphics and Dual Graphics Design
Guidance and Functional Specification for Muxless AMD PowerXpress technology implementation details.
The second feature introduced in AMD PowerXpress 4.0 is BACO. This feature keeps a portion of the dGPU
powered to enable a fast and seamless switch between iGPU and dGPU. Refer to AMD Platform Switchable
Graphics and Dual Graphics Design Guidance and Functional Specification for BACO implementation details.
For AMD PowerXpress 5.0 technology implementation, all power rails to the dGPU must be gated off.
For a design that supports both AMD PowerXpress 4.0 (BACO) and AMD PowerXpress 5.0, dGPU_VCORE is
controlled by BACO circuitry. Gate off all other power rails. Refer to AMD Platform Switchable Graphics and
Dual Graphics Design Guidance and Functional Specification.
Power Optimization Design Guidelines 289

18.1.5 Device Implementation—SATA

When selecting Serial Advanced Technology Attachment (SATA) storage devices (HDD, ODD) ensure that they
support:
• Device-Initiated Link Power Management (DIPM)
• Host-Initiated Link Power Management (HIPM)
• Device Sleep (DEVSLEEP)
This allows the SATA link to be dynamically placed in the Partial Mode or Slumber Mode Sleep states based on
activity.
SATA ODD Selection: Ensure that ODD devices support Asynchronous Notification (AN). AN is a mechanism
for a device to send a notification to the host that the device requires attention such as when media has been
inserted into an ODD.
For Solid State Devices (SSD), ensure the AHCI OS policy is set to "Lowest".
18.1.6 Device Implementation—HD Audio

When selecting HD audio CODECs ensure they support dynamically placing the device into the ACPI D3 state
during periods in which no audio streams need to be processed. Also, ensure that circuitry to prevent audio
"popping" is in place so that there is no audible clicks or pops when the audio CODEC comes out of D3 and
plays audio. Please refer to the audio CODEC supplier for implementation details.
18.1.7 Device Implementation—Network Device

Often, platforms contain several different communication devices such as modems, wired ENET, WLAN,
WWAN and Bluetooth. In such cases, selecting devices that support ACPI D3 can provide significant power
savings by allowing unused devices to be powered down. Please refer to the specific device supplier for
implementation details.
18.1.8 Device Implementation—TPM 2.0

Disable and deactivate TPM 2.0 if TPM 2.0 functionality is not needed.
18.1.9 Device Implementation—Memory

Use low-power memory. The memory voltage regulator should support switching to different voltages.
18.1.10 Device Implementation—LCD Panel

The LCD panel used should support Dynamic Refresh Rate.
18.2 BIOS and Drivers
18.2.1 BIOS Implementation

The following documentation should be consulted to fully implement all power-saving features and optimize the
system for power:
• Processor Programming Reference (PPR) for AMD Family 17h, Models 60h-6Fh Processors (NDA) and the
Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 50h, Revision A0
Processors (NDA). This guide provides key guidance for system and BIOS optimization for FP6 processors.

18.2.2 Graphics Driver Implementation

Voltage scaling can drop the core iGPU voltage for power savings. The iGPU can also be set to enter a deep-
sleep state by performing an additional engine-clock (SCK) divide down during idle.
Power Optimization Design Guidelines 291

19 Power Regulator Design Guidelines

The design guidelines for power regulation focus on power delivery, conversion, switching, and distribution.
19.1 Power Regulation Overview

This topic describes optimizing component selection and implementation for power consumption for a system
designed for the .
In addition to consideration to what is active and what is powered for each mode, overall efficiency in the power
distribution network also plays a role in the ability of the platform to meet these requirements.
19.2 Power Delivery—Good Design Practice

Power efficiency needs to be addressed during the design phase. Attempting to modify an existing board to
increase power efficiency typically does not yield the best results. BIOS enhancements alone do not yield
maximum benefits. Greatest benefit is achieved when the hardware has been designed with maximum efficiency
in mind.
Component selection is of utmost importance when performing the initial system-design architecture. Ensure
that components and peripherals that are selected support, and can be implemented with, the low-power states
that are detailed later in this chapter.
19.3 Power Conversion—Hierarchy

Avoid excessive levels (stages) of power conversion to maintain efficiency. Figure 173 shows a block diagram
of a common first-stage regulator.
Be careful when using multiple-output supplies. To determine what power supply outputs are used to drive the
secondary power supplies, the effect on overall efficiency versus individual output loading must be understood.

CPU CPU Core

Core Supply
AC Adaptor GPU Core
APU with Integrated Chipset

(15V - 19V ) SOC Core Supply SOC
DDR Logic
Link PHY
Battery VIN DDR PHY
Charger PLL
PHY Supply Link PHY
PLL
PCIe® Supply I/O PHY
Battery
DDR Interface
VDDIO_MEM_S3
DDR
Supply
Digital Logic Supply VTT
LAN
Peripheral Devices
ODD
LDO
HDD
Stage 1 www.teknisi-indonesia.com
LDO WiFi
LCD Logic
Converter
LDO Backlight
Stage 2 PCIe Slot
Converter
Figure 173. Power Conversion Block Diagram (Simplified)
Power-conversion topologies must be considered carefully. Significant efficiency can be lost if improper
topologies are used. Consideration must be given to the quantity and levels of voltages and the current
requirements for each of those rails. Switching regulators must be used in cases where current requirements are
high.
Keep the total number of stages in the current path to two, including the main-input power supply. Each stage
decreases the overall efficiency of the final delivered voltage. The exceptions here are reference voltages that
must track another voltage, or if the current is exceptionally low.
Figure 174 shows the comparison of various power-conversion topologies and their associated efficiencies. The
recommendation for high-current rails is a limit of one regulator stage excluding the AC adapter and battery
charger circuit. The AC adapter and battery are common to all regulators in these examples.
The first example in Figure 174 is a straightforward one-stage switching regulator with a good efficiency rating
of 85%.
The second example is a variant of the first example by adding a low-current, linear regulator plus a high-current
switching regulator. The overall efficiency is not greatly affected by the linear regulator. However, the overall
efficiency is greatly affected by the switching regulator. Switching regulators must not be cascaded (in series).
Power Regulator Design Guidelines 293

Overall
85% Efficient 85% Efficient
Efficiency
Final
Voltage
First Stage 85.0%
Load
(Switcher)
AC Adaptor
Final
Voltage
First Stage
Load 85.0%
(Switcher)
Battery Final
Voltage
Charger Second Stage
Load 72.25% *
(Linear)
* Low Current
Intermediate
Voltage 1
Battery
Final
Voltage
Second Stage
Load 72.25% **
(Switcher)
** High Current
Figure 174. Efficiency Versus Stages of Regulation
Generally, switching regulators are used when high-current levels are required; they have higher power
efficiency and introduce less heat.
Linear regulators can be used in applications where low-current levels are needed. Linear regulators are smaller
than switching regulators but less efficient. If linear regulators are used for high current, their inefficiency leads
to excess heat being dissipated. Furthermore, the linear regulator may require a heatsink to ensure reliable
operation even at relatively low-current levels.
Other applications that warrant the use of a linear regulator are:
• Any rails that need to source and sink current are usually easier to implement with a linear solution.
• Any rails that need to be extremely quiet, with low noise such as reference voltages or power supplies for
PLLs, typically are better served by a linear regulator. However, the current requirement for these types of
loads is typically low; therefore, efficiency is not an issue.
If a linear regulator must be used, it must be connected to the lowest-voltage rail possible to minimize the
efficiency loss and the additional heat introduced to the system. Unless the current levels are extremely low,
linear regulator efficiency is lower than switchers. Figure 175 demonstrates the power delivery efficiency for
various power-supply solutions.

Overall
Efficiency
3.3 V @ 1.28 A First Stage 1.8 V @ 2.0 A 3.6 W

Input 85% Efficient
(Switcher) Load
4.2 W 3.6 W
3.3 V @ 2.0 A First Stage 1.8 V @ 2.0 A 3.6 W 55% Efficient

Input (Overloaded)
(Linear) Load
6.6 W 3.6 W
5.0 V @ 2.0 A First Stage 1.8 V @ 2.0 A 3.6 W 36% Efficient

Input (Overloaded)
(Linear) Load
10.0 W 3.6 W
Figure 175. Power Delivery Efficiency for Various Power Supply Solutions
19.3.1 Stage 1 Regulator—Main Power Supply

The efficiency of the system cannot be higher than the efficiency of the main power supply. Derive all of the
high-current rails directly from the battery voltage for maximum efficiency. Avoid multiple levels or series
connection of power supplies. Figure 173 shows a simplified block diagram of power delivery with all voltages
shown derived through two levels of conversion.
For most designs, all power flows through the main power supply; therefore, this is where power optimization
begins. Size the main supply appropriately. It needs to be large enough to handle all expected peripherals and
add-in cards, but not be oversized so that while operating in a typical system configuration, efficiency begins to
fall off due to insufficient loading. All power supplies have efficiency curves. When the current load is zero, the
efficiency is also zero. Most are at their maximum efficiency when loaded above 80%. Another area to watch is
multiple output supplies, the effect on overall efficiency versus individual output loading must also be
understood as this plays a role in determining what power supply outputs are used to drive the secondary power
supplies.
Power supplies have three operating ranges:
• Underloaded
• Properly Loaded
• Overloaded
See Figure 176 for an example of Power Efficiency curves showing the three regions. An extreme case is when
the load current is zero because the efficiency is also zero.

%
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
Underloaded Properly Loaded Overloaded
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
W
3
Figure 176. Power Efficiency Curves
19.3.1.1 Power Quality and Power Factor Correction (PFC)

Ideal power is delivered with voltage and current in phase, with no harmonic distortion. Figure 177 shows the
voltage and current waveforms for ideal power. Note that there are no harmonics on either waveform. Only the
fundamental frequency is present.
y
Voltage
Current
1
Ideal Conditions
- π/2 O π/2 π 3π/2 2π x

i in phase with V
-1
Figure 177. Ideal Power

Power quality is measured in terms of power factor and total harmonic distortion (THD). Power factor is the
ratio of real power to apparent power. Total harmonic distortion is the ratio of total harmonic power to
fundamental power, effectively a signal-to-noise ratio.
Figure 178 shows the voltage and current phase relationships for three types of linear loads: resistive, capacitive,
and inductive. Waveforms of nonlinear loads are not shown.
Voltage
Current
Power
PAVG
Resistive Load
PowerFactor = 1 iR in phase with VR
(PAPPARENT)2 = (PREAL)2 +
(PREACTIVE)2
Voltage
Current
Power
PAVG
Capacitive Load
PowerFactor = 0 www.teknisi-indonesia.com iC leads VC by 90º
Voltage
Current
Power
PAVG
Inductive Load
PowerFactor = 0 iL lags VL by 90º
Figure 178. Voltage-Current Phase Relationships
19.3.1.1.1 PFC in Inductive systems

Figure 179 illustrates the amount of phase correction needed in inductive systems. The dark blue current
waveform requires a phase shift of 90 degrees (lag) to be in phase with the voltage. The magenta waveform
requires a shift of 60 degrees to align with the voltage. The yellow waveform requires a shift of 30 degrees. The
turquoise waveform represents the corrected waveform, which aligns with the voltage and has a Power Factor of
1.0.

Voltage 0º
Current -90º (PF=0)
Current -60º (PF=.35)
Current -30º
(PF=.606)
Current 0º (PF=1)
Correction
(Lag)
0.50
0.43
0.25
n
io
ct
0.00
re
or
C
90º (AVG = 0)
60º (AVG= 0.25)
30º (AVG=0.43)
0º (AVG=0.5)
Figure 179. PFC Phase Adjustment in Inductive Systems
19.3.1.1.2 PFC in Capacitive Systems

Figure 180 illustrates the amount of phase correction needed in capacitive systems. The dark blue current
waveform requires a phase shift of −90 degrees (lead) to be in phase with the voltage. The magenta waveform
requires a shift of −60 degrees to align with the voltage. The yellow waveform requires a shift of −30 degrees.
The turquoise waveform represents the corrected waveform, which aligns with the voltage and has a Power
Factor of 1.0.

Voltage 0º
Current 90º (PF=0)
Current 120º (PF=.35)
Current 150º (PF=.606)
Current 180º (PF=1)
Correction
(Lead)
90º (AVG = 0)
120º (AVG= -0.25)
150º (AVG= -0.43)
180º (AVG= -0.5)
n
io
ct
re
or
C
0.00
www.teknisi-indonesia.com -0.25
-0.43
-0.50
Figure 180. PFC Phase Adjustment in Capacitive Systems
19.3.1.2 Agency Requirements
19.4 Switching Regulator Design Considerations

The switching regulator is increasing in popularity because it offers the advantages of higher power-conversion
efficiency and increased design flexibility. Thus, multiple output voltages of different polarities can be generated
from a single input voltage.
19.4.1 Switching Regulator Topologies

There are many topologies for switching regulators. Four commonly used types are:
• Buck converts a DC voltage to a lower DC voltage (step down)
• Boost converts a DC voltage to a higher DC voltage (step up)
• Buck-boost (or invert) converts a DC voltage to a DC voltage opposite in polarity to the input
• Flyback converts a DC voltage to a lower or higher DC voltage, as well as multiple outputs

Buck regulators can deliver as much as 1,000 watts with efficiencies ranging from 80 to 90%. The energy-
storage mechanism is a single inductor. The buck regulator operates with pulsed input current, requiring an input
filter. The output operates in continuous mode, meaning that the current through the inductor never drops to zero
or goes negative resulting in lower output-voltage ripple.
Boost regulators can deliver in the range of 100 to 200 watts with efficiencies ranging from 65 to 75%. The
energy storage mechanism is a single inductor. The boost regulator operated in continuous input mode,
eliminating the need for an input filter. Pulsed output current increases output voltage ripple, thereby requiring
larger output filtering.
Buck-boost regulators can deliver in the range of 100 to 200 watts with efficiencies ranging from 70 to 80%. The
energy storage mechanism is a single inductor. The buck-boost regulator operates with pulsed input current,
requiring an input filter. Pulsed output current increases output-voltage ripple, thereby requiring larger output
filtering.
Flyback regulators can deliver as much as 250 watts with efficiencies ranging from 70 to 80%. The energy
storage mechanism is a transformer. The flyback regulator operates with pulsed input current, requiring an input
filter. Pulsed output current increases output-voltage ripple, thereby requiring larger output filtering. Electrical
isolation is required in high-voltage applications.
19.4.2 Switching Regulator Types

In addition to the primary power supply, these multiple-transistor regulators are the highest power regulators in
the system.
• Push-Pull: A two-transistor regulator efficient at low input voltages
• Half-Bridge: A two-transistor regulator used in many off-line applications
• Full-Bridge: A four-transistor regulator that can generate the highest output power of all the types listed
The main core voltage regulator typically is powered from the input voltage (VIN), as the current requirements
can be quite high. For this type of regulator, the major components that have a direct impact on efficiency are the
controller IC, the high- and low-side MOSFETS, the inductor, and the filter capacitors. Regulators on a
computer board typically are switching buck-regulator designs. Figure 181 shows a simplified schematic of a
high-current buck regulator.
The main power supply voltage regulator is typically a multiple phase design consisting of two or more
inductors, each with the associated high- and low-side MOSFETs. The output(s) are variable voltages. The and
other internal voltage rail P-States define the voltage levels depending on the level of performance required.
Also, memory designs may need to support multiple voltage levels.

VIN
Q1
C1
L1
Control
VOUT
Q2
C2
Feedback
Figure 181. Example Buck Regulator Simplified Schematic Diagram
19.4.2.1 Voltage Regulator Design Power Flow

During normal operation, a continuous-mode buck regulator switches between placing power into the inductor
(Q1 in Figure 181 is on) and allowing the power stored in the inductor to decrease (Q2 in Figure 181 is on).
In a continuous regulator, the inductor current is never zero; it increases while Q1 is on and decreases while Q1
is off.
See Figure 182 for a representation of the current flow in the inductor for a power supply operating in
continuous mode.

Current
Q1 on Q1 off Q1 on Q1 off
Q2 off Q2 on Q2 off Q2 on
Time
Figure 182. Continuous Mode Inductor Current
There are several areas that are critical to the efficiency of the design. Regulator designs that allow the inductor
current to drop to zero during each cycle are called discontinuous regulators. A continuous-mode design may
operate in discontinuous mode when lightly loaded. Generally, discontinuous mode has a greater output ripple,
requiring larger bulk-storage capacitors on the output. Discontinuous mode is not as efficient, and it can place
larger demands on the bulk-storage capacitors. If the supply operates in discontinuous mode, it must be designed
to support this. For example, the regulator typically has a mode that switches off the low-side MOSFET after a
specified period in order to prevent the reverse flow of current through the inductor. This is referred to as diode-
emulation mode. Depending on the regulator, this mode may have to be enabled or disabled for the current
output required.
19.4.3 Component Selection

The following sections discuss characteristics of major components in power regulators.
19.4.3.1 Power MOSFET Selection—Ideal MOSFET

The ideal switching regulator MOSFET would have RG = ∞, RDS(ON) = 0 when on, and RDS(ON) = ∞ when off. It
would also have instantaneous switching speeds and finally, it would exhibit zero gate capacitance. Because
such a device does not exist, the designer must carefully select the best MOSFETs for the power supply. This
usually means that there are different MOSFETs chosen for the high side (Q1), and the low side (Q2) shown in
Figure 181.
19.4.3.2 Power MOSFET Selection—MOSFET RDS(ON)

The switching transistors used play a large role in the efficiency of the regulator. All of the input power must
pass through the high side (Q1) MOSFET in Figure 181. Here, a low RDS(ON) is critical to minimizing loss while
the MOSFET is on. This low RDS(ON) requirement is also true for the low side (Q2), because when Q1 is off, Q2
is switched on and all power delivered from the inductor, L1, to the load must flow through Q2. Therefore, for
both Q1 and Q2, a device with a low RDS(ON) is critical for good efficiency.
19.4.3.3 Power MOSFET Selection—MOSFET Switching Speed

For the high side and low side MOSFETs, besides a low RDS(ON), switching speed is critical for efficiency of the
regulator. The high side MOSFET is subject to the full input voltage as it is turning off. The longer it takes to
ramp from full on to off, the greater the dissipated power. As Q1 is turned off, and Q2 is turned on there are two

issues: first, if Q1 and Q2 are both on at the same time, as can happen as Q1 is switching off and Q2 is switching
on, there is shoot-through current. This wastes power as the input power is essentially shorted to ground. If Q2
does not switch on quickly, the parasitic diode in Q2 carries the inductor current as Q1 switches off and Q2 has
not yet switched on. The internal diode is usually not very efficient and the result is excessive heating of Q2 and
a resulting efficiency loss.
19.4.3.4 Power MOSFET Selection—MOSFET Gate Loss

Finally, the gate-to-source capacitance is important for this device. During steady-state operation, there is
essentially zero current flow in or out of the gate of a MOSFET transistor. But, MOSFETs have gate to source
capacitance, and when the gate is driven with an AC waveform such as the gate drive in a switching regulator,
this capacitance results in gate-current flow. Because the current flow does not contribute to the output power, it
is also wasted. Also, a MOSFET with a better performing body diode helps reduce losses during the time that Q1
and Q2 are both off and the inductor current is flowing through the body diode of Q2.
19.4.3.5 Inductor Selection

The inductor is critical for proper operation and peak efficiency. It must be sized large enough that it can carry
the full current that the power supply is designed to deliver. There are three factors when evaluating inductor
loss. First, there is the DC resistance of the conductors and, because of this, there are losses as the current flows
through the inductor. The DC resistance value should be provided by the manufacturer. Knowing this, the
inductor loss due to the DCR (DC resistance) of the inductor can be calculated with the following formula:
2
Pdc = Irms × Rdc
Equation 1. Inductor Loss due to DC Resistance
Where:
Pdc = DC losses in Watts
IRMS = rms value of the peak current applied across the inductor
Rdc = DC resistance of the inductor
The magnetic materials used also contribute to the inductor efficiency. The core loss is the amount of power that
the core consumes during operation. As the frequency of operation for a given inductor is increased, the core loss
increases. The core area also contributes to loss, the more material (effective core volume) the greater the loss.
Because of this, the core material, both type and area becomes one of the key factors when selecting an inductor.
The inductor must be sized for the maximum current so that it does not saturate, but not be so large that
efficiency is lowered. Also, the core must be composed of the appropriate material for the intended frequency.
The core loss is also provided by the inductor manufacturer. Once the core loss is known, the power consumed
due to core loss can be calculated by the following formula.
Pcore = K1 × ƒX × BY × Ve
Where:
Pcore = Power loss due to the core, in milliwatts
K1 = the constant for the core material, provided by the inductor manufacturer
ƒ = Frequency in kHz
B = Peak flux density in kGauss
X = Frequency exponent
Y = Flux density exponent

Ve = Effective core volume in cubic cm
The final parameter that determines inductor loss is the AC loss. Because the input side of the inductor is an AC
waveform, the inductor is therefore subjected to AC voltage and AC current. This results in losses due to the AC
resistance. The inductor manufacturer can provide the AC resistance for the inductor being evaluated. Once the
ACR (AC resistance) is known, the loss due to AC resistance can be calculated by the following formula.
Pac = Irms2 × Rac
Where:
Pac = AC loss in Watts
Irms = rms value of the peak current applied across the inductor
Rac = AC resistance of the inductor, provided by the inductor manufacturer
Once these three parameters are known, the total power loss for the inductor can be determined by adding the
three values together.
Ploss = Pdc + Pac + Pcore
The inductor must be selected to handle the maximum power that the power supply is designed to deliver, but
this may not be the overall efficiency design maximum. The system needs to be evaluated to determine the
current and voltage requirements, and plotting these operating points over time, a map can be created that shows
the percentage of operation while running the target applications. Next, the percentage of time at various power
levels can be evaluated. Knowing these numbers can help determine what power levels may need to be
optimized for maximum efficiency.
To achieve the best possible efficiency and stability, it is recommended that the power supply designer work
closely with the technical representative from the company that is providing the power supply controller. They
usually have recommendations regarding inductor and MOSFET selections that result in good overall efficiency.
19.4.3.6 Voltage Regulator Capacitor Selection

Besides the obvious, filtering out transients and providing bulk storage, the capacitors used, especially the bulk
storage capacitors, also affect the efficiency of the power supply. All capacitors have a series resistance, or ESR.
Because this results in loss as current flows, the ESR of the capacitor results in dissipation as current flows in
and out of the capacitor. For this reason, when selecting the capacitors for any high-current power supply,
choose components with the lowest ESR possible. This not only improves the efficiency of the power supply but
it also improves the transient response of the power supply as well.
The dissipation factor must also be considered when selecting a capacitor for a power supply. This is determined
by the dielectric material and general construction of the capacitor. The dissipation factor is the tendency of the
dielectric to absorb and convert some of the applied AC energy to heat. The dissipation factor should be
provided by the capacitor manufacturer, and it is related to the ESR and the reactance of the capacitor, as shown
by the following formula.
Dissipation Factor = tanδ = ESR/Xc
Where:
ESR = Effective Series Resistance, as provided by the manufacturer
Xc = AC reactance of the capacitor
The power dissipated by the capacitor, Ploss, can be shown by the following formula. Note that besides wasting
energy, dissipation can result in excessive heating and premature failure.
Ploss = ESR × IRMS2

Where:
Ploss = Power dissipated by the capacitor, shown in Watts
ESR = Effective Series Resistance, as provided by the manufacturer
IRMS = RMS ripple current
19.5 Power Distribution from the Regulator

With the increasing current levels in today's designs, delivering the power to the components can have the same
effect on efficiency as tuning the regulator design.
This lost power not only takes away from the delivered power, it also produces excess heat, which needs to be
removed. The formula below shows how to calculate power loss due to board resistance.
Ploss = I2 × R
Where:
Ploss = Power dissipated by the trace or pour, shown in Watts
I = Sustained average current
R = Resistance of the current path (board trace or pour)
To minimize loss in the power distribution, higher current power rails need to be implemented as copper pours
on the board using suitably weighted copper.
Avoid any areas where the copper pour is "necked down," or where excessive vias reduce the effective width of
the pour. For extremely high current levels consider the use of parallel pours on additional layers. This helps
reduce the resistance and power dissipated within the board.
Place the power supply as close to the as possible. Reducing the length of the pour decreases the resistance.
Increase the width of the pour to reduce the effective resistance. Figure 183 is an example of where the copper
pour is necked down reducing the effective width of the pour and must be avoided. The resistance of the pour is
the greatest at the narrowest point, thus minimizing the benefit for using a pour in the first place. The goal is to
create a wide, consistent shape that can effectively carry the current.

Figure 183. Copper Pour—Necked Down Example
Figure 184 shows another example of something to avoid or minimize when laying out a copper pour. While the
outline of the copper pour shown in Figure 184 is consistent; the actual effective width has been severely
minimized due to careless via placement. Remember, vias have a void area for vias that do not connect to the
net.
Figure 184. Copper Pour—Bad Via Placement Example
Figure 184 illustrates an example of a poor copper pour implementation. Figure 185 illustrates a better example.
Although vias pass through the plane in the center of the pour, the effect of the reduced width is not as bad as the
example shown in Figure 184.

_PCB_Pour_Better_Example.vsd
Figure 185. Copper Pour—Good Via Placement Example
Also, when changing layers, be sure to use sufficient vias to minimize the resistance of the layer change. The
actual number of vias required depends on the size of the via, copper weight of the layers and the wall thickness
of the plating within the via. At the socket, avoid using a single via for multiple power or ground pins. Always
use a single via for each power and ground pin, with the via placed as close as possible to the pin. Stagger vias to
avoid creating large void areas in planes. Always follow the recommendations found in Power Distribution
Network Design Guidelines regarding the type, number and placement for decoupling capacitors.
Figure 186 shows example recommended and not recommended via usage for power and ground pins.
Recommended, Not Recommended, via

one via per power pin shared between power
pins
Figure 186. Power and Ground Via Placement

It is recommended to provide a separate via for each power and ground pin. Unless capacitor placement dictates
using shared vias, do not place multiple power or ground pins on a single via.
19.5.1 Power Status Indicator

Power status indicator is a feature that enhances the efficiency of the power supply. Most power supplies do not
operate at their maximum efficiency when lightly loaded. Because the current range for the can vary widely
when the is operating in a lower power P-State, the core voltage regulator does not operate at maximum
efficiency. This works against the system as it attempts to minimize power consumption by entering a lower
power P-State.
To help improve the efficiency at lower power levels, the core power supply can be designed to switch
operational modes when the current requirements are low. There are several strategies that the power supply
designer can incorporate to improve operational efficiency when operating at lower currents, such as shedding
power supply phases. By reducing the number of active phases, the MOSFET gate charge and discharge currents
are reduced as are the shoot-through currents as the high- and low-side MOSFETS are switched on and off.
Furthermore, inductor currents can be closer to ideal, as the on-times are longer for one or two phases supplying
a reduced current as opposed to the on-times if four phases are active for a low current. Each power supply
controller benefits from efficiency-enhancing techniques. Work with the power-supply vendor to ensure that the
design is optimal.

Appendix A GRAPHICS CONNECTOR PINOUTS

Connector Pinouts
Table 140 lists the complete pinout of the Mini DisplayPort connector including signal names and descriptions
(provided for reference).
Table 140. Pinout of Mini DisplayPort Connector
Pin DP Connector Description
1 GND Ground
2 HPD Hot Plug Detect
3 ML_Lane 0(p) MainLink, Lane0 Data+
4 VSS or CAD (Config1)11 VSS or CAD (Config1)
5 ML_Lane 0(n) MainLink, Lane0 Data-
6 VSS or CEC (Config2)22 VSS or CEC (Config2)
7 GND Ground
8 GND Ground
11 ML_Lane 1(n) main Link, Lane1 Data-
12
13
ML_Lane 3(n)
GND
MainLink, Lane3 Data-
Ground
14 GND Ground
16 AUX CH(p) Aux Channel, Data+
18 AUX CH(n) Aux Channel, Data-
19 GND Ground
20 DP_PWR Power Out
Note: 1. GND in DP mode and Cable Adaptor Detect (CAD) in DP++, DVI and HDMI modes.
™
2. GND in DP and DVI modes and is Consumer Electronics Control (CEC) in HDMI mode. The processor does not support CEC in HDMI
mode.
Table 140 lists the complete pinout of the Mini DisplayPort connector including signal names and descriptions
(provided for reference).
Table 141. Pinout of Mini DisplayPort Connector
1 GND Ground
309
Table 141. Pinout of Mini DisplayPort Connector (continued)

4 VSS or CAD (Config1)11 VSS or CAD (Config1)
6 VSS or CEC (Config2)22 VSS or CEC (Config2)
7 GND Ground
8 GND Ground
11 ML_Lane 1(n) main Link, Lane1 Data-
13 GND Ground
14 GND Ground
16 AUX CH(p) Aux Channel, Data+
18 AUX CH(n) Aux Channel, Data-
19
GND Ground
20 DP_PWR Power Out
Note: 1. GND in DP mode and Cable Adaptor Detect (CAD) in DP++, DVI and HDMI modes.
™
2. GND in DP and DVI modes and is Consumer Electronics Control (CEC) in HDMI mode. The processor does not support CEC in HDMI
mode.
Table 142 lists the pinout for the HDMI connector
Table 142. Pinout of HDMI™ Connector

™
Pin HDMI Signal Description
1 TMDS Data2+ TMDS Data
2 TMDS Data2 Shield Grounding Shield
3 TMDS Data2– TMDS Data
6 TMDS Data1– TMDS Data
9 TMDS Data0- TMDS Data
10 TMDS Clock+ TMDS Clock
310
Table 142. Pinout of HDMI™ Connector (continued)

™
Pin HDMI Signal Description
11 TMDS Clock Shield Grounding Shield
12 TMDS Clock– TMDS Clock
13 CEC Consumer Electronics Control
14 RESERVED –
15 SCL Display Data Channel - Clock
16 SDA Display Data Channel - Data
17 DDC/CEC Ground Digital Ground
18 +5 V Power
311
Appendix B HEIGHT-RESTRICTION DRAWINGS

Height-Restriction Drawings for FP6 Motherboards
Refer to the Thermal Design Guide for FP6 Processors (NDA) for information about the design of thermal
solutions for FP6 processor-based systems. Figure 187 and Figure 188 provide keepout and height restrictions
required to enable using SDLE on a FP6 processor-based system. See Static and Dynamic Load Emulator 2
(SDLE2) User Guide (NDA) for information about SDLE. Also you can search DevHub for other SDLE related
information https://devhub.amd.com/search/sdle .
312
8 7 6 5 4 3 2 1
REVISIONS
ZONE REV. DESCRIPTION DATE APPROVED
1 INITIAL RELEASE 7/25/18 CLG
F
F
E E
56178 Rev. 1.03 January 2020
D D
C C
B B
Figure 187. FP6 Processor SDLE Component Keepout Height-Restrictions Sheet 1 of 2

No Heatsink
UNLESS OTHERWISE SPECIFIED: NAME DATE

DIMENSIONS ARE IN MM
DRAWN 3/7/18
ADVANCED MICRO DEVICES
CLG
TOLERANCES: CHECKED - -
ANGULAR MACH: 0.5°
TITLE:
A ANGULAR BEND: 1.0° ENG APPR. - A
-
TWO PLACE DECIMAL: .50 FP6 SDLE component Keepout
THREE PLACE DECIMAL:
.250 MFG APPR.
Height Restriction
INTERPRET GEOMETRIC Q.A.
PROPRIETARY AND CONFIDENTIALTOLERANCING PER:
COMMENTS:
THE INFORMATION CONTAINED IN THIS MATERIAL
DRAWING IS THE SOLE PROPERTY OF SIZE DWG. NO. REV
ADVANCED MICRO DEVICES. ANY N/A
REPRODUCTION IN PART OR AS A WHOLE
FINISH
WITHOUT THE WRITTEN PERMISSION OF 2
ADVANCED MICRO DEVICES IS N/A C 97Z0000800
PROHIBITED.
DO NOT SCALE DRAWING SCALE: 1:5 SHEET 1 OF 2
8 7 6 5 4 3 2 1
313
FP6 Processor Motherboard Design Guide
8 7 6 5 4 3 2 1
314
F
F
Component height restriction zone
No components allowed
E Maximum component height allowed is 9.5mm E
110
FP6 Processor Motherboard Design Guide
60
D D
2 1 .5 0
A1
38
43
76
C C
16.50
33
B B
Figure 188. FP6 Processor SDLE Component Keepout Height-Restrictions Sheet 2 of 2

ADVANCED MICRO DEVICES

TITLE:
A A
FP6 SDLE component Keepout
Height Restriction
SIZE DWG. NO. REV
C 97Z0000800 2
SCALE: 1:2 SHEET 2 OF 2
8 7 6 5 4 3 2 1
56178 Rev. 1.03 January 2020
Glossary
accelerated processing unit (APU)
Processing device that integrates a central processing unit (CPU) and a graphics processing unit (GPU)
on the same die, designed to improve data transfer rates between the components and reduce power
consumption.
cyclic redundancy check (CRC)
An error-detecting algorithm used to produce a checksum and detect changes to raw data. A cyclic
redundancy check is computed and appended to data prior to transmission or storage; the CRC
checksum is compared to an independent checksum calculation to confirm that no changes occurred to
the data during storage or transit. The CRC is particularly good at detecting common errors caused by
noise in transmission.
DDR (DDR)
A bus operating with double data rate transfers data on both the rising and the falling edges of the clock
signal.
differential signaling
A method of transmitting information electrically with two complementary signals sent on two paired
conductors, called a differential pair. Because external interference tend to affect both conductors
together, and information is sent only by the difference between the conductors, the technique improves
resistance to electromagnetic noise compared with use of only one conductor and an un-paired reference.
dual in-line memory module (DIMM)
A series of dynamic random access memory integrated circuits. DIMMs differ from single in-line
memory modules (SIMMs) in that DIMMs have separate electrical contacts on each side of the module;
on SIMMs the contacts on both sides are redundant.
dynamic random-access memory (DRAM)
A type of random-access memory that stores each bit of data in a separate capacitor within an integrated
circuit.
dynamic random-access memory down
Discrete dynamic random-access memory (DRAM) device soldered to the motherboard.
general purpose port (GPP)
In current usage, a GPP generally refers to a a high-data transfer port that complies with the PCI Express
(PCIe) standard. That association, however, can change with technology changes.
graphics processing unit (GPU)
Dedicated hardware for graphics processing that may reside on a card, soldered down on the
motherboard, or integrated into the same IC as the CPU.
low-voltage translator (LVX)
Device or logic that converts voltage signals from one level to another level so that devices with
different signal levels can communicate.
peripheral component interconnect (PCI)
Industry specification for connecting hardware devices to a computer's central processor. The PCI
specification defines the electrical characteristics and signal protocol for the interconnect bus.
peripheral component interconnect express (PCIe®)
Expansion bus standard designed to replace the older PCI and AGP bus standards. A key difference
between PCIe and PCI is bus topology. PCI uses a shared parallel bus architecture, where the PCI host
and all devices share a common set of address/data/control lines. In contrast, PCIe is based on point-to-
point topology, with separate serial links connecting every device to the root complex (host).
realtime clock (RTC)
Glossary 315
Timer that keeps track of the current wall-clock time. Benefits of using the realtime clock to keep time
include low power consumption, accuracy, and the ability to free the main system for time-critical tasks.
SDRAM
Dynamic random access memory (DRAM) that is synchronized with the system bus.
solid-state disk (SSD)
Data storage device that contains no moving parts but instead uses integrated circuits as memory to store
data persistently.
switchable graphics (SG)
Platform feature that enables a system to switch between an internal graphics processor and a discrete
graphics processor, either manually or automatically, depending on the system.
low power (LP)
Low Power.
universal serial bus (USB)
Universal Serial Bus.
316 Glossary

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AMD Confidential—Advance Information

Publication # 56178 Revision: 1.03

Advanced Micro Devices

Dolby Laboratories, Inc.

List of Tables .................................................................................................................................... 13

List of Abbreviations ....................................................................................................................... 16

4 Clock Design Guidelines....................................................................................................................47

4.2.1 RTCCLK Real Time Clock (RTC) and Battery Interface...................................................................... 49

5 Memory Design Guidelines............................................................................................................... 53

7 Display Interface Design Guidelines.............................................................................................. 138

7.5.1 Layout Guidelines—DisplayPort ML to DP or eDP Connectors......................................................... 158

8 USB Interface Design Guidelines................................................................................................... 170

9 DisplayPort Alternate Mode/USB to USB-C® Connector Design Guidelines............................187

10 SATA Interface Design Guidelines...............................................................................................198

11 Audio Interface Design Guidelines...............................................................................................203

12 Secure Biometric Camera Solution.............................................................................................. 209

13 ACPI Interface Design Guidelines............................................................................................... 211

13.2.2 Modern Standby Power/Reset Design PCIe® Devices.......................................................................213

14 Miscellaneous Signals Design Guidelines.................................................................................... 226

15 Power Distribution Network Design Guidelines......................................................................... 261

15.1 Power Distribution Network Design Guidelines............................................................................................... 261

16 EMI and ESD Design Guidelines................................................................................................. 272

18 Power Optimization Design Guidelines....................................................................................... 288

18.1.1 Device Implementation—USB........................................................................................................... 288

19 Power Regulator Design Guidelines.............................................................................................292

Appendix B HEIGHT-RESTRICTION DRAWINGS.................................................................... 312

Figure 52. DRAM Placement—Dual-Rank x16 SDP DRAMs............................................................................................... 91

Figure 107. Example 2 USB Micro-B VSS/Reference Plane Void.......................................................................................174

Figure 163. Power Connections for Processor and Dual-Plane Supply.................................................................................267

Table 108. Modern Standby Wake Source/Events................................................................................................................ 216

Date Revision Description

Date Revision Description

Date Revision Description

• Chapter 1: Added PID# 56490 to Reference Documents Table.

November 2018 0.10 Preliminary release.

Table 1. Feature Compatibility

FP6 Type 1 FP6 Type 2

On-chip Graphics Four Display Controllers

Four Display Interfaces

DDR EVENT_L Yes

Voltage Planes VDDCR

Serial Advanced Technology Attachment Yes

Secure Digital I/O (SDIO) No

HDA/Soundwire/Inter-IC Sound (I2S) Yes

Inter-Integrated Circuit (I2C) Yes

Universal Video Decoder (UVD) Yes

Table 1. Feature Compatibility (continued)

FP6 Type 1 FP6 Type 2

System Management Bus (SMBus) Yes

Low Pin Count/Serial Peripheral Interface (LPC/ Yes

Enhanced Serial Peripheral Interface (eSPI) Yes

Universal Asynchronous Receiver/Transmitter Yes

1.2 General Power Supply Guidelines

1.3 Pinout Assignment www.teknisi-indonesia.com

1.4 Package Information

1.5 Reference Documents

Table 2. Reference Documents