A Switched Current Sigma Delta Modulator using a

Low Distortion Feedfoward Topology

Cesar Augusto Prior Cesar Ramos Rodrigues

Microeletronics Group - Gmicro Microeletronics Group - Gmicro
Federal University of Santa Maria Federal University of Santa Maria
Santa Maria – RS, Brazil Santa Maria – RS, Brazil
[email protected] [email protected]

Abstract—Implementation of feedforward paths for low- For SI technique, the input impedance is low, and the
distortion topologies on switched capacitor sigma-delta (SC-SD) parasitic gate-to-source capacitance (Cgs) is small. Thus, SI
modulators was successfully reported elsewhere [13]. In this technique is inherently suitable for the high-frequency
paper we propose the use of a similar low distortion topology on applications. Unfortunately, the main drawback in this
an implementation of a switched current sigma-delta (SI-SD) implementation is the non-linearity of SI memory cell, given
modulator. The objective is a reduction of harmonic distortion by harmonic distortion [4][5], finite conductance ratio
observed in implementations with simple integrator cells. In this between output to input stages, and mismatch between mirror
approach, one of the main SI cell drawbacks, the harmonic transistors, which are typically higher than 0.1% in standard
distortion due to conductance variation, can be reduced by
CMOS processes [3].
alleviating the signal in the integrators path. In this approach,
the integrators ideally process only noise. Relaxing requirements The SC technique is the dominant choice in SD
of integrators allows simpler and faster switched-current implementation because of its high accuracy and lower noise
integrator circuits. The feedforward SI-SD modulator was in present CMOS technologies.
designed in XFAB CMOS 0.6µm technology. Simulated results
points to a reduction of harmonic distortion from 2% in a Nonetheless, advances in SI implementations, voltage and
classical 2nd order feedback topology to 0.2% in the feed feature size progressive reductions may favor this technique
forward design. It also provides a reduction of 30% in the silicon making it comparable to the SC solution.
area, and higher sampling frequency.
Most of SI-SD designs reported in literature, such as [3][6]
are classical 2nd order feedback topologies implementations,
I. INTRODUCTION typically represented in Fig. 1.
As integrated circuits move into ultra-deep-submicron
CMOS technologies, new analog design techniques are
required in order to keep or enhance the performance,
avoiding the problems from scale and voltage reductions.
The Sigma-Delta modulator is one of the most popular
implementations for high accuracy ADC, requiring few Figure 1. Classical 2nd order Σ∆ modulator
modifications of standard CMOS technologies. There are
currently two techniques employed for SD implementation: The linear model, given in eq. (1) denotes a Signal
switched-capacitor (SC), or switched-current (SI). Transfer Function, STF=Z-2, and a Noise Transfer Function,
NTF=(1-Z-1)2, when g1=g1’=1, g1’g2gq=1 and g2’=2g1’g2 [7].
In SC circuits, most of speed and linearity performance
relies on operational amplifiers’ (opamps) characteristics.
g1 (1)
Unfortunately, high-dc gain, linear settling time, and large Y (Z ) = X ( Z ) Z - 2 + Q ( Z )(1 - Z - 1 ) 2
phase margin, are design tradeoffs in opamp’s design, and are g 1'
very difficult to satisfy simultaneously [1][2]. Moreover, as all
MOS transistors operate in saturation region, the capacitance In this topology, the linearity relies mainly on the
mismatch errors in SC circuit need be reduced to less than performance of SI integrators. That justifies the efforts to
0.01% with double poly-silicon process and linear capacitors improve the cell. [8][9][10][11][12].
[3].

This work is supported by FINEP and MCT/CNPq.

978-1-4244-7773-9/10/$26.00 ©2010 IEEE 296

 An alternative to minimize nonlinearities due the
integrators is the feedforward topology, originally
implemented by [13] in a SC- Σ∆ converter.
The main advantage of including feedforward paths in Σ∆
modulators is to relax the requirements on analog blocks. The
general topology of a loop filter is represented in Fig. 2.

Figure 3. Matlab-Simulink Feedforward 2nd order Σ∆ modulator

Figure 2. Feedforward 2nd order Σ∆ modulator

Analysis of the linearized system, assuming an ideal

digital-to-analog converter (DAC) and coefficients
g1=g1’=g2=g3=1, g2’=0 and g3’=2, leads to the following results
on the feedforward modulator [14]:

STF = y / x = 1 , (2)

NTF = y / q = (1 - Z -1 )2 , (3)

i1 = -Z -1 (1 - Z -1 )Q(Z ) , (4)

i2 = -Z -2Q(Z ) . (5) Figure 4. Power Spectral Density Matlab-Simulink Feedforward 2nd order
Where q and Q(z) is the quantization noise in time and Z Σ∆ modulator
domains.
As the signal transfer function is forced to unity by
feedforwarding, ideally no signal is processed by integrators,
just the quantization noise.
Hence, if instead of choosing complex current integrator
topologies for non-linearity minimization, we propose the use
of simpler SI memory cells in feedforward Σ∆ modulator in
order to circumvent not idealities in the integrators. The
implementation of SI memory cells with a single transistor is
demonstrated at simulation level. Its advantages are: higher
speed, low area and low cost of basic digital CMOS process.

II. THE SI FEEDFORWARD MODULATOR

A. High Level Implementation
The high level simulation of feedforward Σ∆ modulator,
shown in Fig. 3 was realized in Matlab/Simulink using its Figure 5. Power Spectral Density at the first and second integrator, Matlab-
ideal block libraries. The output bitstream is saved into a file, Simulink Feedforward 2nd order Σ∆ modulator
and processed by built-in power spectral density (PSD) script,
the schematic is shown in Fig. 3. B. Eletrical Implementation
The PSD of the output bitstream sampled at 5MHz, 5000 The simulation of a full SI feedfoward Σ∆ modulator
points in 1ms time, is shown in Fig. 4. electrical was performed with XFAB 0.6µm CMOS
The PSD spectra at the first and second integrators are technology parameters.
shown in Fig. 5. , confirming the hypothesis of minimum The integrator is implemented with a single SI cell [7], as
signal processing. shown in Fig. 6. Transistors M9, M20 and M26, M18 form the
differential SI integrator. Each cell is biased with 30µA.
During clock phase F1, integrated current signal flows
through nodes IO1+ and IO1_, being mirrored with a 4:1 ratio

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(2:1 in differential mode) to the next stage. The feedforwarded
integrated current signal is supplied through nodes Icm+, and
Icm_, being mirrored with a ratio of 2:1 (1:1 in differential
mode) to the comparator block. The differential structure
imposes a common mode balance on the crossover current
mirrors (nodes Vgs_M9 and Vgs_M26).

Figure 7. Differential comparator

The block diagram of the full Σ∆ modulator is shown in

Fig. 8. Nodes Ic+ and Ic_ sum the input signal with outputs of
the first and second integrators according to their coefficients.
The DAC is a 1 bit V-I converter, such as in [7]. During
the in the clock phase Φ2, the output of the V-I converter
delivers + or -15µA, depending on the present state of the
output bitstream.
Figure 6. Single SI Diferential Memory Cell

The current comparator is shown in Fig. 7. It consists of a

two stage current sensing, cascaded with a differential track-
and-latch comparator.

Figure 8. Electrical CMOS-SI-Feedforward 2nd order Σ∆ modulator

III. SIMULATION RESULTS Simulation results are summarized in TABLE I. Figures of

SNR and THD obtained for SI-Σ∆, designed with classic 2nd
Simulated tests of the SI modulator were performed with order feedback and low distortion feedforward topologies are
sinusoidal inputs with a frequency of 10kHz, and amplitude of compared. Although both designs are made of blocks with the
12µA, 10µA, 5µA, 1µA, 0.1µA. The PSD plot of the output same topologies, the implementation of feedforward, and the
bitstream for all input signals is presented in Fig. 9. If the consequent reduction of the amount of signal processed by SI
Signal-to-noise ratio (SNR) is computed for simulation run cells, result in a reduction of the harmonic distortion of 90%,
and plotted against the input data, it results in a dynamic range 16.7% on power consumption, and 33.3% on silicon area.
graph shown in Fig. 10.
Fig. 11. illustrates the PSD of integrators output currents,
demonstrating that the signal is minimally processed.

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 The decrement of area and consumption derives from
smaller transistor, bias current, and one DAC less than in
feedback topology. The relaxed operation permits also higher
oversampling rates, increasing the SNR, and the ENOB in
ADC implementations.

IV. CONCLUSIONS
The use of a low distortion topology in SI-Σ∆ modulator
permits to relax integrator cells’ linearity constraints, because
the amplitudes of signals processed by them are drastically
reduced. In addition to harmonic reduction, decreasing the
signal levels at integrators allows implementations with
simpler, smaller, faster integrators; and the elimination of one
Figure 9. PSD at output bitstream of feedfoward Σ∆ modulator
feedback path from the DAC. Simulation results show that
feedforwarding signal provides a THD reduction of
approximately 20 dB for a -10dB input signal, using the same
circuit blocks. An area reduction of nearly 30% is also
estimated.

REFERENCES
[1] Maloberti, Franco., “Data Converters”, Springer, Netherlands, 2007,
ISBN-10 0-387-32485-2.
[2] Schereir, R., Temes, G., “ Understanding Delta-Sigma Data
Converters”, John Wiley & Sons Inc. NY, 2004.
[3] Guo-Ming Sung, Chih-Ping Yu, Dong-An Yao, “A comparison of
second-order sigma-delta modulator between switched-capacitor and
switched-current techniques”, Circuits and Systems, 2008. APCCAS
2008. IEEE Asia Pacific, DOI: 10.1109/APCCAS.2008.4746234
Publication Year: 2008, Page(s): 1172 – 1175.
[4] De La Rosa, J. M.;Pérez-Verdú, B; Medeiro, F.; del Río, R.;
Figure 10. Dynamic Range of feedfoward Σ∆ modulator
Rodríguez-Vásquez, A.; “Analysis of Error Mechanisms in Switched-
Current Sigma-Delta Modulators”, Analog Integrated Circuits and
Signal Processing, 38, 175–201, 2004, Kluwer Publishers. Netherlands.
[5] J. Martins, V. Dias e M. Silva, “Harmonic Distortion in Switched-
Current Circuits”, IEEE International Symposium on Circuits and
Systems, Hong Kong, 1997, pp. 2000-2004.
[6] Guo-Ming Sung Dong-An Yao Kuo-Hsuan Chang Shyue-Ru Yao,“A
Second-Order Sigma-Delta Modulator With Switched-Current Memory
Cell For Closed-Loop Motor Control System” Power Electronics
Specialists Conference, 2006. ISSN: 0275-9306, ISBN: 0-7803-9716-9.
[7] De La Rosa, J. M.;Pérez-Verdú, B.;Rodriguez-Vazquez, A.;
“Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta
Modulators dor Digital Communication Chips”, Kluwer Academic
Publishers, Boston, 2002, ISBN: 0-7923-7678-1.
[8] Hughes, J. B.; “Analogue IC Design: the Current Mode Approach”,
edited by C. Toumazou et al, pp. 424-435, IEE Circuit and Systems
Series 2, 1990.
Figure 11. PSD at output of first and second integrators [9] Toumazou, C.; et al; “Regulated Cascode Switched-Current Memory
Cell,” Electronic Letters, Vol. 26, No. 5, pp. 303-305, March 1990.
[10] Hughes, J.B; Moulding, K.W.;“S2I: A Switched-Current Technique for
TABLE I. ADC IMPLEMENTATIONS. COMPARATIVE RESULTS High Performance”, Electronics Letters, Vol. 29, pp1400-1401, 1993.
[11] Battersby, N. C.; Toumazou, C.; "Class AB Switched-Current Memory
Modulator for Analogue Sampled Data Systems", Electronics Letters, Vol. 27, pp.
SI_FB SI_FF SI_FF SI_FF
Parameter 873-875, 1991.
Area(mm2) 0.12 0.08 0.08 0.08 [12] Nairn, D.; “Zero-Voltage Switching in Switched-Current Circuits”,
IEEE International Symposium on Circuits and Systems, 1994, pp. 289-
Consumption(mW) 12 10 10 10 292.
Frequency (MHz) 5 5 20 50 [13] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-
Band-width (kHz) 10 10 10 10 distortion delta–sigma ADC topology,” Electronics Letters, Vol. 37, pp.
737–738, 2001.
SNR(dB) 60 60 80 90 [14] Ahmed Gharbiya, Trevor C. Caldwell, and D. A. Johns “High-Speed
ENOB 9 9 12 14 Oversampling Analog-to-Digital Converters” International Journal of
THD (%) 2 0.2 0.2 0.5 High Speed Electronics and Systems, World Scientific Publishing
Company, 2005.

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