PhD Comprehensive Examination

Department of Computer Science & Engineering

GROUP – C

Date: 09-Apr-2021 Duration: 1 Hour 15 Minutes Maximum Marks: 30

[ Answer any three questions ]

1. (a) Consider the combinatorial circuit given below. Derive the minimal sum-of-product expression
for the output of F. (2)

(b) First draw the state diagram and then design a synchronous counter using JK flip-flop, which
goes through the following states 1, 4, 2, 3, 1, 4 ,2, 3,… repeatedly. (4)

(c) Assume that in a combinatorial circuit with output F, the minterms can be given as below,
where m denotes the minterms and d denotes the don’t care conditions.

F(A, B, C, D)= ∑ m(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)

Derive all the prime implicants and essential prime implicants using K-Map. (4)

2. (a) Consider the sequential circuit given below, implemented using JK flip-flops. Assume that the
circuit is initialized with Q2Q1Q0 = 000. Compute the state sequence of this circuit in the next 4
clock cycles. (3)

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 (b) Design a 1-to-8 demultiplexer using two 1-to-4 demultiplexers and a NOT gate. You are not
allowed to use any other types of gates. (2)

(c) Implement the following Boolean function with a multiplexer (of smallest size). You are only
allowed to use a single multiplexer and any number of NOT gates. (3)

F(P, Q, R, S) = ∑ m(0, 1, 3, 4, 8, 9, 15).

(d) Construct a JK flip-flop using a D flip-flop, a 2-to-1 multiplexer and a NOT gate.
(2)

3. (a) Consider the IEEE 754 single precision floating point representation which has the 31st bit as
sign bit (S), 30th to 23rd bit as Exponent (E) and 22nd to 0th bit as Mantissa (M). The decimal value
of such a number is given by

with E being converted to decimal before subtraction and M kept in binary. Convert the decimal
no 8.25 to IEEE 754 single precision floating point representation. (3)

(b) For the instruction sequence given below, list all dependencies of type Read After Write
(RAW), Write After Write (WAW), and Write After Read (WAR). The instruction format is
(operation, destination, source1, source2). (7)

I0: add r1 r2 r3
I1: sub r3 r1 r2
I2: add r4 r1 r3
I3: mul r1 r2 r3

4. (a) Consider the subleq instruction, “subleq a, b, c” with a, b, c being direct memory addresses,
having the following semantic meaning.

Mem[b] = Mem[b] - Mem[a]; if (Mem[b] ≤ 0) goto c;

where Mem[x] represents the content of the memory location with address x. The conditional
branching can be suppressed by setting the third operand equal to the address of the next
instruction in sequence. If the third operand is not written, this suppression is implied. Consider
that you are using a computer with only this single instruction in the ISA. Write a sequence of
subleq instructions with suitable parameters such that the sequence realises the instruction “MOV
a, b” which results in the content at location b getting replaced by the content at location a, with
the content of all other memory locations remaining exactly same. Assume that there exists a
writable location Z initially containing 0. (6)

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 (b) In the context of caching, recall that the miss penalty is the additional time it takes for memory
access in the event of a cache miss. Therefore, a cache miss takes (hit_time + miss_penalty) time
to service a request. Suppose that you have a cache system with the following properties.

(i) L1 cache hits in 1 cycle (miss rate 25%)

Compute the Average Memory Access Time (in number of cycles) for the memory system.
(4)

5. (a) Consider the following set of processes, given along with their arrival times and their CPU
burst times (both in units of milliseconds (msec)).

Process P1 P2 P3 P4 P5 P6

Arrival Time (msec) 0 2 3 5 6 8

CPU Burst (msec) 7 4 6 2 8 5

Calculate the average waiting time of the processes for the following scheduling algorithms:
(i) preemptive Shortest Job First (also known as Shortest Remaining Time First (SRT)), (ii) round-
robin scheduling with time quantum of 3 msec. (2 + 2)

(b) It is time for elections amidst the pandemic. Consider that a polling station has one polling
agent, one voting machine, and a waiting room with exactly N seats (placed maintaining social
distancing). Voters come to this polling station to cast their votes following some rules. If a voter
arrives, and finds that one voter is casting the vote and all N waiting room seats are occupied,
he/she immediately leaves the polling station according to the rules. Otherwise, the voter sits on
one of the empty waiting room seats and waits. If there is no one casting vote at a particular point
of time, any one of the waiting voters can approach the agent and cast his/her vote. The agent goes
to sleep if there is no voter in the polling station. If a voter comes and finds the agent sleeping, the
voter wakes up the agent.

We want to simulate this situation considering that the agent and each voter are implemented as a
thread/process, all of which will run concurrently. Assume that the following three semaphores
and one variable are already declared and initialized as shown:

semaphore agentReady = 0, voterReady = 0, accessSeats = 1;

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 Every semaphore has P( ) (or, wait( ) ) and V( ) (or, signal( ) ) functions available as
<semaphore>.P( ) and <semaphore>.V( ). For example, the semaphore agentReady has the
functions agentReady.P( ) and agentReady.V( ) available.

Fill in the blanks (marked as blank(i), blank(ii), ….) in the functions below to implement the agent
and a voter, so as to ensure that the agent and voters are synchronized and free from deadlock.
Note that each blank can have one or more P( ) or V( ) statements. (6)

void agent( ){
while (true) {
____________ blank (i) _________________
numFreeSeats = numFreeSeats + 1; // one voter casts vote; one seat freed
_____________blank (ii) _________________
helpVoterCastVote( );
_____________blank (iii) _________________
} // end while( )
} // end agent( )

void voter( ){
_____________blank (iv) ___________________
if ( numFreeSeats > 0 ){
numFreeSeats = numFreeSeats – 1; // sit on one free seat
_____________ blank (v) ________________
castVote( );
} else{
_____________ blank (vi) ________________
leaveWithoutCastingVote( );
} // end else
} // end voter( )

6. (a) Consider the different states in the life cycle of a process, ready, running, and waiting. For each
state transition mentioned below, mention if the transition is possible directly (i.e., not via some
other intermediate state). If yes, give one example of a situation when the said transition can take
place directly. If no, explain your answer. (i) Ready state to Running state, (ii) Running state to
Ready state, (iii) Running state to Waiting state, (iv) Ready state to Waiting state, and (v) Waiting
state to Ready state. (5)

(b) Consider a demand paged memory management system with a 32-bit address space, 4 KB page
size, and 8 GB main memory. Assume that a 1-level page table is used for the system. First state
what fields the page table will contain, and the number of bits in each field. Then show how a 32-
bit virtual address will be mapped to a physical address in this system. (3 + 2)
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