ELECTRICAL AND ELECTRONIC ENGINEERING

PARALLEL DATA TRANSFERS (I/O Operations)

INTRODUCTION

No computer regardless of its size, speed, computing abilities or other sophisticated features, is very useful unless it
can communicate with the outside world (communicate with other equipment in that system that are called
peripherals). This communication involves raw data coming into the CPU and transfer of processed data from the
computer to the peripheral.
The computer and the peripherals seldom operate at the same speed. The speed and /or timing differences somehow
must be reconciled. The data format of the peripheral may be different from that used by the computer. Some
means of format conversion is needed.
Commonly used peripherals are:
CRT display, keyboards, FD memories, HD, CD, Printers/Plotters, ADC and DAC, magnetic tapes and cassette
drivers.

INPUT/OUTPUT (I/O) AND DEVICE INTERFACING

In interfacing the microprocessor with the peripheral devices, the following functions are involved:

 Data buffering: Uses registers to hold data for some time. This reconciles the timing differences
between faster microprocessors and slower peripherals.
 Address decoding
for peripheral selection: Several peripherals can be accessed by use of external memory data bus and
connecting the I/O device chip to it. The right buffer must first be selected for
the desired peripheral. The buffer address given by the microprocessor must be
decoded.
 Command decoding: The microprocessor must inform the peripheral of what to do by using the
command signals on the control bus.
 Status decoding: Status signals are sent from peripheral to the microprocessor to inform the
correct condition of the peripheral.
 Control and timing: All communication between microprocessor and the peripheral need to be
synchronized and coordinated with the rest of the system.

PROGRAMMED INPUT OUTPUT

It is a mode of transferring data between the CPU and the logic within the peripheral. The transfers are initiated and
controlled entirely by the microprocessor. Such data transfers are executed by instructions, series of program steps
or sub-routines. During data transfers, the system follows a pre-established sequence of events called a protocol.

Example:
OUTPUT Protocol tells CPU to inform the addressed that a data word has been placed in a certain location
(buffer register) from which the peripheral can access.
INPUT CPU informs peripheral that it is waiting for it to output the word and place it in a pre-defined
location such as input buffer or accumulator. Some systems will inform the microprocessor that it
has completed the protocol step.
All times the peripherals are under control of the microprocessor.

Conditional/Unconditional programmed I/O transfer

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Unconditional
Takes place whenever the CPU so directs it.
No check is made by the CPU to determine READY or BUSY status.
Peripheral must be ready to accept or send data whenever the CPU initiates such transfer.

Conditional
Microprocessor first queries the peripheral status to find out whether it is ready to perform a transfer as shown in
Figure 1.

It is a two I/O transfer (IOT) instruction

(i) The CPU makes decision to repeat query or continue to the next instruction depending on status of
peripheral.
(ii) When the peripheral is ready, program advances to the next instruction that executes transfer.

Operation of the circuit:

The microprocessor sends an address to the peripheral address decoder

When the peripheral is ready for a data transfer, it set a status flip-flop.
The microprocessor sends out the first instruction to query the status of the peripheral.
The respective AND gate will output peripheral response.
If the peripheral is ready for transfers, the CPU stops sending queries to it and advances to next Input/Output
transfer instruction.
Word transfer is initiated and when complete, the peripheral status flip-flop is reset.
Microprocessor disables the command decoder and peripheral address decoder to release the data bus for next
operation.

Types of Input / Output

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Isolated Input / Output
Isolated I/O (also referred as peripheral I/O or direct I/O) uses dedicated input (IN) and output (OUT) instructions to
transfer data between the I/O device and the microprocessor. Isolated I/O uses separate map for the I/O space,
freeing the entire memory for use by the program.

Memory-mapped Input / Output

In memory-mapped I/O, a memory location is assigned to be input or output port, so it uses a portion of memory
space for I/O transfers. This reduces the amount of memory available, but simplifies the hardware. “MOV”
instruction is used instead of “IN” and “OUT” instructions.

Instruction format

Op-code: Bit/bits to identify instruction as an IOT instruction, single or multiword and the type of operation
(IN/OUT).

Command code: Field contain the code commanding the I/O chip to perform an I/O operation. Note that the
interface chip decodes the bits of the command.
Commands are sent to the selected peripheral in addition to status and control signals.

Address decoding: When decoded by the interface chip, it will select and activate one of the several peripherals in the
system.

The 8255 programmable Peripheral Interface (PPI)

The 8255 PPI chip shown in Figure 2 is designed to permit easy implementation of parallel I/O into the
microcomputer. The 8255 is one of the most widely used I/O chips. It has three separately accessible ports, A, B,
and C. Above all the user can program the individual ports to be input or output, and change them dynamically.

Fig. 2: The block diagram of the 8255 Chip

PA0-PA7 (Port A): This 8-bit port can be programmed all as input or all as output or all bits as bi-directional
input/output.

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PB0-PB7 (Port B): This 8-bit port can be programmed all as input or all as output or all bits as bi-directional
port.
PC0-PC7 (Port C): This 8-bit port can be all input or all output. It can also be split into two parts:

CU (Upper 4 bits PC4-PC7) and

CL (Lower 4 bits PC0-PC3).

Each can be used for input or output.

RD and WR: These two active low signals are inputs to the 8255. If the 8255 is using isolated I/O design, IOR
or IOW of the system bus are connected to these two pins. If the port uses memory-mapped I/O,
MEMR and MEMW activate them.
RESET: This is an active high signal input to the 8255 used to clear the control register. When RESET is
activated, all ports are initialized as input ports.
A0, A1,
and CS: While CS selects the entire chip, it is A0 and A1 that select the specific port. A0 and A1 are used
to access ports A, B, C, or the control register according to the table below.

Intel 8255 (a) Detailed block diagram (b) Address mapping

Programming Modes of PPI

Mode 0: Simple input or output mode:

This mode 0 is the basic input output mode. In this mode any ports A,B or C can be programmed as input or output.
Note that in this mode a given port cannot be both input or output port at the same time.
One major characteristic of port C is that one can program CL (PC0-PC3) and CU (PC4-PC7) independent of each
other.
The Control Register; is used to configure the individual ports as to be in input or output mode.

The Control Register in Mode 0

D7 D6 D5 D4 D3 D2 D1 D0
1=Mode 0 Mode selection Port A Port C Mode Port B Port C

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I/O Mode 00 = Mode 0 1=input (PC7-PC4) Selection 1=input (PC3-PC0)
01 = Mode 1 0=output 1=input 0=Mode 0 0=output 1=input
1X = Mode 2 0=output 1=Mode 1 0=output

Mode 1: I/O with handshaking capability:

One of the most powerful features of the 8255 is the ability to handle handshaking signals. Handshaking refers to the
process of communicating back and forth between two intelligent devices. Printer is a good example for Mode 1
Interfacing. Port A and B are used for input or output while Port C is used for handshaking signals.

3) Mode 2: Bi-directional I/O with handshaking:

In this mode data is transferred both in and out via the same port with handshaking capability. Port A is used as a bi-
directional port and port C is used for handshaking signals. Port B can be configured to be in Mode 0 or 1.

Input/output Instructions in 8086 CPU

In addition to memory, 80x86 microprocessors are able to access I/O ports. Ports are accessed either to bring data
from the port into the CPU (inputting) or to send data from the CPU to the port (outputting).
The 8086 microprocessor can access information from ports as well as from the memory. There are two instructions
for this purpose “IN” and “OUT”. These instructions can send data from the accumulator (AX, AL or AH) to ports
or receive data from ports into the accumulator.

Inputting Data Outputting Data

Format IN dest, source OUT dest, source
(1) IN AL, port# OUT port#, AL
(2) MOV DX, port# MOV DX, port#
IN AL,DX OUT DX,AL

In format (1) above, port# is the address of the port, and can be from 00 to FFH. This 8-bit address allows 256 input
ports and 256 output ports. No segment register is involved in computing the address, in contrast to the data
accessed from memory.
In format (2), port# is the address of the port, and can be from 0000 to FFFFH. This 16-bit address allows 65,536
input ports and 65,536 output ports. No segment register (DS) is involved.

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