ISSN 2347 - 7911

International Journal for Innovations in Engineering, Science and Management

Available online at: www.ijiesm.com Volume 5, Issue 6, June 2017

FPGA Implementation of RC6 encryption/decryption algorithm by using VHDL

Ashish Kumar Sumit Kumar Gupta Anand Singh
Reasearch Scholar M.Tech ECE Associate Prof. Dept. of ECE Associate Prof. Dept. of ECE
Bansal I.E.T ,Lko(India) Bansal I.E.T ,Lko(India) Bansal I.E.T ,Lko(India)
[email protected] [email protected] [email protected]

Abstract:- The National Institute of Standards and Technology bits), the number of rounds, and the size of the encryption key
(NIST) in the U.S. has initiated a process to develop an Advanced (in bytes). Since the AES submission is targeted at w = 32
Encryption Standard (AES) specifying a private-key encryption and r = 20, we implemented this version of RC6 algorithm,
algorithm replacement for the Data Encryption Standard using a 32 bits word size, 20 rounds and 16 bytes encryption
(DES).In this paper, we implemented RC6 encryption algorithm key lengths[14]. The RC6 block cipher diagram as shown in
that have the same structure of encryption and decryption. We
the fig 1.
devise our algorithm by inserting a symmetric layer using simple
rotation and XOR operations, in which the half of whole RC6
rounds uses encryption procedure and the rest of it are employs
decryption one. The symmetry layer is put between encryption part Plain Text
and decryption one. Nevertheless, the proposed algorithm ENCRYPTION/
improves encryption security by inserting the symmetric layer
because a differential and linear analysis has a difficulty in Cipher DECRYPTION
analyzing an encrypted stream. In this paper, we devlop a RC6 Key
algorithm on to the hardware implementation perspective with
Field Programmable Gate Arrays (FPGAs) as the target Figure 1: RC6 Cipher Block Diagram
technology. Our analysis and synthesis studies of the ciphers
suggest that it would be desirable for FPGA implementations to
A key schedule generates 2r + 4 words (w bits each) from the
have a simpler cipher design that makes use of simpler operations
that not only possess good cryptographic properties, but also make b-bytes key provided by the user. These values (called round
the overall cipher design efficient from the hardware keys) are stored in an array S [0, 2r+3] and are used in both
implementation perspective encryption and decryption. RC6 works on a block size of 64
Keywords- AES, DES, FPGA. bits and it is very similar to RC5 in structure, using data-
dependent rotations, modular addition and XOR operations;
I. Introduction in fact, RC6 could be viewed as interweaving two parallel
The design of RC6 began with a consideration of RC5 as a RC5 encryption processes[14]. However, RC6 does use an
potential candidate for an AES submission. Modifications extra multiplication operation not present in RC5 in order to
were then made to meet the AES requirements, to increase make the rotation dependent on every bit in a word, and not
security, and to improve performance. The inner loop, just the least significant few bits. The computation of f(X) =
however, is based around the same “half-round" found in (X × (2X + 1)) mod 2w is the most critical arithmetic
RC5. RC5 was intentionally designed to be extremely simple, operation of this block cipher.
to invite analysis shedding light on the security provided by 1. The best attack on RC6 appears to be exhaustive search for
extensive use of data-dependent rotations. Since RC5 was the user-supplied Encryption key.
proposed in 1995, various studies provided a greater 2. The data requirements to mount more sophisticated attacks
understanding of how RC5's structure and operations on RC6 such as Differential and linear cryptanalysis exceed
contribute to its security. While no practical attack on RC5 the available data.
has been found, the studies provide some interesting 3. There are no known examples of what might be termed
theoretical attacks, generally based on the fact that the “weak" keys.
“rotation amounts" in RC5 do not depend on all of the bits in
a register. RC6 was designed to thwart such attacks, and 1.1 Objective
indeed to thwart all known attacks, providing a cipher that 1) For securing the data firstly plain data converted into
can offer the security required for the lifespan of the cipher text by Encryption process and then cipher text
AES[13]. converted into plain text by decryption process through RC6.
RC6 is more exactly specified as RC6-w/r/b, where the 2) Design of RC6 and implement on Xilinx Spartan 3E.
parameters w, r, and b respectively express the word size (in

24
All Rights Reserved © 2017 IJIESM
 ISSN 2347 - 7911
International Journal for Innovations in Engineering, Science and Management
Available online at: www.ijiesm.com Volume 5, Issue 6, June 2017

II. RC6 algorithm overall implementation that is smaller and faster when
RC6-w/r/b operates on units of four w-bit words using the compared to the one-stage barrel- shifter implementation.
following six basic operations. The base-two logarithm of w IV. Design Architecture
will be denoted by log w. 4.1 RC6 Key Schedule Module
 a + b integer addition modulo 2w The majority of the research papers done so far about the
 a - b integer subtraction modulo 2w RC6 algorithm and its implementation in hardware, and more
 a xor b bitwise exclusive-or of w-bit words specifically in FPGAs, assume that key scheduling is done
 a X b integer multiplication modulo 2w outside of the FPGA. All of the sub keys are downloaded to
 a<<<b rotate the w-bit word a to the left by the the key storage unit of the FPGA and are then used in both
amount given by the least significant log w bits of b encryption and decryption. Our project is different in the
 a>>>b rotate the w-bit word a to the right by the sense that we are performing key scheduling and generating
amount given by the least significant log w bits of b all of the sub keys inside the FPGA. Once the key schedule
algorithm has executed and all of the sub keys have been
2.1 Key Schedule Algorithm generated, encryption and decryption will be started. If the
user wishes to input a new key, the key schedule algorithm
The user supplies a key of b bytes, where 0#b#255. From this will run again and a new set of sub keys will be generated to
key, 2r + 4 words (w bits each) are derived and stored in the be later used in en encryption and decryption. Fig 2 shows the
array S (0;… 2r + 3). This array is used in both encryption diagram for RC6 Key Schedule Module
and decryption.
2.2 Encryption and Decryption Algorithm
RC6 works with 4 w-bit registers A, B, C, D which contain
the initial input plaintext as well as the output cipher text at
the end of encryption[4]. The 1st byte of plaintext or cipher
text is placed in the least-significant byte of A, the last byte of
Plain text or cipher text is placed into the most-significant
byte. Figure shows the details encryption and decryption
algorithms for the RC6-5/20/256.
III. Design Analysis

3.1 Multiplication
When implementing the RC6 algorithm, it was first
determined that the RC6 modulo 232 multiplication was the
dominant element of the round function in terms of required
logic resources. Each RC6 round requires two copies of
modulo 232 multiplier. However, it was found that the RC6
round function does not require a general modulo 232
Fig 2 RC6 key schedule module
multiplier. The RC6 multipliers implement the function A
(2A + 1) which may be implemented as 2A2 + A. Therefore,
the multiplication operation was replaced with an array
squarer with summed partial products, requiring fewer
hardware resources and resulting in a faster implementation.
3.2 Variable Shifting
Variable shifting operations have the potential to require
considerable hardware resources, the 5-bit variable shifting
required by the RC6 round function required few hardware
resources. Instead of implementing a 32-to-1 multiplexer for
each of the thirty-two rotation output bits (controlled by the
five shifting bits), a multi-level multiplexing approach was
used. The variable rotation is broken into multiple stages,
each of which is controlled by one of the five shifting
bits[11]. For each rotation output bit of a given stage, a 2-to-1
multiplexer controlled by the stage's shifting bit is used. This
implementation requires a total of 160 2-to-1 multiplexers as
opposed to the thirty-two 32-to-1 multiplexers required for a
one-stage implementation. However, using 2-to-1
multiplexers to form the five-stage barrel-shifter results in an Fig 3 RC6 main module
Input
25
All Rights Reserved © 2017 IJIESM
 ISSN 2347 - 7911
International Journal for Innovations in Engineering, Science and Management
Available online at: www.ijiesm.com Volume 5, Issue 6, June 2017

 Key Input: Key to be used by encryption

/decryption
 Key Avail: Indicates that the key is available to be
read
 Data Input: Message/Cipher text is entered into
the cipher
 Data Avail: Indicates data is available to be read
for enc/dec
 Clock: Master Clock
 Reset: Master Reset
 Enc/Dec: Enc/Dec 0/1 encryption/ decryption
selection
 Output

 Key Read: Indicates the key has been read Figure 5: Simulation of Encryption
 Data Read: Entered into the cipher
 Data Out: Cipher text/ Plaintext is output through Input (Plain Output(cipher
this port text) text)
 Data Write: Data becomes available on output bus 0001 FADO
 Ready: Indicates that the key has been generated 0002 C70D
and the unit is ready for enc/dec. 0003 6062
V. RC6 block diagram 0004 9157
To begin with, the data is first read in 128 bits and broken Table1: Description of the Encrypted data
down to 4 x 32 bits words (A, B, C and D). Initially, and in Simulation of Decryption
case of encryption, the first two words in the S array are Figure 6 shows the waveform for simulation of decrypted
added to B and D. For Decryption, the two words are data from cipher text into plain text. There are four input
subtracted a multiplexer that controls the input for the core converted the cipher text into plain text. When give the input
for every round. So the final addition and subtraction will be obtained the reverse result of encryption.
done before sending it as the cipher data. RC6 block diagram
is shown in below Fig 4

Figure 6: Simulation of Decryption

Fig 4 RC6 block diagram Input Output(plain

VI. Result and conclusion (cipher text) text)
6.1 Result FADO 0001
Figure 5 shows the waveform for simulation of encrypted C70D 0002
data from plain text to cipher text There are four input which 6062 0003
are in plain text and that converted into cipher text .when give 9157 0004
the input the result obtained after 3000 ns. Table 2: Description of the Decrypted data

26
All Rights Reserved © 2017 IJIESM
 ISSN 2347 - 7911
International Journal for Innovations in Engineering, Science and Management
Available online at: www.ijiesm.com Volume 5, Issue 6, June 2017

6.2 Conclusion 1367 vol.2

RC6 meets the requirement given by NIST to the new AES.
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