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Array Multiplier 8x8 Verilog Code

The document describes a structural implementation of an 8x8 bit multiplier module. It includes: 1. Half adder (HA) and full adder (FA) modules to perform bitwise multiplication. 2. A multiplier_8x8_struct module that instantiates HAs and FAs in 7 lines to multiply each bit pair of inputs A and B. 3. A testbench module multiplier_8x8_struct_tb that applies random inputs A and B to the multiplier module and monitors the output.

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5K views5 pages

Array Multiplier 8x8 Verilog Code

The document describes a structural implementation of an 8x8 bit multiplier module. It includes: 1. Half adder (HA) and full adder (FA) modules to perform bitwise multiplication. 2. A multiplier_8x8_struct module that instantiates HAs and FAs in 7 lines to multiply each bit pair of inputs A and B. 3. A testbench module multiplier_8x8_struct_tb that applies random inputs A and B to the multiplier module and monitors the output.

Uploaded by

Jimmy
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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module HA(output sum, carry, input a, b);

assign sum = a^b;

assign carry = (a&b);

endmodule

module FA(output sum, carry, input a,b,cin);

assign sum =(a^b^cin);

assign carry = ((a&b)|(a&cin)|(b&cin));

endmodule

module multiplier_8x8_struct(output [15:0] out, input [7:0] A, B, input clk);

assign out[0]= (A[0]&B[0]); //p0

wire [64:0] s, c;

//line 1

HA HA11(product[1],c[0],(A[0]&B[1]),(A[1]&B[0])); //p1

FA FA11(s[1],c[1],(A[1]&B[1]),(A[2]&B[0]),c[0]);

FA FA12(s[2],c[2],(A[2]&B[1]),(A[3]&B[0]),c[1]);

FA FA13(s[3],c[3],(A[3]&B[1]),(A[4]&B[0]),c[2]);

FA FA14(s[4],c[4],(A[4]&B[1]),(A[5]&B[0]),c[3]);
FA FA15(s[5],c[5],(A[5]&B[1]),(A[6]&B[0]),c[4]);

FA FA16(s[6],c[6],(A[6]&B[1]),(A[7]&B[0]),c[5]);

HA HA12(s[7],c[7],c[6],(A[7]&B[1]));

//line 2

HA HA21(product[2],c[8],(A[0]&B[2]),s[1]); //p2

FA FA21(s[9],c[9],(A[1]&B[2]),s[2],c[8]);

FA FA22(s[10],c[10],(A[2]&B[2]),s[3],c[9]);

FA FA23(s[11],c[11],(A[3]&B[2]),s[4],c[10]);

FA FA24(s[12],c[12],(A[4]&B[2]),s[5],c[11]);

FA FA25(s[13],c[13],(A[5]&B[2]),s[6],c[12]);

FA FA26(s[14],c[14],(A[6]&B[2]),s[7],c[13]);

FA FA27(s[15],c[15],(A[7]&B[2]),c[7],c[14]);

//line 3

HA HA31(product[3],c[16],(A[0]&B[3]),s[9]); //p3

FA FA31(s[17],c[17],(A[1]&B[3]),s[10],c[16]);

FA FA32(s[18],c[18],(A[2]&B[3]),s[11],c[17]);

FA FA33(s[19],c[19],(A[3]&B[3]),s[12],c[18]);

FA FA34(s[20],c[20],(A[4]&B[3]),s[13],c[19]);

FA FA35(s[21],c[21],(A[5]&B[3]),s[14],c[20]);

FA FA36(s[22],c[22],(A[6]&B[3]),s[15],c[21]);

FA FA37(s[23],c[23],(A[7]&B[3]),c[15],c[22]);

//line 4

HA HA41(product[4],c[24],(A[0]&B[4]),s[17]); //p4

FA FA41(s[25],c[25],(A[1]&B[4]),s[18],c[24]);

FA FA42(s[26],c[26],(A[2]&B[4]),s[19],c[25]);

FA FA43(s[27],c[27],(A[3]&B[4]),s[20],c[26]);

FA FA44(s[28],c[28],(A[4]&B[4]),s[21],c[27]);
FA FA45(s[29],c[29],(A[5]&B[4]),s[22],c[28]);

FA FA46(s[30],c[30],(A[6]&B[4]),s[23],c[29]);

FA FA47(s[31],c[31],(A[7]&B[4]),c[23],c[30]);

//line 5

HA HA51(product[5],c[32],(A[0]&B[5]),s[25]); //p5

FA FA51(s[33],c[33],(A[1]&B[5]),s[26],c[32]);

FA FA52(s[34],c[34],(A[2]&B[5]),s[27],c[33]);

FA FA53(s[35],c[35],(A[3]&B[5]),s[28],c[34]);

FA FA54(s[36],c[36],(A[4]&B[5]),s[29],c[35]);

FA FA55(s[37],c[37],(A[5]&B[5]),s[30],c[36]);

FA FA56(s[38],c[38],(A[6]&B[5]),s[31],c[37]);

FA FA57(s[39],c[39],(A[7]&B[5]),c[31],c[38]);

//line 6

HA HA61(product[6],c[40],(A[0]&B[6]),s[33]); //p6

FA FA61(s[41],c[41],(A[1]&B[6]),s[34],c[40]);

FA FA62(s[42],c[42],(A[2]&B[6]),s[35],c[41]);

FA FA63(s[43],c[43],(A[3]&B[6]),s[36],c[42]);

FA FA64(s[44],c[44],(A[4]&B[6]),s[37],c[43]);

FA FA65(s[45],c[45],(A[5]&B[6]),s[38],c[44]);

FA FA66(s[46],c[46],(A[6]&B[6]),s[39],c[45]);

FA FA67(s[47],c[47],(A[7]&B[6]),c[39],c[46]);

//line 7

HA HA71(product[7],c[48],(A[0]&B[7]),s[41]); //p7

FA FA71(product[8],c[49],(A[1]&B[7]),s[42],c[48]);//p8

FA FA72(product[9],c[50],(A[2]&B[7]),s[43],c[49]);//p9

FA FA73(product[10],c[51],(A[3]&B[7]),s[44],c[50]);//p10

FA FA74(product[11],c[52],(A[4]&B[7]),s[45],c[51]);//p11
FA FA75(product[12],c[53],(A[5]&B[7]),s[46],c[52]);//p12

FA FA76(product[13],c[54],(A[6]&B[7]),s[47],c[53]);//p13

FA FA77(product[14],product[15],(A[7]&B[7]),c[47],c[54]); //p14,15

Endmodule

module multiplier_8x8_struct_tb(); //setting inputs and output

wire [15:0] out;

reg [7:0] A;

reg [7:0] B;

reg clk;

multiplier_8x8_struct dut (.A(A), .B(B), .out(out), .clk(clk)); // initialization

initial begin

A <= 0;

B <= 0;

clk <= 0;

end

always #100 clk <= ~clk;

always #25 A <= $random; // every 25ns value of input is randomized

always #25 B <= $random;

always @(A or B) // if any input changes the message appears

$monitor ("At time %4d, A is %d, B is %d and output is %d", $time, A, B, out); //
message for extra info
endmodule

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