Accepted Manuscript

A FPGA based Implementation of Sobel Edge Detection

Nazma Nausheen, Ayan Seal, Pritee Khanna, Santanu Haldar

PII: S0141-9331(16)30228-9
DOI: 10.1016/j.micpro.2017.10.011
Reference: MICPRO 2629

To appear in: Microprocessors and Microsystems

Received date: 26 September 2016

Accepted date: 26 October 2017

Please cite this article as: Nazma Nausheen, Ayan Seal, Pritee Khanna, Santanu Haldar, A FPGA
based Implementation of Sobel Edge Detection, Microprocessors and Microsystems (2017), doi:
10.1016/j.micpro.2017.10.011

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 ACCEPTED MANUSCRIPT

Highlights

– A FPGA based architecture for Sobel Edge Detection algorithm is pro-

posed.
– An 8-bit architecture is proposed to retrieve the addresses of pixels involved
in convolution process.
– The proposed architectures reduce the time and space complexity compare
to two existing architectures.

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Noname manuscript No.
(will be inserted by the editor)

A FPGA based Implementation of Sobel Edge

Detection

Nazma Nausheen · Ayan Seal · Pritee

Khanna · Santanu Haldar

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the date of receipt and acceptance should be inserted later

Abstract This paper presents an architecture for Sobel edge detection on

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Field Programmable Gate Array (FPGA) board, which is inexpensive in terms
of computation. Hardware implementation of the Sobel edge detection algo-
rithm is chosen because hardware presents a good scope of parallelism over
software. On the other hand, Sobel edge detection can work with less dete-

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rioration in high level of noise. A compact study is also been done based on
the previous methods. The proposed architecture uses less number of logic
gates with respect to previous method. Space complexity is also reduced using
proposed architecture.
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Keywords FPGA · Edge detection · Sobel operator · Hardware architecture
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1 Introduction

Edges are basically the noticeable variation of intensities in an image. Edges

help to identify the location of an object and the boundary of a particular
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entity in the image. It also helps in feature extraction and pattern recognition.
Hence, edge detection is of great importance in computer vision. So far, most
of the researchers have chosen software for implementation of basic edge de-
tection algorithms and their variations [2]. But, it has been established that it
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is not an efficient approach for real time applications. Implementation of edge

detection algorithms on hardware platform is more efficient for real time appli-
cations. With the advancement of VLSI technology, hardware implementation
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Nazma Nausheen · Ayan Seal · Pritee Khanna

Computer Science and Engineering
PDPM Indian Institute of Information Technology, Design and Manufacturing Jabalpur
Madhya Pradesh, India, Pin-482005 E-mail: [email protected]
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Santanu Haldar
Department of Computer Application Kalyani Government Engineering College
Kalyani, Nadia, West Bengal-742101, India
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A FPGA based Implementation of Sobel Edge Detection 3

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Fig. 1 Architecture of FPGA board adopted from [4]

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presents a scope to parallelize subroutines in a program. Hence, hardware im-
plementation provides much faster alternative as compared to software. In

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1994 Boo et al. [3] have proposed hardware implementation of edge detection
using Sobel operator using VLSI technology within application specific inte-
grated circuit (IC). In the past few years extensive work has been done in
the area of Field programmable Gate Array (FPGA) based implementation
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of edge detection algorithm which in turn implements image processing in
real time. In 2009 real time algorithms have been designed to detect edges on
FPGA board [12]. Parallelism of any algorithm is possible due to integration
of large number of transistors (10k-100k) on a single silicon chip using VLSI
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technology [10]. All embedded systems are designed and implemented on Ap-
plication Specific Integrated Circuit (ASIC) or FPGA. FPGA is an IC with
Configurable Logical Blocks (CLBs) [5]. CLBs are interconnected using rout-
ing channels on a silicon board based on the desired operation. The internal
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connections can be configured using Hardware Description Languages (HDL)

like VHDL [9] or Verilog. The silicon board consists of input/output ports on
the boundary to take the input and provide the output as shown in figure
1. These HDLs provide a medium of simulation of the designed IC to see if
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anything can go wrong. These programmed ICs are emulated on FPGA board
after correct simulation. In 2007, T.A.Abbasi et al. [1] presented an architec-
ture for Sobel edge detection on FPGA. Later in 2012, this architecture was
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found to be inefficient with respect to space and time complexity by S.Halder

et al. [8]. Architecture proposed by them saved time and took lesser space than
the architecture proposed by T.A.Abbasi et al. [1]. However, this architecture
also had disadvantages of redundant storage of pixels and also there is scope of
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reduction in the architecture. The motivation of proposed work is to overcome

these shortcomings of architecture proposed in [8]. The contributions of the
present work are as follows:
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4 Nazma Nausheen et al.

• An 8-bit architecture has been proposed to retrieve the addresses of pixels

involved in convolution process for reducing the space complexity in the
convolution process.
• A modified architecture by replacing some components in the architecture
proposed by [8] for reducing the time complexity of Sobel edge detection
algorithm.
The organization of the paper is as follows. Section II gives a brief introduction
of Sobel edge detection algorithm. Section III presents a modified version of the
traditional Sobel edge detection algorithm. Section IV depicts the methodology
followed in this work. Experimental results and discussion are presented in
Section V. Finally, Section VI concludes this work.

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2 Sobel Edge Detection Algorithm

Sobel Edge detection algorithm is a gradient based edge detection method [6]-

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[7], which finds edges using horizontal mask (HM) and vertical mask (VM) [11].
One mask is simply transpose of the other as follows:
   
−1 −2 −1 −1 0 1
V M =  0 0 0  , HM = −2 0 2
1 2 1
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−1 0 1
For the convolution process, an image is scanned from left to right and top to
bottom of an image using HM and VM separately. Convolution is the process
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multiplying each intensity value of an image with its local neighbors, weighted
by the mask. Let [P ]3×3 be a sub-window of an image, as in figure 2, to be
convolved with HM and VM separately.
The horizontal gradient Gx and the vertical gradient Gy of the center pixel
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(P4 ) of sub-window are given by equations 1 and 2 respectively.

Gx = f1 − f2 (1)
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where f1 = (P6 + 2 × P7 + P8 ), f2 = (P0 + 2 × P1 + P2 )

Gy = f3 − f4 (2)
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Fig. 2 A 3 × 3 subwindow of an image

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A FPGA based Implementation of Sobel Edge Detection 5

where f3 = (P2 + 2 × P5 + P8 ), f4 = (P0 + 2 × P3 + P6 )

The resultant gradient of the center pixel of the sub-window is given by equa-
tion 3.

G = |Gx | + |Gy | (3)

The gradient of P4 is further used to determine whether it is an edge pixel

or not by comparing it with the predefined threshold value. If the gradient of
P4 is greater than threshold value, then P4 is considered to be an edge pixel
(denoted as 1). Otherwise, P4 is treated as non-edge pixel (denoted as 0). This
is shown in equation 4.
(

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1, if G > T
Dop = (4)
0, otherwise

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3 Simplification of the Traditional Sobel Edge Detection Algorithm

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A few adjustments are required in traditional Sobel edge detection algorithm
because 8-bit architecture has been adopted here for hardware implementation.
In [8], S. Halder et al. simplified the traditional algorithm. Some changes have

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been done in the simplified version of algorithm proposed by S.Halder et al. [8].
In equation 1, the values of f1 and f2 will be maximum when each of the
contributing pixels of sub-window will have maximum intensity values, i.e.,
255. The same happens with f3 and f4 in equation 2. So, the maximum possible
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value of f1 , f2 , f3 and f4 is 4 × 255, thus it will require 10-bit architecture for
implementation.To resolve this issue, values of f1 , f2 , f3 and f4 are limited to
one fourth of the original values. Hence, each of the contributing pixels has
to be divided by 4 before finding out values of f1 , f2 , f3 and f4 , as shown in
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equations 5 to 8.
1 1 1
f1 = P6 + P7 + P8 (5)
4 2 4
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1 1 1
f2 = P0 + P1 + P2 (6)
4 2 4
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1 1 1
f3 = P2 + P5 + P8 (7)
4 2 4
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1 1 1
f4 = P0 + P3 + P6 (8)
4 2 4
For the same reasons, Gx and Gy has to be divided by 2 and the new equation
for G is given as:
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1 1
G= |Gx | − |Gy | (9)
2 2
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6 Nazma Nausheen et al.

Now, equations 1, 2 and 3 can be rewritten as:

Gx = f1 − f2 (10)

where f1 = ( 81 P6 + 14 P7 + 18 P8 ), f2 = ( 81 P0 + 14 P1 + 18 P2 )

Gy = f3 − f4 (11)

where f3 = ( 18 P2 + 14 P5 + 18 P8 ), f4 = ( 81 P0 + 14 P3 + 18 P6 )
The following four cases have to be considered because the absolute value of
Gx and Gy are calculated in equation 3.
Case 1: If both Gx and Gy are positive.

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G1 = (f1 − f2 ) + (f3 − f4 )

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1 1 1 1 1 1 1 1 1
= P6 + P7 + P8 − P0 − P1 − P2 + P2 + P 5 + P8
8 4 8 8 4 8 8 4 8

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1 1 1
− P0 − P3 − P6 (12)
8 4 8
1 1 1 1 1 1
= ( P5 + P7 + P8 ) − ( P0 + P1 + P3 )
4 4 4 4 4 4
= f5 − f6
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where f5 = ( 41 P5 + 14 P7 + 14 P8 ) and f6 = ( 14 P0 + 41 P1 + 14 P3 )
Case 2: If Gx is positive and Gy is negative.
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G2 = (f1 − f2 ) + (f4 − f3 )
1 1 1 1 1
= P6 + P7 + P8 − P0 − P 1
8 4 8 8 4
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1 1 1 1 1 1 1
− P2 + P 0 + P3 + P6 − P2 − P5 − P8 (13)
8 8 4 8 8 4 8
1 1 1 1 1 1
= ( P3 + P 6 + P7 ) − ( P1 + P2 + P5 )
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4 4 4 4 4 4
= f7 − f8

where: f7 = ( 41 P3 + 14 P6 + 14 P7 ) and f8 = ( 14 P1 + 41 P2 + 14 P5 )
Case 3: If Gx is negative and Gy is positive.
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G3 = (f2 − f1 ) + (f3 − f4 )
1 1 1 1 1
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= P0 + P 1 + P2 − P6 − P 7
8 4 8 8 4
1 1 1 1 1 1 1
− P8 + P 2 + P5 + P8 − P0 − P3 − P8 (14)
8 8 4 8 8 4 8
1 1 1 1 1 1
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= ( P1 + P2 + P 5 ) − ( P3 + P6 + P7 )
4 4 4 4 4 4
= f8 − f7
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A FPGA based Implementation of Sobel Edge Detection 7

Case 4: If Gx and Gy are both negative.

G4 = (f2 − f1 ) + (f4 − f3 )
1 1 1 1 1
= P0 + P1 + P2 − P6 − P 1
8 4 8 8 4
1 1 1 1 1 1 1
− P8 + P0 + P 3 + P6 − P2 − P5 − P8 (15)
8 8 4 8 8 4 8
1 1 1 1 1 1
= ( P0 + P 1 + P3 ) − ( P5 + P7 + P8 )
4 4 4 4 4 4
= f6 − f5

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At a particular instant of time, one out of four cases will be true and rest of the
cases will be false. Suppose, if case 1 is true then f1 and f3 are greater than or

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equal to f2 and f4 , respectively. Hence, in that case G1 is greatest among all,
which is considered as resultant gradient, G, of the center pixel (P4 ) of sub-
window. These four cases are exclusive of each other. In turn, it is observed

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that the value of G will be the maximum of four possible values,which can be
represented by equation 16.

G = max(G1 , G2 , G3 , G4 )

= max(f9 , f10 ) US
= max(|f5 − f6 |, |f7 − f8 |) (16)
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where f9 = |f5 − f6 | and f10 = |f7 − f8 |. Finally, equation 4 is replaced by
equation 17 for deciding whether the center pixel, P4 , is an edge pixel or not.
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0, if f9 < T and f10 < T
Do p = (17)
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1, otherwise

4 Methodology
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Let image I is stored as a rectangular array of elements, ‘A’ with m rows

and n columns. As memory of the computer is simply a sequence of addressed
locations, the programming language stores this two-dimensional array, ‘A’, in
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memory by a block of m × n sequential memory locations either row by row

in row-major order or column by column in column-major order. The order of
elements and their adresses change with the above specified techniques. This
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can further be illustrated with an example.

Consider an image represented as array ‘A’ shown in figure 3. The computer
does not keep track the address of every element of a linear array. Rather, it
keeps track the address of the first element A(0,0), which is known as base
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address, B and computes the address of a particular element, A(i,j), as:

Rowmajor : loc(A(i, j)) = B + n × i + j (18)

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8 Nazma Nausheen et al.

Fig. 3 An image I stored as two-dimensional array, ‘A’, with m rows and n columns

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Fig. 4 Row major and Column major order storage of ’A’(from left to right)
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or the equation

Columnmajor : loc(A(i, j)) = B + i + m × j (19)

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Figure 4 shows the ways a two dimensional array, [A]m×n , are represented in
memory by equation 18 and 19.
Figure 5 demonstrates the convolution process. It is clear from the figure that
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a predefined mask of size 3 × 3 has to be moved from top-left to bottom-right

corner of an image. In each iteration, the specified mask has to be moved one
position right and one position down when columns exhaust in a particular
row. So, 9 pixels are involved in each iteration during convolution. Authors
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in [8], considered 9 pixels of a 3 × 3 sub-window as one group of an image and

stored them using equation 18 for each iteration. It means that one group of 9
pixels is stored in a column for the first iteration. Again one group of 9 pixels
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is stored at the end of the above column in the second iteration. This process
has to be continued till bottom-right corner of an image. Figure 6 shows the
way how a 3 × 3 sub-window of an image can be stored in a linear array using
equation 18.
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If the above mentioned strategy is used to store the pixel information of an

image, then no algorithm is required to extract the 9 pixels for each iteration
during convolution. It only extracts the 9 pixels group-wise sequentially for
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A FPGA based Implementation of Sobel Edge Detection 9

Fig. 5 Scanning of an image using mask

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Fig. 6 Group-wise storage of pixels for convolution
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each iteration. This strategy is expensive in terms of space because information
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of a particular pixel is repeated. As seen in figure 6 there are multiple storage
of same pixels, for e.g., pixel at location (0,1) with value 5 has appeared twice.
On the other hand, row-major/column-major order takes less space to store
the pixel information of an image in a linear array. At most m × n entries
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will be there in this linear array if a two-dimensional array has m rows and
n columns. But, it requires an efficient FPGA based hardware architecture to
extract 9 pixels in each iteration during convolution process. After fetching, 9
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pixels are convolved with mask.

The whole work is divided into two parts, of which the first part deals with the
extraction of indices of the pixels of the sub-window from the image, which
are convolved with mask and the second part deals with the simplification of
the circuitry used for detecting the edges.
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4.1 Architecture for extraction of indices of sub-window pixels

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Figure 7 shows a 3 × 3 random sub-window with relative indices, which will be

convolved with Sobel mask in each iteration during convolution. Algorithm 1
is used to extract the indices of the 9 pixels, which helps to fetch the intensity
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values of the extracted locations by A(lt ) where, t varies from 0 to 8. Then

these intensity values are convolved with predefined masks for finding out gra-
dient.
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Fig. 7 A random 3 × 3 sub-window with relative indices

Algorithm 1 Extraction of Indices

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1: procedure iExtract()

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2: //Variable ‘i’ represents row number whereas j represents column number
3: //Variable ‘B’ is the base address of the array
4: //Variable ‘n’ is the total number of the column of an image
5:

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6: for i = 1 to n − 2 do
7: Set k = B + i ∗ n
8: for j = 1 to n − 2 do
9: l0 = k − n + j − 1
10: l1 = k − n + j
11:
12:
13:
14:
15:
l2 = k − n + (j + 1)
l3 = k + (j − 1)
l4 = k + j
l5 = k + (j + 1)
l6 = k + n + (j − 1)
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16: l7 = k + n + j
17: l8 = k + n + (j + 1)
18: end for
19: end for
20: end procedure
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It is clear from the algorithm that there are three operations namely, sub-
traction, addition and multiplication, involved for finding out indices, to fetch
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the intensity values for the convolution process. A FPGA based hardware
architecture is proposed based on the mathematical operations involved in al-
gorithm 1. Figure 8 shows the hardware circuit for finding out the indices.
Adder/subtractor composite block is sufficient for the above specified opera-
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tions.
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4.2 Modified architecture for Sobel Algorithm

The extracted intensity values Pt = A(lt ) are fed into the next level of FPGA
based architecture as inputs for the convolution process. It is clear from section
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3 that subtraction, addition, division, absolute value and comparison need to

be performed for detecting the edge pixel of an image. For subtraction and
addition 8-bit adder-subtractor composite block is used. It has also been ob-
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A FPGA based Implementation of Sobel Edge Detection 11

Fig. 8 A FPGA based architecture for extraction of indices

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Fig. 9 Architecture for finding absolute values

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served that each intensity value for the convolution process has to be divided
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by 4. Normally, divider is used for division operation. But, right shift oper-
ator is used here twice to divided each intensity value by 4 because divider
takes more time compare to right shift operator. A 2:1 multiplexer is used for
finding absolute values of |f5 − f6 | and |f7 − f8 | as shown in equation 16 . To
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find the absolute value the subtraction is done in two ways viz. by subtracting
subtrahend from minuend and by swapping the positions of subtrahend and
minuend as in figure 9. The carry bit of the subtractor block when turns out
to be concludes the result as negative. This carry bit is used as the select line
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of the multiplexer. If carry bit is 1, then f9 = f5 − f6 , otherwise f9 = f6 − f5 .

Same circuitry is used to find value of f10 .
After finding the absolute values, the values of f9 and f10 are compared with
predefined threshold (T) as shown in equation 17 for deciding whether a pixel
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of an image is an edge pixel or not. Generally, a comparator is used to com-

pare two values but, complexity of a comparator is more. So, instead of a
comparator, two subtractors and a NAND gate are used for the comparison
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which reduces the complexity. The carry bits of both the subtractors as shown
in figure 10 are fed into a NAND gate to take the decision for edge pixel. The
truth table of NAND gate suggest that when both the inputs are 1 then only
output is 0 otherwise 1. In other words, when f9 and f10 are less than the
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predefined threshold, there will be absence of edge pixel otherwise the corre-
sponding pixel is considered to be an edge pixel.
The final architecture is represented in figure 11, which takes input directly
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12 Nazma Nausheen et al.

Fig. 10 Architecture for comparison with Threshold

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from the addressing circuit and computes the edge pixel by comparing gradi-

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ent with the threshold. Different components for the convolution process are
depicted above. Figure 11 shows the complete FPGA based architecture for
Sobel edge detection algorithm.

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A FPGA based Implementation of Sobel Edge Detection 13

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Fig. 11 Proposed circuit for hardware implementation of Sobel edge detection algorithm
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5 Experimental Results and Discussion

The proposed architectures are implemented using VHDL. The program is sim-
ulated followed by synthesis on Xilinx Sparta 6 XC6SLX43TQG144 FPGA
board. The simulation is done on grayscale images of various sizes using a
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predefined threshold. Figure 12 shows 8-bit grayscale input images and their
corresponding edge images by hardware and software implementations respec-
tively. In both the cases, same threshold of intensity value 27 has been chosen.
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Table 1 shows the comparitive study of device utilisation summary in case

of both the architecture when synthesized on Sparta 6 XC6SLX43TQG144
board. The design is capable of operating at a frequency of 504.007 MHz. The
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comparisons with existing design have been made in table 2 to show the time
of execution of architectures.
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14 Nazma Nausheen et al.

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Fig. 12 Row 1: Grayscale images; Row 2: Edges by hardware implementation on FPGA;
Row 3: Edge by software implementation on MATLAB.
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Table 1 Device Utilisation Summary
Total Santanu et.al Method [8] Proposed Method
No.of slice registers 4800 49 0
No. of slice LUTs 2400 135 114
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No. of fully used LUT-FF 38 0

No. of unique control sets 1 0
No. of Bonded IOBs 102 58 57
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Table 2 Timing Summary

Maximum Minimum Time to process Time to process
Frequency Period 128 × 128 image 512 × 512 image
Halder et. al [8] 236.572 MHz 4.227 ns 0.07 ms 1.10 ms
Proposed Method 504.007 MHz 1.984 ns 0.032 ms 0.52 ms
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6 Conclusions
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The proposed architecture of Sobel edge detection uses direct indexing of de-
sired pixels unlike the redundant storage of sub-window pixels as in the previ-
ous architectures thus reducing space complexity. The circuit is able to perform
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at a faster frequency than existing designs. Hence, the time to process an im-
age is less comparatively. When this architecture is used for large databases it
will show a significant difference. The time complexity of the proposed algo-
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A FPGA based Implementation of Sobel Edge Detection 15

rithm is less than previously existing algorithm for hardware implementation

of Sobel edge detection. Also, in main architecture, certain significant changes
have been made which improve the resource utilization and make efficient use
of FPGA board. It opens up the possibility of implementation of some parallel
architecture on the same board.

Acknowledgments Ayan Seal is thankful to Deity, Government of India

for providing him Young Faculty Research Fellowship under Visvesvaraya PhD
Scheme for Electronics and IT.

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