Computer Architecture and Organization Assignment II

Computer architecture and organization assignment II
1. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the
remainder the immediate operand or an operand address.
A. What is the maximum directly addressable memory capacity (in bytes)?
B. Discuss the impact on the system speed if the microprocessor bus has
a. a 32-bit local address bus and a 16-bit local data bus, or
b. a 16-bit local address bus and a 16-bit local data bus.
C. How many bits are needed for the program counter and the instruction register?
2. Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers
are 16 bits wide) and having a 16-bit data bus.
A. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?
B. What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?
C. What architectural features will allow this microprocessor to access a separate “I/O space”?
D. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support?
How many 16-bit I/Oports? Explain.
3. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a
bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this
microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the
external clock frequency supplied to the microprocessor? State any other assumptions you make, and explain. Hint: Determine the number
of bytes that can be transferred per bus cycle.
4. Consider a computer system that contains an I/O module controlling a simple keyboard/ printer teletype. The following registers are
contained in the processor and connected directly to the system bus:
INPR: Input Register, 8 bits
OUTR: Output Register, 8 bits
FGI: Input Flag, 1 bit
FGO: Output Flag, 1 bit
IEN: Interrupt Enable, 1 bit
Keystroke input from the teletype and printer output to the teletype are controlled by the I/O module. The teletype is able to encode an
alphanumeric symbol to an 8-bit word and decode an 8-bit word into an alphanumeric symbol.
A. Describe how the processor, using the first four registers listed in this problem, can achieve I/O with the teletype.
B. Describe how the function can be performed more efficiently by also employing IEN.
5. A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five
stages: fetch opcode (four bus clock cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to operand (three
cycles), and store operand (three cycles).
A. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory
read and memory write operation?
B. Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles
6. The Intel 8086 is a 16-bit processor similar in many ways to the 8-bit 8088. The 8086 uses a 16-bit bus that can transfer 2 bytes at a time,
provided that the lower-order byte has an even address. However, the 8086 allows both even- and odd-aligned word operands. If an odd-
aligned word is referenced, two memory cycles, each consisting of four bus cycles, are required to transfer the word. Consider an
instruction on the 8086 that involves two 16-bit operands. How long does it take to fetch the operands? Give the range of possible answers.
Assume a clocking rate of 4 MHz and no wait states.
7. Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16- bit microprocessor. Assume that, on average, 20%
of the operands and instructions are 32 bits long, 40% are 16 bits long, and 40% are only 8 bits long. Calculate the improvement achieved
when fetching instructions and operands with the 32-bit microprocessor.
8. Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of
four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a
cache hit/miss.Where in the cache is the word from memory location ABCDE8F8 mapped?
9. Given the following specifications for an external cache memory: four-way set associative;line size of two 16-bit words; able to
accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Design the cache
structure with all pertinent information and show how it interprets the processor’s addresses.
10. Consider a machine with a byte addressable main memory of 2 16 bytes and block size of 8 bytes. Assume that a direct mapped cache
consisting of 32 lines is used with this machine.
A. How is a 16-bit memory address divided into tag, line number, and byte number?
B. Into what line would bytes with each of the following addresses be stored?
a. 0001 0001 0001 1011
b. 1100 0011 0011 0100
c. 1101 0000 0001 1101
d. 1010 1010 1010 1010
C. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along
with it?
D. How many total bytes of memory can be stored in the cache?
E. Why is the tag also stored in the cache?
11. Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size.
A.Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following
parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag.
B. Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number
of blocks in main memory, number of lines in cache, size of tag.
C. Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following
parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number
of lines in cache, size of tag.
12. Consider a memory system with the following parameters:
A. What is the cost of 1 Mbyte of main memory?

B. What is the cost of 1 Mbyte of main memory using cache memory technology?
C. If the effective access time is 10% greater than the cache access time, what is the hit ratio H?
13. The performance of a single-level cache system for a read operation can be characterized by the following equation: where Ta is the
average access time, Tc is the cache access time, Tm is the memory access time (memory to processor register), and H is the hit ratio. For
simplicity, we assume that the word in question is loaded into the cache in parallel with the load to processor register.
A. Define Tb = time to transfer a line between cache and main memory, and W fraction of write references. Revise the preceding
equation to account for writes as well as reads, using a write-through policy.
B. Define Wb as the probability that a line in the cache has been altered. Provide an equation for Ta for the write-back policy.
14. What are two senses in which the term random-access memory is used?
15. What is the difference between DRAM and SRAM in terms of application?
16. What is the difference between DRAM and SRAM in terms of characteristics such as speed, size, and cost?
17. Explain why one type of RAM is considered to be analog and the other digital.
18. What are some applications for ROM?
19. What are the differences among EPROM, EEPROM, and flash memory?
20. What are the major functions of an I/O module?
21. List and briefly define three techniques for performing I/O.
22. What is the difference between memory-mapped I/O and isolated I/O?
23. When a device interrupt occurs, how does the processor determine which device issued the interrupt?
24. On a typical microprocessor, a distinct I/O address is used to refer to the I/O data registers and a distinct address for the control and status
registers in an I/O controller for a given device. Such registers are referred to as ports. In the Intel 8088, two I/O instruction formats are
used. In one format, the 8-bit opcode specifies an I/O operation; this is followed by an 8-bit port address. Other I/O opcodes imply that the
port address is in the 16-bit DX register. How many ports can the 8088 address in each I/O addressing mode?
25. Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis.
A. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt service routine (ISR), execute it, and return
to the main program). Determine what fraction of processor time is consumed by this I/O device if it interrupts for every byte.
B. Now assume that the device has two 16-byte buffers and interrupts the processor when one of the buffers is full. Naturally, interrupt
processing takes longer, because the ISR must transfer 16 bytes. While executing the ISR, the processor takes about 8 s for the transfer
of each byte. Determine what fraction of processor time is consumed by this I/O device in this case.
C. Now assume that the processor is equipped with a block transfer I/O instruction such as that found on the Z8000.This permits the
associated ISR to transfer each byte of a block in only 2 s. Determine what fraction of processor time is consumed by this I/O device
in this case.

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Computer architecture and organization assignment II

A. What is the cost of 1 Mbyte of main memory?

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