Module Alarm
Module Alarm
input Clk;
input reset;
input h[4:0],m[5:0];
input IN,AL,ST;
begin
if(reset == 1'b1)
seconds = 0;
minutes = 0;
hours = 0;
end
if (IN) begin
hours<=H;
minutes<=M;
seconds = seconds + 1;
if(seconds == 60)
seconds = 0;
minutes = minutes + 1;
if(minutes == 60)
minutes = 0;
hours = hours + 1;
if(hours == 24)
hours = 0;
end
else
seconds = seconds + 1;
if(seconds == 60)
seconds = 0;
minutes = minutes + 1;
if(minutes == 60)
minutes = 0;
hours = hours + 1;
if(hours == 24)
hours = 0;
end
end
//Alarm function
always @(posedge(clk) or posedge(reset))
begin
if(reset)
AL<=0;
else
begin
if({h,m}=={H,M})
begin
if(AL)
ALARM<= 1;
end
if(ST)
Alarm <=0;
end
end
endmodule
Testbench
module alarm_clock_tb( );
reg Clk;
reg reset;
reg M[5:0],H[4:0];
reg h[4:0],m[5:0];
reg IN,AL,ST;
wire ALARM;
alarm_clock uut(Clk,reset,M,H,h,m,IN,AL,ST,seconds,minutes,hours,ALARM);
// clock 10Hz
initial
begin
Clk = 0;
end
initial
begin
reset=1;
H=14;
M=45;
#1000
reset=0;
IN=0;
H=4;
M=25;
#1000
IN=1;
H=5;
M=15;
IN=0;
#1000
IN=1;
H=3;
M=0;
h=3;
m=0;
AL=0;
#1000
AL=1;
#1000
ST=1;
end
endmodule