Chapter 3 Memory and Basic IO Interface
Chapter 3 Memory and Basic IO Interface
Memory interface
I/O interface
Peripheral I/O
Interfacing output devices
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WHAT IS AN INTERFACE
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INTERFACING EXAMPLE BLOCK DIAGRAM
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MEMORY INTERFACE
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8085 INTERFACING PINS
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MEMORY INTERFACE
Memory pin
Vcc
D7-D0
A10-0
RAM
/CS
/RD
/WR
Gnd 7
MEMORY INTERFACE
Memory requirement
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MEMORY INTERFACE
Accessing Memory
For the microprocessor to access (Read or Write)
information in memory (RAM or ROM), it needs to do
the following:
Select the right memory chip (using part of the address bus).
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MEMORY INTERFACE
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MEMORY INTERFACE EXAMPLE
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MEMORY INTERFACE EXAMPLE
Understand the pin for the memory
Data pins: D0-D7 connected to the memory
chip.
Address pins: a memory of size 2kB x 8
will have 211 different memory locations.
11 address lines A0 to A10.
/CS pin: chip select
/OE pin: active-low enable output pin
/WR pin: active-low data written on the
memory 16
MEMORY INTERFACE EXAMPLE
memory chip).
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MEMORY INTERFACE EXAMPLE
Address bus Interfacing
We have a 2kB RAM with 11 address lines.
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MEMORY INTERFACE EXAMPLE
Connecting Control Signals
OE (Output Enable) and WR (Memory Write)
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COMPLETE INTERFACE
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EXERCISE
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CONTENTS
Memory interface
I/O interface
Peripheral I/O
Interfacing output devices
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INTERFACING INPUT OUTPUT DEVICES
I/O device
Are communicating channel for
microprocessor to outside world
Keyboards and display units
Mode of interfacing
Parallel I/O: Eight bit data transferred at a time
Transfer data
Instructions
IN and OUT 26
PERIPHERAL I/O INSTRUCTIONS
Instruction
IN / OUT
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PERIPHERAL I/O- INTERFACING LED OUTPUT
Peripheral I/O interface for LED output
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PERIPHERAL I/O- INTERFACING LED OUTPUT
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CONTENTS
Memory interface
I/O interface
Peripheral I/O
Interfacing output devices
32
MEMORY MAPPED I/O
I/O devices are addressed with address from
memory
Data transfer
LDA, STA
Control signal
/MEMR and /MEMW
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MEMORY MAPPED I/O
device
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MEMORY MAPPED I/O
Memory–mapped vs. peripheral I/O
Characteristic Memory-mapped I/O Peripheral I/O
Data transfer Between any reg. and I/O Between I/O and A
Machine cycle
Time required to complete one operation
T-state
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Subdivision of operation performed in one clock period
MEMORY INTERFACE
Consider MVI A, 32H
Consists of 2 byte (Instruction MVI A and Data 32H)
It needs two machine cycle(Opcode Fetch and memory
read)
Needs Seven T-State ( 4 fetch and 3 memory read)
Clock frequency f=2MHz
T-state = clock period(1/f)= 0.5µs
Execution time for Op-code Fetch: (4T)*0.5=2µs
Execution time for memory read: (3T)*0.5=1.5µs
Execution time for Instruction: (7T)*0.5=3.5µs 37
MEMORY INTERFACE
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CONTENTS
Memory interface
I/O interface
Peripheral I/O
Interfacing output devices
39