CHAPTER 1

INTRODUCTION TO MICROPROCESSORS

MICROPROCESSORS
• A Microprocessor is a multipurpose, Programmable clock-driven, register based
electronic device that read binary instruction from a storage device called memory,
accepts binary data as input and processes data according to those instructions and
provides results as outputs.
• A Microprocessor is a clock driven semiconductor device consisting of electronic
circuits manufactured by using either a LSI or VLSI technique.
• A typical programmable machine can be represented with three components : MPU,
Memory and I/O as shown in Figure

Memory

Microprocessor

I/O

Figure: A Programmable Machine

• These three components work together or interact with each other to perform a given
task; thus they comprise a system
• The machine (system) represented in above figure can be programmed to turn traffic
lights on and off, compute mathematical functions, or keep trace of guidance system.
• This system may be simple or sophisticated, depending on its applications.
• The MPU applications are classified primarily in two categories : reprogrammable
systems and embedded systems
• In reprogrammable systems, such as Microcomputers, the MPU is used for computing
and data processing.
• In embedded systems, the microprocessor is a part of a final product and is not
available for reprogramming to end user.

MICROCOMPUTER

• As the name implies, Microcomputers are small computers

• They range from small controllers that work directly with 4-bit words to larger units
that work directly with 32-bit words

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 • Some of the more powerful Microcomputers have all or most of the features of earlier
minicomputers.
• Examples of Microcomputers are Intel 8051 controller-a single board computer, IBM
PC and Apple Macintosh computer.

MICRO CONTROLLER

• Single-chip Microcomputers are also known as Microcontrollers.

• They are used primarily to perform dedicated functions.
• They are used primarily to perform dedicated functions or as slaves in distributed
processing.
• Generally they include all the essential elements of a computer on a single chip:
MPU, R/W memory, ROM and I/O lines.
• Typical examples of the single-chip microcomputers are the Intel 8051, AT89C51,
AT89C52 and Zilog Z8.
• Most of the micro controllers have an 8-bit word size, at least 64 bytes of R/W
memory, and 1K byte of ROM
• I/O lines varies from 16 to 40

APPLICATIONS OF MICROPROCESSOR
• Microcomputers
• Industrial Control
• Robotics
• Traffic Lights
• Washing Machines
• Microwave Oven
• Security Systems
• On Board Systems

Difference between Microprocessors and Microcontrollers

Although both microprocessor and microcontrollers have been designed for real time
applications and they share many common features, they have significant differences
which are as follows:

Microprocessor Microcontroller

1. Microprocessor is a silicon chip 1. Microcontroller is a silicon chip

which includes ALU, register circuit which includes microprocessor,
and control circuits. memory and I/O in a single package.
2. The general block diagram to show 2. The general block diagram of
microprocessor is as shown below: microcontroller is as shown below:

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 MPU
MPU

ALU CU Memory I/O

Input Output

Register Peripheral Devices

Array • A/D Converter
• Timer
• Serial I/O

Memory

3. Normally used for general 3. Normally microcontrollers are used

purpose computers as CPU. for specific purposes (embedded
system) e.g. traffic light controller,
4. The performance speed, i.e. clock printer, etc.
speed of microprocessor is higher 4. The performance speed of
ranging frequency from MHz to GHz. microcontroller is relatively slower
than that of microprocessors, with
5. Addition of external RAM, ROM and clock speed from 3-33 MHz.
I/O ports makes these systems 5. Has fixed memory and all peripherals
bulkier and much more expensive. are embedded together on a single
chip, so are not bulkier and are
6. Microprocessors are more versatile cheaper than microprocessors.
than microcontrollers as the designers 6. As microcontrollers have already
can decide on the amount of RAM, fixed amount of RAM, ROM and I/O
ROM and I/O ports needed to fit the ports, so are not versatile as the user
task at hand. E.gs. Intel 8085, 8086, cannot change the amount of memory
Motorola 68000, Intel Core i7, etc. and I/O ports. E.gs. AT89C51,
ATmega32, AT89S52, etc.

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 Evolution of Intel Microprocessors
4 bit Microprocessors
4004
Introduced in 1971
First microprocessor by Intel
It was a 4-bit microprocessor
Its clock speed was 740 KHz
It had 2,300 transistors
It could execute around 60,000 instructions per seconds
Used in calculators

4040
Introduced in 1974
4-bit microprocessor
3,000 transistors were used
Clock speed was 740 KHz
Interrupt features were available

8 Bit Microprocessors
8008
Introduced in 1972 it was first 8 bit microprocessor
Its clock speed was 500 KHz
Could execute 50,000 instruction per second
Used in: Computer terminals, Calculator, Bottling Machines, industrial Robots
8080
Introduced in 1974
It was also 8-bit microprocessor
Its clock speed was 2 MHz
It has 6,000 transistors
10 times faster than 8008
Could execute 500,000 instructions per second
Used In: Calculators, Industrial Robots
8085
Introduced in 1976
It was also 8-bit microprocessor
Its clock speed was 3 MHz
Its data bus is 8 bit and address bus is 16 bit
It has 6,500 transistors
It could execute 769,230 instructions per second
It could access 64KB of memory
It has 246 instructions
Used In: early PC, On-Board Instrument Data Processors

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16 Bit Microprocessors
8086
Introduced in 1978
First 16-bit microprocessor
Clock speed is 5 to 10 MHz
Data bus is 16-bit and address bus is 20-bit
It had 29,000 transistors
It could execute 2.5 million instructions per second
Could access 1MB of memory
It had 22,000 instructions
Used In: CPU of Microcomputers

8088
Introduced in 1979
It was also 16-bit microprocessor
It was creates as cheaper version of Intel’s 8086
16-bit processor with an 8-bit data bus
Could execute 2.5 million instructions per second
The chip become the most popular in the computer industry when IBM used it for its first PC
80286
Introduced in 1982
It was 16-bit microprocessor
Its clock speed was 8 MHz
Data bus is 16-bit and address bus is 24-bit
Could address 16 MB of memory
It has 134,000 transistors
Could execute 4-million instructions per second

32 Bit Microprocessors
80386
Introduced in 1986
First 32-bit microprocessor
Data bus is 32 bit and address bus is 32-bit
It could address 4GB of memory
It has 275,000 transistors
Clock speed varied from 16 MHz to 33 MHz depending upon different versions
Different Versions
80386DX
80386SX
80386SL
80486
Introduced in 1989
32-bit microprocessor
Had 1.2 million transistors
Clock speed varied from 16 MHz to 100 MHz depending upon the various versions
It had five different versions
80486DX
80486SX
80486DX2
80486SL
80486DX4
8KB of cache memory was introduced
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Pentium
Introduced in 1993
It was also 32-bit microprocessor
Clock speed was 66 MHz
Data bus is 32-bit and address bus is 32-bit
Could address 4GB of memory
Could execute 110 million instructions per second
Cache memory
8KB for Instruction
8KB for data
Upgraded Version: Pentium Pro

Pentium II
Introduced in 1997
32-bit microprocessor
Clock speed was 233 to 450 MHz
MMX technology was supported
L2 cache and processor were on one circuit
Upgraded Version: Pentium II Xenon

Pentium III
Introduced in 1999
It was 32-bit microprocessor
Clock speed varied from 500 MHz to 1.4 GHz
It had 9.5 million transistors

Pentium IV
Introduced in 2000
32-bit microprocessor
Clock speed was from 1.3 GHz to 3.8 GHz
L1 cache was 32 KB and L2 cache was 256 KB
It had 42 million transistors
Intel Dual Core
Introduced in 2006
It is 32-bit or 64 bit Microprocessor
It has 2-cores
Both cores have their own internal bus and L1 cache but share the external bus and L2 cache
Support SMT (Simultaneously Multithreading Technology)

64 Bit Microprocessors

Intel Core 2
Introduced in 2006
64-bit microprocessor
Clock speed is from 1.2 GHz to 3GHz
It has 291 million transistors
L1 cache- 64 KB per core
L2 cache- 4 MB
Versions:
Intel Core 2 Duo
Intel Core 2 Quad
Intel Core 2 Extreme

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Intel Core i7
Introduced in 2008
64-bit microprocessor
It has 4 physical cores
Clock speed is from 2.66 GHz to 3.33 GHz
It has 781 million transistors
L1 cache- 64 KB per core
L2 cache- 256 KB
L3 cache- 4 MB

Intel Core i5
Introduced in 2009
It is a 64-bit microprocessor
It has 4 physical cores
Its clock speed is from 2.40 GHz to 3.60 GHz
It has 781 million transistors
L1 cache- 64 KB per core
L2 cache- 256 KB
L3 cache- 8 MB

Intel Core i3
Introduced in 2010
64-bit microprocessor
It has 2 physical cores
Clock speed is from 2.93 GHz to 3.33 GHz
It has 781 million transistors
L1 cache- 64 KB per core
L2 cache- 512 KB
L3 cache- 4 MB

Intel Core i9
Introduced in 2017
64-bit microprocessor
It has 10 physical cores
Clock speed is from 3.3 GHz to 4.5 GHz
It has around 7 billion transistors
L3 smart cache- 13.75MB

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Advantages of Microprocessor based system
Computational/processing speed is high.
Intelligence has been brought to systems.
Automation of industrial processes and office administration.
Since the devices are programmable, there is flexibility to alter the system by changing the software
alone.
Less number of components, compact in size and cost less. Also it is more reliable.
Operation and maintenance are easier.

Disadvantages of Microprocessor based System

7. It has limitations on the size of data.
8. The applications are limited by the physical address space.
9. The analog signals cannot be processed directly and digitizing the analog signals introduces errors.
10. The speed of execution is slow and so real time applications are not possible.
11. Most of the microprocessors does not support floating point operations.

Harvard vs. Von Neumann Architecture

Two dominant computer architectures exist for designing microprocessors and microcontrollers.
These two architectures include Harvard and von Neumann. The Harvard and von Neumann
architectures consist of four major subsystems: memory, input/output (I/O), arithmetic/logic unit
(ALU), and control unit (diagrammed in Figures 1a and 1b). The ALU and control unit operate
together to form the central processing unit (CPU). Instructions and data are stored in high-speed
memories called registers within the CPU. Each of these components interact together to
complete the execution of instructions.

Program CPU Data

Memory Memory
(instructions
)

I/O

Figure 1a: Harvard Architecture

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 Program CPU
Memory and
Data
Memory

I/O

Figure 1b: von Neumann Architecture

The von Neumann architecture allows for one instruction to be read from memory or
data to be read/written from/to memory at a time. In other words, an instruction fetch
and data operation cannot be performed at the same time. Instructions and data are
stored in the same memory subsystem and share a communication pathway or bus to the
CPU. This constraint is referred to as the von Neumann bottleneck and directly impacts
the performance of the system.

The von Neumann bottleneck limits the throughput or data transfer rate between the CPU
and memory. In order to complete most operations, the CPU is required to wait for data.
The bottleneck becomes more of a burden on high-performance systems as memory and
processing speed increases. The Harvard architecture addresses some of these limitations.

The Harvard architecture alternatively consists of separate pathways or buses for

interaction between the CPU and memory. The separation allows for instructions and
data to be accessed concurrently. Also, a new instruction may be fetched from memory
at the same time another one is finishing execution, allowing for a primitive form of
pipelining. Pipelining decreases the execution time of one instruction, but main memory
access time, in many cases, is a major bottleneck in the overall performance of the
system

Bus Structure of microprocessor:

A bus is a path or a collection of wires or lines that carries data, address and control
signals.
There are three buses in Microprocessor:
1.Address Bus
2.Data Bus
3.Control Bus

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 Fig: Bus Structure of 8085 microprocessor
1. Address Bus:- The bus over which the CPU sends out the address of the memory location is known as
Address bus. The address bus carries the address of memory location to be written or to be read from.
The address bus is unidirectional. It means bits flowing occur only in one direction, only from
microprocessor to peripheral devices. We can find that how much memory location it can use the
formula2^ N. where N is the number of bits used for address lines.
8085 Microprocessor has 16 bit address bus.
here, 2^16 = 65536bytes or 64Kb
So we can say that it can access up to 64 kb memory location.

2.Data Bus:-8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit data starting from
00000000H (00H) to 11111111H (FFH). Here 'H' tells the Hexadecimal Number. It is bidirectional. These
lines are used for data flowing in both direction means data can be transferred or can be received through
these lines. The data bus also connects the I/O ports and CPU. The largest number that can appear on the
data bus is 11111111.
It has 8 parallel lines of data bus. So it can access upto 2^8 = 256 data bus lines.

3.Control Bus:-The control bus is used for sending control signals to the memory and I/O devices. The
CPU sends control signal on the control bus to enable the outputs of addressed memory devices or I/O
port devices.

Some of the control bus signals are as follows:

1.Memory read
2.Memory write
3.I/O read
4.I/O write.

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 CHAPTER 2
8085 Microprocessors and ALP

8085 INTRODUCTION
The features of INTEL 8085 are:
• It is an 8 bit processor.
• It is a single chip N-MOS device with 40 pins.
• It works on 5 Volt dc power supply.
• The maximum clock frequency is 3 MHz while minimum frequency is 500 KHz.
• It provides 74 instructions with 5 different addressing modes.
• It has multiplexed address and data bus (AD0-AD7).
• It provides 16 address lines so it can access 216 =64K bytes of memory.
• It generates 8 bit I/O address so it can access 28=256 input ports.

8085 Pin Diagram

Some important pins are:

AD0-AD7: Multiplexed Address and data lines.

A8-A15: Tri-stated higher order address lines.

ALE: Address latch enable is an output signal. It goes high when operation is started
by processor.

S0, S1: These are the status signals used to indicate type of operation.
RD: Read is active low input signal used to read data from I/O device or memory.
WR: Write is an active low output signal used write data on memory or an I/O device.

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 READY: This an output signal used to check the status of output device. If it is low,
µP will WAIT until it is high.

TRAP: It is an Edge triggered highest priority, non-maskable interrupt. After TRAP,

restart occurs and execution starts from address 0024H.

RST 5.5, 6.5, 7.5: These are maskable interrupts and have low priority than TRAP.

INTR & INTA: INTR is an interrupt request signal after which µP generates INTA or
interrupt acknowledge signal.

IO/M: This is output pin or signal used to indicate whether 8085 is working in I/O
mode (IO/M=1) or Memory mode (IO/M=0).

HOLD & HLDA: HOLD is an input signal .When µP receives HOLD signal it
completes current machine cycle and stops executing next instruction. In response to
HOLD µP generates HLDA that is HOLD Acknowledge signal.

RESET IN: This is input signal. When RESET IN is low µp restarts and starts
executing from location 0000H.

SID: Serial input data is input pin used to accept serial 1 bit data.

SOD: Serial output data is output pin used to send serial 1 bit data.

X1, X2: These are clock input signals and are connected to external LC or RC circuit.
These are divide by two so if 6 MHz is connected to X1X2, the operating frequency
becomes 3 MHz.

VCC & VSS: Power supply VCC=+ -5Volt& VSS=-GND reference.

RESTART INTERRUPTS;
These three inputs have the same timing as INTR except they cause an
internal RESTART to be automatically inserted.
RST 7.5 - Highest Priority
RST 6.5
RST 5.5- Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 2CH (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 34H (hexadecimal) address.

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 RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 3CH (hexadecimal) address.

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 8085 ARCHITECTURE

Figure: Internal Architecture of 8085 microprocessor.

ARITHMETIC AND LOGIC UNIT (ALU)
Accumulator:
It is 8 bit general purpose register. It is connected to ALU. So, most of the operations
are done in Accumulator (A).

Temporary register:
It is not available for user. All the arithmetic and logical operations are done in the
temporary register but user can’t access it.

Flag Register: It is an 8-bit register which consists of 5 flip flops used to know status
of various operations done.

S Z - AC - P - CY

Fig. 8085 Flag Register

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 S: Sign flag is set when result of an operation is negative.
Z: Zero flag is set when result of an operation is 0.
AC: Auxiliary carry flag is set when there is a carry out of lower nibble or lower four
bits of the operation.
CY: Carry flag is set when there is carry generated by an operation.
P: Parity flag is set when result contains even number of 1’s.
Rest are don’t care flip flops and reserved for future use.

REGISTER ARRAY
Temporary registers (W, Z): These are not available for user. These are loaded only
when there is an operation being performed.
General purpose: There are six 8-bit general purposes register in 8085 namely B, C,
D, E, H and L. These are used for various data manipulations. They can be used in
pairs as 16-bit registers. The register pairs are: BC pair, DE pair and HL pair. Special
purpose: There are two special purpose registers in 8085:
SP (Stack Pointer): It is a 16-bit register used to hold the address of stack during
stack operation i.e PUSH and POP operations.
PC (Program Counter): It is a 16-bit register which holds the address of next
instruction to be fetched. When a single byte instruction is executed PC is
automatically incremented by 1. Upon reset PC contents are set to 0000H.

TIMIMG AND CONTROL UNIT

This unit synchronizes all the microprocessor operations with the clock and generates
the control signals necessary for communication between the microprocessor and
peripherals. The and signals are sync pulse indicating the availability of data on the
data bus.
INSTRUCTION REGISTER AND DECODER
The instruction register and decoder are part of ALU. When an instruction is fetched
from memory, it is loaded in the instruction register. The decoder decodes the
instruction and establishes the sequence of events to flow. The instruction register is
not programmable and cannot be accessed through any instructions.

INTERRUPT CONTROL
It accepts different interrupts like TRAP, RST 5.5, RST 6.5, RST 7.5 and INTR.
INTA is interrupt acknowledgement signal.

SERIAL IO CONTROL
It is used to accept and send the serial 1 bit data by using SID and SOD signals and it
can be performed by using SIM & RIM instructions.

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 8085 INSTRUCTION SETS
a) Data Transfer Instructions
b) Arithmetic Instructions
c) Logical Instructions
d) Rotate Instructions
e) Branching Instructions
f) Control Instructions

a) Data Transfer instructions

Mnemonics Description Example
• Copies the content of source MOV A, B
register Rs into destination
MOV Rd, Rs register Rd
• Rs and Rd can be A, B, C, D,
E, H, L
• Copies the content of memory MOV A, M
location M into the
destination register Rd
MOV Rd, M • Rd can be A, B, C, D, E, H, L
• The memory location M is
specified by HL pair
• Copies the content of register MOV M, A
Rs into memory location M
MOV M, Rs • Rs can be A, B, C, D, E, H, L
• The memory location M is
specified by HL pair
• The 8-bit data is stored in the MVI A, 32H
destination register Rd
MVI Rd, 8-bit • Rd can be A, B, C, D, E, H, L

MVI M, 8-bit • The 8-it data is stored in MVI M, 32H

memory location M
• M is specified by HL pair
LDA 16-bit • Copies the content of memory LDA 2015H

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 (Load Accumulator location specified by 16-bit A ←[2015 ]
Direct) address into A
STA 16-bit • Copies the content of A into STA 2015H
(Store Accumulator 16-bit memory address A→[ 2015]
Direct)
• Copies the content of memory LDAX B
LDAX Rp location specified by register
(Load Accumulator pair Rp into A
Inirect) • Rp can be B or D i.e. BC pair
or DE pair
• Copies the content of A into STAX B
STAX Rp 16-bit memory address
(Store Accumulator specified by register pair Rp
Indirect) • Rp can be B or D i.e. BC pair
or DE pair
LXI Rp, 16-bit • Loads 16-bit data into register LXI H, 2015H
(Load Register Pair) pair L←15
• Rp can be B, D or H i.e. BC H←20
pair, DE pair or HL pair
IN 8-bit • The data from i/p port IN 40H
specified by 8-bit address is A← [40]
transferred into A 40H is address
of input port
OUT 8-bit • The data of A is transferred OUT 10H
into output port specified by A→ [10]
8-bit address 10H is address
of output port
XCHG • Exchange the content of HL XCHG
pair with DE pair i.e. the H→D
content of H and D are L→E
exchanged whereas content of
L and E are exchanged

b) Arithmetic Instructions
Mnemonics Description Example
• The content of register ADD B
ADD R/M /memory (R/M) is added to A←A+B
(add the A and result is stored in A
register/memory) • The memory M is specified ADD M
by HL pair A←A+M
• The content of register ADC B
ADC R/M /memory (R/M) is added to A←A+B+CF
(add with carry) the A along with carry flag
CF and result is stored in A ADC M
• The memory M is specified A←A+M+CF
by HL pair
ADI 8-bit • The 8-bit data is added to A ADI 32H
(add immediate) and result is stored in A A←A+32
ACI 8-bit • The 8-bit data is added to A ACI 32H

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 (add immediate along with carry flag CF and A←A+32+CF
with carry) result is stored in A
• The content of register SUB B
SUB R/M /memory (R/M) is subtracted A←A-B
(subtract from A and result is stored in
register/memory) A SUB M
• The memory M is specified A←A-M
by HL pair
• The content of register SBB B
SBB R/M /memory (R/M) is subtracted A←A-B-BF
(subtract with from A along with borrow
borrow) flag BF and result is stored in SBB M
A A←A-M-CF
• The memory M is specified
by HL pair
SUI 8-bit • The 8-bit data is subtracted SUI 32H
(subtract from A and result is stored in A←A-32
immediate) A
• Increment the content of INR B
INR R/M register/memory by 1 B←B+1
(Increment • Memory is specified by HL
Register/Memory) pair INR M
M←M+1
• Decrement the content of DCR B
DCR R/M register/memory by 1 B←B-1
(Decrement • Memory is specified by HL
Register/Memory) pair DCR M
M←M-1
INX Rp • Increment the content of INX H
(Increment Register register pair Rp by 1 HL←HL+1
Pair)
DCX Rp • Decrement the content of DCX H
(Decrement register pair Rp by 1 HL←HL-1
Register Pair)

c) Logical Instructions
Mnemonics Description Example
CMP R/M • Compares the content of CMP B
(Compare register/memory with A
Register/Memory) • The result of comparison is: CMP M
If A< R/M : Carry Flag CY=1
If A= R/M : Zero Flag Z=1
If A> R/M : Carry Flag CY=0
CPI 8-bit • Compares 8-bit data with A
(Compare • The result of comparison is:
Immediate)
If A< 8-bit : Carry Flag CY=1 CPI 55H
If A= 8-bit : Zero Flag Z=1
If A> 8-bit : Carry Flag CY=0

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 ANA R/M • The content of A are logically ANA B
(logical AND ANDed with the content of A←A.B
register/memory) register/memory and result is
stored in A ANA M
• Memory M must be specified A←A.M
by HL pair
ANI 8-bit • The content of A are logically ANI 32H
(AND immediate) ANDed with the 8-bit data A←A.32H
and result is stored in A
ORA R/M • The content of A are logically ORA B
(logical OR ORed with the content of
register/memory) register/memory and result is
stored in A ORA M
• Memory M must be specified
by HL pair
ORI 8-bit • The content of A are logically ORI 32H
(OR immediate) ORed with the 8-bit data and
result is stored in A
XRA R/M • The content of A are logically XRA B
(logical XOR XORed with the content of
register/memory) register/memory and result is
stored in A XRA M
• Memory M must be specified
by HL pair
XRI 8-bit • The content of A are logically XRI 32H
(XOR immediate) XORed with the 8-bit data
and result is stored in A

d) Rotate Instructions
Mnemonics Description Example
RLC • Each bit of A is rotated left by RLC
(Rotate one bit position.
Accumulator Left) • Bit D7 is placed in the
position of D0.
RRC • Each bit of A is rotated right RRC
(Rotate by one bit position.
Accumulator Right) • Bit D0 is placed in the
position of D7.
RAL • Each bit of A is rotated left by RAL
(Rotate one bit position along with
Accumulator Left carry flag CY
with Carry) • Bit D7 is placed in CY and
CY in the position of D0.
RAR • Each bit of A is rotated right RLC
(Rotate by one bit position along with
Accumulator Right carry flag CY.
with Carry) • Bit D7 is placed in CY and
CY in the position of D0.

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 e) Branching Instructions
Mnemonics Description Example
JMP 16-bit The program sequence is transferred JMP C000H
(Unconditional to the memory location specified by
Jump) 16-bit address
JC Jump on Carry (CY=1)
JNC Jump No Carry (CY=0)
JP Jump on Positive (S=0)
JM Jump on Negative (S=1)
JZ Jump on Zero (Z=1)
JNZ Jump No Zero (Z=0)
JPE Jump on Parity Even (P=1)
JPO Jump on Parity Odd (P=0)
CALL 16-bit The program sequence is transferred CALL C000H
to the subroutine at memory location
specified by the 16-bit address
RET The program sequence is transferred RET
from the subroutine program to
calling program

f) Control Instructions
Mnemonics Description Example
NOP No operation is performed NOP
HLT The CPU finishes executing the HLT
current instruction and stops any
further execution

8085 ADDRESSING MODES

The ways by which operands are specified in an instruction are called
addressing modes. The different addressing modes of 8085 are:
1. Immediate Addressing Mode
In immediate addressing mode, the data is specified in the instruction itself. The data will
be apart of the program instruction. All instructions that have ‘I’ in their mnemonics are of
Immediate addressing type.
Examples: MVI A, 05H
ADI 55H
LXI H, C000H
2. Register Addressing Mode
If the data is present in the register and the register are specified in an instruction, than
it is called register addressing mode.
Example: MOV A, B
ADD B
ANA C

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 3. Direct Addressing Mode
In direct addressing mode, the address of the data is specified in the instruction.
The data will be in memory. In this addressing mode, the program instructions
and data can be stored in different memory blocks. This type of addressing can be
identified by 16-bit address present in the instruction.
Example: LDA 2000H
STA 2000H
IN 10H
OUT 01H

4. Register Indirect Addressing Mode

If the register pair which contains the address of the data is specified in
the instruction, than it is called register indirect addressing mode.
Example: LDAX B
STAX D
MOV M, A
MOV B, M

5. Implied Addressing Mode

If the opcode in an instruction tells about the operand, than it is called implied
addressing mode.
Example: RAL
RRC

TIMING DIAGRAMS OF 8085 INSTRUCTIONS

a) Related Terms
Instruction Cycle: The time taken to complete the execution of an instruction
is called instruction cycle. It is the combinations of machine cycles.

Machine Cycle: The time taken by the processor to access memory location,
IO ports or to acknowledge an interrupt once is called as machine cycles. It is
the combinations of T-states.

T-States: It is the sub-division of operation performed in one clock cycle

of processor’s clock.

b) Status Signals for Various Machine Cycles

Machine Cycles Status Signals
IO/ ̅̅̅
̅̅̅
S1 S0
Opcode Fetch 0 1 1
Memory Read 0 1 0
Memory Write 0 0 1
IO Read 1 1 0
IO Write 1 0 1

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 c) Types of Instruction On the Basis of Size One
Byte Instructions
These Instruction use a total memory of one-byte
These Instructions include the opcode and operand in the same byte.
Examples: MOV C, A
ADD B RLC

Two Byte Instructions

These instructions use a total memory of two bytes.
The first byte specifies the opcode and second byte specifies the operand
Examples: MVI A, 32H
ADI 30H IN
40H

Three Byte Instructions

These instructions use a total memory of three bytes.
The first byte specifies the opcode and the remaining two bytes specifies the 16-bit
address i.e. second byte specifies the lower order address and third byte specifies the
higher order address.
Example: LDA 2070H STA
2050H LXI H,
2070H
Machine Cycle of 8085:
The various machine cycles are
1. Opcode fetch …………….. -4 /6T
2. Memory Read ……………. -3T
3. Memory Write ……………. -3T
4. I/O Read ………………….. -3T
5. I/O Write …………………. -3T
6. Interrupt Acknowledge …… - 6 / 12 T
7. Bus Idle …………………… -2 /3T

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