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D D D D D D: SN54HC74, SN74HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

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0% found this document useful (0 votes)
65 views24 pages

D D D D D D: SN54HC74, SN74HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS


WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003

D Wide Operating Voltage Range of 2 V to 6 V SN54HC74 . . . J OR W PACKAGE

D Outputs Can Drive Up To 10 LSTTL Loads


SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 15 ns 1CLR 1 14 VCC
D ±4-mA Output Drive at 5 V 1D 2 13 2CLR

D Low Input Current of 1 µA Max


1CLK
1PRE
3
4
12
11
2D
2CLK
description/ordering information 1Q 5 10 2PRE
1Q 6 9 2Q
The ’HC74 devices contain two independent GND 7 8 2Q
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets SN54HC74 . . . FK PACKAGE
or resets the outputs, regardless of the levels of (TOP VIEW)
the other inputs. When PRE and CLR are inactive

1CLR

2CLR
VCC
(high), data at the data (D) input meeting the setup

NC
1D
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK) 3 2 1 20 19
pulse. Clock triggering occurs at a voltage level 1CLK 4 18 2D
and is not directly related to the rise time of CLK. NC 5 17 NC
Following the hold-time interval, data at the 1PRE 6 16 2CLK
D input can be changed without affecting the NC 7 15 NC
levels at the outputs. 1Q 8 14 2PRE
9 10 11 12 13

1Q

2Q
2Q
NC
GND
NC – No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube of 25 SN74HC74N SN74HC74N
Tube of 50 SN74HC74D
SOIC – D Reel of 2500 SN74HC74DR HC74
Reel of 250 SN74HC74DT
–40°C to 85°C SOP – NS Reel of 2000 SN74HC74NSR HC74
SSOP – DB Reel of 2000 SN74HC74DBR HC74
Tube of 90 SN74HC74PW
TSSOP – PW Reel of 2000 SN74HC74PWR HC74
Reel of 250 SN74HC74PWT
CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J
–55°C to 125°C CFP – W Tube of 150 SNJ54HC74W SNJ54HC74W
LCCC – FK Tube of 55 SNJ54HC74FK
SNJ54HC74FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H† H†
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0
† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.

logic diagram (positive logic)


PRE

C
CLK C
Q
C TG

C C
C
C

D TG TG
TG

Q
C C
C
CLR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003

recommended operating conditions (see Note 3)


SN54HC74 SN74HC74
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
TA = 25°C SN54HC74 SN74HC74
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 1.998 1.9 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 4 80 40 µA
Ci 2 V to 6 V 3 10 10 10 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC74 SN74HC74
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 6 4.2 5
fclock Clock frequency 4.5 V 31 21 25 MHz
6V 0 36 0 25 0 29
2V 100 150 125
PRE or CLR low 4.5 V 20 30 25
6V 17 25 21
tw Pulse duration ns
2V 80 120 100
CLK high or low 4.5 V 16 24 20
6V 14 20 17
2V 100 150 125
Data 4.5 V 20 30 25
6V 17 25 21
tsu ↑
Setup time before CLK↑ ns
2V 25 40 30
PRE or CLR inactive 4.5 V 5 8 6
6V 4 7 5
2V 0 0 0
th ↑
Hold time, data after CLK↑ 4.5 V 0 0 0 ns
6V 0 0 0

switching characteristics over recommended operating free-air temperature range, CL = 50 pF


(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HC74 SN74HC74
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 6 10 4.2 5
fmax 4.5 V 31 50 21 25 MHz
6V 36 60 25 29
2V 70 230 345 290
PRE or CLR Q or Q 4.5 V 20 46 69 58
6V 15 39 59 49
tpd
d ns
2V 70 175 250 220
CLK Q or Q 4.5 V 20 35 50 44
6V 15 30 42 37
2V 28 75 110 95
tt Q or Q 4.5 V 8 15 22 19 ns
6V 6 13 19 16

operating characteristics, TA = 25°C


PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003

PARAMETER MEASUREMENT INFORMATION


VCC
From Output Test High-Level
Under Test Point 50% 50%
Pulse
0V
CL = 50 pF
tw
(see Note A)
Low-Level VCC
Pulse 50% 50%
LOAD CIRCUIT
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS

VCC VCC
Reference 50% Input 50% 50%
Input
0V 0V
tsu th tPLH tPHL

Data VCC In-Phase VOH


90% 90% 90% 90%
Input 50% 50% Output 50% 50%
10% 10% 0 V 10% 10%
VOL
tr tf
tr tf
tPHL tPLH
VOLTAGE WAVEFORMS VOH
Out-of-Phase 90% 90%
SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% 50%
Output 10% 10%
VOL
tf tr

VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5


PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8405601VCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8405601VC
& Green A
SNV54HC74J
5962-8405601VDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8405601VD
& Green A
SNV54HC74W
84056012A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84056012A
& Green SNJ54HC
74FK
8405601CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601CA
& Green SNJ54HC74J
8405601DA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601DA
& Green SNJ54HC74W
JM38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302B2A
JM38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302BCA
JM38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302BDA
M38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302B2A
M38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302BCA
M38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65302BDA
SN54HC74J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC74J
& Green
SN74HC74D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC74DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N

SN74HC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N

SN74HC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SNJ54HC74FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84056012A
& Green SNJ54HC
74FK
SNJ54HC74J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601CA
& Green SNJ54HC74J
SNJ54HC74W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601DA
& Green SNJ54HC74W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2021

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :

• Catalog : SN74HC74, SN54HC74


• Automotive : SN74HC74-Q1, SN74HC74-Q1
• Enhanced Product : SN74HC74-EP, SN74HC74-EP
• Military : SN54HC74
• Space : SN54HC74-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3
PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2021

• Enhanced Product - Supports Defense, Aerospace and Medical Applications


• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jun-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC74DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC74PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jun-2021

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC74DBR SSOP DB 14 2000 853.0 449.0 35.0
SN74HC74DR SOIC D 14 2500 366.0 364.0 50.0
SN74HC74DR SOIC D 14 2500 853.0 449.0 35.0
SN74HC74DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC74DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC74DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74HC74DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC74DT SOIC D 14 250 210.0 185.0 35.0
SN74HC74NSR SO NS 14 2000 853.0 449.0 35.0
SN74HC74PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC74PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC74PWT TSSOP PW 14 250 853.0 449.0 35.0

Pack Materials-Page 2
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN


(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP


[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE


[0.38]

0 -15 14X .008-.014


TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE


NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)


[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX


(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE


28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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