ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT

EXPERIMENT 2: Multistage Amplifier

Program Outcomes (POs) Addressed by the Activity

a. ability to apply knowledge of mathematics and science to solve
engineering problems
b. ability to design and conduct fieldworks, as well as to analyse and
interpret data
c. ability to function on multidisciplinary teams
d. ability to use techniques, skills, and modern engineering tools necessary for engineering
practice

Activity’s Intended Learning Outcomes (AILOs)

At the end of this activity, the student shall be able to:
a. identify instrument use in Multi Stage Amplifier
b. calculate different parameters in the given circuit

Objectives of the Activity

The objectives of this activity are to:
a. To measure DC and AC voltages in a multistage FET amplifier
b. To obtain measure values of voltage amplification ( Av ),input impedance
(Zi) and output impedance (Zo).

EQUIPMENT REQUIRED

1 unit Steel Tape

2 units Range Poles
Marking Pins
Plumb Bobs

RESUME OF THEORY

The DC bias of JFET is determined by the device transfer characteristic (Vp and IDSS) and
the external circuit connected to it. The AC voltage gain at this DC bias point is then
dependent on the device parameters (gm or gfs) and circuit drain resistance. AC Voltage
Gain: The voltage gain of an amplifier stage can be calculated from
Where: gm = gmo ( 1- Vgs/ Vp) with gmo = 2 IDSS / |Vp|

AC Input Impedance: The AC input impedance is

Zi= RG
AC Output Impedance : The AC output impedance is

Zo= RD
PROCEDURE

Part 1: Measurement of IDSS and Vp

It is necessary to obtain values of IDSS and Vp for both Q1 and Q2. Use a characteristic
curve tracer, if available, to determine the values of I DSS and Vp . Obtain readings at VDS =
10 V.

Go on to part 2.
Otherwise , use the following steps to obtain these values.
Construct the circuit with RD= 510 (but with Rs= 0). Measure and record.

A. Calculate the values of drain current, I D

ID = (VDD - VD)/RD

since this is the drain current at Vgs = 0V

IDSS (Q1)= ID= 7.55 mA
(using the value of ID just calculated)

Replace Q1 and repeat measurement with Q2.

V(measured) VD= 6.15 V

Calculate the value of drain current, I D

ID= (VDD - VD)/RD
(calculated) ID = 2 mA

Q1 – 2N4222
Q2 – 2N4223

since this is the drain current at VGS =0V

IDSS (Q2)= ID = 9.87 mA
(using the value of ID just calculated)
a. Now connect RS= 1KΩ. Measure and record the values of
(measured) VGS = -1.77 mA

Q2 – 2N4223 (measured) VD = 9.10V

Using the measured values just obtained, calculate Vp as follows.

ID= (VDD - VD) /RD
(calculated)ID= 9.88 mA
VP= VGS/ [1-  (ID- IDSS)]
(calculated) VP (Q2)= -3.07 V

Replace transistor Q2 and repeat step b measurements.

(measured) VGS = -1.77 mA
(measured) VD= 9.10 V
Using the values just obtained, calculate Vp as follows.
ID= (VDD - VD) / RD
(calculated) ID= 9.88 mA
VP=
(calculated) Vp (Q1) = -4.12 V

Part 2. DC Bias of Common-Source Circuit

a. Calculate the DC bias expected in the circuit, using IDSS and VP obtained in part 1 for
each transistor.
Draw graphs of the equations
ID = IDSS [1- (VGS/VP)]2 and VGS = -IDRS
To graphically obtain the equation intersection or use a computer or programmable
calculator to solve the simultaneous equations.
The calculated DC bias values are: (calculated) VGS1 = -2.10 V .

using VD1 = VDD – ID1RD1

(calculated) VD2 = 18.929

(calculated) ID1 = 2.1 mA

b. Build the circuit using RG1= RG2 = 1M, RS1= RS2 = 510, and RD1= RD2 = 2.4K, Set
VDD = 20V.
c. Measure the DC bias voltages
(measured) VG1= 351 uV
(measured)VS1= 2.10V
(measured)VD1= 17.9 V
(measured)VGS1= -2 V
Determine the value of ID under DC bias conditions (using nominal resistor values)
ID1 = VS2 / RS2
(Calculated)ID 1 = 2.1mA
(measured)VG2 = -39.9 mV
(measured)VS2=2.09 V
(measured)VD2=18.3 V
(measured)VGS2= -1.91 mV
Determine the value of ID2 under DC bias conditions
ID2 = VS1 / RS1
ID2= 2.09 V
 Compare the DC bias value calculated in step a with those measured in step c.
Almost the same because they have the same gain, drain and source value. A little discrepancy on the values.

Part 3. AC Voltage gain of amplifier.

a. Calculate the voltage gain of the common-source amplifier of Fig. above.
For stage 2:
AV2 = -gm(RD2 || RL)
With gm = Using VP (Q1), IDSS (Q1) from Part 1 and VGS1 calculated in part 2
(calculated) AV1 = 1380.009

Calculate overall amplifier gain:

AV = AV1  AV2
(calculated) AV = 1431233.692

b. Connect input of Vsig = 10mV, rms at  = 1KHz. Use the oscilloscope to obtain an
undistorted output voltage, adjusting V sig if necessary. Measure and record.
(measured) Vsig = 10mV
(measured) VL= -1.084 uV

Calculate the voltage gain of the overall amplifier

AV= VL / Vsig
AV = -9259.259V
Measure and record
(measure) VO1 = 16.3 mV
Calculate the gain of each stage:
AV1 = Vo1 / Vsig
(measured) AV1= 1.63
AV2 = VL / Vo1
(measured) AV2 = 2.816

Part 4. Input and Output Impedance Measurements

a. The input impedance is

Zi = RG1
Zi = 10M
b. The output impedance is
Zo = RD2
Zo = 510
c. Connect a 10K resistor, RS in series with the input signal, V sig= 10 mV, rms at  =
100Hz.
Measure Vi1.
(measured)
Vi1=20 mV
Determine the input impedance using
Zi= [ Vi1/ (Vsig-Vi1)] RS
Zi = -2000
 Remove measurement resistor , RS
d. Measure VL
(measured) VL= 0V
Disconnect load RL = 10 K. Measure output voltage, Vo
(measured) Vo= 16.3 mV
Determine the AC output impedance using
Zo = Vo - Vi1( RL)
VL
Zo = -8.88

Activity Report
Section: TT066
Date Performed: 05/20/2021
Course Code: ELECS2L
Date Submitted: 05/31/2021
Course Title: ELECTRONIC CIRCUIT ANALYSIS AND DESIGN (LAB)
Instructor: Engr. Carlo Romero
Group No.: The Gwapings
Activity No.: 2
Group Members:
Signature:
1.Aguila, Karl
2.Arevalo, Lennard
3.Escandor, Jayrald
4.Lazo, Frodolfre Reginald

2.8.1 Data and Results

Compare the input impedance calculated in step a with that determined from
measurements in step c.
they are different in value because the first step was the value of the resistor given on the circuit and the
second step was the measured values

Compare the output impedance calculated in step b with that determined from
measurements in step d.
the output impedance is smaller than the input and they are different because the first step was the value of
the resistor given on the circuit and the second step was the measured values

Calculations
2.8.3 Observations (if applicable)
Calculations were provided below..
2.8.4 Conclusion/s

In this experiment we learned that in amplifying a signal it is ideal to

use two or more stage amplifier circuit to get better and more great
amplification.
In RC coupled amplifiers, the capacitive coupling capacitor and the load
on the first stage serve as the RC coupling. The input impedance of the second
stage acts as a load on the first stage. The RC coupling connects the output of
the first stage of the amplifier to the input, specifically the base of the second
stage. Any signal applied in the input is amplified in the first stage and will be
further amplified in the second stage of the amplifier. The coupling capacitor
isolates the two stages from a dc viewpoint but acts as a short-circuit equivalent
for the ac response.
VGS = 0

Measured
IDSS=7.55 mA

Calculated
(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟏𝟎 − 𝟔. 𝟏𝟓)
𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟓𝟒𝟗𝟎 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

Measured
ID= 2 mA
Calculated
(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟏𝟎 − 𝟖. 𝟗𝟖)
𝑰𝑫 = = = 𝟐 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

VGS = (VG – VS) = (0V – 2V) = -2V

VGS= -2V

𝑽𝑮𝑺 −𝟐
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟐𝟏𝟎 𝑽
𝑰 𝟐
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟓𝟓
VGS = 0

Measured
IDSS=9.87 mA

Calculated
(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟏𝟎 − 𝟒. 𝟗𝟔)
𝑰𝑫𝑺𝑺 = = = 𝟗. 𝟖𝟖𝟐𝟑 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

Measured
ID= 1.77 mA

Calculated
(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟏𝟎 − 𝟗. 𝟏𝟎)
𝑰𝑫 = = = 𝟏. 𝟕𝟔𝟒𝟕 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

VGS = (VG – VS) = (0V – 1.77V) = -1.77V

VGS= -1.77V

𝑽𝑮𝑺 −𝟏. 𝟕𝟕
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟑. 𝟎𝟕 𝑽
𝑰 𝟏. 𝟕𝟕
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟗. 𝟖𝟕
Part 2

MEASURED stage1 MEASURED stage2

VGS = -2 V VGS = -1.91 mV
ID = 1.56 mA IDS = -1.54 mA
VS =2.10 V VS =2.09 V
VG = 351uV VG = -39.9 mV
VD = 17.9 V VD = 18.3 V

CALCULATED stage1
VG =0
VS= 2.10 V
VGS = (VG – VS) = (0V – 2.10V) = -2.10 V

(𝑽𝑺 ) 𝟐. 𝟏𝟎
𝑰𝑫 = = = 𝟐. 𝟏 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.1mA) (510Ω) = 18.929 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)

𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎
𝑽𝑮𝑺 −𝟐. 𝟎𝟑
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟖𝟔𝟕 𝑽
𝑰𝑫 𝟐. 𝟎𝟑
𝟏−√ √
𝑰𝑫𝑺𝑺 𝟏 − 𝟕. 𝟔𝟓
𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟔𝟓𝟒
|𝑽𝑷 | | − 𝟒. 𝟏𝟖𝟔𝟕|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟏𝟎)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟔𝟓𝟒) ( ) = 𝟐. 𝟕𝟎𝟓𝟗
𝑽𝑮𝑺𝒐𝒇𝒇 |𝟒. 𝟏𝟖𝟔𝟕|

𝑨𝑽𝟏 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟕𝟎𝟓𝟗(𝟓𝟏𝟎||𝟎) = 𝟏𝟑𝟖𝟎. 𝟎𝟎𝟗

CALCULATED stage2
VG =0
VS= 2.09 V
VGS = (VG – VS) = (0V – 2.09V) = -2.09 V

(𝑽𝑺 ) 𝟐. 𝟎𝟗
𝑰𝑫 = = = 𝟐. 𝟎𝟗 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.09mA) (510Ω) = 18.9341 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)
𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

𝑽𝑮𝑺 −𝟐. 𝟎𝟗
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟑𝟕𝟖𝟕 𝑽
𝑰 𝟐. 𝟎𝟗
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟔𝟓

𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟒𝟗𝟒
|𝑽𝑷 | | − 𝟒. 𝟑𝟕𝟖𝟕|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟎𝟗)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟒𝟗𝟒) ( ) = 𝟐. 𝟒𝟔𝟓𝟕
𝑽𝑮𝑺𝒐𝒇𝒇 𝟒. 𝟑𝟕𝟖𝟕

𝑨𝑽𝟐 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟒𝟔𝟓𝟕(𝟓𝟏𝟎||𝟐. 𝟒𝒌) = 𝟏𝟎𝟑𝟕. 𝟏𝟏𝟗𝟏

𝑨𝑽 𝒕𝒐𝒕𝒂𝒍 = 𝑨𝑽𝟏 × 𝑨𝑽𝟐 = 𝟏𝟑𝟖𝟎. 𝟎𝟎𝟗 × 𝟏𝟎𝟑𝟕. 𝟏𝟏𝟗𝟏 = 1431233.692

Part 3 - Connect input of Vsig= 10mV, rms at  = 1KHz.

MEASURED stage1 MEASURED stage2

VGS = -4 mV VGS = -6.16 mV
IDS = 9.01 uA IDS = -1.54 mA
VS =2.03 V VS =2.03 V
VG = 325 uV VG = 320 uV
VD = 19 V VD = 19 V

CALCULATED stage1

VG =0
VS= 2.10 V
VGS = (VG – VS) = (0V – 2.03V) = -2.03 V

(𝑽𝑺 ) 𝟐. 𝟎𝟑
𝑰𝑫 = = = 𝟐. 𝟎𝟑 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.03mA) (510Ω) = 18.9647 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)

𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎
𝑽𝑮𝑺 −𝟐. 𝟎𝟑
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟖𝟔𝟔 𝑽
𝑰 𝟐. 𝟎𝟑
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟔𝟓

𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟔𝟓𝟒
|𝑽𝑷 | | − 𝟒. 𝟏𝟖𝟔𝟔|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟎𝟑)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟔𝟓𝟒) ( ) = 𝟐. 𝟔𝟒𝟒𝟗
𝑽𝑮𝑺𝒐𝒇𝒇 𝟒. 𝟏𝟖𝟔𝟔

𝑨𝑽𝟏 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟔𝟒𝟒𝟗(𝟓𝟏𝟎||𝟎) = 𝟏𝟑𝟒𝟖. 𝟖𝟕𝟒𝟓

CALCULATED stage2

VG =0
VS= 2.09 V
VGS = (VG – VS) = (0V – 2.03V) = -2.03 V

(𝑽𝑺 ) 𝟐. 𝟎𝟑
𝑰𝑫 = = = 𝟐. 𝟎𝟑 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.03mA) (510Ω) = 18.9647 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)

𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

𝑽𝑮𝑺 −𝟐. 𝟎𝟑
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟖𝟔𝟔 𝑽
𝑰 𝟐. 𝟎𝟑
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟔𝟓

𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟔𝟓𝟒
|𝑽𝑷 | | − 𝟒. 𝟏𝟖𝟔𝟔|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟎𝟑)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟔𝟓𝟒) ( ) = 𝟐. 𝟔𝟒𝟒𝟗
𝑽𝑮𝑺𝒐𝒇𝒇 𝟒. 𝟏𝟖𝟔𝟔

𝑨𝑽𝟐 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟔𝟒𝟒𝟗(𝟓𝟏𝟎||𝟐. 𝟒𝒌) = 𝟏𝟏𝟏𝟐. 𝟒𝟕𝟑𝟖

𝑨𝑽 𝒕𝒐𝒕𝒂𝒍 = 𝑨𝑽𝟏 × 𝑨𝑽𝟐 = 𝟏𝟑𝟒𝟖. 𝟖𝟕𝟒𝟓 × 𝟏𝟏𝟏𝟐. 𝟒𝟕𝟑𝟖 = 1500587.598

𝟏 𝟏
𝒁𝒊 = 𝑹𝑺 || = 𝟏𝒌|| = 𝟎. 𝟑𝟕𝟕𝟗
𝒈𝒎 𝟐. 𝟔𝟒𝟒𝟗
Part 4 - Connect input of Vsig= 10mV, rms at  = 100KHz.

MEASURED stage1 MEASURED stage2

VGS = -6.35 mV VGS = 4.61 V
IDS = 8.48 uA IDS = -8.48 uA
VS =2.03 V VS =2.03 V
VG = 325 uV VG = 317 mV
VD = 19 V VD = 19 V

CALCULATED stage1

VG =0
VS= 2.03 V
VGS = (VG – VS) = (0V – 2.03V) = -2.03 V

(𝑽𝑺 ) 𝟐. 𝟎𝟑
𝑰𝑫 = = = 𝟐. 𝟎𝟑 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.1mA) (510Ω) = 18.9647 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)

𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎

𝑽𝑮𝑺 −𝟐. 𝟎𝟑
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟖𝟔𝟔 𝑽
𝑰 𝟐. 𝟎𝟑
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟔𝟓

𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟔𝟓𝟒
|𝑽𝑷 | | − 𝟒. 𝟏𝟖𝟔𝟔|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟎𝟑)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟔𝟓𝟒) ( ) = 𝟐. 𝟔𝟒𝟒𝟗
𝑽𝑮𝑺𝒐𝒇𝒇 𝟒. 𝟏𝟖𝟔𝟔

𝑨𝑽𝟏 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟔𝟒𝟒𝟗(𝟓𝟏𝟎||𝟎) = 𝟏𝟑𝟒𝟖. 𝟖𝟕𝟒𝟓

CALCULATED stage2

VG =0
VS= 2.09 V
VGS = (VG – VS) = (0V – 2.03V) = -2.03 V

(𝑽𝑺 ) 𝟐. 𝟎𝟑
𝑰𝑫 = = = 𝟐. 𝟎𝟑 𝒎𝑨
𝑹𝑺 𝟏𝟎𝟎𝟎

VD = VDD – IDRD = 20V – (2.09mA) (510Ω) = 18.9647 V

(𝑽𝑫𝑫 − 𝑽𝑫 ) (𝟐𝟎 − 𝟏𝟔. 𝟏)

𝑰𝑫𝑺𝑺 = = = 𝟕. 𝟔𝟓 𝒎𝑨
𝑹𝑫 𝟓𝟏𝟎
𝑽𝑮𝑺 −𝟐. 𝟎𝟑
𝑽𝒑 = 𝑽𝑮𝑺𝒐𝒇𝒇 = = = −𝟒. 𝟏𝟖𝟔𝟔 𝑽
𝑰 𝟐. 𝟎𝟑
𝟏−√ 𝑫 𝟏−√
𝑰𝑫𝑺𝑺 𝟕. 𝟔𝟓

𝟐𝑰𝑫𝑺𝑺 𝟐 × 𝟕. 𝟔𝟓
𝒈𝒎𝒐 = = = 𝟑. 𝟔𝟓𝟒
|𝑽𝑷 | | − 𝟒. 𝟏𝟖𝟔𝟔|

𝟏 − 𝑽𝑮𝑺 𝟏 − (−𝟐. 𝟎𝟑)

𝒈𝒎 = 𝒈𝒎𝒐 ( ) = (𝟑. 𝟔𝟓𝟒) ( ) = 𝟐. 𝟔𝟒𝟒𝟗
𝑽𝑮𝑺𝒐𝒇𝒇 𝟒. 𝟏𝟖𝟔𝟔

𝑨𝑽𝟐 = 𝒈𝒎(𝑹𝑫 ||𝑹𝑳 ) = 𝟐. 𝟔𝟒𝟒𝟗(𝟓𝟏𝟎||𝟐. 𝟒𝒌) = 𝟏𝟏𝟏𝟐. 𝟒𝟕𝟑𝟖

𝑨𝑽 𝒕𝒐𝒕𝒂𝒍 = 𝑨𝑽𝟏 × 𝑨𝑽𝟐 = 𝟏𝟑𝟒𝟖. 𝟖𝟕𝟒𝟓 × 𝟏𝟏𝟏𝟐. 𝟒𝟕𝟑𝟖 = 1500587.598

𝑽𝒊𝟏 𝟐𝟎 𝒎𝑽
𝒁𝒊 = ( ) (𝑹𝑺 ) = ( ) (𝟏𝒌) = −𝟐𝟎𝟎𝟎
𝑽𝑺𝑰𝑮 − 𝑽𝒊𝟏 𝟏𝟎𝒎𝑽 − 𝟐𝟎𝒎𝑽

𝒁𝒐 = (𝑽𝒐 − 𝑽𝒊𝟏 )(𝑹𝑳 ) = (𝟏𝟔. 𝟑 𝒎𝑽 − 𝟐𝟎𝒎𝑽)(𝟐. 𝟒𝒌) = −𝟖. 𝟖𝟖