AN4325

Application note
Getting started with STM32F030xx and STM32F070xx series
hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the STM32F0x0xx products family and describes the minimum hardware
resources required to develop an application.
This document includes detailed reference design schematics and the description of the
main components, interfaces and modes.

Table 1. Applicable products

Type Part number

STM32F030F4, STM32F030CC, STM32F030RC, STM32F030C6,

Microcontrollers STM32F030K6, STM32F030C8, STM32F030R8,
STM32F070C6, STM32F070CB, STM32F070F6, STM32F070RB.

Note: In this document, the notation used for STM32F030xx devices is STM32F030 and the
notation used for STM32F070xx devices is STM32F070. When referring to both series the
notation STM32F0x0 is used. The pin count and memory size do not impact this hardware
description.

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Contents AN4325

Contents

1 Power supplies and reset sources of the STM32F0x0 family . . . . . . . . 6

1.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent analog power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.2 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.1 Power-on reset (POR) / power-down reset (PDR) . . . . . . . . . . . . . . . . . . 8
1.2.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 High speed external clock signal (HSE) OSC clock . . . . . . . . . . . . . . . . . 12
2.2 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 SWD port (serial wire debug) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Serial wire debug (SWD) pin assignment . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.2 SWD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.3 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . 18
4.3.4 SWD port connection with standard SWD connector . . . . . . . . . . . . . . 18

5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Ground and power supply (VDD, VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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AN4325 Contents

5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.4 SWD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.6 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Hardware migration from STM32F1 series to STM32F0x0 devices . . 24

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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List of tables AN4325

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. SWD port pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. STM32F1 and STM32F030 series pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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AN4325 List of figures

List of figures

Figure 1. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Schottky diode connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. SWD port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. STM32F030 microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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Power supplies and reset sources of the STM32F0x0 family AN4325

1 Power supplies and reset sources of the STM32F0x0

family

1.1 Power supply schemes

The STM32F0x0 family features different products with different supply schemes. It includes
an internal regulator in order to have an internal 1.8 V supply for the core and the digital
logic.
There is a variety of power supply schemes:
• VDD from 2.4 V to 3.6 V: external power supply for I/Os and the internal 1.8 V domain.
Provided externally through VDD pins.
• VDDA from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, HSI,
HSI14, LSI and PLL.
The VDDA voltage level must always be greater than or equal to the VDD voltage level
and must be provided first.

Figure 1. Power supply scheme

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AN4325 Power supplies and reset sources of the STM32F0x0 family

1.1.1 Independent analog power supply

To improve conversion accuracy and to extend the supply flexibility, the analog domain has
an independent power supply which can be separately filtered and shielded from noise on
the PCB.
• The ADC voltage supply input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on pin VSSA.
The VDDA supply can be equal to or higher than VDD. This allows VDD to stay low while still
providing the full performance for the analog blocks.
When a single supply is used, VDDA must be externally connected to VDD. It is
recommended to use an external filtering circuit in order to ensure a noise free VDDA.
When VDDA is different from VDD, VDDA must be always higher or equal to VDD. To keep
safe potential difference between VDDA and VDD during power-up/power-down, an external
Schottky diode may be used between VDD and VDDA. Refer to the datasheet for the
maximum allowed difference.

Figure 2. Schottky diode connection

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1.1.2 Voltage regulator

The voltage regulator is always enabled after reset.
It works under two different modes:
• Main (MR) is used in normal operating mode (Run),
• Low power (LPR) can be used in Stop mode where the power demand is reduced.
In standby mode, the regulator is in power-down mode. In this mode, the regulator output is
in high impedance and the kernel circuitry is powered down, inducing zero consumption and
the loss of the register and SRAM contents. However, the following features are available if
configured:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
a hardware option. Once started it cannot be stopped except by a reset.
• Real-time clock (RTC): configured by the RTCEN bit in the RTC domain control register
(RCC_BDCR).
• Internal low speed oscillator (LSI): configured by the LSION bit in the Control/Status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): configured by the LSEON bit in the RTC domain
control register (RCC_BDCR).

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Power supplies and reset sources of the STM32F0x0 family AN4325

1.2 Reset and power supply supervisor

1.2.1 Power-on reset (POR) / power-down reset (PDR)

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits
which are always active and ensure proper operation above a threshold of 2.4 V.
The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, VPOR/PDR, without the need for an external reset circuit.
• The POR monitors only the VDD supply voltage. During the startup phase, VDDA must
arrive first and be greater than or equal to VDD.
• The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power
supply supervisor can be disabled (by programming a dedicated option bit
VDDA_MONITOR) to reduce the power consumption if the application design ensures that
VDDA is higher than or equal to VDD.
For more details on the power on / power down reset threshold, refer to the electrical
characteristics section in the datasheet.

Figure 3. Power on reset/power down reset waveform

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AN4325 Power supplies and reset sources of the STM32F0x0 family

1.2.2 System reset

A system reset sets all registers to their reset values, except the reset flags in the clock
controller CSR register and the registers in the RTC domain. A system reset is generated
when one of the following events occurs:
• A low level on the NRST pin (external reset)
• System window watchdog event (WWDG reset)
• Independent watchdog event (IWDG reset)
• A software reset (SW reset)
• Low-power management reset
• Option byte loader reset
• Power reset.
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In the case of an external reset, the reset is generated while the NRST pin is
asserted low.

Figure 4. Simplified diagram of the reset circuit

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Software reset
The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex®-M0 technical
reference manual for more details.

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Power supplies and reset sources of the STM32F0x0 family AN4325

Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, two low-power
mode security resets are available. If enabled in Option bytes, the resets are generated in
the following conditions:
• Entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in
User Option Bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
• Entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User
Option Bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.

Option byte loader reset

The option byte loader reset is generated when OBL_LAUNCH (bit 13) is set in the
FLASH_CR register. This bit launches the option byte loading by software.

Power reset
A power reset sets all registers to their reset values, except the RTC domain. See Table 2.

RTC domain reset

An RTC domain reset only affects the RTC, LSE and LSI. It is generated when one of the
following events occurs. SeeTable 2.

Table 2. System reset

Modes Power reset RTC domain reset

POR/PDR reset yes yes

Exiting Standby mode yes no
Setting the BDRST bit in
no yes
RCC_BDCR

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AN4325 Clocks

2 Clocks

Different clock sources can be used to drive the system clock (SYSCLK):
• HSI 8 MHz RC oscillator clock (high-speed internal clock signal)
• HSE oscillator clock (high-speed external clock signal)
• PLL clock
The devices have other secondary clock sources:
• 40 kHz low-speed internal RC (LSI RC) that drives the independent watchdog and,
optionally, the RTC used for auto-wakeup from the Stop/Standby modes.
• 32.768 kHz low-speed external crystal (LSE crystal) that optionally drives the RTC.
• HSI 14MHz RC oscillator (HSI14) dedicated for ADC.
Each clock source can be switched on or off independently when it is not used, to optimize
the power consumption. Refer to reference manual STM32F030x4/6/8/C and
STM32F070x6/B advanced ARM®-based 32-bit MCUs (RM0360) for a description of the
clock tree.

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Clocks AN4325

2.1 High speed external clock signal (HSE) OSC clock

The high speed external clock signal can be generated from two possible clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock.
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and the startup stabilization time. The
loading capacitance values must be adjusted according to the selected resonator.

Figure 5. HSE/ LSE clock sources

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External crystal/ceramic resonator (HSE crystal)

The 4 to 32 MHz external oscillator has the advantage of producing a very accurate
frequency on the main clock. Refer to the electrical characteristics section of the datasheet
for more details about the associated hardware configuration.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).

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AN4325 Clocks

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. The user selects this mode by setting the HSEBYP and HSEON bits in the Clock
control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-
60% duty cycle depending on the frequency (refer to the datasheet) has to drive the
OSC_IN pin while the OSC_OUT pin can be used a GPIO. See Figure 5.

2.2 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low power-
consumption on the other.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt register (RCC_CIR).

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. The user selects this mode by setting the LSEBYP and LSEON bits in the RTC
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See
Figure 5.

2.3 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator
has the advantage of providing a clock source at low cost (no external components). It also
has a faster startup time than the HSE crystal oscillator however, even with calibration, the
frequency is less accurate than an external crystal oscillator or ceramic resonator.

Calibration
The RC oscillator frequencies can vary from one chip to another due to manufacturing
process variations, Therefore, it is possible to route the HSI clock to the MCO multiplexer,
then the clock can be input to Timer 14 allowing the user to calibrate the oscillator.

2.4 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and RTC. The clock frequency is

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25
Clocks AN4325

around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical
characteristics section of the datasheets.

2.5 ADC clock

The ADC clock is either the dedicated 14 MHz RC oscillator (HSI14) or PCLK divided by 2
or 4. When the ADC clock is derived from PCLK, it is in an opposite phase with PCLK. The
14 MHz RC oscillator can be configured by software either to be turned on/off ("auto-off
mode") by the ADC interface or to be always enabled.

2.6 Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
• If a failure is detected on the HSE oscillator clock, the oscillator is automatically
disabled.
– A clock failure event is sent to the break inputs of TIM1 advanced control timer
and TIM15, TIM16 and TIM17 general purpose timers.
– An interrupt is generated to inform the software about the failure (clock security
system interrupt CSSI), allowing the MCU to perform recovery operations.
– CSSI is linked to the Cortex®-M0 NMI (non-maskable interrupt) exception vector.
• If the HSE oscillator is used directly or indirectly as the system clock (indirectly means
that it is used as the PLL input clock, and the PLL clock is used as the system clock), a
detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL that is being used as a system clock when the failure occurs, the
PLL is disabled too.
For details, see the reference manual STM32F030x4/6/8/C and STM32F070x6/B advanced
ARM®-based 32-bit MCUs (RM0360) available from the STMicroelectronics website
www.st.com.

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AN4325 Boot configuration

3 Boot configuration

In the STM32F0x0, three different boot modes can be selected through the BOOT0 pin and
boot configuration bits nBOOT1 in the User option byte, as shown in the following table:

Table 3. Boot modes

Boot mode configuration
Mode
nBOOT1 bit BOOT0 pin

x 0 Main Flash memory is selected as boot space(1)

1 1 System memory is selected as boot space
0 1 Embedded SRAM is selected as boot space
1. For STM32F070x6 and STM32F030xC devices, see also Empty check description.

The Boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is
up to the user to set Boot mode configuration related to the required Boot mode.
The Boot mode configuration is also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is
accessible as follows:
• Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
• Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF EC00 on
STM32F030x4, STM32F030x6 and STM32F030x8 devices, 0x1FFF C400 on
STM32F070x6 devices, 0x1FFF C800 on STM32F070xB and 0x1FFF D800 on
STM32F030xC devices).
• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Empty check
On STM32F070x6 and STM32F030xC devices only, internal empty check flag is
implemented to allow easy programming of the virgin devices by the boot loader. This flag is
used when BOOT0 pin is defining Main Flash memory as the target boot space. When the
flag is set, the device is considered as empty and System memory (boot loader) is selected
instead of the Main Flash as a boot space to allow user to program the Flash memory.
This flag is updated only during Option bytes loading: it is set when the content of the
address 0x08000 0000 is read as 0xFFFF FFFF, otherwise it is cleared. It means a power
on or setting of OBL_LAUNCH bit in FLASH_CR register is needed to clear this flag after
programming of a virgin device to execute user code after System reset.

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Boot configuration AN4325

Note: If the device is programmed for a first time but the Option bytes are not reloaded, the device
will still select System memory as a boot space after a System reset. The boot loader code
is able to detect this situation and will change the boot memory mapping to Main Flash and
perform a jump to user code programmed there.

Physical remap
Once the boot mode is selected, the application software can modify the memory accessible
in the code area. This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1). Unlike Cortex® M3 and M4, the
M0 CPU does not support the vector table relocation. For application code which is located
in a different address than 0x0800 0000, some additional code must be added in order to be
able to serve the application interrupts. A solution will be to relocate by software the vector
table to the internal SRAM:
• Copy the vector table from the Flash (mapped at the base of the application load
address) to the base address of the SRAM at 0x2000 0000.
• Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.
• Then once an interrupt occurs, the Cortex®-M0 processor will fetch the interrupt
handler start address from the relocated vector table in SRAM, then it will jump to
execute the interrupt handler located in the Flash.
This operation should be done at the initialization phase of the application. Please refer to
application note STM32F0xx in-application programming using the USART (AN4065) and
attached IAP code from www.st.com for more details.

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory using one of the following serial
interfaces:
• USART on pins PA14/PA15 or PA9/PA10
• I2C on pins PB6/PB7 (STM32F070xx and STM32F030xC devices only)
• USB DFU interface (STM32F070xx devices only)
For further details, please refer to application note STM32 microcontroller system memory
boot mode (AN2606).

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AN4325 Debug management

4 Debug management

4.1 Introduction
The host/target interface is the hardware equipment that connects the host to the application
board. This interface is made of three components: a hardware debug tool, an SWD
connector and a cable connecting the host to the debug tool.
Figure 6 shows the connection of the host to the evaluation board.

Figure 6. Host-to-board connection

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4.2 SWD port (serial wire debug)

The STM32F0x0 core integrates the serial wire debug port (SW-DP). It is an ARM®
standard CoreSight™ debug port with a 2-pin (clock + data) interface to the debug access
port.

4.3 Pinout and debug port pins

The STM32F0x0 MCU is offered in various packages with varying numbers of available
pins.

4.3.1 Serial wire debug (SWD) pin assignment

The same SWD pin assignment is available on all STM32F0x0 packages.

Table 4. SWD port pins

SWD port
SWD pin name Pin assignment
Type Debug assignment

SWDIO I/O Serial wire data input/output PA13

SWCLK I Serial wire clock PA14

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Debug management AN4325

4.3.2 SWD pin assignment

After reset (SYSRESETn or PORESETn), the pins used for the SWD are assigned as
dedicated pins which are immediately usable by the debugger host.
However, the MCU offers the possibility to disable the SWD, therefore releasing the
associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable
SWD port, check reference manual STM32F030x4/6/8/C and STM32F070x6/B advanced
ARM®-based 32-bit MCUs (RM0360) on the section of I/O pin alternate function multiplexer
and mapping.

4.3.3 Internal pull-up and pull-down on SWD pins

Once the SWD I/O is released by the user software, the GPIO controller takes control of
these pins. The reset states of the GPIO control registers put the I/Os in the equivalent
states:
• SWDIO: alternate function pull-up
• SWCLK: alternate function pull-down
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.

4.3.4 SWD port connection with standard SWD connector

Figure 7 shows the connection between the STM32F0x0 and a standard SWD connector.

Figure 7. SWD port connection

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18/26 DocID024966 Rev 2

AN4325 Recommendations

5 Recommendations

5.1 Printed circuit board

For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a
separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This
provides good decoupling and a good shielding effect. For many applications, economical
reasons prohibit the use of this type of board. In this case, the major requirement is to
ensure a good structure for ground and for the power supply.

5.2 Component position

A preliminary layout of the PCB must make separate circuits:
• High-current circuits
• Low-voltage circuits
• Digital component circuits
• Circuits separated according to their EMI contribution. This will reduce cross-coupling
on the PCB that introduces noise.

5.3 Ground and power supply (VDD, VDDA)

Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all
ground returns should be to a single point. Loops must be avoided or have a minimum area.
In order to improve analog performance, the user must use separate supply sources for VDD
and VDDA, and place the decoupling capacitors as close as possible to the device. The
power supplies should be implemented close to the ground line to minimize the area of the
supplies loop. This is due to the fact that the supply loop acts as an antenna, and is
therefore the main transmitter and receiver of EMI. All component-free PCB areas must be
filled with additional grounding to create a kind of shielding (especially when using single-
layer PCBs).

5.4 Decoupling
All power supply and ground pins must be properly connected to the power supplies. These
connections, including pads, tracks and vias should have as low an impedance as possible.
This is typically achieved with thick track widths and, preferably, the use of dedicated power
supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with 100 nF filtering ceramic
capacitor and a chemical capacitor of about 4.7 µF connected between the supply pins of
the STM32F0x0 device. These capacitors need to be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF,
but exact values depend on the application needs. Figure 8 shows the typical layout of such
a VDD/VSS pair.

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Recommendations AN4325

Figure 8. Typical layout for VDD/VSS pair

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5.5 Other signals

When designing an application, the EMC performance can be improved by closely studying:
• Signals for which a temporary disturbance affects the running process permanently
(such as interrupts and handshaking strobe signals, but not LED commands). For
these signals, a surrounding ground trace, shorter lengths and the absence of noisy
and sensitive traces nearby (crosstalk effect) improve EMC performance.
• Digital signals: the best possible electrical margin must be reached for the two logical
states and slow Schmitt triggers are recommended to eliminate parasitic states.
• Noisy signals (clock, etc.)
• Sensitive signals (high impedance, etc.)

5.6 Unused I/Os and features

All microcontrollers are designed for a variety of applications and often a particular
application does not use 100% of the MCU resources.
To increase EMC performance and avoid extra power consumption, unused clocks,
counters or I/Os, should not be left free. I/Os should be connected to a fixed logic level of 0
or 1 by an external or internal pull-up or pull-down on the unused I/O pin. The other option is
to configure GPIO as output mode using software. Unused features should be frozen or
disabled, which is their default value.

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AN4325 Reference design

6 Reference design

6.1 Description
The reference design shown in Figure 9, introduces the STM32F0x0, a highly integrated
microcontroller running at 48 MHz, that combines the Cortex®-M0 32-bit RISC CPU core
with 64 Kbytes of embedded Flash memory and 8 Kbytes of SRAM.

6.1.1 Clock
Two clock sources are used for the microcontroller:
• HSE: X1– 8 MHz crystal for the STM32F0x0 microcontroller
• LSE: X2– 32.768 kHz crystal for the embedded RTC
Refer to Section 2: Clocks on page 11.

6.1.2 Reset
The reset signal in Figure 9 is active low. The reset sources include:
• Reset button (B1)
• Debugging tools via the connector CN1
Refer to Section 1.2.2: System reset on page 9.

6.1.3 Boot mode

The boot option is configured by setting BOOT0 through switch SW1 and option bit
nBOOT1. Refer to Section 3: Boot configuration on page 15.

6.1.4 SWD interface

The reference design shows the connection between the STM32F0x0 and a standard SWD
connector. Refer to Section 4: Debug management on page 17.
Note: It is recommended to connect the reset pin in order to be able to reset the application from
the tool.

6.1.5 Power supply

Refer to Section 1.1: Power supply schemes on page 6.

6.1.6 Pinouts and pin description

Please refer to the STM32F0x0 datasheets available on www.st.com for the pinout
information and pin description of each device.

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Reference design AN4325

6.2 Component references

Table 5. Mandatory components
Component Reference Value Quantity Comments

Microcontroller U1 STM32F030R8T6 1 64-pin package.

Capacitor C1/C2 100 nF 2 Ceramic capacitors (decoupling capacitors).
Capacitor C3 10 nF 1 Ceramic capacitor (decoupling capacitor).
Capacitor C5 1 µF 1 Used for VDDA.
Capacitor C6 4.7 µF 1 Used for VDD.

Table 6. Optional components

Component Reference Value Quantity Comments

Used for HSE: the value depends on the crystal

Resistor R1 390 Ω 1 characteristics.
This value is given only as a typical example.
Resistor R2 10 KΩ 1 Used for BOOT0 pin.
Capacitor C4 100 nF 1 Ceramic capacitor for RESET button.
Used for LSE: the value depends on the crystal
Capacitor C7/C8 10 pF 2
characteristics.
Used for HSE: the value depends on the crystal
Capacitor C9/C10 20 pF 2
characteristics.
Quartz X1 8 MHz 1 Used for HSE.
Quartz X2 32 kHz 1 Used for LSE.
Switch SW1 - 1 Used to select the correct boot mode.
Push-button B1 - 1 Used as reset button.
SWD connector CN1 FTSH-105-01-L-DV 1 Used for program/debug of the MCU.

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AN4325 Reference design

Figure 9. STM32F030 microcontroller reference schematic

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25
Hardware migration from STM32F1 series to STM32F0x0 devices AN4325

7 Hardware migration from STM32F1 series to

STM32F0x0 devices

The entry-level STM32F030 and general-purpose STM32F1xxx families are pin-to-pin

compatible. All peripherals shares the same pins in the two families, but there are some
minor differences between packages.
The transition from the STM32F1 series to the STM32F030 devices is simple as only a few
pins are impacted. The impacted pins are shown in bold in Table 7.

Table 7. STM32F1 and STM32F030 series pinout differences(1)

Package STM32F1 series STM32F030 devices

LQFP64 LQFP48 Pinout Pinout

1 1 VBAT VDD
5 5 PD0 - OSC_IN PF0 - OSC_IN
6 6 PD1 - OSC_OUT PF1 - OSC_OUT
18 - VSS_4 PF4
19 - VDD_4 PF5
28 20 BOOT1 - PB2 PB2
47 35 VSS_2 PF6
48 36 VDD_2 PF7
1. Highlighted in bold the impacted pins of the transition between STM32F1 series to STM32F030 devices.

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AN4325 Revision history

8 Revision history

Table 8. Document revision history

Date Revision Changes

10-Nov-2014 1 Initial release.

01-Apr-2016 2 Added the support for STM32F070xx along the document.

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 AN4325

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